19c92ab61SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 201acf691SAdam Lee /* 301acf691SAdam Lee * Copyright (C) 2013 BayHub Technology Ltd. 401acf691SAdam Lee * 501acf691SAdam Lee * Authors: Peter Guo <peter.guo@bayhubtech.com> 601acf691SAdam Lee * Adam Lee <adam.lee@canonical.com> 757322d54Sernest.zhang * Ernest Zhang <ernest.zhang@bayhubtech.com> 801acf691SAdam Lee */ 901acf691SAdam Lee 1001acf691SAdam Lee #include <linux/pci.h> 110086fc21Sernest.zhang #include <linux/mmc/host.h> 120086fc21Sernest.zhang #include <linux/mmc/mmc.h> 130086fc21Sernest.zhang #include <linux/delay.h> 147d440617SShirley Her (SC) #include <linux/iopoll.h> 1501acf691SAdam Lee 1601acf691SAdam Lee #include "sdhci.h" 1701acf691SAdam Lee #include "sdhci-pci.h" 18361eeda0SAdrian Hunter 19361eeda0SAdrian Hunter /* 20361eeda0SAdrian Hunter * O2Micro device registers 21361eeda0SAdrian Hunter */ 22361eeda0SAdrian Hunter 23361eeda0SAdrian Hunter #define O2_SD_MISC_REG5 0x64 24361eeda0SAdrian Hunter #define O2_SD_LD0_CTRL 0x68 25361eeda0SAdrian Hunter #define O2_SD_DEV_CTRL 0x88 26361eeda0SAdrian Hunter #define O2_SD_LOCK_WP 0xD3 27361eeda0SAdrian Hunter #define O2_SD_TEST_REG 0xD4 28361eeda0SAdrian Hunter #define O2_SD_FUNC_REG0 0xDC 29361eeda0SAdrian Hunter #define O2_SD_MULTI_VCC3V 0xEE 30361eeda0SAdrian Hunter #define O2_SD_CLKREQ 0xEC 31361eeda0SAdrian Hunter #define O2_SD_CAPS 0xE0 32361eeda0SAdrian Hunter #define O2_SD_ADMA1 0xE2 33361eeda0SAdrian Hunter #define O2_SD_ADMA2 0xE7 34361eeda0SAdrian Hunter #define O2_SD_INF_MOD 0xF1 35361eeda0SAdrian Hunter #define O2_SD_MISC_CTRL4 0xFC 36*1ad9f880SShirley Her #define O2_SD_MISC_CTRL 0x1C0 37*1ad9f880SShirley Her #define O2_SD_PWR_FORCE_L0 0x0002 38361eeda0SAdrian Hunter #define O2_SD_TUNING_CTRL 0x300 39361eeda0SAdrian Hunter #define O2_SD_PLL_SETTING 0x304 4057322d54Sernest.zhang #define O2_SD_MISC_SETTING 0x308 41361eeda0SAdrian Hunter #define O2_SD_CLK_SETTING 0x328 42361eeda0SAdrian Hunter #define O2_SD_CAP_REG2 0x330 43361eeda0SAdrian Hunter #define O2_SD_CAP_REG0 0x334 44361eeda0SAdrian Hunter #define O2_SD_UHS1_CAP_SETTING 0x33C 45361eeda0SAdrian Hunter #define O2_SD_DELAY_CTRL 0x350 46361eeda0SAdrian Hunter #define O2_SD_UHS2_L1_CTRL 0x35C 47361eeda0SAdrian Hunter #define O2_SD_FUNC_REG3 0x3E0 48361eeda0SAdrian Hunter #define O2_SD_FUNC_REG4 0x3E4 49361eeda0SAdrian Hunter #define O2_SD_LED_ENABLE BIT(6) 50361eeda0SAdrian Hunter #define O2_SD_FREG0_LEDOFF BIT(13) 51361eeda0SAdrian Hunter #define O2_SD_FREG4_ENABLE_CLK_SET BIT(22) 52361eeda0SAdrian Hunter 53361eeda0SAdrian Hunter #define O2_SD_VENDOR_SETTING 0x110 54361eeda0SAdrian Hunter #define O2_SD_VENDOR_SETTING2 0x1C8 550086fc21Sernest.zhang #define O2_SD_HW_TUNING_DISABLE BIT(4) 560086fc21Sernest.zhang 579674bab4SShirley Her (SC) #define O2_PLL_DLL_WDT_CONTROL1 0x1CC 5869d91ed1SErnest Zhang(WH) #define O2_PLL_FORCE_ACTIVE BIT(18) 5969d91ed1SErnest Zhang(WH) #define O2_PLL_LOCK_STATUS BIT(14) 6069d91ed1SErnest Zhang(WH) #define O2_PLL_SOFT_RESET BIT(12) 617d440617SShirley Her (SC) #define O2_DLL_LOCK_STATUS BIT(11) 6269d91ed1SErnest Zhang(WH) 6369d91ed1SErnest Zhang(WH) #define O2_SD_DETECT_SETTING 0x324 6469d91ed1SErnest Zhang(WH) 657d440617SShirley Her (SC) static const u32 dmdn_table[] = {0x2B1C0000, 667d440617SShirley Her (SC) 0x2C1A0000, 0x371B0000, 0x35100000}; 677d440617SShirley Her (SC) #define DMDN_SZ ARRAY_SIZE(dmdn_table) 687d440617SShirley Her (SC) 697d440617SShirley Her (SC) struct o2_host { 707d440617SShirley Her (SC) u8 dll_adjust_count; 717d440617SShirley Her (SC) }; 727d440617SShirley Her (SC) 73908fd508SShirley Her (SC) static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host) 74908fd508SShirley Her (SC) { 75908fd508SShirley Her (SC) ktime_t timeout; 76908fd508SShirley Her (SC) u32 scratch32; 77908fd508SShirley Her (SC) 78908fd508SShirley Her (SC) /* Wait max 50 ms */ 79908fd508SShirley Her (SC) timeout = ktime_add_ms(ktime_get(), 50); 80908fd508SShirley Her (SC) while (1) { 81908fd508SShirley Her (SC) bool timedout = ktime_after(ktime_get(), timeout); 82908fd508SShirley Her (SC) 83908fd508SShirley Her (SC) scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE); 84908fd508SShirley Her (SC) if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT 85908fd508SShirley Her (SC) == (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT) 86908fd508SShirley Her (SC) break; 87908fd508SShirley Her (SC) 88908fd508SShirley Her (SC) if (timedout) { 89908fd508SShirley Her (SC) pr_err("%s: Card Detect debounce never finished.\n", 90908fd508SShirley Her (SC) mmc_hostname(host->mmc)); 91908fd508SShirley Her (SC) sdhci_dumpregs(host); 92908fd508SShirley Her (SC) return; 93908fd508SShirley Her (SC) } 94908fd508SShirley Her (SC) udelay(10); 95908fd508SShirley Her (SC) } 96908fd508SShirley Her (SC) } 97908fd508SShirley Her (SC) 98908fd508SShirley Her (SC) static void sdhci_o2_enable_internal_clock(struct sdhci_host *host) 99908fd508SShirley Her (SC) { 100908fd508SShirley Her (SC) ktime_t timeout; 101908fd508SShirley Her (SC) u16 scratch; 102908fd508SShirley Her (SC) u32 scratch32; 103908fd508SShirley Her (SC) 104908fd508SShirley Her (SC) /* PLL software reset */ 105908fd508SShirley Her (SC) scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); 106908fd508SShirley Her (SC) scratch32 |= O2_PLL_SOFT_RESET; 107908fd508SShirley Her (SC) sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); 108908fd508SShirley Her (SC) udelay(1); 109908fd508SShirley Her (SC) scratch32 &= ~(O2_PLL_SOFT_RESET); 110908fd508SShirley Her (SC) sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); 111908fd508SShirley Her (SC) 112908fd508SShirley Her (SC) /* PLL force active */ 113908fd508SShirley Her (SC) scratch32 |= O2_PLL_FORCE_ACTIVE; 114908fd508SShirley Her (SC) sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); 115908fd508SShirley Her (SC) 116908fd508SShirley Her (SC) /* Wait max 20 ms */ 117908fd508SShirley Her (SC) timeout = ktime_add_ms(ktime_get(), 20); 118908fd508SShirley Her (SC) while (1) { 119908fd508SShirley Her (SC) bool timedout = ktime_after(ktime_get(), timeout); 120908fd508SShirley Her (SC) 121908fd508SShirley Her (SC) scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1); 122908fd508SShirley Her (SC) if (scratch & O2_PLL_LOCK_STATUS) 123908fd508SShirley Her (SC) break; 124908fd508SShirley Her (SC) if (timedout) { 125908fd508SShirley Her (SC) pr_err("%s: Internal clock never stabilised.\n", 126908fd508SShirley Her (SC) mmc_hostname(host->mmc)); 127908fd508SShirley Her (SC) sdhci_dumpregs(host); 128908fd508SShirley Her (SC) goto out; 129908fd508SShirley Her (SC) } 130908fd508SShirley Her (SC) udelay(10); 131908fd508SShirley Her (SC) } 132908fd508SShirley Her (SC) 133908fd508SShirley Her (SC) /* Wait for card detect finish */ 134908fd508SShirley Her (SC) udelay(1); 135908fd508SShirley Her (SC) sdhci_o2_wait_card_detect_stable(host); 136908fd508SShirley Her (SC) 137908fd508SShirley Her (SC) out: 138908fd508SShirley Her (SC) /* Cancel PLL force active */ 139908fd508SShirley Her (SC) scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); 140908fd508SShirley Her (SC) scratch32 &= ~O2_PLL_FORCE_ACTIVE; 141908fd508SShirley Her (SC) sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); 142908fd508SShirley Her (SC) } 143908fd508SShirley Her (SC) 144908fd508SShirley Her (SC) static int sdhci_o2_get_cd(struct mmc_host *mmc) 145908fd508SShirley Her (SC) { 146908fd508SShirley Her (SC) struct sdhci_host *host = mmc_priv(mmc); 147908fd508SShirley Her (SC) 1487d440617SShirley Her (SC) if (!(sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1) & O2_PLL_LOCK_STATUS)) 149908fd508SShirley Her (SC) sdhci_o2_enable_internal_clock(host); 150908fd508SShirley Her (SC) 151908fd508SShirley Her (SC) return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 152908fd508SShirley Her (SC) } 153908fd508SShirley Her (SC) 154908fd508SShirley Her (SC) static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value) 155908fd508SShirley Her (SC) { 156908fd508SShirley Her (SC) u32 scratch_32; 157908fd508SShirley Her (SC) 158908fd508SShirley Her (SC) pci_read_config_dword(chip->pdev, 159908fd508SShirley Her (SC) O2_SD_PLL_SETTING, &scratch_32); 160908fd508SShirley Her (SC) 161908fd508SShirley Her (SC) scratch_32 &= 0x0000FFFF; 162908fd508SShirley Her (SC) scratch_32 |= value; 163908fd508SShirley Her (SC) 164908fd508SShirley Her (SC) pci_write_config_dword(chip->pdev, 165908fd508SShirley Her (SC) O2_SD_PLL_SETTING, scratch_32); 166908fd508SShirley Her (SC) } 167908fd508SShirley Her (SC) 1687d440617SShirley Her (SC) static u32 sdhci_o2_pll_dll_wdt_control(struct sdhci_host *host) 1697d440617SShirley Her (SC) { 1707d440617SShirley Her (SC) return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); 1717d440617SShirley Her (SC) } 1727d440617SShirley Her (SC) 1737d440617SShirley Her (SC) /* 1747d440617SShirley Her (SC) * This function is used to detect dll lock status. 1757d440617SShirley Her (SC) * Since the dll lock status bit will toggle randomly 1767d440617SShirley Her (SC) * with very short interval which needs to be polled 1777d440617SShirley Her (SC) * as fast as possible. Set sleep_us as 1 microsecond. 1787d440617SShirley Her (SC) */ 1797d440617SShirley Her (SC) static int sdhci_o2_wait_dll_detect_lock(struct sdhci_host *host) 1807d440617SShirley Her (SC) { 1817d440617SShirley Her (SC) u32 scratch32 = 0; 1827d440617SShirley Her (SC) 1837d440617SShirley Her (SC) return readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host, 1847d440617SShirley Her (SC) scratch32, !(scratch32 & O2_DLL_LOCK_STATUS), 1, 1000000); 1857d440617SShirley Her (SC) } 1867d440617SShirley Her (SC) 1870086fc21Sernest.zhang static void sdhci_o2_set_tuning_mode(struct sdhci_host *host) 1880086fc21Sernest.zhang { 1890086fc21Sernest.zhang u16 reg; 1900086fc21Sernest.zhang 1910086fc21Sernest.zhang /* enable hardware tuning */ 1920086fc21Sernest.zhang reg = sdhci_readw(host, O2_SD_VENDOR_SETTING); 1930086fc21Sernest.zhang reg &= ~O2_SD_HW_TUNING_DISABLE; 1940086fc21Sernest.zhang sdhci_writew(host, reg, O2_SD_VENDOR_SETTING); 1950086fc21Sernest.zhang } 1960086fc21Sernest.zhang 1970086fc21Sernest.zhang static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode) 1980086fc21Sernest.zhang { 1990086fc21Sernest.zhang int i; 2000086fc21Sernest.zhang 2017b7d897eSshirley her sdhci_send_tuning(host, opcode); 2020086fc21Sernest.zhang 2030086fc21Sernest.zhang for (i = 0; i < 150; i++) { 2040086fc21Sernest.zhang u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2050086fc21Sernest.zhang 2060086fc21Sernest.zhang if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { 2070086fc21Sernest.zhang if (ctrl & SDHCI_CTRL_TUNED_CLK) { 2080086fc21Sernest.zhang host->tuning_done = true; 2090086fc21Sernest.zhang return; 2100086fc21Sernest.zhang } 2110086fc21Sernest.zhang pr_warn("%s: HW tuning failed !\n", 2120086fc21Sernest.zhang mmc_hostname(host->mmc)); 2130086fc21Sernest.zhang break; 2140086fc21Sernest.zhang } 2150086fc21Sernest.zhang 2160086fc21Sernest.zhang mdelay(1); 2170086fc21Sernest.zhang } 2180086fc21Sernest.zhang 2190086fc21Sernest.zhang pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", 2200086fc21Sernest.zhang mmc_hostname(host->mmc)); 2210086fc21Sernest.zhang sdhci_reset_tuning(host); 2220086fc21Sernest.zhang } 2230086fc21Sernest.zhang 2247d440617SShirley Her (SC) /* 2257d440617SShirley Her (SC) * This function is used to fix o2 dll shift issue. 2267d440617SShirley Her (SC) * It isn't necessary to detect card present before recovery. 2277d440617SShirley Her (SC) * Firstly, it is used by bht emmc card, which is embedded. 2287d440617SShirley Her (SC) * Second, before call recovery card present will be detected 2297d440617SShirley Her (SC) * outside of the execute tuning function. 2307d440617SShirley Her (SC) */ 2317d440617SShirley Her (SC) static int sdhci_o2_dll_recovery(struct sdhci_host *host) 2327d440617SShirley Her (SC) { 2337d440617SShirley Her (SC) int ret = 0; 2347d440617SShirley Her (SC) u8 scratch_8 = 0; 2357d440617SShirley Her (SC) u32 scratch_32 = 0; 2367d440617SShirley Her (SC) struct sdhci_pci_slot *slot = sdhci_priv(host); 2377d440617SShirley Her (SC) struct sdhci_pci_chip *chip = slot->chip; 2387d440617SShirley Her (SC) struct o2_host *o2_host = sdhci_pci_priv(slot); 2397d440617SShirley Her (SC) 2407d440617SShirley Her (SC) /* UnLock WP */ 2417d440617SShirley Her (SC) pci_read_config_byte(chip->pdev, 2427d440617SShirley Her (SC) O2_SD_LOCK_WP, &scratch_8); 2437d440617SShirley Her (SC) scratch_8 &= 0x7f; 2447d440617SShirley Her (SC) pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); 2457d440617SShirley Her (SC) while (o2_host->dll_adjust_count < DMDN_SZ && !ret) { 2467d440617SShirley Her (SC) /* Disable clock */ 2477d440617SShirley Her (SC) sdhci_writeb(host, 0, SDHCI_CLOCK_CONTROL); 2487d440617SShirley Her (SC) 2497d440617SShirley Her (SC) /* PLL software reset */ 2507d440617SShirley Her (SC) scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); 2517d440617SShirley Her (SC) scratch_32 |= O2_PLL_SOFT_RESET; 2527d440617SShirley Her (SC) sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1); 2537d440617SShirley Her (SC) 2547d440617SShirley Her (SC) pci_read_config_dword(chip->pdev, 2557d440617SShirley Her (SC) O2_SD_FUNC_REG4, 2567d440617SShirley Her (SC) &scratch_32); 2577d440617SShirley Her (SC) /* Enable Base Clk setting change */ 2587d440617SShirley Her (SC) scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET; 2597d440617SShirley Her (SC) pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32); 2607d440617SShirley Her (SC) o2_pci_set_baseclk(chip, dmdn_table[o2_host->dll_adjust_count]); 2617d440617SShirley Her (SC) 2627d440617SShirley Her (SC) /* Enable internal clock */ 2637d440617SShirley Her (SC) scratch_8 = SDHCI_CLOCK_INT_EN; 2647d440617SShirley Her (SC) sdhci_writeb(host, scratch_8, SDHCI_CLOCK_CONTROL); 2657d440617SShirley Her (SC) 2667d440617SShirley Her (SC) if (sdhci_o2_get_cd(host->mmc)) { 2677d440617SShirley Her (SC) /* 2687d440617SShirley Her (SC) * need wait at least 5ms for dll status stable, 2697d440617SShirley Her (SC) * after enable internal clock 2707d440617SShirley Her (SC) */ 2717d440617SShirley Her (SC) usleep_range(5000, 6000); 2727d440617SShirley Her (SC) if (sdhci_o2_wait_dll_detect_lock(host)) { 2737d440617SShirley Her (SC) scratch_8 |= SDHCI_CLOCK_CARD_EN; 2747d440617SShirley Her (SC) sdhci_writeb(host, scratch_8, 2757d440617SShirley Her (SC) SDHCI_CLOCK_CONTROL); 2767d440617SShirley Her (SC) ret = 1; 2777d440617SShirley Her (SC) } else { 2787d440617SShirley Her (SC) pr_warn("%s: DLL unlocked when dll_adjust_count is %d.\n", 2797d440617SShirley Her (SC) mmc_hostname(host->mmc), 2807d440617SShirley Her (SC) o2_host->dll_adjust_count); 2817d440617SShirley Her (SC) } 2827d440617SShirley Her (SC) } else { 2837d440617SShirley Her (SC) pr_err("%s: card present detect failed.\n", 2847d440617SShirley Her (SC) mmc_hostname(host->mmc)); 2857d440617SShirley Her (SC) break; 2867d440617SShirley Her (SC) } 2877d440617SShirley Her (SC) 2887d440617SShirley Her (SC) o2_host->dll_adjust_count++; 2897d440617SShirley Her (SC) } 2907d440617SShirley Her (SC) if (!ret && o2_host->dll_adjust_count == DMDN_SZ) 2917d440617SShirley Her (SC) pr_err("%s: DLL adjust over max times\n", 2927d440617SShirley Her (SC) mmc_hostname(host->mmc)); 2937d440617SShirley Her (SC) /* Lock WP */ 2947d440617SShirley Her (SC) pci_read_config_byte(chip->pdev, 2957d440617SShirley Her (SC) O2_SD_LOCK_WP, &scratch_8); 2967d440617SShirley Her (SC) scratch_8 |= 0x80; 2977d440617SShirley Her (SC) pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); 2987d440617SShirley Her (SC) return ret; 2997d440617SShirley Her (SC) } 3007d440617SShirley Her (SC) 3010086fc21Sernest.zhang static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode) 3020086fc21Sernest.zhang { 3030086fc21Sernest.zhang struct sdhci_host *host = mmc_priv(mmc); 3040086fc21Sernest.zhang int current_bus_width = 0; 305*1ad9f880SShirley Her u32 scratch32 = 0; 306*1ad9f880SShirley Her u16 scratch = 0; 3070086fc21Sernest.zhang 3080086fc21Sernest.zhang /* 3090086fc21Sernest.zhang * This handler only implements the eMMC tuning that is specific to 3100086fc21Sernest.zhang * this controller. Fall back to the standard method for other TIMING. 3110086fc21Sernest.zhang */ 3127b7d897eSshirley her if ((host->timing != MMC_TIMING_MMC_HS200) && 3137b7d897eSshirley her (host->timing != MMC_TIMING_UHS_SDR104)) 3140086fc21Sernest.zhang return sdhci_execute_tuning(mmc, opcode); 3150086fc21Sernest.zhang 3167b7d897eSshirley her if (WARN_ON((opcode != MMC_SEND_TUNING_BLOCK_HS200) && 3177b7d897eSshirley her (opcode != MMC_SEND_TUNING_BLOCK))) 3180086fc21Sernest.zhang return -EINVAL; 319*1ad9f880SShirley Her 320*1ad9f880SShirley Her /* Force power mode enter L0 */ 321*1ad9f880SShirley Her scratch = sdhci_readw(host, O2_SD_MISC_CTRL); 322*1ad9f880SShirley Her scratch |= O2_SD_PWR_FORCE_L0; 323*1ad9f880SShirley Her sdhci_writew(host, scratch, O2_SD_MISC_CTRL); 324*1ad9f880SShirley Her 325*1ad9f880SShirley Her /* wait DLL lock, timeout value 5ms */ 326*1ad9f880SShirley Her if (readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host, 327*1ad9f880SShirley Her scratch32, (scratch32 & O2_DLL_LOCK_STATUS), 1, 5000)) 328*1ad9f880SShirley Her pr_warn("%s: DLL can't lock in 5ms after force L0 during tuning.\n", 329*1ad9f880SShirley Her mmc_hostname(host->mmc)); 3307d440617SShirley Her (SC) /* 3317d440617SShirley Her (SC) * Judge the tuning reason, whether caused by dll shift 3327d440617SShirley Her (SC) * If cause by dll shift, should call sdhci_o2_dll_recovery 3337d440617SShirley Her (SC) */ 3347d440617SShirley Her (SC) if (!sdhci_o2_wait_dll_detect_lock(host)) 3357d440617SShirley Her (SC) if (!sdhci_o2_dll_recovery(host)) { 3367d440617SShirley Her (SC) pr_err("%s: o2 dll recovery failed\n", 3377d440617SShirley Her (SC) mmc_hostname(host->mmc)); 3387d440617SShirley Her (SC) return -EINVAL; 3397d440617SShirley Her (SC) } 3400086fc21Sernest.zhang /* 3410086fc21Sernest.zhang * o2 sdhci host didn't support 8bit emmc tuning 3420086fc21Sernest.zhang */ 3430086fc21Sernest.zhang if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) { 3440086fc21Sernest.zhang current_bus_width = mmc->ios.bus_width; 3450f7b79a4SRaul E Rangel mmc->ios.bus_width = MMC_BUS_WIDTH_4; 3460086fc21Sernest.zhang sdhci_set_bus_width(host, MMC_BUS_WIDTH_4); 3470086fc21Sernest.zhang } 3480086fc21Sernest.zhang 3490086fc21Sernest.zhang sdhci_o2_set_tuning_mode(host); 3500086fc21Sernest.zhang 3510086fc21Sernest.zhang sdhci_start_tuning(host); 3520086fc21Sernest.zhang 3530086fc21Sernest.zhang __sdhci_o2_execute_tuning(host, opcode); 3540086fc21Sernest.zhang 3550086fc21Sernest.zhang sdhci_end_tuning(host); 3560086fc21Sernest.zhang 3570f7b79a4SRaul E Rangel if (current_bus_width == MMC_BUS_WIDTH_8) { 3580f7b79a4SRaul E Rangel mmc->ios.bus_width = MMC_BUS_WIDTH_8; 3590086fc21Sernest.zhang sdhci_set_bus_width(host, current_bus_width); 3600f7b79a4SRaul E Rangel } 3610086fc21Sernest.zhang 362*1ad9f880SShirley Her /* Cancel force power mode enter L0 */ 363*1ad9f880SShirley Her scratch = sdhci_readw(host, O2_SD_MISC_CTRL); 364*1ad9f880SShirley Her scratch &= ~(O2_SD_PWR_FORCE_L0); 365*1ad9f880SShirley Her sdhci_writew(host, scratch, O2_SD_MISC_CTRL); 366*1ad9f880SShirley Her 3677b7d897eSshirley her sdhci_reset(host, SDHCI_RESET_CMD); 3687b7d897eSshirley her sdhci_reset(host, SDHCI_RESET_DATA); 3697b7d897eSshirley her 3700086fc21Sernest.zhang host->flags &= ~SDHCI_HS400_TUNING; 3710086fc21Sernest.zhang return 0; 3720086fc21Sernest.zhang } 37301acf691SAdam Lee 374706adf6bSPeter Guo static void o2_pci_led_enable(struct sdhci_pci_chip *chip) 375706adf6bSPeter Guo { 376706adf6bSPeter Guo int ret; 377706adf6bSPeter Guo u32 scratch_32; 378706adf6bSPeter Guo 379706adf6bSPeter Guo /* Set led of SD host function enable */ 380706adf6bSPeter Guo ret = pci_read_config_dword(chip->pdev, 381706adf6bSPeter Guo O2_SD_FUNC_REG0, &scratch_32); 382706adf6bSPeter Guo if (ret) 383706adf6bSPeter Guo return; 384706adf6bSPeter Guo 385706adf6bSPeter Guo scratch_32 &= ~O2_SD_FREG0_LEDOFF; 386706adf6bSPeter Guo pci_write_config_dword(chip->pdev, 387706adf6bSPeter Guo O2_SD_FUNC_REG0, scratch_32); 388706adf6bSPeter Guo 389706adf6bSPeter Guo ret = pci_read_config_dword(chip->pdev, 390706adf6bSPeter Guo O2_SD_TEST_REG, &scratch_32); 391706adf6bSPeter Guo if (ret) 392706adf6bSPeter Guo return; 393706adf6bSPeter Guo 394706adf6bSPeter Guo scratch_32 |= O2_SD_LED_ENABLE; 395706adf6bSPeter Guo pci_write_config_dword(chip->pdev, 396706adf6bSPeter Guo O2_SD_TEST_REG, scratch_32); 397706adf6bSPeter Guo } 398706adf6bSPeter Guo 399f0cbd780SBen Hutchings static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip) 40001acf691SAdam Lee { 40101acf691SAdam Lee u32 scratch_32; 40201acf691SAdam Lee int ret; 40301acf691SAdam Lee /* Improve write performance for SD3.0 */ 40401acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32); 40501acf691SAdam Lee if (ret) 40601acf691SAdam Lee return; 40701acf691SAdam Lee scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14)); 40801acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32); 40901acf691SAdam Lee 41001acf691SAdam Lee /* Enable Link abnormal reset generating Reset */ 41101acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32); 41201acf691SAdam Lee if (ret) 41301acf691SAdam Lee return; 41401acf691SAdam Lee scratch_32 &= ~((1 << 19) | (1 << 11)); 41501acf691SAdam Lee scratch_32 |= (1 << 10); 41601acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32); 41701acf691SAdam Lee 41801acf691SAdam Lee /* set card power over current protection */ 41901acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32); 42001acf691SAdam Lee if (ret) 42101acf691SAdam Lee return; 42201acf691SAdam Lee scratch_32 |= (1 << 4); 42301acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32); 42401acf691SAdam Lee 42501acf691SAdam Lee /* adjust the output delay for SD mode */ 42601acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492); 42701acf691SAdam Lee 42801acf691SAdam Lee /* Set the output voltage setting of Aux 1.2v LDO */ 42901acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32); 43001acf691SAdam Lee if (ret) 43101acf691SAdam Lee return; 43201acf691SAdam Lee scratch_32 &= ~(3 << 12); 43301acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32); 43401acf691SAdam Lee 43501acf691SAdam Lee /* Set Max power supply capability of SD host */ 43601acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32); 43701acf691SAdam Lee if (ret) 43801acf691SAdam Lee return; 43901acf691SAdam Lee scratch_32 &= ~(0x01FE); 44001acf691SAdam Lee scratch_32 |= 0x00CC; 44101acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32); 44201acf691SAdam Lee /* Set DLL Tuning Window */ 44301acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, 44401acf691SAdam Lee O2_SD_TUNING_CTRL, &scratch_32); 44501acf691SAdam Lee if (ret) 44601acf691SAdam Lee return; 44701acf691SAdam Lee scratch_32 &= ~(0x000000FF); 44801acf691SAdam Lee scratch_32 |= 0x00000066; 44901acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32); 45001acf691SAdam Lee 45101acf691SAdam Lee /* Set UHS2 T_EIDLE */ 45201acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, 45301acf691SAdam Lee O2_SD_UHS2_L1_CTRL, &scratch_32); 45401acf691SAdam Lee if (ret) 45501acf691SAdam Lee return; 45601acf691SAdam Lee scratch_32 &= ~(0x000000FC); 45701acf691SAdam Lee scratch_32 |= 0x00000084; 45801acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32); 45901acf691SAdam Lee 46001acf691SAdam Lee /* Set UHS2 Termination */ 46101acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32); 46201acf691SAdam Lee if (ret) 46301acf691SAdam Lee return; 46401acf691SAdam Lee scratch_32 &= ~((1 << 21) | (1 << 30)); 46501acf691SAdam Lee 46601acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32); 46701acf691SAdam Lee 46801acf691SAdam Lee /* Set L1 Entrance Timer */ 46901acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32); 47001acf691SAdam Lee if (ret) 47101acf691SAdam Lee return; 47201acf691SAdam Lee scratch_32 &= ~(0xf0000000); 47301acf691SAdam Lee scratch_32 |= 0x30000000; 47401acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32); 47501acf691SAdam Lee 47601acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, 47701acf691SAdam Lee O2_SD_MISC_CTRL4, &scratch_32); 47801acf691SAdam Lee if (ret) 47901acf691SAdam Lee return; 48001acf691SAdam Lee scratch_32 &= ~(0x000f0000); 48101acf691SAdam Lee scratch_32 |= 0x00080000; 48201acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32); 48301acf691SAdam Lee } 48401acf691SAdam Lee 48502a3c0bdSernest.zhang static void sdhci_pci_o2_enable_msi(struct sdhci_pci_chip *chip, 48602a3c0bdSernest.zhang struct sdhci_host *host) 48702a3c0bdSernest.zhang { 48802a3c0bdSernest.zhang int ret; 48902a3c0bdSernest.zhang 49002a3c0bdSernest.zhang ret = pci_find_capability(chip->pdev, PCI_CAP_ID_MSI); 49102a3c0bdSernest.zhang if (!ret) { 49202a3c0bdSernest.zhang pr_info("%s: unsupport msi, use INTx irq\n", 49302a3c0bdSernest.zhang mmc_hostname(host->mmc)); 49402a3c0bdSernest.zhang return; 49502a3c0bdSernest.zhang } 49602a3c0bdSernest.zhang 49702a3c0bdSernest.zhang ret = pci_alloc_irq_vectors(chip->pdev, 1, 1, 49802a3c0bdSernest.zhang PCI_IRQ_MSI | PCI_IRQ_MSIX); 49902a3c0bdSernest.zhang if (ret < 0) { 50002a3c0bdSernest.zhang pr_err("%s: enable PCI MSI failed, err=%d\n", 50102a3c0bdSernest.zhang mmc_hostname(host->mmc), ret); 50202a3c0bdSernest.zhang return; 50302a3c0bdSernest.zhang } 50402a3c0bdSernest.zhang 50502a3c0bdSernest.zhang host->irq = pci_irq_vector(chip->pdev, 0); 50602a3c0bdSernest.zhang } 50702a3c0bdSernest.zhang 50869d91ed1SErnest Zhang(WH) static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk) 50969d91ed1SErnest Zhang(WH) { 51069d91ed1SErnest Zhang(WH) /* Enable internal clock */ 51169d91ed1SErnest Zhang(WH) clk |= SDHCI_CLOCK_INT_EN; 51269d91ed1SErnest Zhang(WH) sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 51369d91ed1SErnest Zhang(WH) 5147d440617SShirley Her (SC) sdhci_o2_enable_internal_clock(host); 51569d91ed1SErnest Zhang(WH) if (sdhci_o2_get_cd(host->mmc)) { 51669d91ed1SErnest Zhang(WH) clk |= SDHCI_CLOCK_CARD_EN; 51769d91ed1SErnest Zhang(WH) sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 51869d91ed1SErnest Zhang(WH) } 51969d91ed1SErnest Zhang(WH) } 52069d91ed1SErnest Zhang(WH) 521580b946eSZou Wei static void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock) 52269d91ed1SErnest Zhang(WH) { 52369d91ed1SErnest Zhang(WH) u16 clk; 5247b7d897eSshirley her u8 scratch; 5257b7d897eSshirley her u32 scratch_32; 5267b7d897eSshirley her struct sdhci_pci_slot *slot = sdhci_priv(host); 5277b7d897eSshirley her struct sdhci_pci_chip *chip = slot->chip; 52869d91ed1SErnest Zhang(WH) 52969d91ed1SErnest Zhang(WH) host->mmc->actual_clock = 0; 53069d91ed1SErnest Zhang(WH) 53169d91ed1SErnest Zhang(WH) sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 53269d91ed1SErnest Zhang(WH) 53369d91ed1SErnest Zhang(WH) if (clock == 0) 53469d91ed1SErnest Zhang(WH) return; 53569d91ed1SErnest Zhang(WH) 5367b7d897eSshirley her if ((host->timing == MMC_TIMING_UHS_SDR104) && (clock == 200000000)) { 5377b7d897eSshirley her pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); 5387b7d897eSshirley her 5397b7d897eSshirley her scratch &= 0x7f; 5407b7d897eSshirley her pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 5417b7d897eSshirley her 5427b7d897eSshirley her pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32); 5437b7d897eSshirley her 5447b7d897eSshirley her if ((scratch_32 & 0xFFFF0000) != 0x2c280000) 5457b7d897eSshirley her o2_pci_set_baseclk(chip, 0x2c280000); 5467b7d897eSshirley her 5477b7d897eSshirley her pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); 5487b7d897eSshirley her 5497b7d897eSshirley her scratch |= 0x80; 5507b7d897eSshirley her pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 5517b7d897eSshirley her } 5527b7d897eSshirley her 55369d91ed1SErnest Zhang(WH) clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 55469d91ed1SErnest Zhang(WH) sdhci_o2_enable_clk(host, clk); 55569d91ed1SErnest Zhang(WH) } 55669d91ed1SErnest Zhang(WH) 557580b946eSZou Wei static int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot) 55801acf691SAdam Lee { 55901acf691SAdam Lee struct sdhci_pci_chip *chip; 56001acf691SAdam Lee struct sdhci_host *host; 5617d440617SShirley Her (SC) struct o2_host *o2_host = sdhci_pci_priv(slot); 562de23f0b7SRaul E Rangel u32 reg, caps; 56357322d54Sernest.zhang int ret; 56401acf691SAdam Lee 56501acf691SAdam Lee chip = slot->chip; 56601acf691SAdam Lee host = slot->host; 567de23f0b7SRaul E Rangel 5687d440617SShirley Her (SC) o2_host->dll_adjust_count = 0; 569de23f0b7SRaul E Rangel caps = sdhci_readl(host, SDHCI_CAPABILITIES); 570de23f0b7SRaul E Rangel 571de23f0b7SRaul E Rangel /* 572de23f0b7SRaul E Rangel * mmc_select_bus_width() will test the bus to determine the actual bus 573de23f0b7SRaul E Rangel * width. 574de23f0b7SRaul E Rangel */ 575de23f0b7SRaul E Rangel if (caps & SDHCI_CAN_DO_8BIT) 576de23f0b7SRaul E Rangel host->mmc->caps |= MMC_CAP_8_BIT_DATA; 577de23f0b7SRaul E Rangel 57801acf691SAdam Lee switch (chip->pdev->device) { 57901acf691SAdam Lee case PCI_DEVICE_ID_O2_SDS0: 58001acf691SAdam Lee case PCI_DEVICE_ID_O2_SEABIRD0: 58101acf691SAdam Lee case PCI_DEVICE_ID_O2_SEABIRD1: 58201acf691SAdam Lee case PCI_DEVICE_ID_O2_SDS1: 58301acf691SAdam Lee case PCI_DEVICE_ID_O2_FUJIN2: 58401acf691SAdam Lee reg = sdhci_readl(host, O2_SD_VENDOR_SETTING); 58501acf691SAdam Lee if (reg & 0x1) 58601acf691SAdam Lee host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12; 58701acf691SAdam Lee 58802a3c0bdSernest.zhang sdhci_pci_o2_enable_msi(chip, host); 58902a3c0bdSernest.zhang 59057322d54Sernest.zhang if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) { 59157322d54Sernest.zhang ret = pci_read_config_dword(chip->pdev, 59257322d54Sernest.zhang O2_SD_MISC_SETTING, ®); 59357322d54Sernest.zhang if (ret) 59457322d54Sernest.zhang return -EIO; 59557322d54Sernest.zhang if (reg & (1 << 4)) { 59657322d54Sernest.zhang pr_info("%s: emmc 1.8v flag is set, force 1.8v signaling voltage\n", 59757322d54Sernest.zhang mmc_hostname(host->mmc)); 59857322d54Sernest.zhang host->flags &= ~SDHCI_SIGNALING_330; 59957322d54Sernest.zhang host->flags |= SDHCI_SIGNALING_180; 60057322d54Sernest.zhang host->mmc->caps2 |= MMC_CAP2_NO_SD; 60157322d54Sernest.zhang host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 60269d91ed1SErnest Zhang(WH) pci_write_config_dword(chip->pdev, 60369d91ed1SErnest Zhang(WH) O2_SD_DETECT_SETTING, 3); 60457322d54Sernest.zhang } 60569d91ed1SErnest Zhang(WH) 60669d91ed1SErnest Zhang(WH) slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd; 60757322d54Sernest.zhang } 60857322d54Sernest.zhang 609cdd2b769Sshirley her if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD1) { 610cdd2b769Sshirley her slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd; 611cdd2b769Sshirley her host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 612cdd2b769Sshirley her host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 613cdd2b769Sshirley her } 614cdd2b769Sshirley her 6150086fc21Sernest.zhang host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning; 6160086fc21Sernest.zhang 61701acf691SAdam Lee if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2) 61801acf691SAdam Lee break; 61901acf691SAdam Lee /* set dll watch dog timer */ 62001acf691SAdam Lee reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2); 62101acf691SAdam Lee reg |= (1 << 12); 62201acf691SAdam Lee sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2); 62301acf691SAdam Lee 62401acf691SAdam Lee break; 62501acf691SAdam Lee default: 62601acf691SAdam Lee break; 62701acf691SAdam Lee } 62801acf691SAdam Lee 62901acf691SAdam Lee return 0; 63001acf691SAdam Lee } 63101acf691SAdam Lee 632580b946eSZou Wei static int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip) 63301acf691SAdam Lee { 63401acf691SAdam Lee int ret; 63501acf691SAdam Lee u8 scratch; 63601acf691SAdam Lee u32 scratch_32; 63701acf691SAdam Lee 63801acf691SAdam Lee switch (chip->pdev->device) { 63901acf691SAdam Lee case PCI_DEVICE_ID_O2_8220: 64001acf691SAdam Lee case PCI_DEVICE_ID_O2_8221: 64101acf691SAdam Lee case PCI_DEVICE_ID_O2_8320: 64201acf691SAdam Lee case PCI_DEVICE_ID_O2_8321: 64301acf691SAdam Lee /* This extra setup is required due to broken ADMA. */ 64401acf691SAdam Lee ret = pci_read_config_byte(chip->pdev, 64501acf691SAdam Lee O2_SD_LOCK_WP, &scratch); 64601acf691SAdam Lee if (ret) 64701acf691SAdam Lee return ret; 64801acf691SAdam Lee scratch &= 0x7f; 64901acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 65001acf691SAdam Lee 65101acf691SAdam Lee /* Set Multi 3 to VCC3V# */ 65201acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08); 65301acf691SAdam Lee 65401acf691SAdam Lee /* Disable CLK_REQ# support after media DET */ 65501acf691SAdam Lee ret = pci_read_config_byte(chip->pdev, 65601acf691SAdam Lee O2_SD_CLKREQ, &scratch); 65701acf691SAdam Lee if (ret) 65801acf691SAdam Lee return ret; 65901acf691SAdam Lee scratch |= 0x20; 66001acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch); 66101acf691SAdam Lee 66201acf691SAdam Lee /* Choose capabilities, enable SDMA. We have to write 0x01 66301acf691SAdam Lee * to the capabilities register first to unlock it. 66401acf691SAdam Lee */ 66501acf691SAdam Lee ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch); 66601acf691SAdam Lee if (ret) 66701acf691SAdam Lee return ret; 66801acf691SAdam Lee scratch |= 0x01; 66901acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch); 67001acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73); 67101acf691SAdam Lee 67201acf691SAdam Lee /* Disable ADMA1/2 */ 67301acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39); 67401acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08); 67501acf691SAdam Lee 67601acf691SAdam Lee /* Disable the infinite transfer mode */ 67701acf691SAdam Lee ret = pci_read_config_byte(chip->pdev, 67801acf691SAdam Lee O2_SD_INF_MOD, &scratch); 67901acf691SAdam Lee if (ret) 68001acf691SAdam Lee return ret; 68101acf691SAdam Lee scratch |= 0x08; 68201acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch); 68301acf691SAdam Lee 68401acf691SAdam Lee /* Lock WP */ 68501acf691SAdam Lee ret = pci_read_config_byte(chip->pdev, 68601acf691SAdam Lee O2_SD_LOCK_WP, &scratch); 68701acf691SAdam Lee if (ret) 68801acf691SAdam Lee return ret; 68901acf691SAdam Lee scratch |= 0x80; 69001acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 69101acf691SAdam Lee break; 69201acf691SAdam Lee case PCI_DEVICE_ID_O2_SDS0: 69301acf691SAdam Lee case PCI_DEVICE_ID_O2_SDS1: 69401acf691SAdam Lee case PCI_DEVICE_ID_O2_FUJIN2: 69501acf691SAdam Lee /* UnLock WP */ 69601acf691SAdam Lee ret = pci_read_config_byte(chip->pdev, 69701acf691SAdam Lee O2_SD_LOCK_WP, &scratch); 69801acf691SAdam Lee if (ret) 69901acf691SAdam Lee return ret; 70001acf691SAdam Lee 70101acf691SAdam Lee scratch &= 0x7f; 70201acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 70301acf691SAdam Lee 704706adf6bSPeter Guo /* DevId=8520 subId= 0x11 or 0x12 Type Chip support */ 705706adf6bSPeter Guo if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) { 706706adf6bSPeter Guo ret = pci_read_config_dword(chip->pdev, 707706adf6bSPeter Guo O2_SD_FUNC_REG0, 708706adf6bSPeter Guo &scratch_32); 709706adf6bSPeter Guo scratch_32 = ((scratch_32 & 0xFF000000) >> 24); 710706adf6bSPeter Guo 711706adf6bSPeter Guo /* Check Whether subId is 0x11 or 0x12 */ 712706adf6bSPeter Guo if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) { 7133665ff03Sernest.zhang scratch_32 = 0x25100000; 714706adf6bSPeter Guo 715706adf6bSPeter Guo o2_pci_set_baseclk(chip, scratch_32); 716706adf6bSPeter Guo ret = pci_read_config_dword(chip->pdev, 717706adf6bSPeter Guo O2_SD_FUNC_REG4, 718706adf6bSPeter Guo &scratch_32); 719706adf6bSPeter Guo 720706adf6bSPeter Guo /* Enable Base Clk setting change */ 721706adf6bSPeter Guo scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET; 722706adf6bSPeter Guo pci_write_config_dword(chip->pdev, 723706adf6bSPeter Guo O2_SD_FUNC_REG4, 724706adf6bSPeter Guo scratch_32); 725706adf6bSPeter Guo 726706adf6bSPeter Guo /* Set Tuning Window to 4 */ 727706adf6bSPeter Guo pci_write_config_byte(chip->pdev, 728706adf6bSPeter Guo O2_SD_TUNING_CTRL, 0x44); 729706adf6bSPeter Guo 730706adf6bSPeter Guo break; 731706adf6bSPeter Guo } 732706adf6bSPeter Guo } 733706adf6bSPeter Guo 734706adf6bSPeter Guo /* Enable 8520 led function */ 735706adf6bSPeter Guo o2_pci_led_enable(chip); 736706adf6bSPeter Guo 73701acf691SAdam Lee /* Set timeout CLK */ 73801acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, 73901acf691SAdam Lee O2_SD_CLK_SETTING, &scratch_32); 74001acf691SAdam Lee if (ret) 74101acf691SAdam Lee return ret; 74201acf691SAdam Lee 74301acf691SAdam Lee scratch_32 &= ~(0xFF00); 74401acf691SAdam Lee scratch_32 |= 0x07E0C800; 74501acf691SAdam Lee pci_write_config_dword(chip->pdev, 74601acf691SAdam Lee O2_SD_CLK_SETTING, scratch_32); 74701acf691SAdam Lee 74801acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, 74901acf691SAdam Lee O2_SD_CLKREQ, &scratch_32); 75001acf691SAdam Lee if (ret) 75101acf691SAdam Lee return ret; 75201acf691SAdam Lee scratch_32 |= 0x3; 75301acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32); 75401acf691SAdam Lee 75501acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, 75601acf691SAdam Lee O2_SD_PLL_SETTING, &scratch_32); 75701acf691SAdam Lee if (ret) 75801acf691SAdam Lee return ret; 75901acf691SAdam Lee 76001acf691SAdam Lee scratch_32 &= ~(0x1F3F070E); 76101acf691SAdam Lee scratch_32 |= 0x18270106; 76201acf691SAdam Lee pci_write_config_dword(chip->pdev, 76301acf691SAdam Lee O2_SD_PLL_SETTING, scratch_32); 76401acf691SAdam Lee 76501acf691SAdam Lee /* Disable UHS1 funciton */ 76601acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, 76701acf691SAdam Lee O2_SD_CAP_REG2, &scratch_32); 76801acf691SAdam Lee if (ret) 76901acf691SAdam Lee return ret; 77001acf691SAdam Lee scratch_32 &= ~(0xE0); 77101acf691SAdam Lee pci_write_config_dword(chip->pdev, 77201acf691SAdam Lee O2_SD_CAP_REG2, scratch_32); 77301acf691SAdam Lee 77401acf691SAdam Lee if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) 77501acf691SAdam Lee sdhci_pci_o2_fujin2_pci_init(chip); 77601acf691SAdam Lee 77701acf691SAdam Lee /* Lock WP */ 77801acf691SAdam Lee ret = pci_read_config_byte(chip->pdev, 77901acf691SAdam Lee O2_SD_LOCK_WP, &scratch); 78001acf691SAdam Lee if (ret) 78101acf691SAdam Lee return ret; 78201acf691SAdam Lee scratch |= 0x80; 78301acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 78401acf691SAdam Lee break; 78501acf691SAdam Lee case PCI_DEVICE_ID_O2_SEABIRD0: 78601acf691SAdam Lee case PCI_DEVICE_ID_O2_SEABIRD1: 78701acf691SAdam Lee /* UnLock WP */ 78801acf691SAdam Lee ret = pci_read_config_byte(chip->pdev, 78901acf691SAdam Lee O2_SD_LOCK_WP, &scratch); 79001acf691SAdam Lee if (ret) 79101acf691SAdam Lee return ret; 79201acf691SAdam Lee 79301acf691SAdam Lee scratch &= 0x7f; 79401acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 79501acf691SAdam Lee 79601acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, 797706adf6bSPeter Guo O2_SD_PLL_SETTING, &scratch_32); 79801acf691SAdam Lee 79901acf691SAdam Lee if ((scratch_32 & 0xff000000) == 0x01000000) { 80001acf691SAdam Lee scratch_32 &= 0x0000FFFF; 80101acf691SAdam Lee scratch_32 |= 0x1F340000; 80201acf691SAdam Lee 80301acf691SAdam Lee pci_write_config_dword(chip->pdev, 80401acf691SAdam Lee O2_SD_PLL_SETTING, scratch_32); 80501acf691SAdam Lee } else { 80601acf691SAdam Lee scratch_32 &= 0x0000FFFF; 8073665ff03Sernest.zhang scratch_32 |= 0x25100000; 80801acf691SAdam Lee 80901acf691SAdam Lee pci_write_config_dword(chip->pdev, 81001acf691SAdam Lee O2_SD_PLL_SETTING, scratch_32); 81101acf691SAdam Lee 81201acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, 81301acf691SAdam Lee O2_SD_FUNC_REG4, 81401acf691SAdam Lee &scratch_32); 81501acf691SAdam Lee scratch_32 |= (1 << 22); 81601acf691SAdam Lee pci_write_config_dword(chip->pdev, 81701acf691SAdam Lee O2_SD_FUNC_REG4, scratch_32); 81801acf691SAdam Lee } 81901acf691SAdam Lee 820706adf6bSPeter Guo /* Set Tuning Windows to 5 */ 821706adf6bSPeter Guo pci_write_config_byte(chip->pdev, 822706adf6bSPeter Guo O2_SD_TUNING_CTRL, 0x55); 82301acf691SAdam Lee /* Lock WP */ 82401acf691SAdam Lee ret = pci_read_config_byte(chip->pdev, 82501acf691SAdam Lee O2_SD_LOCK_WP, &scratch); 82601acf691SAdam Lee if (ret) 82701acf691SAdam Lee return ret; 82801acf691SAdam Lee scratch |= 0x80; 82901acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 83001acf691SAdam Lee break; 83101acf691SAdam Lee } 83201acf691SAdam Lee 83301acf691SAdam Lee return 0; 83401acf691SAdam Lee } 83501acf691SAdam Lee 836b7813f0fSAdrian Hunter #ifdef CONFIG_PM_SLEEP 837580b946eSZou Wei static int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip) 83801acf691SAdam Lee { 83901acf691SAdam Lee sdhci_pci_o2_probe(chip); 84030cf2803SAdrian Hunter return sdhci_pci_resume_host(chip); 84101acf691SAdam Lee } 842b7813f0fSAdrian Hunter #endif 843328be8beSErnest Zhang(WH) 84469d91ed1SErnest Zhang(WH) static const struct sdhci_ops sdhci_pci_o2_ops = { 84569d91ed1SErnest Zhang(WH) .set_clock = sdhci_pci_o2_set_clock, 84669d91ed1SErnest Zhang(WH) .enable_dma = sdhci_pci_enable_dma, 84769d91ed1SErnest Zhang(WH) .set_bus_width = sdhci_set_bus_width, 84869d91ed1SErnest Zhang(WH) .reset = sdhci_reset, 84969d91ed1SErnest Zhang(WH) .set_uhs_signaling = sdhci_set_uhs_signaling, 85069d91ed1SErnest Zhang(WH) }; 85169d91ed1SErnest Zhang(WH) 852328be8beSErnest Zhang(WH) const struct sdhci_pci_fixes sdhci_o2 = { 853328be8beSErnest Zhang(WH) .probe = sdhci_pci_o2_probe, 854328be8beSErnest Zhang(WH) .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 85549baa01cSDaniel Drake .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 856328be8beSErnest Zhang(WH) .probe_slot = sdhci_pci_o2_probe_slot, 857328be8beSErnest Zhang(WH) #ifdef CONFIG_PM_SLEEP 858328be8beSErnest Zhang(WH) .resume = sdhci_pci_o2_resume, 859328be8beSErnest Zhang(WH) #endif 86069d91ed1SErnest Zhang(WH) .ops = &sdhci_pci_o2_ops, 8617d440617SShirley Her (SC) .priv_size = sizeof(struct o2_host), 862328be8beSErnest Zhang(WH) }; 863