1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 2 * 3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 * 10 * Thanks to the following companies for their support: 11 * 12 * - JMicron (hardware and technical support) 13 */ 14 15 #include <linux/string.h> 16 #include <linux/delay.h> 17 #include <linux/highmem.h> 18 #include <linux/module.h> 19 #include <linux/pci.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/slab.h> 22 #include <linux/device.h> 23 #include <linux/mmc/host.h> 24 #include <linux/mmc/mmc.h> 25 #include <linux/scatterlist.h> 26 #include <linux/io.h> 27 #include <linux/gpio.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/mmc/slot-gpio.h> 30 #include <linux/mmc/sdhci-pci-data.h> 31 #include <linux/acpi.h> 32 33 #include "cqhci.h" 34 35 #include "sdhci.h" 36 #include "sdhci-pci.h" 37 38 static void sdhci_pci_hw_reset(struct sdhci_host *host); 39 40 #ifdef CONFIG_PM_SLEEP 41 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip) 42 { 43 mmc_pm_flag_t pm_flags = 0; 44 int i; 45 46 for (i = 0; i < chip->num_slots; i++) { 47 struct sdhci_pci_slot *slot = chip->slots[i]; 48 49 if (slot) 50 pm_flags |= slot->host->mmc->pm_flags; 51 } 52 53 return device_set_wakeup_enable(&chip->pdev->dev, 54 (pm_flags & MMC_PM_KEEP_POWER) && 55 (pm_flags & MMC_PM_WAKE_SDIO_IRQ)); 56 } 57 58 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 59 { 60 int i, ret; 61 62 sdhci_pci_init_wakeup(chip); 63 64 for (i = 0; i < chip->num_slots; i++) { 65 struct sdhci_pci_slot *slot = chip->slots[i]; 66 struct sdhci_host *host; 67 68 if (!slot) 69 continue; 70 71 host = slot->host; 72 73 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 74 mmc_retune_needed(host->mmc); 75 76 ret = sdhci_suspend_host(host); 77 if (ret) 78 goto err_pci_suspend; 79 } 80 81 return 0; 82 83 err_pci_suspend: 84 while (--i >= 0) 85 sdhci_resume_host(chip->slots[i]->host); 86 return ret; 87 } 88 89 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip) 90 { 91 struct sdhci_pci_slot *slot; 92 int i, ret; 93 94 for (i = 0; i < chip->num_slots; i++) { 95 slot = chip->slots[i]; 96 if (!slot) 97 continue; 98 99 ret = sdhci_resume_host(slot->host); 100 if (ret) 101 return ret; 102 } 103 104 return 0; 105 } 106 107 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip) 108 { 109 int ret; 110 111 ret = cqhci_suspend(chip->slots[0]->host->mmc); 112 if (ret) 113 return ret; 114 115 return sdhci_pci_suspend_host(chip); 116 } 117 118 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip) 119 { 120 int ret; 121 122 ret = sdhci_pci_resume_host(chip); 123 if (ret) 124 return ret; 125 126 return cqhci_resume(chip->slots[0]->host->mmc); 127 } 128 #endif 129 130 #ifdef CONFIG_PM 131 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip) 132 { 133 struct sdhci_pci_slot *slot; 134 struct sdhci_host *host; 135 int i, ret; 136 137 for (i = 0; i < chip->num_slots; i++) { 138 slot = chip->slots[i]; 139 if (!slot) 140 continue; 141 142 host = slot->host; 143 144 ret = sdhci_runtime_suspend_host(host); 145 if (ret) 146 goto err_pci_runtime_suspend; 147 148 if (chip->rpm_retune && 149 host->tuning_mode != SDHCI_TUNING_MODE_3) 150 mmc_retune_needed(host->mmc); 151 } 152 153 return 0; 154 155 err_pci_runtime_suspend: 156 while (--i >= 0) 157 sdhci_runtime_resume_host(chip->slots[i]->host); 158 return ret; 159 } 160 161 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip) 162 { 163 struct sdhci_pci_slot *slot; 164 int i, ret; 165 166 for (i = 0; i < chip->num_slots; i++) { 167 slot = chip->slots[i]; 168 if (!slot) 169 continue; 170 171 ret = sdhci_runtime_resume_host(slot->host); 172 if (ret) 173 return ret; 174 } 175 176 return 0; 177 } 178 179 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip) 180 { 181 int ret; 182 183 ret = cqhci_suspend(chip->slots[0]->host->mmc); 184 if (ret) 185 return ret; 186 187 return sdhci_pci_runtime_suspend_host(chip); 188 } 189 190 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip) 191 { 192 int ret; 193 194 ret = sdhci_pci_runtime_resume_host(chip); 195 if (ret) 196 return ret; 197 198 return cqhci_resume(chip->slots[0]->host->mmc); 199 } 200 #endif 201 202 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask) 203 { 204 int cmd_error = 0; 205 int data_error = 0; 206 207 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 208 return intmask; 209 210 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 211 212 return 0; 213 } 214 215 static void sdhci_pci_dumpregs(struct mmc_host *mmc) 216 { 217 sdhci_dumpregs(mmc_priv(mmc)); 218 } 219 220 /*****************************************************************************\ 221 * * 222 * Hardware specific quirk handling * 223 * * 224 \*****************************************************************************/ 225 226 static int ricoh_probe(struct sdhci_pci_chip *chip) 227 { 228 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 229 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 230 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 231 return 0; 232 } 233 234 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 235 { 236 slot->host->caps = 237 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 238 & SDHCI_TIMEOUT_CLK_MASK) | 239 240 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 241 & SDHCI_CLOCK_BASE_MASK) | 242 243 SDHCI_TIMEOUT_CLK_UNIT | 244 SDHCI_CAN_VDD_330 | 245 SDHCI_CAN_DO_HISPD | 246 SDHCI_CAN_DO_SDMA; 247 return 0; 248 } 249 250 #ifdef CONFIG_PM_SLEEP 251 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 252 { 253 /* Apply a delay to allow controller to settle */ 254 /* Otherwise it becomes confused if card state changed 255 during suspend */ 256 msleep(500); 257 return sdhci_pci_resume_host(chip); 258 } 259 #endif 260 261 static const struct sdhci_pci_fixes sdhci_ricoh = { 262 .probe = ricoh_probe, 263 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 264 SDHCI_QUIRK_FORCE_DMA | 265 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 266 }; 267 268 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 269 .probe_slot = ricoh_mmc_probe_slot, 270 #ifdef CONFIG_PM_SLEEP 271 .resume = ricoh_mmc_resume, 272 #endif 273 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 274 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 275 SDHCI_QUIRK_NO_CARD_NO_RESET | 276 SDHCI_QUIRK_MISSING_CAPS 277 }; 278 279 static const struct sdhci_pci_fixes sdhci_ene_712 = { 280 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 281 SDHCI_QUIRK_BROKEN_DMA, 282 }; 283 284 static const struct sdhci_pci_fixes sdhci_ene_714 = { 285 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 286 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 287 SDHCI_QUIRK_BROKEN_DMA, 288 }; 289 290 static const struct sdhci_pci_fixes sdhci_cafe = { 291 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 292 SDHCI_QUIRK_NO_BUSY_IRQ | 293 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 294 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 295 }; 296 297 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 298 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 299 }; 300 301 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 302 { 303 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 304 return 0; 305 } 306 307 /* 308 * ADMA operation is disabled for Moorestown platform due to 309 * hardware bugs. 310 */ 311 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 312 { 313 /* 314 * slots number is fixed here for MRST as SDIO3/5 are never used and 315 * have hardware bugs. 316 */ 317 chip->num_slots = 1; 318 return 0; 319 } 320 321 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 322 { 323 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 324 return 0; 325 } 326 327 #ifdef CONFIG_PM 328 329 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 330 { 331 struct sdhci_pci_slot *slot = dev_id; 332 struct sdhci_host *host = slot->host; 333 334 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 335 return IRQ_HANDLED; 336 } 337 338 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 339 { 340 int err, irq, gpio = slot->cd_gpio; 341 342 slot->cd_gpio = -EINVAL; 343 slot->cd_irq = -EINVAL; 344 345 if (!gpio_is_valid(gpio)) 346 return; 347 348 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 349 if (err < 0) 350 goto out; 351 352 err = gpio_direction_input(gpio); 353 if (err < 0) 354 goto out_free; 355 356 irq = gpio_to_irq(gpio); 357 if (irq < 0) 358 goto out_free; 359 360 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 361 IRQF_TRIGGER_FALLING, "sd_cd", slot); 362 if (err) 363 goto out_free; 364 365 slot->cd_gpio = gpio; 366 slot->cd_irq = irq; 367 368 return; 369 370 out_free: 371 devm_gpio_free(&slot->chip->pdev->dev, gpio); 372 out: 373 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 374 } 375 376 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 377 { 378 if (slot->cd_irq >= 0) 379 free_irq(slot->cd_irq, slot); 380 } 381 382 #else 383 384 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 385 { 386 } 387 388 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 389 { 390 } 391 392 #endif 393 394 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 395 { 396 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 397 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC; 398 return 0; 399 } 400 401 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 402 { 403 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 404 return 0; 405 } 406 407 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 408 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 409 .probe_slot = mrst_hc_probe_slot, 410 }; 411 412 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 413 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 414 .probe = mrst_hc_probe, 415 }; 416 417 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 418 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 419 .allow_runtime_pm = true, 420 .own_cd_for_runtime_pm = true, 421 }; 422 423 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 424 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 425 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 426 .allow_runtime_pm = true, 427 .probe_slot = mfd_sdio_probe_slot, 428 }; 429 430 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 431 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 432 .allow_runtime_pm = true, 433 .probe_slot = mfd_emmc_probe_slot, 434 }; 435 436 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 437 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 438 .probe_slot = pch_hc_probe_slot, 439 }; 440 441 enum { 442 INTEL_DSM_FNS = 0, 443 INTEL_DSM_V18_SWITCH = 3, 444 INTEL_DSM_DRV_STRENGTH = 9, 445 INTEL_DSM_D3_RETUNE = 10, 446 }; 447 448 struct intel_host { 449 u32 dsm_fns; 450 int drv_strength; 451 bool d3_retune; 452 }; 453 454 static const guid_t intel_dsm_guid = 455 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F, 456 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61); 457 458 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 459 unsigned int fn, u32 *result) 460 { 461 union acpi_object *obj; 462 int err = 0; 463 size_t len; 464 465 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL); 466 if (!obj) 467 return -EOPNOTSUPP; 468 469 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { 470 err = -EINVAL; 471 goto out; 472 } 473 474 len = min_t(size_t, obj->buffer.length, 4); 475 476 *result = 0; 477 memcpy(result, obj->buffer.pointer, len); 478 out: 479 ACPI_FREE(obj); 480 481 return err; 482 } 483 484 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 485 unsigned int fn, u32 *result) 486 { 487 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 488 return -EOPNOTSUPP; 489 490 return __intel_dsm(intel_host, dev, fn, result); 491 } 492 493 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 494 struct mmc_host *mmc) 495 { 496 int err; 497 u32 val; 498 499 intel_host->d3_retune = true; 500 501 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 502 if (err) { 503 pr_debug("%s: DSM not supported, error %d\n", 504 mmc_hostname(mmc), err); 505 return; 506 } 507 508 pr_debug("%s: DSM function mask %#x\n", 509 mmc_hostname(mmc), intel_host->dsm_fns); 510 511 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 512 intel_host->drv_strength = err ? 0 : val; 513 514 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 515 intel_host->d3_retune = err ? true : !!val; 516 } 517 518 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 519 { 520 u8 reg; 521 522 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 523 reg |= 0x10; 524 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 525 /* For eMMC, minimum is 1us but give it 9us for good measure */ 526 udelay(9); 527 reg &= ~0x10; 528 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 529 /* For eMMC, minimum is 200us but give it 300us for good measure */ 530 usleep_range(300, 1000); 531 } 532 533 static int intel_select_drive_strength(struct mmc_card *card, 534 unsigned int max_dtr, int host_drv, 535 int card_drv, int *drv_type) 536 { 537 struct sdhci_host *host = mmc_priv(card->host); 538 struct sdhci_pci_slot *slot = sdhci_priv(host); 539 struct intel_host *intel_host = sdhci_pci_priv(slot); 540 541 return intel_host->drv_strength; 542 } 543 544 static int bxt_get_cd(struct mmc_host *mmc) 545 { 546 int gpio_cd = mmc_gpio_get_cd(mmc); 547 struct sdhci_host *host = mmc_priv(mmc); 548 unsigned long flags; 549 int ret = 0; 550 551 if (!gpio_cd) 552 return 0; 553 554 spin_lock_irqsave(&host->lock, flags); 555 556 if (host->flags & SDHCI_DEVICE_DEAD) 557 goto out; 558 559 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 560 out: 561 spin_unlock_irqrestore(&host->lock, flags); 562 563 return ret; 564 } 565 566 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 567 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 568 569 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 570 unsigned short vdd) 571 { 572 int cntr; 573 u8 reg; 574 575 sdhci_set_power(host, mode, vdd); 576 577 if (mode == MMC_POWER_OFF) 578 return; 579 580 /* 581 * Bus power might not enable after D3 -> D0 transition due to the 582 * present state not yet having propagated. Retry for up to 2ms. 583 */ 584 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 585 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 586 if (reg & SDHCI_POWER_ON) 587 break; 588 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 589 reg |= SDHCI_POWER_ON; 590 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 591 } 592 } 593 594 #define INTEL_HS400_ES_REG 0x78 595 #define INTEL_HS400_ES_BIT BIT(0) 596 597 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc, 598 struct mmc_ios *ios) 599 { 600 struct sdhci_host *host = mmc_priv(mmc); 601 u32 val; 602 603 val = sdhci_readl(host, INTEL_HS400_ES_REG); 604 if (ios->enhanced_strobe) 605 val |= INTEL_HS400_ES_BIT; 606 else 607 val &= ~INTEL_HS400_ES_BIT; 608 sdhci_writel(host, val, INTEL_HS400_ES_REG); 609 } 610 611 static void sdhci_intel_voltage_switch(struct sdhci_host *host) 612 { 613 struct sdhci_pci_slot *slot = sdhci_priv(host); 614 struct intel_host *intel_host = sdhci_pci_priv(slot); 615 struct device *dev = &slot->chip->pdev->dev; 616 u32 result = 0; 617 int err; 618 619 err = intel_dsm(intel_host, dev, INTEL_DSM_V18_SWITCH, &result); 620 pr_debug("%s: %s DSM error %d result %u\n", 621 mmc_hostname(host->mmc), __func__, err, result); 622 } 623 624 static const struct sdhci_ops sdhci_intel_byt_ops = { 625 .set_clock = sdhci_set_clock, 626 .set_power = sdhci_intel_set_power, 627 .enable_dma = sdhci_pci_enable_dma, 628 .set_bus_width = sdhci_set_bus_width, 629 .reset = sdhci_reset, 630 .set_uhs_signaling = sdhci_set_uhs_signaling, 631 .hw_reset = sdhci_pci_hw_reset, 632 .voltage_switch = sdhci_intel_voltage_switch, 633 }; 634 635 static const struct sdhci_ops sdhci_intel_glk_ops = { 636 .set_clock = sdhci_set_clock, 637 .set_power = sdhci_intel_set_power, 638 .enable_dma = sdhci_pci_enable_dma, 639 .set_bus_width = sdhci_set_bus_width, 640 .reset = sdhci_reset, 641 .set_uhs_signaling = sdhci_set_uhs_signaling, 642 .hw_reset = sdhci_pci_hw_reset, 643 .voltage_switch = sdhci_intel_voltage_switch, 644 .irq = sdhci_cqhci_irq, 645 }; 646 647 static void byt_read_dsm(struct sdhci_pci_slot *slot) 648 { 649 struct intel_host *intel_host = sdhci_pci_priv(slot); 650 struct device *dev = &slot->chip->pdev->dev; 651 struct mmc_host *mmc = slot->host->mmc; 652 653 intel_dsm_init(intel_host, dev, mmc); 654 slot->chip->rpm_retune = intel_host->d3_retune; 655 } 656 657 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode) 658 { 659 int err = sdhci_execute_tuning(mmc, opcode); 660 struct sdhci_host *host = mmc_priv(mmc); 661 662 if (err) 663 return err; 664 665 /* 666 * Tuning can leave the IP in an active state (Buffer Read Enable bit 667 * set) which prevents the entry to low power states (i.e. S0i3). Data 668 * reset will clear it. 669 */ 670 sdhci_reset(host, SDHCI_RESET_DATA); 671 672 return 0; 673 } 674 675 static void byt_probe_slot(struct sdhci_pci_slot *slot) 676 { 677 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 678 679 byt_read_dsm(slot); 680 681 ops->execute_tuning = intel_execute_tuning; 682 } 683 684 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 685 { 686 byt_probe_slot(slot); 687 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 688 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 689 MMC_CAP_CMD_DURING_TFR | 690 MMC_CAP_WAIT_WHILE_BUSY; 691 slot->hw_reset = sdhci_pci_int_hw_reset; 692 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 693 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 694 slot->host->mmc_host_ops.select_drive_strength = 695 intel_select_drive_strength; 696 return 0; 697 } 698 699 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot) 700 { 701 int ret = byt_emmc_probe_slot(slot); 702 703 slot->host->mmc->caps2 |= MMC_CAP2_CQE; 704 705 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) { 706 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES, 707 slot->host->mmc_host_ops.hs400_enhanced_strobe = 708 intel_hs400_enhanced_strobe; 709 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; 710 } 711 712 return ret; 713 } 714 715 static void glk_cqe_enable(struct mmc_host *mmc) 716 { 717 struct sdhci_host *host = mmc_priv(mmc); 718 u32 reg; 719 720 /* 721 * CQE gets stuck if it sees Buffer Read Enable bit set, which can be 722 * the case after tuning, so ensure the buffer is drained. 723 */ 724 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 725 while (reg & SDHCI_DATA_AVAILABLE) { 726 sdhci_readl(host, SDHCI_BUFFER); 727 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 728 } 729 730 sdhci_cqe_enable(mmc); 731 } 732 733 static const struct cqhci_host_ops glk_cqhci_ops = { 734 .enable = glk_cqe_enable, 735 .disable = sdhci_cqe_disable, 736 .dumpregs = sdhci_pci_dumpregs, 737 }; 738 739 static int glk_emmc_add_host(struct sdhci_pci_slot *slot) 740 { 741 struct device *dev = &slot->chip->pdev->dev; 742 struct sdhci_host *host = slot->host; 743 struct cqhci_host *cq_host; 744 bool dma64; 745 int ret; 746 747 ret = sdhci_setup_host(host); 748 if (ret) 749 return ret; 750 751 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); 752 if (!cq_host) { 753 ret = -ENOMEM; 754 goto cleanup; 755 } 756 757 cq_host->mmio = host->ioaddr + 0x200; 758 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 759 cq_host->ops = &glk_cqhci_ops; 760 761 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 762 if (dma64) 763 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 764 765 ret = cqhci_init(cq_host, host->mmc, dma64); 766 if (ret) 767 goto cleanup; 768 769 ret = __sdhci_add_host(host); 770 if (ret) 771 goto cleanup; 772 773 return 0; 774 775 cleanup: 776 sdhci_cleanup_host(host); 777 return ret; 778 } 779 780 #ifdef CONFIG_ACPI 781 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 782 { 783 acpi_status status; 784 unsigned long long max_freq; 785 786 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 787 "MXFQ", NULL, &max_freq); 788 if (ACPI_FAILURE(status)) { 789 dev_err(&slot->chip->pdev->dev, 790 "MXFQ not found in acpi table\n"); 791 return -EINVAL; 792 } 793 794 slot->host->mmc->f_max = max_freq * 1000000; 795 796 return 0; 797 } 798 #else 799 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 800 { 801 return 0; 802 } 803 #endif 804 805 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 806 { 807 int err; 808 809 byt_probe_slot(slot); 810 811 err = ni_set_max_freq(slot); 812 if (err) 813 return err; 814 815 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 816 MMC_CAP_WAIT_WHILE_BUSY; 817 return 0; 818 } 819 820 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 821 { 822 byt_probe_slot(slot); 823 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 824 MMC_CAP_WAIT_WHILE_BUSY; 825 return 0; 826 } 827 828 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 829 { 830 byt_probe_slot(slot); 831 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | 832 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE; 833 slot->cd_idx = 0; 834 slot->cd_override_level = true; 835 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 836 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 837 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 838 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) 839 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 840 841 return 0; 842 } 843 844 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 845 .allow_runtime_pm = true, 846 .probe_slot = byt_emmc_probe_slot, 847 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 848 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 849 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 850 SDHCI_QUIRK2_STOP_WITH_TC, 851 .ops = &sdhci_intel_byt_ops, 852 .priv_size = sizeof(struct intel_host), 853 }; 854 855 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = { 856 .allow_runtime_pm = true, 857 .probe_slot = glk_emmc_probe_slot, 858 .add_host = glk_emmc_add_host, 859 #ifdef CONFIG_PM_SLEEP 860 .suspend = sdhci_cqhci_suspend, 861 .resume = sdhci_cqhci_resume, 862 #endif 863 #ifdef CONFIG_PM 864 .runtime_suspend = sdhci_cqhci_runtime_suspend, 865 .runtime_resume = sdhci_cqhci_runtime_resume, 866 #endif 867 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 868 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 869 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 870 SDHCI_QUIRK2_STOP_WITH_TC, 871 .ops = &sdhci_intel_glk_ops, 872 .priv_size = sizeof(struct intel_host), 873 }; 874 875 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 876 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 877 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 878 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 879 .allow_runtime_pm = true, 880 .probe_slot = ni_byt_sdio_probe_slot, 881 .ops = &sdhci_intel_byt_ops, 882 .priv_size = sizeof(struct intel_host), 883 }; 884 885 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 886 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 887 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 888 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 889 .allow_runtime_pm = true, 890 .probe_slot = byt_sdio_probe_slot, 891 .ops = &sdhci_intel_byt_ops, 892 .priv_size = sizeof(struct intel_host), 893 }; 894 895 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 896 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 897 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 898 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 899 SDHCI_QUIRK2_STOP_WITH_TC, 900 .allow_runtime_pm = true, 901 .own_cd_for_runtime_pm = true, 902 .probe_slot = byt_sd_probe_slot, 903 .ops = &sdhci_intel_byt_ops, 904 .priv_size = sizeof(struct intel_host), 905 }; 906 907 /* Define Host controllers for Intel Merrifield platform */ 908 #define INTEL_MRFLD_EMMC_0 0 909 #define INTEL_MRFLD_EMMC_1 1 910 #define INTEL_MRFLD_SD 2 911 #define INTEL_MRFLD_SDIO 3 912 913 #ifdef CONFIG_ACPI 914 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) 915 { 916 struct acpi_device *device, *child; 917 918 device = ACPI_COMPANION(&slot->chip->pdev->dev); 919 if (!device) 920 return; 921 922 acpi_device_fix_up_power(device); 923 list_for_each_entry(child, &device->children, node) 924 if (child->status.present && child->status.enabled) 925 acpi_device_fix_up_power(child); 926 } 927 #else 928 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {} 929 #endif 930 931 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 932 { 933 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 934 935 switch (func) { 936 case INTEL_MRFLD_EMMC_0: 937 case INTEL_MRFLD_EMMC_1: 938 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 939 MMC_CAP_8_BIT_DATA | 940 MMC_CAP_1_8V_DDR; 941 break; 942 case INTEL_MRFLD_SD: 943 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 944 break; 945 case INTEL_MRFLD_SDIO: 946 /* Advertise 2.0v for compatibility with the SDIO card's OCR */ 947 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195; 948 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 949 MMC_CAP_POWER_OFF_CARD; 950 break; 951 default: 952 return -ENODEV; 953 } 954 955 intel_mrfld_mmc_fix_up_power_slot(slot); 956 return 0; 957 } 958 959 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 960 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 961 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 962 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 963 .allow_runtime_pm = true, 964 .probe_slot = intel_mrfld_mmc_probe_slot, 965 }; 966 967 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 968 { 969 u8 scratch; 970 int ret; 971 972 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 973 if (ret) 974 return ret; 975 976 /* 977 * Turn PMOS on [bit 0], set over current detection to 2.4 V 978 * [bit 1:2] and enable over current debouncing [bit 6]. 979 */ 980 if (on) 981 scratch |= 0x47; 982 else 983 scratch &= ~0x47; 984 985 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 986 } 987 988 static int jmicron_probe(struct sdhci_pci_chip *chip) 989 { 990 int ret; 991 u16 mmcdev = 0; 992 993 if (chip->pdev->revision == 0) { 994 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 995 SDHCI_QUIRK_32BIT_DMA_SIZE | 996 SDHCI_QUIRK_32BIT_ADMA_SIZE | 997 SDHCI_QUIRK_RESET_AFTER_REQUEST | 998 SDHCI_QUIRK_BROKEN_SMALL_PIO; 999 } 1000 1001 /* 1002 * JMicron chips can have two interfaces to the same hardware 1003 * in order to work around limitations in Microsoft's driver. 1004 * We need to make sure we only bind to one of them. 1005 * 1006 * This code assumes two things: 1007 * 1008 * 1. The PCI code adds subfunctions in order. 1009 * 1010 * 2. The MMC interface has a lower subfunction number 1011 * than the SD interface. 1012 */ 1013 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 1014 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 1015 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 1016 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 1017 1018 if (mmcdev) { 1019 struct pci_dev *sd_dev; 1020 1021 sd_dev = NULL; 1022 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 1023 mmcdev, sd_dev)) != NULL) { 1024 if ((PCI_SLOT(chip->pdev->devfn) == 1025 PCI_SLOT(sd_dev->devfn)) && 1026 (chip->pdev->bus == sd_dev->bus)) 1027 break; 1028 } 1029 1030 if (sd_dev) { 1031 pci_dev_put(sd_dev); 1032 dev_info(&chip->pdev->dev, "Refusing to bind to " 1033 "secondary interface.\n"); 1034 return -ENODEV; 1035 } 1036 } 1037 1038 /* 1039 * JMicron chips need a bit of a nudge to enable the power 1040 * output pins. 1041 */ 1042 ret = jmicron_pmos(chip, 1); 1043 if (ret) { 1044 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1045 return ret; 1046 } 1047 1048 /* quirk for unsable RO-detection on JM388 chips */ 1049 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 1050 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1051 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 1052 1053 return 0; 1054 } 1055 1056 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 1057 { 1058 u8 scratch; 1059 1060 scratch = readb(host->ioaddr + 0xC0); 1061 1062 if (on) 1063 scratch |= 0x01; 1064 else 1065 scratch &= ~0x01; 1066 1067 writeb(scratch, host->ioaddr + 0xC0); 1068 } 1069 1070 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 1071 { 1072 if (slot->chip->pdev->revision == 0) { 1073 u16 version; 1074 1075 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 1076 version = (version & SDHCI_VENDOR_VER_MASK) >> 1077 SDHCI_VENDOR_VER_SHIFT; 1078 1079 /* 1080 * Older versions of the chip have lots of nasty glitches 1081 * in the ADMA engine. It's best just to avoid it 1082 * completely. 1083 */ 1084 if (version < 0xAC) 1085 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 1086 } 1087 1088 /* JM388 MMC doesn't support 1.8V while SD supports it */ 1089 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1090 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 1091 MMC_VDD_29_30 | MMC_VDD_30_31 | 1092 MMC_VDD_165_195; /* allow 1.8V */ 1093 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 1094 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 1095 } 1096 1097 /* 1098 * The secondary interface requires a bit set to get the 1099 * interrupts. 1100 */ 1101 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1102 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1103 jmicron_enable_mmc(slot->host, 1); 1104 1105 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 1106 1107 return 0; 1108 } 1109 1110 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 1111 { 1112 if (dead) 1113 return; 1114 1115 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1116 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1117 jmicron_enable_mmc(slot->host, 0); 1118 } 1119 1120 #ifdef CONFIG_PM_SLEEP 1121 static int jmicron_suspend(struct sdhci_pci_chip *chip) 1122 { 1123 int i, ret; 1124 1125 ret = sdhci_pci_suspend_host(chip); 1126 if (ret) 1127 return ret; 1128 1129 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1130 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1131 for (i = 0; i < chip->num_slots; i++) 1132 jmicron_enable_mmc(chip->slots[i]->host, 0); 1133 } 1134 1135 return 0; 1136 } 1137 1138 static int jmicron_resume(struct sdhci_pci_chip *chip) 1139 { 1140 int ret, i; 1141 1142 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1143 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1144 for (i = 0; i < chip->num_slots; i++) 1145 jmicron_enable_mmc(chip->slots[i]->host, 1); 1146 } 1147 1148 ret = jmicron_pmos(chip, 1); 1149 if (ret) { 1150 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1151 return ret; 1152 } 1153 1154 return sdhci_pci_resume_host(chip); 1155 } 1156 #endif 1157 1158 static const struct sdhci_pci_fixes sdhci_o2 = { 1159 .probe = sdhci_pci_o2_probe, 1160 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1161 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 1162 .probe_slot = sdhci_pci_o2_probe_slot, 1163 #ifdef CONFIG_PM_SLEEP 1164 .resume = sdhci_pci_o2_resume, 1165 #endif 1166 }; 1167 1168 static const struct sdhci_pci_fixes sdhci_jmicron = { 1169 .probe = jmicron_probe, 1170 1171 .probe_slot = jmicron_probe_slot, 1172 .remove_slot = jmicron_remove_slot, 1173 1174 #ifdef CONFIG_PM_SLEEP 1175 .suspend = jmicron_suspend, 1176 .resume = jmicron_resume, 1177 #endif 1178 }; 1179 1180 /* SysKonnect CardBus2SDIO extra registers */ 1181 #define SYSKT_CTRL 0x200 1182 #define SYSKT_RDFIFO_STAT 0x204 1183 #define SYSKT_WRFIFO_STAT 0x208 1184 #define SYSKT_POWER_DATA 0x20c 1185 #define SYSKT_POWER_330 0xef 1186 #define SYSKT_POWER_300 0xf8 1187 #define SYSKT_POWER_184 0xcc 1188 #define SYSKT_POWER_CMD 0x20d 1189 #define SYSKT_POWER_START (1 << 7) 1190 #define SYSKT_POWER_STATUS 0x20e 1191 #define SYSKT_POWER_STATUS_OK (1 << 0) 1192 #define SYSKT_BOARD_REV 0x210 1193 #define SYSKT_CHIP_REV 0x211 1194 #define SYSKT_CONF_DATA 0x212 1195 #define SYSKT_CONF_DATA_1V8 (1 << 2) 1196 #define SYSKT_CONF_DATA_2V5 (1 << 1) 1197 #define SYSKT_CONF_DATA_3V3 (1 << 0) 1198 1199 static int syskt_probe(struct sdhci_pci_chip *chip) 1200 { 1201 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1202 chip->pdev->class &= ~0x0000FF; 1203 chip->pdev->class |= PCI_SDHCI_IFDMA; 1204 } 1205 return 0; 1206 } 1207 1208 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 1209 { 1210 int tm, ps; 1211 1212 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 1213 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 1214 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 1215 "board rev %d.%d, chip rev %d.%d\n", 1216 board_rev >> 4, board_rev & 0xf, 1217 chip_rev >> 4, chip_rev & 0xf); 1218 if (chip_rev >= 0x20) 1219 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 1220 1221 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 1222 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 1223 udelay(50); 1224 tm = 10; /* Wait max 1 ms */ 1225 do { 1226 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 1227 if (ps & SYSKT_POWER_STATUS_OK) 1228 break; 1229 udelay(100); 1230 } while (--tm); 1231 if (!tm) { 1232 dev_err(&slot->chip->pdev->dev, 1233 "power regulator never stabilized"); 1234 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 1235 return -ENODEV; 1236 } 1237 1238 return 0; 1239 } 1240 1241 static const struct sdhci_pci_fixes sdhci_syskt = { 1242 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 1243 .probe = syskt_probe, 1244 .probe_slot = syskt_probe_slot, 1245 }; 1246 1247 static int via_probe(struct sdhci_pci_chip *chip) 1248 { 1249 if (chip->pdev->revision == 0x10) 1250 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 1251 1252 return 0; 1253 } 1254 1255 static const struct sdhci_pci_fixes sdhci_via = { 1256 .probe = via_probe, 1257 }; 1258 1259 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 1260 { 1261 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 1262 return 0; 1263 } 1264 1265 static const struct sdhci_pci_fixes sdhci_rtsx = { 1266 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1267 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 1268 SDHCI_QUIRK2_BROKEN_DDR50, 1269 .probe_slot = rtsx_probe_slot, 1270 }; 1271 1272 /*AMD chipset generation*/ 1273 enum amd_chipset_gen { 1274 AMD_CHIPSET_BEFORE_ML, 1275 AMD_CHIPSET_CZ, 1276 AMD_CHIPSET_NL, 1277 AMD_CHIPSET_UNKNOWN, 1278 }; 1279 1280 /* AMD registers */ 1281 #define AMD_SD_AUTO_PATTERN 0xB8 1282 #define AMD_MSLEEP_DURATION 4 1283 #define AMD_SD_MISC_CONTROL 0xD0 1284 #define AMD_MAX_TUNE_VALUE 0x0B 1285 #define AMD_AUTO_TUNE_SEL 0x10800 1286 #define AMD_FIFO_PTR 0x30 1287 #define AMD_BIT_MASK 0x1F 1288 1289 static void amd_tuning_reset(struct sdhci_host *host) 1290 { 1291 unsigned int val; 1292 1293 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1294 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 1295 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1296 1297 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1298 val &= ~SDHCI_CTRL_EXEC_TUNING; 1299 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1300 } 1301 1302 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 1303 { 1304 unsigned int val; 1305 1306 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 1307 val &= ~AMD_BIT_MASK; 1308 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 1309 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 1310 } 1311 1312 static void amd_enable_manual_tuning(struct pci_dev *pdev) 1313 { 1314 unsigned int val; 1315 1316 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 1317 val |= AMD_FIFO_PTR; 1318 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 1319 } 1320 1321 static int amd_execute_tuning(struct sdhci_host *host, u32 opcode) 1322 { 1323 struct sdhci_pci_slot *slot = sdhci_priv(host); 1324 struct pci_dev *pdev = slot->chip->pdev; 1325 u8 valid_win = 0; 1326 u8 valid_win_max = 0; 1327 u8 valid_win_end = 0; 1328 u8 ctrl, tune_around; 1329 1330 amd_tuning_reset(host); 1331 1332 for (tune_around = 0; tune_around < 12; tune_around++) { 1333 amd_config_tuning_phase(pdev, tune_around); 1334 1335 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1336 valid_win = 0; 1337 msleep(AMD_MSLEEP_DURATION); 1338 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 1339 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 1340 } else if (++valid_win > valid_win_max) { 1341 valid_win_max = valid_win; 1342 valid_win_end = tune_around; 1343 } 1344 } 1345 1346 if (!valid_win_max) { 1347 dev_err(&pdev->dev, "no tuning point found\n"); 1348 return -EIO; 1349 } 1350 1351 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 1352 1353 amd_enable_manual_tuning(pdev); 1354 1355 host->mmc->retune_period = 0; 1356 1357 return 0; 1358 } 1359 1360 static int amd_probe(struct sdhci_pci_chip *chip) 1361 { 1362 struct pci_dev *smbus_dev; 1363 enum amd_chipset_gen gen; 1364 1365 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1366 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 1367 if (smbus_dev) { 1368 gen = AMD_CHIPSET_BEFORE_ML; 1369 } else { 1370 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1371 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1372 if (smbus_dev) { 1373 if (smbus_dev->revision < 0x51) 1374 gen = AMD_CHIPSET_CZ; 1375 else 1376 gen = AMD_CHIPSET_NL; 1377 } else { 1378 gen = AMD_CHIPSET_UNKNOWN; 1379 } 1380 } 1381 1382 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1383 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1384 1385 return 0; 1386 } 1387 1388 static const struct sdhci_ops amd_sdhci_pci_ops = { 1389 .set_clock = sdhci_set_clock, 1390 .enable_dma = sdhci_pci_enable_dma, 1391 .set_bus_width = sdhci_set_bus_width, 1392 .reset = sdhci_reset, 1393 .set_uhs_signaling = sdhci_set_uhs_signaling, 1394 .platform_execute_tuning = amd_execute_tuning, 1395 }; 1396 1397 static const struct sdhci_pci_fixes sdhci_amd = { 1398 .probe = amd_probe, 1399 .ops = &amd_sdhci_pci_ops, 1400 }; 1401 1402 static const struct pci_device_id pci_ids[] = { 1403 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh), 1404 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc), 1405 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc), 1406 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc), 1407 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712), 1408 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712), 1409 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714), 1410 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714), 1411 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe), 1412 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron), 1413 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron), 1414 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron), 1415 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron), 1416 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt), 1417 SDHCI_PCI_DEVICE(VIA, 95D0, via), 1418 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx), 1419 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk), 1420 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0), 1421 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2), 1422 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2), 1423 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd), 1424 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio), 1425 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio), 1426 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc), 1427 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc), 1428 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio), 1429 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio), 1430 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc), 1431 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio), 1432 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio), 1433 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd), 1434 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc), 1435 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc), 1436 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio), 1437 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd), 1438 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd), 1439 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio), 1440 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio), 1441 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc), 1442 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc), 1443 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc), 1444 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc), 1445 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio), 1446 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd), 1447 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc), 1448 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc), 1449 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc), 1450 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio), 1451 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd), 1452 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc), 1453 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio), 1454 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd), 1455 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc), 1456 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio), 1457 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd), 1458 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc), 1459 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio), 1460 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd), 1461 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc), 1462 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd), 1463 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd), 1464 SDHCI_PCI_DEVICE(O2, 8120, o2), 1465 SDHCI_PCI_DEVICE(O2, 8220, o2), 1466 SDHCI_PCI_DEVICE(O2, 8221, o2), 1467 SDHCI_PCI_DEVICE(O2, 8320, o2), 1468 SDHCI_PCI_DEVICE(O2, 8321, o2), 1469 SDHCI_PCI_DEVICE(O2, FUJIN2, o2), 1470 SDHCI_PCI_DEVICE(O2, SDS0, o2), 1471 SDHCI_PCI_DEVICE(O2, SDS1, o2), 1472 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2), 1473 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), 1474 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan), 1475 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), 1476 /* Generic SD host controller */ 1477 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, 1478 { /* end: all zeroes */ }, 1479 }; 1480 1481 MODULE_DEVICE_TABLE(pci, pci_ids); 1482 1483 /*****************************************************************************\ 1484 * * 1485 * SDHCI core callbacks * 1486 * * 1487 \*****************************************************************************/ 1488 1489 int sdhci_pci_enable_dma(struct sdhci_host *host) 1490 { 1491 struct sdhci_pci_slot *slot; 1492 struct pci_dev *pdev; 1493 1494 slot = sdhci_priv(host); 1495 pdev = slot->chip->pdev; 1496 1497 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1498 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1499 (host->flags & SDHCI_USE_SDMA)) { 1500 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1501 "doesn't fully claim to support it.\n"); 1502 } 1503 1504 pci_set_master(pdev); 1505 1506 return 0; 1507 } 1508 1509 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1510 { 1511 struct sdhci_pci_slot *slot = sdhci_priv(host); 1512 int rst_n_gpio = slot->rst_n_gpio; 1513 1514 if (!gpio_is_valid(rst_n_gpio)) 1515 return; 1516 gpio_set_value_cansleep(rst_n_gpio, 0); 1517 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1518 udelay(10); 1519 gpio_set_value_cansleep(rst_n_gpio, 1); 1520 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1521 usleep_range(300, 1000); 1522 } 1523 1524 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1525 { 1526 struct sdhci_pci_slot *slot = sdhci_priv(host); 1527 1528 if (slot->hw_reset) 1529 slot->hw_reset(host); 1530 } 1531 1532 static const struct sdhci_ops sdhci_pci_ops = { 1533 .set_clock = sdhci_set_clock, 1534 .enable_dma = sdhci_pci_enable_dma, 1535 .set_bus_width = sdhci_set_bus_width, 1536 .reset = sdhci_reset, 1537 .set_uhs_signaling = sdhci_set_uhs_signaling, 1538 .hw_reset = sdhci_pci_hw_reset, 1539 }; 1540 1541 /*****************************************************************************\ 1542 * * 1543 * Suspend/resume * 1544 * * 1545 \*****************************************************************************/ 1546 1547 #ifdef CONFIG_PM_SLEEP 1548 static int sdhci_pci_suspend(struct device *dev) 1549 { 1550 struct pci_dev *pdev = to_pci_dev(dev); 1551 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1552 1553 if (!chip) 1554 return 0; 1555 1556 if (chip->fixes && chip->fixes->suspend) 1557 return chip->fixes->suspend(chip); 1558 1559 return sdhci_pci_suspend_host(chip); 1560 } 1561 1562 static int sdhci_pci_resume(struct device *dev) 1563 { 1564 struct pci_dev *pdev = to_pci_dev(dev); 1565 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1566 1567 if (!chip) 1568 return 0; 1569 1570 if (chip->fixes && chip->fixes->resume) 1571 return chip->fixes->resume(chip); 1572 1573 return sdhci_pci_resume_host(chip); 1574 } 1575 #endif 1576 1577 #ifdef CONFIG_PM 1578 static int sdhci_pci_runtime_suspend(struct device *dev) 1579 { 1580 struct pci_dev *pdev = to_pci_dev(dev); 1581 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1582 1583 if (!chip) 1584 return 0; 1585 1586 if (chip->fixes && chip->fixes->runtime_suspend) 1587 return chip->fixes->runtime_suspend(chip); 1588 1589 return sdhci_pci_runtime_suspend_host(chip); 1590 } 1591 1592 static int sdhci_pci_runtime_resume(struct device *dev) 1593 { 1594 struct pci_dev *pdev = to_pci_dev(dev); 1595 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1596 1597 if (!chip) 1598 return 0; 1599 1600 if (chip->fixes && chip->fixes->runtime_resume) 1601 return chip->fixes->runtime_resume(chip); 1602 1603 return sdhci_pci_runtime_resume_host(chip); 1604 } 1605 #endif 1606 1607 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1608 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1609 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1610 sdhci_pci_runtime_resume, NULL) 1611 }; 1612 1613 /*****************************************************************************\ 1614 * * 1615 * Device probing/removal * 1616 * * 1617 \*****************************************************************************/ 1618 1619 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1620 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1621 int slotno) 1622 { 1623 struct sdhci_pci_slot *slot; 1624 struct sdhci_host *host; 1625 int ret, bar = first_bar + slotno; 1626 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 1627 1628 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1629 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1630 return ERR_PTR(-ENODEV); 1631 } 1632 1633 if (pci_resource_len(pdev, bar) < 0x100) { 1634 dev_err(&pdev->dev, "Invalid iomem size. You may " 1635 "experience problems.\n"); 1636 } 1637 1638 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1639 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1640 return ERR_PTR(-ENODEV); 1641 } 1642 1643 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1644 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1645 return ERR_PTR(-ENODEV); 1646 } 1647 1648 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 1649 if (IS_ERR(host)) { 1650 dev_err(&pdev->dev, "cannot allocate host\n"); 1651 return ERR_CAST(host); 1652 } 1653 1654 slot = sdhci_priv(host); 1655 1656 slot->chip = chip; 1657 slot->host = host; 1658 slot->rst_n_gpio = -EINVAL; 1659 slot->cd_gpio = -EINVAL; 1660 slot->cd_idx = -1; 1661 1662 /* Retrieve platform data if there is any */ 1663 if (*sdhci_pci_get_data) 1664 slot->data = sdhci_pci_get_data(pdev, slotno); 1665 1666 if (slot->data) { 1667 if (slot->data->setup) { 1668 ret = slot->data->setup(slot->data); 1669 if (ret) { 1670 dev_err(&pdev->dev, "platform setup failed\n"); 1671 goto free; 1672 } 1673 } 1674 slot->rst_n_gpio = slot->data->rst_n_gpio; 1675 slot->cd_gpio = slot->data->cd_gpio; 1676 } 1677 1678 host->hw_name = "PCI"; 1679 host->ops = chip->fixes && chip->fixes->ops ? 1680 chip->fixes->ops : 1681 &sdhci_pci_ops; 1682 host->quirks = chip->quirks; 1683 host->quirks2 = chip->quirks2; 1684 1685 host->irq = pdev->irq; 1686 1687 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1688 if (ret) { 1689 dev_err(&pdev->dev, "cannot request region\n"); 1690 goto cleanup; 1691 } 1692 1693 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1694 1695 if (chip->fixes && chip->fixes->probe_slot) { 1696 ret = chip->fixes->probe_slot(slot); 1697 if (ret) 1698 goto cleanup; 1699 } 1700 1701 if (gpio_is_valid(slot->rst_n_gpio)) { 1702 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1703 gpio_direction_output(slot->rst_n_gpio, 1); 1704 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1705 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1706 } else { 1707 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1708 slot->rst_n_gpio = -EINVAL; 1709 } 1710 } 1711 1712 host->mmc->pm_caps = MMC_PM_KEEP_POWER; 1713 host->mmc->slotno = slotno; 1714 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1715 1716 if (device_can_wakeup(&pdev->dev)) 1717 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ; 1718 1719 if (slot->cd_idx >= 0) { 1720 ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx, 1721 slot->cd_override_level, 0, NULL); 1722 if (ret == -EPROBE_DEFER) 1723 goto remove; 1724 1725 if (ret) { 1726 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 1727 slot->cd_idx = -1; 1728 } 1729 } 1730 1731 if (chip->fixes && chip->fixes->add_host) 1732 ret = chip->fixes->add_host(slot); 1733 else 1734 ret = sdhci_add_host(host); 1735 if (ret) 1736 goto remove; 1737 1738 sdhci_pci_add_own_cd(slot); 1739 1740 /* 1741 * Check if the chip needs a separate GPIO for card detect to wake up 1742 * from runtime suspend. If it is not there, don't allow runtime PM. 1743 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 1744 */ 1745 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 1746 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 1747 chip->allow_runtime_pm = false; 1748 1749 return slot; 1750 1751 remove: 1752 if (chip->fixes && chip->fixes->remove_slot) 1753 chip->fixes->remove_slot(slot, 0); 1754 1755 cleanup: 1756 if (slot->data && slot->data->cleanup) 1757 slot->data->cleanup(slot->data); 1758 1759 free: 1760 sdhci_free_host(host); 1761 1762 return ERR_PTR(ret); 1763 } 1764 1765 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 1766 { 1767 int dead; 1768 u32 scratch; 1769 1770 sdhci_pci_remove_own_cd(slot); 1771 1772 dead = 0; 1773 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 1774 if (scratch == (u32)-1) 1775 dead = 1; 1776 1777 sdhci_remove_host(slot->host, dead); 1778 1779 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 1780 slot->chip->fixes->remove_slot(slot, dead); 1781 1782 if (slot->data && slot->data->cleanup) 1783 slot->data->cleanup(slot->data); 1784 1785 sdhci_free_host(slot->host); 1786 } 1787 1788 static void sdhci_pci_runtime_pm_allow(struct device *dev) 1789 { 1790 pm_suspend_ignore_children(dev, 1); 1791 pm_runtime_set_autosuspend_delay(dev, 50); 1792 pm_runtime_use_autosuspend(dev); 1793 pm_runtime_allow(dev); 1794 /* Stay active until mmc core scans for a card */ 1795 pm_runtime_put_noidle(dev); 1796 } 1797 1798 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 1799 { 1800 pm_runtime_forbid(dev); 1801 pm_runtime_get_noresume(dev); 1802 } 1803 1804 static int sdhci_pci_probe(struct pci_dev *pdev, 1805 const struct pci_device_id *ent) 1806 { 1807 struct sdhci_pci_chip *chip; 1808 struct sdhci_pci_slot *slot; 1809 1810 u8 slots, first_bar; 1811 int ret, i; 1812 1813 BUG_ON(pdev == NULL); 1814 BUG_ON(ent == NULL); 1815 1816 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 1817 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 1818 1819 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 1820 if (ret) 1821 return ret; 1822 1823 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 1824 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 1825 if (slots == 0) 1826 return -ENODEV; 1827 1828 BUG_ON(slots > MAX_SLOTS); 1829 1830 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 1831 if (ret) 1832 return ret; 1833 1834 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 1835 1836 if (first_bar > 5) { 1837 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 1838 return -ENODEV; 1839 } 1840 1841 ret = pcim_enable_device(pdev); 1842 if (ret) 1843 return ret; 1844 1845 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 1846 if (!chip) 1847 return -ENOMEM; 1848 1849 chip->pdev = pdev; 1850 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 1851 if (chip->fixes) { 1852 chip->quirks = chip->fixes->quirks; 1853 chip->quirks2 = chip->fixes->quirks2; 1854 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 1855 } 1856 chip->num_slots = slots; 1857 chip->pm_retune = true; 1858 chip->rpm_retune = true; 1859 1860 pci_set_drvdata(pdev, chip); 1861 1862 if (chip->fixes && chip->fixes->probe) { 1863 ret = chip->fixes->probe(chip); 1864 if (ret) 1865 return ret; 1866 } 1867 1868 slots = chip->num_slots; /* Quirk may have changed this */ 1869 1870 for (i = 0; i < slots; i++) { 1871 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 1872 if (IS_ERR(slot)) { 1873 for (i--; i >= 0; i--) 1874 sdhci_pci_remove_slot(chip->slots[i]); 1875 return PTR_ERR(slot); 1876 } 1877 1878 chip->slots[i] = slot; 1879 } 1880 1881 if (chip->allow_runtime_pm) 1882 sdhci_pci_runtime_pm_allow(&pdev->dev); 1883 1884 return 0; 1885 } 1886 1887 static void sdhci_pci_remove(struct pci_dev *pdev) 1888 { 1889 int i; 1890 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1891 1892 if (chip->allow_runtime_pm) 1893 sdhci_pci_runtime_pm_forbid(&pdev->dev); 1894 1895 for (i = 0; i < chip->num_slots; i++) 1896 sdhci_pci_remove_slot(chip->slots[i]); 1897 } 1898 1899 static struct pci_driver sdhci_driver = { 1900 .name = "sdhci-pci", 1901 .id_table = pci_ids, 1902 .probe = sdhci_pci_probe, 1903 .remove = sdhci_pci_remove, 1904 .driver = { 1905 .pm = &sdhci_pci_pm_ops 1906 }, 1907 }; 1908 1909 module_pci_driver(sdhci_driver); 1910 1911 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 1912 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 1913 MODULE_LICENSE("GPL"); 1914