1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 3 * 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 5 * 6 * Thanks to the following companies for their support: 7 * 8 * - JMicron (hardware and technical support) 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/string.h> 13 #include <linux/delay.h> 14 #include <linux/highmem.h> 15 #include <linux/module.h> 16 #include <linux/pci.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/slab.h> 19 #include <linux/device.h> 20 #include <linux/mmc/host.h> 21 #include <linux/mmc/mmc.h> 22 #include <linux/scatterlist.h> 23 #include <linux/io.h> 24 #include <linux/iopoll.h> 25 #include <linux/gpio.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/pm_qos.h> 28 #include <linux/debugfs.h> 29 #include <linux/mmc/slot-gpio.h> 30 #include <linux/mmc/sdhci-pci-data.h> 31 #include <linux/acpi.h> 32 #include <linux/dmi.h> 33 34 #ifdef CONFIG_X86 35 #include <asm/iosf_mbi.h> 36 #endif 37 38 #include "cqhci.h" 39 40 #include "sdhci.h" 41 #include "sdhci-pci.h" 42 43 static void sdhci_pci_hw_reset(struct sdhci_host *host); 44 45 #ifdef CONFIG_PM_SLEEP 46 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip) 47 { 48 mmc_pm_flag_t pm_flags = 0; 49 bool cap_cd_wake = false; 50 int i; 51 52 for (i = 0; i < chip->num_slots; i++) { 53 struct sdhci_pci_slot *slot = chip->slots[i]; 54 55 if (slot) { 56 pm_flags |= slot->host->mmc->pm_flags; 57 if (slot->host->mmc->caps & MMC_CAP_CD_WAKE) 58 cap_cd_wake = true; 59 } 60 } 61 62 if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ)) 63 return device_wakeup_enable(&chip->pdev->dev); 64 else if (!cap_cd_wake) 65 return device_wakeup_disable(&chip->pdev->dev); 66 67 return 0; 68 } 69 70 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 71 { 72 int i, ret; 73 74 sdhci_pci_init_wakeup(chip); 75 76 for (i = 0; i < chip->num_slots; i++) { 77 struct sdhci_pci_slot *slot = chip->slots[i]; 78 struct sdhci_host *host; 79 80 if (!slot) 81 continue; 82 83 host = slot->host; 84 85 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 86 mmc_retune_needed(host->mmc); 87 88 ret = sdhci_suspend_host(host); 89 if (ret) 90 goto err_pci_suspend; 91 92 if (device_may_wakeup(&chip->pdev->dev)) 93 mmc_gpio_set_cd_wake(host->mmc, true); 94 } 95 96 return 0; 97 98 err_pci_suspend: 99 while (--i >= 0) 100 sdhci_resume_host(chip->slots[i]->host); 101 return ret; 102 } 103 104 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip) 105 { 106 struct sdhci_pci_slot *slot; 107 int i, ret; 108 109 for (i = 0; i < chip->num_slots; i++) { 110 slot = chip->slots[i]; 111 if (!slot) 112 continue; 113 114 ret = sdhci_resume_host(slot->host); 115 if (ret) 116 return ret; 117 118 mmc_gpio_set_cd_wake(slot->host->mmc, false); 119 } 120 121 return 0; 122 } 123 124 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip) 125 { 126 int ret; 127 128 ret = cqhci_suspend(chip->slots[0]->host->mmc); 129 if (ret) 130 return ret; 131 132 return sdhci_pci_suspend_host(chip); 133 } 134 135 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip) 136 { 137 int ret; 138 139 ret = sdhci_pci_resume_host(chip); 140 if (ret) 141 return ret; 142 143 return cqhci_resume(chip->slots[0]->host->mmc); 144 } 145 #endif 146 147 #ifdef CONFIG_PM 148 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip) 149 { 150 struct sdhci_pci_slot *slot; 151 struct sdhci_host *host; 152 int i, ret; 153 154 for (i = 0; i < chip->num_slots; i++) { 155 slot = chip->slots[i]; 156 if (!slot) 157 continue; 158 159 host = slot->host; 160 161 ret = sdhci_runtime_suspend_host(host); 162 if (ret) 163 goto err_pci_runtime_suspend; 164 165 if (chip->rpm_retune && 166 host->tuning_mode != SDHCI_TUNING_MODE_3) 167 mmc_retune_needed(host->mmc); 168 } 169 170 return 0; 171 172 err_pci_runtime_suspend: 173 while (--i >= 0) 174 sdhci_runtime_resume_host(chip->slots[i]->host, 0); 175 return ret; 176 } 177 178 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip) 179 { 180 struct sdhci_pci_slot *slot; 181 int i, ret; 182 183 for (i = 0; i < chip->num_slots; i++) { 184 slot = chip->slots[i]; 185 if (!slot) 186 continue; 187 188 ret = sdhci_runtime_resume_host(slot->host, 0); 189 if (ret) 190 return ret; 191 } 192 193 return 0; 194 } 195 196 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip) 197 { 198 int ret; 199 200 ret = cqhci_suspend(chip->slots[0]->host->mmc); 201 if (ret) 202 return ret; 203 204 return sdhci_pci_runtime_suspend_host(chip); 205 } 206 207 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip) 208 { 209 int ret; 210 211 ret = sdhci_pci_runtime_resume_host(chip); 212 if (ret) 213 return ret; 214 215 return cqhci_resume(chip->slots[0]->host->mmc); 216 } 217 #endif 218 219 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask) 220 { 221 int cmd_error = 0; 222 int data_error = 0; 223 224 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 225 return intmask; 226 227 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 228 229 return 0; 230 } 231 232 static void sdhci_pci_dumpregs(struct mmc_host *mmc) 233 { 234 sdhci_dumpregs(mmc_priv(mmc)); 235 } 236 237 static void sdhci_cqhci_reset(struct sdhci_host *host, u8 mask) 238 { 239 if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) && 240 host->mmc->cqe_private) 241 cqhci_deactivate(host->mmc); 242 sdhci_reset(host, mask); 243 } 244 245 /*****************************************************************************\ 246 * * 247 * Hardware specific quirk handling * 248 * * 249 \*****************************************************************************/ 250 251 static int ricoh_probe(struct sdhci_pci_chip *chip) 252 { 253 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 254 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 255 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 256 return 0; 257 } 258 259 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 260 { 261 slot->host->caps = 262 FIELD_PREP(SDHCI_TIMEOUT_CLK_MASK, 0x21) | 263 FIELD_PREP(SDHCI_CLOCK_BASE_MASK, 0x21) | 264 SDHCI_TIMEOUT_CLK_UNIT | 265 SDHCI_CAN_VDD_330 | 266 SDHCI_CAN_DO_HISPD | 267 SDHCI_CAN_DO_SDMA; 268 return 0; 269 } 270 271 #ifdef CONFIG_PM_SLEEP 272 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 273 { 274 /* Apply a delay to allow controller to settle */ 275 /* Otherwise it becomes confused if card state changed 276 during suspend */ 277 msleep(500); 278 return sdhci_pci_resume_host(chip); 279 } 280 #endif 281 282 static const struct sdhci_pci_fixes sdhci_ricoh = { 283 .probe = ricoh_probe, 284 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 285 SDHCI_QUIRK_FORCE_DMA | 286 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 287 }; 288 289 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 290 .probe_slot = ricoh_mmc_probe_slot, 291 #ifdef CONFIG_PM_SLEEP 292 .resume = ricoh_mmc_resume, 293 #endif 294 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 295 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 296 SDHCI_QUIRK_NO_CARD_NO_RESET | 297 SDHCI_QUIRK_MISSING_CAPS 298 }; 299 300 static const struct sdhci_pci_fixes sdhci_ene_712 = { 301 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 302 SDHCI_QUIRK_BROKEN_DMA, 303 }; 304 305 static const struct sdhci_pci_fixes sdhci_ene_714 = { 306 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 307 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 308 SDHCI_QUIRK_BROKEN_DMA, 309 }; 310 311 static const struct sdhci_pci_fixes sdhci_cafe = { 312 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 313 SDHCI_QUIRK_NO_BUSY_IRQ | 314 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 315 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 316 }; 317 318 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 319 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 320 }; 321 322 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 323 { 324 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 325 return 0; 326 } 327 328 /* 329 * ADMA operation is disabled for Moorestown platform due to 330 * hardware bugs. 331 */ 332 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 333 { 334 /* 335 * slots number is fixed here for MRST as SDIO3/5 are never used and 336 * have hardware bugs. 337 */ 338 chip->num_slots = 1; 339 return 0; 340 } 341 342 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 343 { 344 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 345 return 0; 346 } 347 348 #ifdef CONFIG_PM 349 350 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 351 { 352 struct sdhci_pci_slot *slot = dev_id; 353 struct sdhci_host *host = slot->host; 354 355 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 356 return IRQ_HANDLED; 357 } 358 359 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 360 { 361 int err, irq, gpio = slot->cd_gpio; 362 363 slot->cd_gpio = -EINVAL; 364 slot->cd_irq = -EINVAL; 365 366 if (!gpio_is_valid(gpio)) 367 return; 368 369 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 370 if (err < 0) 371 goto out; 372 373 err = gpio_direction_input(gpio); 374 if (err < 0) 375 goto out_free; 376 377 irq = gpio_to_irq(gpio); 378 if (irq < 0) 379 goto out_free; 380 381 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 382 IRQF_TRIGGER_FALLING, "sd_cd", slot); 383 if (err) 384 goto out_free; 385 386 slot->cd_gpio = gpio; 387 slot->cd_irq = irq; 388 389 return; 390 391 out_free: 392 devm_gpio_free(&slot->chip->pdev->dev, gpio); 393 out: 394 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 395 } 396 397 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 398 { 399 if (slot->cd_irq >= 0) 400 free_irq(slot->cd_irq, slot); 401 } 402 403 #else 404 405 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 406 { 407 } 408 409 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 410 { 411 } 412 413 #endif 414 415 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 416 { 417 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 418 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC; 419 return 0; 420 } 421 422 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 423 { 424 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 425 return 0; 426 } 427 428 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 429 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 430 .probe_slot = mrst_hc_probe_slot, 431 }; 432 433 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 434 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 435 .probe = mrst_hc_probe, 436 }; 437 438 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 439 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 440 .allow_runtime_pm = true, 441 .own_cd_for_runtime_pm = true, 442 }; 443 444 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 445 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 446 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 447 .allow_runtime_pm = true, 448 .probe_slot = mfd_sdio_probe_slot, 449 }; 450 451 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 452 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 453 .allow_runtime_pm = true, 454 .probe_slot = mfd_emmc_probe_slot, 455 }; 456 457 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 458 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 459 .probe_slot = pch_hc_probe_slot, 460 }; 461 462 #ifdef CONFIG_X86 463 464 #define BYT_IOSF_SCCEP 0x63 465 #define BYT_IOSF_OCP_NETCTRL0 0x1078 466 #define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8) 467 468 static void byt_ocp_setting(struct pci_dev *pdev) 469 { 470 u32 val = 0; 471 472 if (pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC && 473 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SDIO && 474 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SD && 475 pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC2) 476 return; 477 478 if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0, 479 &val)) { 480 dev_err(&pdev->dev, "%s read error\n", __func__); 481 return; 482 } 483 484 if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE)) 485 return; 486 487 val &= ~BYT_IOSF_OCP_TIMEOUT_BASE; 488 489 if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0, 490 val)) { 491 dev_err(&pdev->dev, "%s write error\n", __func__); 492 return; 493 } 494 495 dev_dbg(&pdev->dev, "%s completed\n", __func__); 496 } 497 498 #else 499 500 static inline void byt_ocp_setting(struct pci_dev *pdev) 501 { 502 } 503 504 #endif 505 506 enum { 507 INTEL_DSM_FNS = 0, 508 INTEL_DSM_V18_SWITCH = 3, 509 INTEL_DSM_V33_SWITCH = 4, 510 INTEL_DSM_DRV_STRENGTH = 9, 511 INTEL_DSM_D3_RETUNE = 10, 512 }; 513 514 struct intel_host { 515 u32 dsm_fns; 516 int drv_strength; 517 bool d3_retune; 518 bool rpm_retune_ok; 519 u32 glk_rx_ctrl1; 520 u32 glk_tun_val; 521 u32 active_ltr; 522 u32 idle_ltr; 523 }; 524 525 static const guid_t intel_dsm_guid = 526 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F, 527 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61); 528 529 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 530 unsigned int fn, u32 *result) 531 { 532 union acpi_object *obj; 533 int err = 0; 534 size_t len; 535 536 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL); 537 if (!obj) 538 return -EOPNOTSUPP; 539 540 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { 541 err = -EINVAL; 542 goto out; 543 } 544 545 len = min_t(size_t, obj->buffer.length, 4); 546 547 *result = 0; 548 memcpy(result, obj->buffer.pointer, len); 549 out: 550 ACPI_FREE(obj); 551 552 return err; 553 } 554 555 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 556 unsigned int fn, u32 *result) 557 { 558 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 559 return -EOPNOTSUPP; 560 561 return __intel_dsm(intel_host, dev, fn, result); 562 } 563 564 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 565 struct mmc_host *mmc) 566 { 567 int err; 568 u32 val; 569 570 intel_host->d3_retune = true; 571 572 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 573 if (err) { 574 pr_debug("%s: DSM not supported, error %d\n", 575 mmc_hostname(mmc), err); 576 return; 577 } 578 579 pr_debug("%s: DSM function mask %#x\n", 580 mmc_hostname(mmc), intel_host->dsm_fns); 581 582 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 583 intel_host->drv_strength = err ? 0 : val; 584 585 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 586 intel_host->d3_retune = err ? true : !!val; 587 } 588 589 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 590 { 591 u8 reg; 592 593 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 594 reg |= 0x10; 595 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 596 /* For eMMC, minimum is 1us but give it 9us for good measure */ 597 udelay(9); 598 reg &= ~0x10; 599 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 600 /* For eMMC, minimum is 200us but give it 300us for good measure */ 601 usleep_range(300, 1000); 602 } 603 604 static int intel_select_drive_strength(struct mmc_card *card, 605 unsigned int max_dtr, int host_drv, 606 int card_drv, int *drv_type) 607 { 608 struct sdhci_host *host = mmc_priv(card->host); 609 struct sdhci_pci_slot *slot = sdhci_priv(host); 610 struct intel_host *intel_host = sdhci_pci_priv(slot); 611 612 if (!(mmc_driver_type_mask(intel_host->drv_strength) & card_drv)) 613 return 0; 614 615 return intel_host->drv_strength; 616 } 617 618 static int bxt_get_cd(struct mmc_host *mmc) 619 { 620 int gpio_cd = mmc_gpio_get_cd(mmc); 621 struct sdhci_host *host = mmc_priv(mmc); 622 unsigned long flags; 623 int ret = 0; 624 625 if (!gpio_cd) 626 return 0; 627 628 spin_lock_irqsave(&host->lock, flags); 629 630 if (host->flags & SDHCI_DEVICE_DEAD) 631 goto out; 632 633 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 634 out: 635 spin_unlock_irqrestore(&host->lock, flags); 636 637 return ret; 638 } 639 640 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 641 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 642 643 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 644 unsigned short vdd) 645 { 646 int cntr; 647 u8 reg; 648 649 sdhci_set_power(host, mode, vdd); 650 651 if (mode == MMC_POWER_OFF) 652 return; 653 654 /* 655 * Bus power might not enable after D3 -> D0 transition due to the 656 * present state not yet having propagated. Retry for up to 2ms. 657 */ 658 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 659 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 660 if (reg & SDHCI_POWER_ON) 661 break; 662 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 663 reg |= SDHCI_POWER_ON; 664 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 665 } 666 } 667 668 static void sdhci_intel_set_uhs_signaling(struct sdhci_host *host, 669 unsigned int timing) 670 { 671 /* Set UHS timing to SDR25 for High Speed mode */ 672 if (timing == MMC_TIMING_MMC_HS || timing == MMC_TIMING_SD_HS) 673 timing = MMC_TIMING_UHS_SDR25; 674 sdhci_set_uhs_signaling(host, timing); 675 } 676 677 #define INTEL_HS400_ES_REG 0x78 678 #define INTEL_HS400_ES_BIT BIT(0) 679 680 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc, 681 struct mmc_ios *ios) 682 { 683 struct sdhci_host *host = mmc_priv(mmc); 684 u32 val; 685 686 val = sdhci_readl(host, INTEL_HS400_ES_REG); 687 if (ios->enhanced_strobe) 688 val |= INTEL_HS400_ES_BIT; 689 else 690 val &= ~INTEL_HS400_ES_BIT; 691 sdhci_writel(host, val, INTEL_HS400_ES_REG); 692 } 693 694 static int intel_start_signal_voltage_switch(struct mmc_host *mmc, 695 struct mmc_ios *ios) 696 { 697 struct device *dev = mmc_dev(mmc); 698 struct sdhci_host *host = mmc_priv(mmc); 699 struct sdhci_pci_slot *slot = sdhci_priv(host); 700 struct intel_host *intel_host = sdhci_pci_priv(slot); 701 unsigned int fn; 702 u32 result = 0; 703 int err; 704 705 err = sdhci_start_signal_voltage_switch(mmc, ios); 706 if (err) 707 return err; 708 709 switch (ios->signal_voltage) { 710 case MMC_SIGNAL_VOLTAGE_330: 711 fn = INTEL_DSM_V33_SWITCH; 712 break; 713 case MMC_SIGNAL_VOLTAGE_180: 714 fn = INTEL_DSM_V18_SWITCH; 715 break; 716 default: 717 return 0; 718 } 719 720 err = intel_dsm(intel_host, dev, fn, &result); 721 pr_debug("%s: %s DSM fn %u error %d result %u\n", 722 mmc_hostname(mmc), __func__, fn, err, result); 723 724 return 0; 725 } 726 727 static const struct sdhci_ops sdhci_intel_byt_ops = { 728 .set_clock = sdhci_set_clock, 729 .set_power = sdhci_intel_set_power, 730 .enable_dma = sdhci_pci_enable_dma, 731 .set_bus_width = sdhci_set_bus_width, 732 .reset = sdhci_reset, 733 .set_uhs_signaling = sdhci_intel_set_uhs_signaling, 734 .hw_reset = sdhci_pci_hw_reset, 735 }; 736 737 static const struct sdhci_ops sdhci_intel_glk_ops = { 738 .set_clock = sdhci_set_clock, 739 .set_power = sdhci_intel_set_power, 740 .enable_dma = sdhci_pci_enable_dma, 741 .set_bus_width = sdhci_set_bus_width, 742 .reset = sdhci_cqhci_reset, 743 .set_uhs_signaling = sdhci_intel_set_uhs_signaling, 744 .hw_reset = sdhci_pci_hw_reset, 745 .irq = sdhci_cqhci_irq, 746 }; 747 748 static void byt_read_dsm(struct sdhci_pci_slot *slot) 749 { 750 struct intel_host *intel_host = sdhci_pci_priv(slot); 751 struct device *dev = &slot->chip->pdev->dev; 752 struct mmc_host *mmc = slot->host->mmc; 753 754 intel_dsm_init(intel_host, dev, mmc); 755 slot->chip->rpm_retune = intel_host->d3_retune; 756 } 757 758 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode) 759 { 760 int err = sdhci_execute_tuning(mmc, opcode); 761 struct sdhci_host *host = mmc_priv(mmc); 762 763 if (err) 764 return err; 765 766 /* 767 * Tuning can leave the IP in an active state (Buffer Read Enable bit 768 * set) which prevents the entry to low power states (i.e. S0i3). Data 769 * reset will clear it. 770 */ 771 sdhci_reset(host, SDHCI_RESET_DATA); 772 773 return 0; 774 } 775 776 #define INTEL_ACTIVELTR 0x804 777 #define INTEL_IDLELTR 0x808 778 779 #define INTEL_LTR_REQ BIT(15) 780 #define INTEL_LTR_SCALE_MASK GENMASK(11, 10) 781 #define INTEL_LTR_SCALE_1US (2 << 10) 782 #define INTEL_LTR_SCALE_32US (3 << 10) 783 #define INTEL_LTR_VALUE_MASK GENMASK(9, 0) 784 785 static void intel_cache_ltr(struct sdhci_pci_slot *slot) 786 { 787 struct intel_host *intel_host = sdhci_pci_priv(slot); 788 struct sdhci_host *host = slot->host; 789 790 intel_host->active_ltr = readl(host->ioaddr + INTEL_ACTIVELTR); 791 intel_host->idle_ltr = readl(host->ioaddr + INTEL_IDLELTR); 792 } 793 794 static void intel_ltr_set(struct device *dev, s32 val) 795 { 796 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 797 struct sdhci_pci_slot *slot = chip->slots[0]; 798 struct intel_host *intel_host = sdhci_pci_priv(slot); 799 struct sdhci_host *host = slot->host; 800 u32 ltr; 801 802 pm_runtime_get_sync(dev); 803 804 /* 805 * Program latency tolerance (LTR) accordingly what has been asked 806 * by the PM QoS layer or disable it in case we were passed 807 * negative value or PM_QOS_LATENCY_ANY. 808 */ 809 ltr = readl(host->ioaddr + INTEL_ACTIVELTR); 810 811 if (val == PM_QOS_LATENCY_ANY || val < 0) { 812 ltr &= ~INTEL_LTR_REQ; 813 } else { 814 ltr |= INTEL_LTR_REQ; 815 ltr &= ~INTEL_LTR_SCALE_MASK; 816 ltr &= ~INTEL_LTR_VALUE_MASK; 817 818 if (val > INTEL_LTR_VALUE_MASK) { 819 val >>= 5; 820 if (val > INTEL_LTR_VALUE_MASK) 821 val = INTEL_LTR_VALUE_MASK; 822 ltr |= INTEL_LTR_SCALE_32US | val; 823 } else { 824 ltr |= INTEL_LTR_SCALE_1US | val; 825 } 826 } 827 828 if (ltr == intel_host->active_ltr) 829 goto out; 830 831 writel(ltr, host->ioaddr + INTEL_ACTIVELTR); 832 writel(ltr, host->ioaddr + INTEL_IDLELTR); 833 834 /* Cache the values into lpss structure */ 835 intel_cache_ltr(slot); 836 out: 837 pm_runtime_put_autosuspend(dev); 838 } 839 840 static bool intel_use_ltr(struct sdhci_pci_chip *chip) 841 { 842 switch (chip->pdev->device) { 843 case PCI_DEVICE_ID_INTEL_BYT_EMMC: 844 case PCI_DEVICE_ID_INTEL_BYT_EMMC2: 845 case PCI_DEVICE_ID_INTEL_BYT_SDIO: 846 case PCI_DEVICE_ID_INTEL_BYT_SD: 847 case PCI_DEVICE_ID_INTEL_BSW_EMMC: 848 case PCI_DEVICE_ID_INTEL_BSW_SDIO: 849 case PCI_DEVICE_ID_INTEL_BSW_SD: 850 return false; 851 default: 852 return true; 853 } 854 } 855 856 static void intel_ltr_expose(struct sdhci_pci_chip *chip) 857 { 858 struct device *dev = &chip->pdev->dev; 859 860 if (!intel_use_ltr(chip)) 861 return; 862 863 dev->power.set_latency_tolerance = intel_ltr_set; 864 dev_pm_qos_expose_latency_tolerance(dev); 865 } 866 867 static void intel_ltr_hide(struct sdhci_pci_chip *chip) 868 { 869 struct device *dev = &chip->pdev->dev; 870 871 if (!intel_use_ltr(chip)) 872 return; 873 874 dev_pm_qos_hide_latency_tolerance(dev); 875 dev->power.set_latency_tolerance = NULL; 876 } 877 878 static void byt_probe_slot(struct sdhci_pci_slot *slot) 879 { 880 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 881 struct device *dev = &slot->chip->pdev->dev; 882 struct mmc_host *mmc = slot->host->mmc; 883 884 byt_read_dsm(slot); 885 886 byt_ocp_setting(slot->chip->pdev); 887 888 ops->execute_tuning = intel_execute_tuning; 889 ops->start_signal_voltage_switch = intel_start_signal_voltage_switch; 890 891 device_property_read_u32(dev, "max-frequency", &mmc->f_max); 892 893 if (!mmc->slotno) { 894 slot->chip->slots[mmc->slotno] = slot; 895 intel_ltr_expose(slot->chip); 896 } 897 } 898 899 static void byt_add_debugfs(struct sdhci_pci_slot *slot) 900 { 901 struct intel_host *intel_host = sdhci_pci_priv(slot); 902 struct mmc_host *mmc = slot->host->mmc; 903 struct dentry *dir = mmc->debugfs_root; 904 905 if (!intel_use_ltr(slot->chip)) 906 return; 907 908 debugfs_create_x32("active_ltr", 0444, dir, &intel_host->active_ltr); 909 debugfs_create_x32("idle_ltr", 0444, dir, &intel_host->idle_ltr); 910 911 intel_cache_ltr(slot); 912 } 913 914 static int byt_add_host(struct sdhci_pci_slot *slot) 915 { 916 int ret = sdhci_add_host(slot->host); 917 918 if (!ret) 919 byt_add_debugfs(slot); 920 return ret; 921 } 922 923 static void byt_remove_slot(struct sdhci_pci_slot *slot, int dead) 924 { 925 struct mmc_host *mmc = slot->host->mmc; 926 927 if (!mmc->slotno) 928 intel_ltr_hide(slot->chip); 929 } 930 931 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 932 { 933 byt_probe_slot(slot); 934 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 935 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 936 MMC_CAP_CMD_DURING_TFR | 937 MMC_CAP_WAIT_WHILE_BUSY; 938 slot->hw_reset = sdhci_pci_int_hw_reset; 939 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 940 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 941 slot->host->mmc_host_ops.select_drive_strength = 942 intel_select_drive_strength; 943 return 0; 944 } 945 946 static bool glk_broken_cqhci(struct sdhci_pci_slot *slot) 947 { 948 return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 949 (dmi_match(DMI_BIOS_VENDOR, "LENOVO") || 950 dmi_match(DMI_SYS_VENDOR, "IRBIS")); 951 } 952 953 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot) 954 { 955 int ret = byt_emmc_probe_slot(slot); 956 957 if (!glk_broken_cqhci(slot)) 958 slot->host->mmc->caps2 |= MMC_CAP2_CQE; 959 960 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) { 961 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES, 962 slot->host->mmc_host_ops.hs400_enhanced_strobe = 963 intel_hs400_enhanced_strobe; 964 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; 965 } 966 967 return ret; 968 } 969 970 static const struct cqhci_host_ops glk_cqhci_ops = { 971 .enable = sdhci_cqe_enable, 972 .disable = sdhci_cqe_disable, 973 .dumpregs = sdhci_pci_dumpregs, 974 }; 975 976 static int glk_emmc_add_host(struct sdhci_pci_slot *slot) 977 { 978 struct device *dev = &slot->chip->pdev->dev; 979 struct sdhci_host *host = slot->host; 980 struct cqhci_host *cq_host; 981 bool dma64; 982 int ret; 983 984 ret = sdhci_setup_host(host); 985 if (ret) 986 return ret; 987 988 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); 989 if (!cq_host) { 990 ret = -ENOMEM; 991 goto cleanup; 992 } 993 994 cq_host->mmio = host->ioaddr + 0x200; 995 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 996 cq_host->ops = &glk_cqhci_ops; 997 998 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 999 if (dma64) 1000 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 1001 1002 ret = cqhci_init(cq_host, host->mmc, dma64); 1003 if (ret) 1004 goto cleanup; 1005 1006 ret = __sdhci_add_host(host); 1007 if (ret) 1008 goto cleanup; 1009 1010 byt_add_debugfs(slot); 1011 1012 return 0; 1013 1014 cleanup: 1015 sdhci_cleanup_host(host); 1016 return ret; 1017 } 1018 1019 #ifdef CONFIG_PM 1020 #define GLK_RX_CTRL1 0x834 1021 #define GLK_TUN_VAL 0x840 1022 #define GLK_PATH_PLL GENMASK(13, 8) 1023 #define GLK_DLY GENMASK(6, 0) 1024 /* Workaround firmware failing to restore the tuning value */ 1025 static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp) 1026 { 1027 struct sdhci_pci_slot *slot = chip->slots[0]; 1028 struct intel_host *intel_host = sdhci_pci_priv(slot); 1029 struct sdhci_host *host = slot->host; 1030 u32 glk_rx_ctrl1; 1031 u32 glk_tun_val; 1032 u32 dly; 1033 1034 if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc)) 1035 return; 1036 1037 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1); 1038 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL); 1039 1040 if (susp) { 1041 intel_host->glk_rx_ctrl1 = glk_rx_ctrl1; 1042 intel_host->glk_tun_val = glk_tun_val; 1043 return; 1044 } 1045 1046 if (!intel_host->glk_tun_val) 1047 return; 1048 1049 if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) { 1050 intel_host->rpm_retune_ok = true; 1051 return; 1052 } 1053 1054 dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) + 1055 (intel_host->glk_tun_val << 1)); 1056 if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1)) 1057 return; 1058 1059 glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly; 1060 sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1); 1061 1062 intel_host->rpm_retune_ok = true; 1063 chip->rpm_retune = true; 1064 mmc_retune_needed(host->mmc); 1065 pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc)); 1066 } 1067 1068 static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp) 1069 { 1070 if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 1071 !chip->rpm_retune) 1072 glk_rpm_retune_wa(chip, susp); 1073 } 1074 1075 static int glk_runtime_suspend(struct sdhci_pci_chip *chip) 1076 { 1077 glk_rpm_retune_chk(chip, true); 1078 1079 return sdhci_cqhci_runtime_suspend(chip); 1080 } 1081 1082 static int glk_runtime_resume(struct sdhci_pci_chip *chip) 1083 { 1084 glk_rpm_retune_chk(chip, false); 1085 1086 return sdhci_cqhci_runtime_resume(chip); 1087 } 1088 #endif 1089 1090 #ifdef CONFIG_ACPI 1091 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 1092 { 1093 acpi_status status; 1094 unsigned long long max_freq; 1095 1096 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 1097 "MXFQ", NULL, &max_freq); 1098 if (ACPI_FAILURE(status)) { 1099 dev_err(&slot->chip->pdev->dev, 1100 "MXFQ not found in acpi table\n"); 1101 return -EINVAL; 1102 } 1103 1104 slot->host->mmc->f_max = max_freq * 1000000; 1105 1106 return 0; 1107 } 1108 #else 1109 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 1110 { 1111 return 0; 1112 } 1113 #endif 1114 1115 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 1116 { 1117 int err; 1118 1119 byt_probe_slot(slot); 1120 1121 err = ni_set_max_freq(slot); 1122 if (err) 1123 return err; 1124 1125 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 1126 MMC_CAP_WAIT_WHILE_BUSY; 1127 return 0; 1128 } 1129 1130 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 1131 { 1132 byt_probe_slot(slot); 1133 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 1134 MMC_CAP_WAIT_WHILE_BUSY; 1135 return 0; 1136 } 1137 1138 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 1139 { 1140 byt_probe_slot(slot); 1141 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | 1142 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE; 1143 slot->cd_idx = 0; 1144 slot->cd_override_level = true; 1145 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 1146 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 1147 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 1148 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) 1149 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 1150 1151 if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI && 1152 slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3) 1153 slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V; 1154 1155 return 0; 1156 } 1157 1158 #ifdef CONFIG_PM_SLEEP 1159 1160 static int byt_resume(struct sdhci_pci_chip *chip) 1161 { 1162 byt_ocp_setting(chip->pdev); 1163 1164 return sdhci_pci_resume_host(chip); 1165 } 1166 1167 #endif 1168 1169 #ifdef CONFIG_PM 1170 1171 static int byt_runtime_resume(struct sdhci_pci_chip *chip) 1172 { 1173 byt_ocp_setting(chip->pdev); 1174 1175 return sdhci_pci_runtime_resume_host(chip); 1176 } 1177 1178 #endif 1179 1180 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 1181 #ifdef CONFIG_PM_SLEEP 1182 .resume = byt_resume, 1183 #endif 1184 #ifdef CONFIG_PM 1185 .runtime_resume = byt_runtime_resume, 1186 #endif 1187 .allow_runtime_pm = true, 1188 .probe_slot = byt_emmc_probe_slot, 1189 .add_host = byt_add_host, 1190 .remove_slot = byt_remove_slot, 1191 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1192 SDHCI_QUIRK_NO_LED, 1193 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1194 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1195 SDHCI_QUIRK2_STOP_WITH_TC, 1196 .ops = &sdhci_intel_byt_ops, 1197 .priv_size = sizeof(struct intel_host), 1198 }; 1199 1200 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = { 1201 .allow_runtime_pm = true, 1202 .probe_slot = glk_emmc_probe_slot, 1203 .add_host = glk_emmc_add_host, 1204 .remove_slot = byt_remove_slot, 1205 #ifdef CONFIG_PM_SLEEP 1206 .suspend = sdhci_cqhci_suspend, 1207 .resume = sdhci_cqhci_resume, 1208 #endif 1209 #ifdef CONFIG_PM 1210 .runtime_suspend = glk_runtime_suspend, 1211 .runtime_resume = glk_runtime_resume, 1212 #endif 1213 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1214 SDHCI_QUIRK_NO_LED, 1215 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1216 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1217 SDHCI_QUIRK2_STOP_WITH_TC, 1218 .ops = &sdhci_intel_glk_ops, 1219 .priv_size = sizeof(struct intel_host), 1220 }; 1221 1222 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 1223 #ifdef CONFIG_PM_SLEEP 1224 .resume = byt_resume, 1225 #endif 1226 #ifdef CONFIG_PM 1227 .runtime_resume = byt_runtime_resume, 1228 #endif 1229 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1230 SDHCI_QUIRK_NO_LED, 1231 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1232 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1233 .allow_runtime_pm = true, 1234 .probe_slot = ni_byt_sdio_probe_slot, 1235 .add_host = byt_add_host, 1236 .remove_slot = byt_remove_slot, 1237 .ops = &sdhci_intel_byt_ops, 1238 .priv_size = sizeof(struct intel_host), 1239 }; 1240 1241 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 1242 #ifdef CONFIG_PM_SLEEP 1243 .resume = byt_resume, 1244 #endif 1245 #ifdef CONFIG_PM 1246 .runtime_resume = byt_runtime_resume, 1247 #endif 1248 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1249 SDHCI_QUIRK_NO_LED, 1250 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1251 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1252 .allow_runtime_pm = true, 1253 .probe_slot = byt_sdio_probe_slot, 1254 .add_host = byt_add_host, 1255 .remove_slot = byt_remove_slot, 1256 .ops = &sdhci_intel_byt_ops, 1257 .priv_size = sizeof(struct intel_host), 1258 }; 1259 1260 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 1261 #ifdef CONFIG_PM_SLEEP 1262 .resume = byt_resume, 1263 #endif 1264 #ifdef CONFIG_PM 1265 .runtime_resume = byt_runtime_resume, 1266 #endif 1267 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1268 SDHCI_QUIRK_NO_LED, 1269 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 1270 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1271 SDHCI_QUIRK2_STOP_WITH_TC, 1272 .allow_runtime_pm = true, 1273 .own_cd_for_runtime_pm = true, 1274 .probe_slot = byt_sd_probe_slot, 1275 .add_host = byt_add_host, 1276 .remove_slot = byt_remove_slot, 1277 .ops = &sdhci_intel_byt_ops, 1278 .priv_size = sizeof(struct intel_host), 1279 }; 1280 1281 /* Define Host controllers for Intel Merrifield platform */ 1282 #define INTEL_MRFLD_EMMC_0 0 1283 #define INTEL_MRFLD_EMMC_1 1 1284 #define INTEL_MRFLD_SD 2 1285 #define INTEL_MRFLD_SDIO 3 1286 1287 #ifdef CONFIG_ACPI 1288 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) 1289 { 1290 struct acpi_device *device, *child; 1291 1292 device = ACPI_COMPANION(&slot->chip->pdev->dev); 1293 if (!device) 1294 return; 1295 1296 acpi_device_fix_up_power(device); 1297 list_for_each_entry(child, &device->children, node) 1298 if (child->status.present && child->status.enabled) 1299 acpi_device_fix_up_power(child); 1300 } 1301 #else 1302 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {} 1303 #endif 1304 1305 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 1306 { 1307 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 1308 1309 switch (func) { 1310 case INTEL_MRFLD_EMMC_0: 1311 case INTEL_MRFLD_EMMC_1: 1312 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1313 MMC_CAP_8_BIT_DATA | 1314 MMC_CAP_1_8V_DDR; 1315 break; 1316 case INTEL_MRFLD_SD: 1317 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1318 break; 1319 case INTEL_MRFLD_SDIO: 1320 /* Advertise 2.0v for compatibility with the SDIO card's OCR */ 1321 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195; 1322 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1323 MMC_CAP_POWER_OFF_CARD; 1324 break; 1325 default: 1326 return -ENODEV; 1327 } 1328 1329 intel_mrfld_mmc_fix_up_power_slot(slot); 1330 return 0; 1331 } 1332 1333 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 1334 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1335 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 1336 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1337 .allow_runtime_pm = true, 1338 .probe_slot = intel_mrfld_mmc_probe_slot, 1339 }; 1340 1341 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 1342 { 1343 u8 scratch; 1344 int ret; 1345 1346 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 1347 if (ret) 1348 return ret; 1349 1350 /* 1351 * Turn PMOS on [bit 0], set over current detection to 2.4 V 1352 * [bit 1:2] and enable over current debouncing [bit 6]. 1353 */ 1354 if (on) 1355 scratch |= 0x47; 1356 else 1357 scratch &= ~0x47; 1358 1359 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 1360 } 1361 1362 static int jmicron_probe(struct sdhci_pci_chip *chip) 1363 { 1364 int ret; 1365 u16 mmcdev = 0; 1366 1367 if (chip->pdev->revision == 0) { 1368 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 1369 SDHCI_QUIRK_32BIT_DMA_SIZE | 1370 SDHCI_QUIRK_32BIT_ADMA_SIZE | 1371 SDHCI_QUIRK_RESET_AFTER_REQUEST | 1372 SDHCI_QUIRK_BROKEN_SMALL_PIO; 1373 } 1374 1375 /* 1376 * JMicron chips can have two interfaces to the same hardware 1377 * in order to work around limitations in Microsoft's driver. 1378 * We need to make sure we only bind to one of them. 1379 * 1380 * This code assumes two things: 1381 * 1382 * 1. The PCI code adds subfunctions in order. 1383 * 1384 * 2. The MMC interface has a lower subfunction number 1385 * than the SD interface. 1386 */ 1387 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 1388 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 1389 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 1390 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 1391 1392 if (mmcdev) { 1393 struct pci_dev *sd_dev; 1394 1395 sd_dev = NULL; 1396 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 1397 mmcdev, sd_dev)) != NULL) { 1398 if ((PCI_SLOT(chip->pdev->devfn) == 1399 PCI_SLOT(sd_dev->devfn)) && 1400 (chip->pdev->bus == sd_dev->bus)) 1401 break; 1402 } 1403 1404 if (sd_dev) { 1405 pci_dev_put(sd_dev); 1406 dev_info(&chip->pdev->dev, "Refusing to bind to " 1407 "secondary interface.\n"); 1408 return -ENODEV; 1409 } 1410 } 1411 1412 /* 1413 * JMicron chips need a bit of a nudge to enable the power 1414 * output pins. 1415 */ 1416 ret = jmicron_pmos(chip, 1); 1417 if (ret) { 1418 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1419 return ret; 1420 } 1421 1422 /* quirk for unsable RO-detection on JM388 chips */ 1423 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 1424 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1425 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 1426 1427 return 0; 1428 } 1429 1430 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 1431 { 1432 u8 scratch; 1433 1434 scratch = readb(host->ioaddr + 0xC0); 1435 1436 if (on) 1437 scratch |= 0x01; 1438 else 1439 scratch &= ~0x01; 1440 1441 writeb(scratch, host->ioaddr + 0xC0); 1442 } 1443 1444 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 1445 { 1446 if (slot->chip->pdev->revision == 0) { 1447 u16 version; 1448 1449 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 1450 version = (version & SDHCI_VENDOR_VER_MASK) >> 1451 SDHCI_VENDOR_VER_SHIFT; 1452 1453 /* 1454 * Older versions of the chip have lots of nasty glitches 1455 * in the ADMA engine. It's best just to avoid it 1456 * completely. 1457 */ 1458 if (version < 0xAC) 1459 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 1460 } 1461 1462 /* JM388 MMC doesn't support 1.8V while SD supports it */ 1463 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1464 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 1465 MMC_VDD_29_30 | MMC_VDD_30_31 | 1466 MMC_VDD_165_195; /* allow 1.8V */ 1467 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 1468 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 1469 } 1470 1471 /* 1472 * The secondary interface requires a bit set to get the 1473 * interrupts. 1474 */ 1475 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1476 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1477 jmicron_enable_mmc(slot->host, 1); 1478 1479 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 1480 1481 return 0; 1482 } 1483 1484 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 1485 { 1486 if (dead) 1487 return; 1488 1489 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1490 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1491 jmicron_enable_mmc(slot->host, 0); 1492 } 1493 1494 #ifdef CONFIG_PM_SLEEP 1495 static int jmicron_suspend(struct sdhci_pci_chip *chip) 1496 { 1497 int i, ret; 1498 1499 ret = sdhci_pci_suspend_host(chip); 1500 if (ret) 1501 return ret; 1502 1503 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1504 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1505 for (i = 0; i < chip->num_slots; i++) 1506 jmicron_enable_mmc(chip->slots[i]->host, 0); 1507 } 1508 1509 return 0; 1510 } 1511 1512 static int jmicron_resume(struct sdhci_pci_chip *chip) 1513 { 1514 int ret, i; 1515 1516 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1517 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1518 for (i = 0; i < chip->num_slots; i++) 1519 jmicron_enable_mmc(chip->slots[i]->host, 1); 1520 } 1521 1522 ret = jmicron_pmos(chip, 1); 1523 if (ret) { 1524 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1525 return ret; 1526 } 1527 1528 return sdhci_pci_resume_host(chip); 1529 } 1530 #endif 1531 1532 static const struct sdhci_pci_fixes sdhci_jmicron = { 1533 .probe = jmicron_probe, 1534 1535 .probe_slot = jmicron_probe_slot, 1536 .remove_slot = jmicron_remove_slot, 1537 1538 #ifdef CONFIG_PM_SLEEP 1539 .suspend = jmicron_suspend, 1540 .resume = jmicron_resume, 1541 #endif 1542 }; 1543 1544 /* SysKonnect CardBus2SDIO extra registers */ 1545 #define SYSKT_CTRL 0x200 1546 #define SYSKT_RDFIFO_STAT 0x204 1547 #define SYSKT_WRFIFO_STAT 0x208 1548 #define SYSKT_POWER_DATA 0x20c 1549 #define SYSKT_POWER_330 0xef 1550 #define SYSKT_POWER_300 0xf8 1551 #define SYSKT_POWER_184 0xcc 1552 #define SYSKT_POWER_CMD 0x20d 1553 #define SYSKT_POWER_START (1 << 7) 1554 #define SYSKT_POWER_STATUS 0x20e 1555 #define SYSKT_POWER_STATUS_OK (1 << 0) 1556 #define SYSKT_BOARD_REV 0x210 1557 #define SYSKT_CHIP_REV 0x211 1558 #define SYSKT_CONF_DATA 0x212 1559 #define SYSKT_CONF_DATA_1V8 (1 << 2) 1560 #define SYSKT_CONF_DATA_2V5 (1 << 1) 1561 #define SYSKT_CONF_DATA_3V3 (1 << 0) 1562 1563 static int syskt_probe(struct sdhci_pci_chip *chip) 1564 { 1565 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1566 chip->pdev->class &= ~0x0000FF; 1567 chip->pdev->class |= PCI_SDHCI_IFDMA; 1568 } 1569 return 0; 1570 } 1571 1572 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 1573 { 1574 int tm, ps; 1575 1576 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 1577 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 1578 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 1579 "board rev %d.%d, chip rev %d.%d\n", 1580 board_rev >> 4, board_rev & 0xf, 1581 chip_rev >> 4, chip_rev & 0xf); 1582 if (chip_rev >= 0x20) 1583 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 1584 1585 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 1586 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 1587 udelay(50); 1588 tm = 10; /* Wait max 1 ms */ 1589 do { 1590 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 1591 if (ps & SYSKT_POWER_STATUS_OK) 1592 break; 1593 udelay(100); 1594 } while (--tm); 1595 if (!tm) { 1596 dev_err(&slot->chip->pdev->dev, 1597 "power regulator never stabilized"); 1598 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 1599 return -ENODEV; 1600 } 1601 1602 return 0; 1603 } 1604 1605 static const struct sdhci_pci_fixes sdhci_syskt = { 1606 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 1607 .probe = syskt_probe, 1608 .probe_slot = syskt_probe_slot, 1609 }; 1610 1611 static int via_probe(struct sdhci_pci_chip *chip) 1612 { 1613 if (chip->pdev->revision == 0x10) 1614 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 1615 1616 return 0; 1617 } 1618 1619 static const struct sdhci_pci_fixes sdhci_via = { 1620 .probe = via_probe, 1621 }; 1622 1623 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 1624 { 1625 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 1626 return 0; 1627 } 1628 1629 static const struct sdhci_pci_fixes sdhci_rtsx = { 1630 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1631 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 1632 SDHCI_QUIRK2_BROKEN_DDR50, 1633 .probe_slot = rtsx_probe_slot, 1634 }; 1635 1636 /*AMD chipset generation*/ 1637 enum amd_chipset_gen { 1638 AMD_CHIPSET_BEFORE_ML, 1639 AMD_CHIPSET_CZ, 1640 AMD_CHIPSET_NL, 1641 AMD_CHIPSET_UNKNOWN, 1642 }; 1643 1644 /* AMD registers */ 1645 #define AMD_SD_AUTO_PATTERN 0xB8 1646 #define AMD_MSLEEP_DURATION 4 1647 #define AMD_SD_MISC_CONTROL 0xD0 1648 #define AMD_MAX_TUNE_VALUE 0x0B 1649 #define AMD_AUTO_TUNE_SEL 0x10800 1650 #define AMD_FIFO_PTR 0x30 1651 #define AMD_BIT_MASK 0x1F 1652 1653 static void amd_tuning_reset(struct sdhci_host *host) 1654 { 1655 unsigned int val; 1656 1657 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1658 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 1659 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1660 1661 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1662 val &= ~SDHCI_CTRL_EXEC_TUNING; 1663 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1664 } 1665 1666 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 1667 { 1668 unsigned int val; 1669 1670 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 1671 val &= ~AMD_BIT_MASK; 1672 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 1673 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 1674 } 1675 1676 static void amd_enable_manual_tuning(struct pci_dev *pdev) 1677 { 1678 unsigned int val; 1679 1680 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 1681 val |= AMD_FIFO_PTR; 1682 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 1683 } 1684 1685 static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode) 1686 { 1687 struct sdhci_pci_slot *slot = sdhci_priv(host); 1688 struct pci_dev *pdev = slot->chip->pdev; 1689 u8 valid_win = 0; 1690 u8 valid_win_max = 0; 1691 u8 valid_win_end = 0; 1692 u8 ctrl, tune_around; 1693 1694 amd_tuning_reset(host); 1695 1696 for (tune_around = 0; tune_around < 12; tune_around++) { 1697 amd_config_tuning_phase(pdev, tune_around); 1698 1699 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1700 valid_win = 0; 1701 msleep(AMD_MSLEEP_DURATION); 1702 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 1703 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 1704 } else if (++valid_win > valid_win_max) { 1705 valid_win_max = valid_win; 1706 valid_win_end = tune_around; 1707 } 1708 } 1709 1710 if (!valid_win_max) { 1711 dev_err(&pdev->dev, "no tuning point found\n"); 1712 return -EIO; 1713 } 1714 1715 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 1716 1717 amd_enable_manual_tuning(pdev); 1718 1719 host->mmc->retune_period = 0; 1720 1721 return 0; 1722 } 1723 1724 static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode) 1725 { 1726 struct sdhci_host *host = mmc_priv(mmc); 1727 1728 /* AMD requires custom HS200 tuning */ 1729 if (host->timing == MMC_TIMING_MMC_HS200) 1730 return amd_execute_tuning_hs200(host, opcode); 1731 1732 /* Otherwise perform standard SDHCI tuning */ 1733 return sdhci_execute_tuning(mmc, opcode); 1734 } 1735 1736 static int amd_probe_slot(struct sdhci_pci_slot *slot) 1737 { 1738 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 1739 1740 ops->execute_tuning = amd_execute_tuning; 1741 1742 return 0; 1743 } 1744 1745 static int amd_probe(struct sdhci_pci_chip *chip) 1746 { 1747 struct pci_dev *smbus_dev; 1748 enum amd_chipset_gen gen; 1749 1750 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1751 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 1752 if (smbus_dev) { 1753 gen = AMD_CHIPSET_BEFORE_ML; 1754 } else { 1755 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1756 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1757 if (smbus_dev) { 1758 if (smbus_dev->revision < 0x51) 1759 gen = AMD_CHIPSET_CZ; 1760 else 1761 gen = AMD_CHIPSET_NL; 1762 } else { 1763 gen = AMD_CHIPSET_UNKNOWN; 1764 } 1765 } 1766 1767 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1768 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1769 1770 return 0; 1771 } 1772 1773 static u32 sdhci_read_present_state(struct sdhci_host *host) 1774 { 1775 return sdhci_readl(host, SDHCI_PRESENT_STATE); 1776 } 1777 1778 static void amd_sdhci_reset(struct sdhci_host *host, u8 mask) 1779 { 1780 struct sdhci_pci_slot *slot = sdhci_priv(host); 1781 struct pci_dev *pdev = slot->chip->pdev; 1782 u32 present_state; 1783 1784 /* 1785 * SDHC 0x7906 requires a hard reset to clear all internal state. 1786 * Otherwise it can get into a bad state where the DATA lines are always 1787 * read as zeros. 1788 */ 1789 if (pdev->device == 0x7906 && (mask & SDHCI_RESET_ALL)) { 1790 pci_clear_master(pdev); 1791 1792 pci_save_state(pdev); 1793 1794 pci_set_power_state(pdev, PCI_D3cold); 1795 pr_debug("%s: power_state=%u\n", mmc_hostname(host->mmc), 1796 pdev->current_state); 1797 pci_set_power_state(pdev, PCI_D0); 1798 1799 pci_restore_state(pdev); 1800 1801 /* 1802 * SDHCI_RESET_ALL says the card detect logic should not be 1803 * reset, but since we need to reset the entire controller 1804 * we should wait until the card detect logic has stabilized. 1805 * 1806 * This normally takes about 40ms. 1807 */ 1808 readx_poll_timeout( 1809 sdhci_read_present_state, 1810 host, 1811 present_state, 1812 present_state & SDHCI_CD_STABLE, 1813 10000, 1814 100000 1815 ); 1816 } 1817 1818 return sdhci_reset(host, mask); 1819 } 1820 1821 static const struct sdhci_ops amd_sdhci_pci_ops = { 1822 .set_clock = sdhci_set_clock, 1823 .enable_dma = sdhci_pci_enable_dma, 1824 .set_bus_width = sdhci_set_bus_width, 1825 .reset = amd_sdhci_reset, 1826 .set_uhs_signaling = sdhci_set_uhs_signaling, 1827 }; 1828 1829 static const struct sdhci_pci_fixes sdhci_amd = { 1830 .probe = amd_probe, 1831 .ops = &amd_sdhci_pci_ops, 1832 .probe_slot = amd_probe_slot, 1833 }; 1834 1835 static const struct pci_device_id pci_ids[] = { 1836 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh), 1837 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc), 1838 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc), 1839 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc), 1840 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712), 1841 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712), 1842 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714), 1843 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714), 1844 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe), 1845 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron), 1846 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron), 1847 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron), 1848 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron), 1849 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt), 1850 SDHCI_PCI_DEVICE(VIA, 95D0, via), 1851 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx), 1852 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk), 1853 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0), 1854 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2), 1855 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2), 1856 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd), 1857 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio), 1858 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio), 1859 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc), 1860 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc), 1861 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio), 1862 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio), 1863 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc), 1864 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio), 1865 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio), 1866 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd), 1867 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc), 1868 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc), 1869 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio), 1870 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd), 1871 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd), 1872 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio), 1873 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio), 1874 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc), 1875 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc), 1876 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc), 1877 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc), 1878 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio), 1879 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd), 1880 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc), 1881 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc), 1882 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc), 1883 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio), 1884 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd), 1885 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc), 1886 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio), 1887 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd), 1888 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc), 1889 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio), 1890 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd), 1891 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc), 1892 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio), 1893 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd), 1894 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc), 1895 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd), 1896 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd), 1897 SDHCI_PCI_DEVICE(INTEL, ICP_EMMC, intel_glk_emmc), 1898 SDHCI_PCI_DEVICE(INTEL, ICP_SD, intel_byt_sd), 1899 SDHCI_PCI_DEVICE(INTEL, EHL_EMMC, intel_glk_emmc), 1900 SDHCI_PCI_DEVICE(INTEL, EHL_SD, intel_byt_sd), 1901 SDHCI_PCI_DEVICE(INTEL, CML_EMMC, intel_glk_emmc), 1902 SDHCI_PCI_DEVICE(INTEL, CML_SD, intel_byt_sd), 1903 SDHCI_PCI_DEVICE(INTEL, CMLH_SD, intel_byt_sd), 1904 SDHCI_PCI_DEVICE(INTEL, JSL_EMMC, intel_glk_emmc), 1905 SDHCI_PCI_DEVICE(INTEL, JSL_SD, intel_byt_sd), 1906 SDHCI_PCI_DEVICE(O2, 8120, o2), 1907 SDHCI_PCI_DEVICE(O2, 8220, o2), 1908 SDHCI_PCI_DEVICE(O2, 8221, o2), 1909 SDHCI_PCI_DEVICE(O2, 8320, o2), 1910 SDHCI_PCI_DEVICE(O2, 8321, o2), 1911 SDHCI_PCI_DEVICE(O2, FUJIN2, o2), 1912 SDHCI_PCI_DEVICE(O2, SDS0, o2), 1913 SDHCI_PCI_DEVICE(O2, SDS1, o2), 1914 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2), 1915 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), 1916 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan), 1917 SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps), 1918 SDHCI_PCI_DEVICE(GLI, 9750, gl9750), 1919 SDHCI_PCI_DEVICE(GLI, 9755, gl9755), 1920 SDHCI_PCI_DEVICE(GLI, 9763E, gl9763e), 1921 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), 1922 /* Generic SD host controller */ 1923 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, 1924 { /* end: all zeroes */ }, 1925 }; 1926 1927 MODULE_DEVICE_TABLE(pci, pci_ids); 1928 1929 /*****************************************************************************\ 1930 * * 1931 * SDHCI core callbacks * 1932 * * 1933 \*****************************************************************************/ 1934 1935 int sdhci_pci_enable_dma(struct sdhci_host *host) 1936 { 1937 struct sdhci_pci_slot *slot; 1938 struct pci_dev *pdev; 1939 1940 slot = sdhci_priv(host); 1941 pdev = slot->chip->pdev; 1942 1943 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1944 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1945 (host->flags & SDHCI_USE_SDMA)) { 1946 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1947 "doesn't fully claim to support it.\n"); 1948 } 1949 1950 pci_set_master(pdev); 1951 1952 return 0; 1953 } 1954 1955 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1956 { 1957 struct sdhci_pci_slot *slot = sdhci_priv(host); 1958 int rst_n_gpio = slot->rst_n_gpio; 1959 1960 if (!gpio_is_valid(rst_n_gpio)) 1961 return; 1962 gpio_set_value_cansleep(rst_n_gpio, 0); 1963 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1964 udelay(10); 1965 gpio_set_value_cansleep(rst_n_gpio, 1); 1966 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1967 usleep_range(300, 1000); 1968 } 1969 1970 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1971 { 1972 struct sdhci_pci_slot *slot = sdhci_priv(host); 1973 1974 if (slot->hw_reset) 1975 slot->hw_reset(host); 1976 } 1977 1978 static const struct sdhci_ops sdhci_pci_ops = { 1979 .set_clock = sdhci_set_clock, 1980 .enable_dma = sdhci_pci_enable_dma, 1981 .set_bus_width = sdhci_set_bus_width, 1982 .reset = sdhci_reset, 1983 .set_uhs_signaling = sdhci_set_uhs_signaling, 1984 .hw_reset = sdhci_pci_hw_reset, 1985 }; 1986 1987 /*****************************************************************************\ 1988 * * 1989 * Suspend/resume * 1990 * * 1991 \*****************************************************************************/ 1992 1993 #ifdef CONFIG_PM_SLEEP 1994 static int sdhci_pci_suspend(struct device *dev) 1995 { 1996 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 1997 1998 if (!chip) 1999 return 0; 2000 2001 if (chip->fixes && chip->fixes->suspend) 2002 return chip->fixes->suspend(chip); 2003 2004 return sdhci_pci_suspend_host(chip); 2005 } 2006 2007 static int sdhci_pci_resume(struct device *dev) 2008 { 2009 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2010 2011 if (!chip) 2012 return 0; 2013 2014 if (chip->fixes && chip->fixes->resume) 2015 return chip->fixes->resume(chip); 2016 2017 return sdhci_pci_resume_host(chip); 2018 } 2019 #endif 2020 2021 #ifdef CONFIG_PM 2022 static int sdhci_pci_runtime_suspend(struct device *dev) 2023 { 2024 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2025 2026 if (!chip) 2027 return 0; 2028 2029 if (chip->fixes && chip->fixes->runtime_suspend) 2030 return chip->fixes->runtime_suspend(chip); 2031 2032 return sdhci_pci_runtime_suspend_host(chip); 2033 } 2034 2035 static int sdhci_pci_runtime_resume(struct device *dev) 2036 { 2037 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2038 2039 if (!chip) 2040 return 0; 2041 2042 if (chip->fixes && chip->fixes->runtime_resume) 2043 return chip->fixes->runtime_resume(chip); 2044 2045 return sdhci_pci_runtime_resume_host(chip); 2046 } 2047 #endif 2048 2049 static const struct dev_pm_ops sdhci_pci_pm_ops = { 2050 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 2051 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 2052 sdhci_pci_runtime_resume, NULL) 2053 }; 2054 2055 /*****************************************************************************\ 2056 * * 2057 * Device probing/removal * 2058 * * 2059 \*****************************************************************************/ 2060 2061 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 2062 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 2063 int slotno) 2064 { 2065 struct sdhci_pci_slot *slot; 2066 struct sdhci_host *host; 2067 int ret, bar = first_bar + slotno; 2068 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 2069 2070 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 2071 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 2072 return ERR_PTR(-ENODEV); 2073 } 2074 2075 if (pci_resource_len(pdev, bar) < 0x100) { 2076 dev_err(&pdev->dev, "Invalid iomem size. You may " 2077 "experience problems.\n"); 2078 } 2079 2080 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 2081 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 2082 return ERR_PTR(-ENODEV); 2083 } 2084 2085 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 2086 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 2087 return ERR_PTR(-ENODEV); 2088 } 2089 2090 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 2091 if (IS_ERR(host)) { 2092 dev_err(&pdev->dev, "cannot allocate host\n"); 2093 return ERR_CAST(host); 2094 } 2095 2096 slot = sdhci_priv(host); 2097 2098 slot->chip = chip; 2099 slot->host = host; 2100 slot->rst_n_gpio = -EINVAL; 2101 slot->cd_gpio = -EINVAL; 2102 slot->cd_idx = -1; 2103 2104 /* Retrieve platform data if there is any */ 2105 if (*sdhci_pci_get_data) 2106 slot->data = sdhci_pci_get_data(pdev, slotno); 2107 2108 if (slot->data) { 2109 if (slot->data->setup) { 2110 ret = slot->data->setup(slot->data); 2111 if (ret) { 2112 dev_err(&pdev->dev, "platform setup failed\n"); 2113 goto free; 2114 } 2115 } 2116 slot->rst_n_gpio = slot->data->rst_n_gpio; 2117 slot->cd_gpio = slot->data->cd_gpio; 2118 } 2119 2120 host->hw_name = "PCI"; 2121 host->ops = chip->fixes && chip->fixes->ops ? 2122 chip->fixes->ops : 2123 &sdhci_pci_ops; 2124 host->quirks = chip->quirks; 2125 host->quirks2 = chip->quirks2; 2126 2127 host->irq = pdev->irq; 2128 2129 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 2130 if (ret) { 2131 dev_err(&pdev->dev, "cannot request region\n"); 2132 goto cleanup; 2133 } 2134 2135 host->ioaddr = pcim_iomap_table(pdev)[bar]; 2136 2137 if (chip->fixes && chip->fixes->probe_slot) { 2138 ret = chip->fixes->probe_slot(slot); 2139 if (ret) 2140 goto cleanup; 2141 } 2142 2143 if (gpio_is_valid(slot->rst_n_gpio)) { 2144 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 2145 gpio_direction_output(slot->rst_n_gpio, 1); 2146 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 2147 slot->hw_reset = sdhci_pci_gpio_hw_reset; 2148 } else { 2149 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 2150 slot->rst_n_gpio = -EINVAL; 2151 } 2152 } 2153 2154 host->mmc->pm_caps = MMC_PM_KEEP_POWER; 2155 host->mmc->slotno = slotno; 2156 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 2157 2158 if (device_can_wakeup(&pdev->dev)) 2159 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ; 2160 2161 if (host->mmc->caps & MMC_CAP_CD_WAKE) 2162 device_init_wakeup(&pdev->dev, true); 2163 2164 if (slot->cd_idx >= 0) { 2165 ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx, 2166 slot->cd_override_level, 0); 2167 if (ret && ret != -EPROBE_DEFER) 2168 ret = mmc_gpiod_request_cd(host->mmc, NULL, 2169 slot->cd_idx, 2170 slot->cd_override_level, 2171 0); 2172 if (ret == -EPROBE_DEFER) 2173 goto remove; 2174 2175 if (ret) { 2176 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 2177 slot->cd_idx = -1; 2178 } 2179 } 2180 2181 if (chip->fixes && chip->fixes->add_host) 2182 ret = chip->fixes->add_host(slot); 2183 else 2184 ret = sdhci_add_host(host); 2185 if (ret) 2186 goto remove; 2187 2188 sdhci_pci_add_own_cd(slot); 2189 2190 /* 2191 * Check if the chip needs a separate GPIO for card detect to wake up 2192 * from runtime suspend. If it is not there, don't allow runtime PM. 2193 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 2194 */ 2195 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 2196 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 2197 chip->allow_runtime_pm = false; 2198 2199 return slot; 2200 2201 remove: 2202 if (chip->fixes && chip->fixes->remove_slot) 2203 chip->fixes->remove_slot(slot, 0); 2204 2205 cleanup: 2206 if (slot->data && slot->data->cleanup) 2207 slot->data->cleanup(slot->data); 2208 2209 free: 2210 sdhci_free_host(host); 2211 2212 return ERR_PTR(ret); 2213 } 2214 2215 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 2216 { 2217 int dead; 2218 u32 scratch; 2219 2220 sdhci_pci_remove_own_cd(slot); 2221 2222 dead = 0; 2223 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 2224 if (scratch == (u32)-1) 2225 dead = 1; 2226 2227 sdhci_remove_host(slot->host, dead); 2228 2229 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 2230 slot->chip->fixes->remove_slot(slot, dead); 2231 2232 if (slot->data && slot->data->cleanup) 2233 slot->data->cleanup(slot->data); 2234 2235 sdhci_free_host(slot->host); 2236 } 2237 2238 static void sdhci_pci_runtime_pm_allow(struct device *dev) 2239 { 2240 pm_suspend_ignore_children(dev, 1); 2241 pm_runtime_set_autosuspend_delay(dev, 50); 2242 pm_runtime_use_autosuspend(dev); 2243 pm_runtime_allow(dev); 2244 /* Stay active until mmc core scans for a card */ 2245 pm_runtime_put_noidle(dev); 2246 } 2247 2248 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 2249 { 2250 pm_runtime_forbid(dev); 2251 pm_runtime_get_noresume(dev); 2252 } 2253 2254 static int sdhci_pci_probe(struct pci_dev *pdev, 2255 const struct pci_device_id *ent) 2256 { 2257 struct sdhci_pci_chip *chip; 2258 struct sdhci_pci_slot *slot; 2259 2260 u8 slots, first_bar; 2261 int ret, i; 2262 2263 BUG_ON(pdev == NULL); 2264 BUG_ON(ent == NULL); 2265 2266 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 2267 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 2268 2269 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 2270 if (ret) 2271 return ret; 2272 2273 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 2274 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 2275 2276 BUG_ON(slots > MAX_SLOTS); 2277 2278 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 2279 if (ret) 2280 return ret; 2281 2282 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 2283 2284 if (first_bar > 5) { 2285 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 2286 return -ENODEV; 2287 } 2288 2289 ret = pcim_enable_device(pdev); 2290 if (ret) 2291 return ret; 2292 2293 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 2294 if (!chip) 2295 return -ENOMEM; 2296 2297 chip->pdev = pdev; 2298 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 2299 if (chip->fixes) { 2300 chip->quirks = chip->fixes->quirks; 2301 chip->quirks2 = chip->fixes->quirks2; 2302 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 2303 } 2304 chip->num_slots = slots; 2305 chip->pm_retune = true; 2306 chip->rpm_retune = true; 2307 2308 pci_set_drvdata(pdev, chip); 2309 2310 if (chip->fixes && chip->fixes->probe) { 2311 ret = chip->fixes->probe(chip); 2312 if (ret) 2313 return ret; 2314 } 2315 2316 slots = chip->num_slots; /* Quirk may have changed this */ 2317 2318 for (i = 0; i < slots; i++) { 2319 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 2320 if (IS_ERR(slot)) { 2321 for (i--; i >= 0; i--) 2322 sdhci_pci_remove_slot(chip->slots[i]); 2323 return PTR_ERR(slot); 2324 } 2325 2326 chip->slots[i] = slot; 2327 } 2328 2329 if (chip->allow_runtime_pm) 2330 sdhci_pci_runtime_pm_allow(&pdev->dev); 2331 2332 return 0; 2333 } 2334 2335 static void sdhci_pci_remove(struct pci_dev *pdev) 2336 { 2337 int i; 2338 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 2339 2340 if (chip->allow_runtime_pm) 2341 sdhci_pci_runtime_pm_forbid(&pdev->dev); 2342 2343 for (i = 0; i < chip->num_slots; i++) 2344 sdhci_pci_remove_slot(chip->slots[i]); 2345 } 2346 2347 static struct pci_driver sdhci_driver = { 2348 .name = "sdhci-pci", 2349 .id_table = pci_ids, 2350 .probe = sdhci_pci_probe, 2351 .remove = sdhci_pci_remove, 2352 .driver = { 2353 .pm = &sdhci_pci_pm_ops 2354 }, 2355 }; 2356 2357 module_pci_driver(sdhci_driver); 2358 2359 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 2360 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 2361 MODULE_LICENSE("GPL"); 2362