1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 3 * 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 5 * 6 * Thanks to the following companies for their support: 7 * 8 * - JMicron (hardware and technical support) 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/string.h> 13 #include <linux/delay.h> 14 #include <linux/highmem.h> 15 #include <linux/module.h> 16 #include <linux/pci.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/slab.h> 19 #include <linux/device.h> 20 #include <linux/mmc/host.h> 21 #include <linux/mmc/mmc.h> 22 #include <linux/scatterlist.h> 23 #include <linux/io.h> 24 #include <linux/iopoll.h> 25 #include <linux/gpio.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/mmc/slot-gpio.h> 28 #include <linux/mmc/sdhci-pci-data.h> 29 #include <linux/acpi.h> 30 #include <linux/dmi.h> 31 32 #ifdef CONFIG_X86 33 #include <asm/iosf_mbi.h> 34 #endif 35 36 #include "cqhci.h" 37 38 #include "sdhci.h" 39 #include "sdhci-pci.h" 40 41 static void sdhci_pci_hw_reset(struct sdhci_host *host); 42 43 #ifdef CONFIG_PM_SLEEP 44 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip) 45 { 46 mmc_pm_flag_t pm_flags = 0; 47 bool cap_cd_wake = false; 48 int i; 49 50 for (i = 0; i < chip->num_slots; i++) { 51 struct sdhci_pci_slot *slot = chip->slots[i]; 52 53 if (slot) { 54 pm_flags |= slot->host->mmc->pm_flags; 55 if (slot->host->mmc->caps & MMC_CAP_CD_WAKE) 56 cap_cd_wake = true; 57 } 58 } 59 60 if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ)) 61 return device_wakeup_enable(&chip->pdev->dev); 62 else if (!cap_cd_wake) 63 return device_wakeup_disable(&chip->pdev->dev); 64 65 return 0; 66 } 67 68 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 69 { 70 int i, ret; 71 72 sdhci_pci_init_wakeup(chip); 73 74 for (i = 0; i < chip->num_slots; i++) { 75 struct sdhci_pci_slot *slot = chip->slots[i]; 76 struct sdhci_host *host; 77 78 if (!slot) 79 continue; 80 81 host = slot->host; 82 83 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 84 mmc_retune_needed(host->mmc); 85 86 ret = sdhci_suspend_host(host); 87 if (ret) 88 goto err_pci_suspend; 89 90 if (device_may_wakeup(&chip->pdev->dev)) 91 mmc_gpio_set_cd_wake(host->mmc, true); 92 } 93 94 return 0; 95 96 err_pci_suspend: 97 while (--i >= 0) 98 sdhci_resume_host(chip->slots[i]->host); 99 return ret; 100 } 101 102 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip) 103 { 104 struct sdhci_pci_slot *slot; 105 int i, ret; 106 107 for (i = 0; i < chip->num_slots; i++) { 108 slot = chip->slots[i]; 109 if (!slot) 110 continue; 111 112 ret = sdhci_resume_host(slot->host); 113 if (ret) 114 return ret; 115 116 mmc_gpio_set_cd_wake(slot->host->mmc, false); 117 } 118 119 return 0; 120 } 121 122 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip) 123 { 124 int ret; 125 126 ret = cqhci_suspend(chip->slots[0]->host->mmc); 127 if (ret) 128 return ret; 129 130 return sdhci_pci_suspend_host(chip); 131 } 132 133 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip) 134 { 135 int ret; 136 137 ret = sdhci_pci_resume_host(chip); 138 if (ret) 139 return ret; 140 141 return cqhci_resume(chip->slots[0]->host->mmc); 142 } 143 #endif 144 145 #ifdef CONFIG_PM 146 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip) 147 { 148 struct sdhci_pci_slot *slot; 149 struct sdhci_host *host; 150 int i, ret; 151 152 for (i = 0; i < chip->num_slots; i++) { 153 slot = chip->slots[i]; 154 if (!slot) 155 continue; 156 157 host = slot->host; 158 159 ret = sdhci_runtime_suspend_host(host); 160 if (ret) 161 goto err_pci_runtime_suspend; 162 163 if (chip->rpm_retune && 164 host->tuning_mode != SDHCI_TUNING_MODE_3) 165 mmc_retune_needed(host->mmc); 166 } 167 168 return 0; 169 170 err_pci_runtime_suspend: 171 while (--i >= 0) 172 sdhci_runtime_resume_host(chip->slots[i]->host, 0); 173 return ret; 174 } 175 176 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip) 177 { 178 struct sdhci_pci_slot *slot; 179 int i, ret; 180 181 for (i = 0; i < chip->num_slots; i++) { 182 slot = chip->slots[i]; 183 if (!slot) 184 continue; 185 186 ret = sdhci_runtime_resume_host(slot->host, 0); 187 if (ret) 188 return ret; 189 } 190 191 return 0; 192 } 193 194 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip) 195 { 196 int ret; 197 198 ret = cqhci_suspend(chip->slots[0]->host->mmc); 199 if (ret) 200 return ret; 201 202 return sdhci_pci_runtime_suspend_host(chip); 203 } 204 205 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip) 206 { 207 int ret; 208 209 ret = sdhci_pci_runtime_resume_host(chip); 210 if (ret) 211 return ret; 212 213 return cqhci_resume(chip->slots[0]->host->mmc); 214 } 215 #endif 216 217 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask) 218 { 219 int cmd_error = 0; 220 int data_error = 0; 221 222 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 223 return intmask; 224 225 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 226 227 return 0; 228 } 229 230 static void sdhci_pci_dumpregs(struct mmc_host *mmc) 231 { 232 sdhci_dumpregs(mmc_priv(mmc)); 233 } 234 235 static void sdhci_cqhci_reset(struct sdhci_host *host, u8 mask) 236 { 237 if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) && 238 host->mmc->cqe_private) 239 cqhci_deactivate(host->mmc); 240 sdhci_reset(host, mask); 241 } 242 243 /*****************************************************************************\ 244 * * 245 * Hardware specific quirk handling * 246 * * 247 \*****************************************************************************/ 248 249 static int ricoh_probe(struct sdhci_pci_chip *chip) 250 { 251 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 252 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 253 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 254 return 0; 255 } 256 257 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 258 { 259 slot->host->caps = 260 FIELD_PREP(SDHCI_TIMEOUT_CLK_MASK, 0x21) | 261 FIELD_PREP(SDHCI_CLOCK_BASE_MASK, 0x21) | 262 SDHCI_TIMEOUT_CLK_UNIT | 263 SDHCI_CAN_VDD_330 | 264 SDHCI_CAN_DO_HISPD | 265 SDHCI_CAN_DO_SDMA; 266 return 0; 267 } 268 269 #ifdef CONFIG_PM_SLEEP 270 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 271 { 272 /* Apply a delay to allow controller to settle */ 273 /* Otherwise it becomes confused if card state changed 274 during suspend */ 275 msleep(500); 276 return sdhci_pci_resume_host(chip); 277 } 278 #endif 279 280 static const struct sdhci_pci_fixes sdhci_ricoh = { 281 .probe = ricoh_probe, 282 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 283 SDHCI_QUIRK_FORCE_DMA | 284 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 285 }; 286 287 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 288 .probe_slot = ricoh_mmc_probe_slot, 289 #ifdef CONFIG_PM_SLEEP 290 .resume = ricoh_mmc_resume, 291 #endif 292 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 293 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 294 SDHCI_QUIRK_NO_CARD_NO_RESET | 295 SDHCI_QUIRK_MISSING_CAPS 296 }; 297 298 static const struct sdhci_pci_fixes sdhci_ene_712 = { 299 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 300 SDHCI_QUIRK_BROKEN_DMA, 301 }; 302 303 static const struct sdhci_pci_fixes sdhci_ene_714 = { 304 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 305 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 306 SDHCI_QUIRK_BROKEN_DMA, 307 }; 308 309 static const struct sdhci_pci_fixes sdhci_cafe = { 310 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 311 SDHCI_QUIRK_NO_BUSY_IRQ | 312 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 313 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 314 }; 315 316 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 317 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 318 }; 319 320 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 321 { 322 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 323 return 0; 324 } 325 326 /* 327 * ADMA operation is disabled for Moorestown platform due to 328 * hardware bugs. 329 */ 330 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 331 { 332 /* 333 * slots number is fixed here for MRST as SDIO3/5 are never used and 334 * have hardware bugs. 335 */ 336 chip->num_slots = 1; 337 return 0; 338 } 339 340 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 341 { 342 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 343 return 0; 344 } 345 346 #ifdef CONFIG_PM 347 348 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 349 { 350 struct sdhci_pci_slot *slot = dev_id; 351 struct sdhci_host *host = slot->host; 352 353 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 354 return IRQ_HANDLED; 355 } 356 357 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 358 { 359 int err, irq, gpio = slot->cd_gpio; 360 361 slot->cd_gpio = -EINVAL; 362 slot->cd_irq = -EINVAL; 363 364 if (!gpio_is_valid(gpio)) 365 return; 366 367 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 368 if (err < 0) 369 goto out; 370 371 err = gpio_direction_input(gpio); 372 if (err < 0) 373 goto out_free; 374 375 irq = gpio_to_irq(gpio); 376 if (irq < 0) 377 goto out_free; 378 379 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 380 IRQF_TRIGGER_FALLING, "sd_cd", slot); 381 if (err) 382 goto out_free; 383 384 slot->cd_gpio = gpio; 385 slot->cd_irq = irq; 386 387 return; 388 389 out_free: 390 devm_gpio_free(&slot->chip->pdev->dev, gpio); 391 out: 392 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 393 } 394 395 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 396 { 397 if (slot->cd_irq >= 0) 398 free_irq(slot->cd_irq, slot); 399 } 400 401 #else 402 403 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 404 { 405 } 406 407 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 408 { 409 } 410 411 #endif 412 413 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 414 { 415 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 416 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC; 417 return 0; 418 } 419 420 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 421 { 422 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 423 return 0; 424 } 425 426 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 427 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 428 .probe_slot = mrst_hc_probe_slot, 429 }; 430 431 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 432 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 433 .probe = mrst_hc_probe, 434 }; 435 436 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 437 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 438 .allow_runtime_pm = true, 439 .own_cd_for_runtime_pm = true, 440 }; 441 442 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 443 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 444 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 445 .allow_runtime_pm = true, 446 .probe_slot = mfd_sdio_probe_slot, 447 }; 448 449 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 450 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 451 .allow_runtime_pm = true, 452 .probe_slot = mfd_emmc_probe_slot, 453 }; 454 455 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 456 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 457 .probe_slot = pch_hc_probe_slot, 458 }; 459 460 #ifdef CONFIG_X86 461 462 #define BYT_IOSF_SCCEP 0x63 463 #define BYT_IOSF_OCP_NETCTRL0 0x1078 464 #define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8) 465 466 static void byt_ocp_setting(struct pci_dev *pdev) 467 { 468 u32 val = 0; 469 470 if (pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC && 471 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SDIO && 472 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SD && 473 pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC2) 474 return; 475 476 if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0, 477 &val)) { 478 dev_err(&pdev->dev, "%s read error\n", __func__); 479 return; 480 } 481 482 if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE)) 483 return; 484 485 val &= ~BYT_IOSF_OCP_TIMEOUT_BASE; 486 487 if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0, 488 val)) { 489 dev_err(&pdev->dev, "%s write error\n", __func__); 490 return; 491 } 492 493 dev_dbg(&pdev->dev, "%s completed\n", __func__); 494 } 495 496 #else 497 498 static inline void byt_ocp_setting(struct pci_dev *pdev) 499 { 500 } 501 502 #endif 503 504 enum { 505 INTEL_DSM_FNS = 0, 506 INTEL_DSM_V18_SWITCH = 3, 507 INTEL_DSM_V33_SWITCH = 4, 508 INTEL_DSM_DRV_STRENGTH = 9, 509 INTEL_DSM_D3_RETUNE = 10, 510 }; 511 512 struct intel_host { 513 u32 dsm_fns; 514 int drv_strength; 515 bool d3_retune; 516 bool rpm_retune_ok; 517 u32 glk_rx_ctrl1; 518 u32 glk_tun_val; 519 }; 520 521 static const guid_t intel_dsm_guid = 522 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F, 523 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61); 524 525 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 526 unsigned int fn, u32 *result) 527 { 528 union acpi_object *obj; 529 int err = 0; 530 size_t len; 531 532 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL); 533 if (!obj) 534 return -EOPNOTSUPP; 535 536 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { 537 err = -EINVAL; 538 goto out; 539 } 540 541 len = min_t(size_t, obj->buffer.length, 4); 542 543 *result = 0; 544 memcpy(result, obj->buffer.pointer, len); 545 out: 546 ACPI_FREE(obj); 547 548 return err; 549 } 550 551 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 552 unsigned int fn, u32 *result) 553 { 554 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 555 return -EOPNOTSUPP; 556 557 return __intel_dsm(intel_host, dev, fn, result); 558 } 559 560 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 561 struct mmc_host *mmc) 562 { 563 int err; 564 u32 val; 565 566 intel_host->d3_retune = true; 567 568 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 569 if (err) { 570 pr_debug("%s: DSM not supported, error %d\n", 571 mmc_hostname(mmc), err); 572 return; 573 } 574 575 pr_debug("%s: DSM function mask %#x\n", 576 mmc_hostname(mmc), intel_host->dsm_fns); 577 578 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 579 intel_host->drv_strength = err ? 0 : val; 580 581 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 582 intel_host->d3_retune = err ? true : !!val; 583 } 584 585 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 586 { 587 u8 reg; 588 589 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 590 reg |= 0x10; 591 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 592 /* For eMMC, minimum is 1us but give it 9us for good measure */ 593 udelay(9); 594 reg &= ~0x10; 595 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 596 /* For eMMC, minimum is 200us but give it 300us for good measure */ 597 usleep_range(300, 1000); 598 } 599 600 static int intel_select_drive_strength(struct mmc_card *card, 601 unsigned int max_dtr, int host_drv, 602 int card_drv, int *drv_type) 603 { 604 struct sdhci_host *host = mmc_priv(card->host); 605 struct sdhci_pci_slot *slot = sdhci_priv(host); 606 struct intel_host *intel_host = sdhci_pci_priv(slot); 607 608 if (!(mmc_driver_type_mask(intel_host->drv_strength) & card_drv)) 609 return 0; 610 611 return intel_host->drv_strength; 612 } 613 614 static int bxt_get_cd(struct mmc_host *mmc) 615 { 616 int gpio_cd = mmc_gpio_get_cd(mmc); 617 struct sdhci_host *host = mmc_priv(mmc); 618 unsigned long flags; 619 int ret = 0; 620 621 if (!gpio_cd) 622 return 0; 623 624 spin_lock_irqsave(&host->lock, flags); 625 626 if (host->flags & SDHCI_DEVICE_DEAD) 627 goto out; 628 629 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 630 out: 631 spin_unlock_irqrestore(&host->lock, flags); 632 633 return ret; 634 } 635 636 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 637 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 638 639 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 640 unsigned short vdd) 641 { 642 int cntr; 643 u8 reg; 644 645 sdhci_set_power(host, mode, vdd); 646 647 if (mode == MMC_POWER_OFF) 648 return; 649 650 /* 651 * Bus power might not enable after D3 -> D0 transition due to the 652 * present state not yet having propagated. Retry for up to 2ms. 653 */ 654 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 655 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 656 if (reg & SDHCI_POWER_ON) 657 break; 658 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 659 reg |= SDHCI_POWER_ON; 660 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 661 } 662 } 663 664 #define INTEL_HS400_ES_REG 0x78 665 #define INTEL_HS400_ES_BIT BIT(0) 666 667 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc, 668 struct mmc_ios *ios) 669 { 670 struct sdhci_host *host = mmc_priv(mmc); 671 u32 val; 672 673 val = sdhci_readl(host, INTEL_HS400_ES_REG); 674 if (ios->enhanced_strobe) 675 val |= INTEL_HS400_ES_BIT; 676 else 677 val &= ~INTEL_HS400_ES_BIT; 678 sdhci_writel(host, val, INTEL_HS400_ES_REG); 679 } 680 681 static int intel_start_signal_voltage_switch(struct mmc_host *mmc, 682 struct mmc_ios *ios) 683 { 684 struct device *dev = mmc_dev(mmc); 685 struct sdhci_host *host = mmc_priv(mmc); 686 struct sdhci_pci_slot *slot = sdhci_priv(host); 687 struct intel_host *intel_host = sdhci_pci_priv(slot); 688 unsigned int fn; 689 u32 result = 0; 690 int err; 691 692 err = sdhci_start_signal_voltage_switch(mmc, ios); 693 if (err) 694 return err; 695 696 switch (ios->signal_voltage) { 697 case MMC_SIGNAL_VOLTAGE_330: 698 fn = INTEL_DSM_V33_SWITCH; 699 break; 700 case MMC_SIGNAL_VOLTAGE_180: 701 fn = INTEL_DSM_V18_SWITCH; 702 break; 703 default: 704 return 0; 705 } 706 707 err = intel_dsm(intel_host, dev, fn, &result); 708 pr_debug("%s: %s DSM fn %u error %d result %u\n", 709 mmc_hostname(mmc), __func__, fn, err, result); 710 711 return 0; 712 } 713 714 static const struct sdhci_ops sdhci_intel_byt_ops = { 715 .set_clock = sdhci_set_clock, 716 .set_power = sdhci_intel_set_power, 717 .enable_dma = sdhci_pci_enable_dma, 718 .set_bus_width = sdhci_set_bus_width, 719 .reset = sdhci_reset, 720 .set_uhs_signaling = sdhci_set_uhs_signaling, 721 .hw_reset = sdhci_pci_hw_reset, 722 }; 723 724 static const struct sdhci_ops sdhci_intel_glk_ops = { 725 .set_clock = sdhci_set_clock, 726 .set_power = sdhci_intel_set_power, 727 .enable_dma = sdhci_pci_enable_dma, 728 .set_bus_width = sdhci_set_bus_width, 729 .reset = sdhci_cqhci_reset, 730 .set_uhs_signaling = sdhci_set_uhs_signaling, 731 .hw_reset = sdhci_pci_hw_reset, 732 .irq = sdhci_cqhci_irq, 733 }; 734 735 static void byt_read_dsm(struct sdhci_pci_slot *slot) 736 { 737 struct intel_host *intel_host = sdhci_pci_priv(slot); 738 struct device *dev = &slot->chip->pdev->dev; 739 struct mmc_host *mmc = slot->host->mmc; 740 741 intel_dsm_init(intel_host, dev, mmc); 742 slot->chip->rpm_retune = intel_host->d3_retune; 743 } 744 745 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode) 746 { 747 int err = sdhci_execute_tuning(mmc, opcode); 748 struct sdhci_host *host = mmc_priv(mmc); 749 750 if (err) 751 return err; 752 753 /* 754 * Tuning can leave the IP in an active state (Buffer Read Enable bit 755 * set) which prevents the entry to low power states (i.e. S0i3). Data 756 * reset will clear it. 757 */ 758 sdhci_reset(host, SDHCI_RESET_DATA); 759 760 return 0; 761 } 762 763 static void byt_probe_slot(struct sdhci_pci_slot *slot) 764 { 765 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 766 struct device *dev = &slot->chip->pdev->dev; 767 struct mmc_host *mmc = slot->host->mmc; 768 769 byt_read_dsm(slot); 770 771 byt_ocp_setting(slot->chip->pdev); 772 773 ops->execute_tuning = intel_execute_tuning; 774 ops->start_signal_voltage_switch = intel_start_signal_voltage_switch; 775 776 device_property_read_u32(dev, "max-frequency", &mmc->f_max); 777 } 778 779 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 780 { 781 byt_probe_slot(slot); 782 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 783 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 784 MMC_CAP_CMD_DURING_TFR | 785 MMC_CAP_WAIT_WHILE_BUSY; 786 slot->hw_reset = sdhci_pci_int_hw_reset; 787 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 788 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 789 slot->host->mmc_host_ops.select_drive_strength = 790 intel_select_drive_strength; 791 return 0; 792 } 793 794 static bool glk_broken_cqhci(struct sdhci_pci_slot *slot) 795 { 796 return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 797 dmi_match(DMI_BIOS_VENDOR, "LENOVO"); 798 } 799 800 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot) 801 { 802 int ret = byt_emmc_probe_slot(slot); 803 804 if (!glk_broken_cqhci(slot)) 805 slot->host->mmc->caps2 |= MMC_CAP2_CQE; 806 807 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) { 808 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES, 809 slot->host->mmc_host_ops.hs400_enhanced_strobe = 810 intel_hs400_enhanced_strobe; 811 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; 812 } 813 814 return ret; 815 } 816 817 static const struct cqhci_host_ops glk_cqhci_ops = { 818 .enable = sdhci_cqe_enable, 819 .disable = sdhci_cqe_disable, 820 .dumpregs = sdhci_pci_dumpregs, 821 }; 822 823 static int glk_emmc_add_host(struct sdhci_pci_slot *slot) 824 { 825 struct device *dev = &slot->chip->pdev->dev; 826 struct sdhci_host *host = slot->host; 827 struct cqhci_host *cq_host; 828 bool dma64; 829 int ret; 830 831 ret = sdhci_setup_host(host); 832 if (ret) 833 return ret; 834 835 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); 836 if (!cq_host) { 837 ret = -ENOMEM; 838 goto cleanup; 839 } 840 841 cq_host->mmio = host->ioaddr + 0x200; 842 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 843 cq_host->ops = &glk_cqhci_ops; 844 845 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 846 if (dma64) 847 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 848 849 ret = cqhci_init(cq_host, host->mmc, dma64); 850 if (ret) 851 goto cleanup; 852 853 ret = __sdhci_add_host(host); 854 if (ret) 855 goto cleanup; 856 857 return 0; 858 859 cleanup: 860 sdhci_cleanup_host(host); 861 return ret; 862 } 863 864 #ifdef CONFIG_PM 865 #define GLK_RX_CTRL1 0x834 866 #define GLK_TUN_VAL 0x840 867 #define GLK_PATH_PLL GENMASK(13, 8) 868 #define GLK_DLY GENMASK(6, 0) 869 /* Workaround firmware failing to restore the tuning value */ 870 static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp) 871 { 872 struct sdhci_pci_slot *slot = chip->slots[0]; 873 struct intel_host *intel_host = sdhci_pci_priv(slot); 874 struct sdhci_host *host = slot->host; 875 u32 glk_rx_ctrl1; 876 u32 glk_tun_val; 877 u32 dly; 878 879 if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc)) 880 return; 881 882 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1); 883 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL); 884 885 if (susp) { 886 intel_host->glk_rx_ctrl1 = glk_rx_ctrl1; 887 intel_host->glk_tun_val = glk_tun_val; 888 return; 889 } 890 891 if (!intel_host->glk_tun_val) 892 return; 893 894 if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) { 895 intel_host->rpm_retune_ok = true; 896 return; 897 } 898 899 dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) + 900 (intel_host->glk_tun_val << 1)); 901 if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1)) 902 return; 903 904 glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly; 905 sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1); 906 907 intel_host->rpm_retune_ok = true; 908 chip->rpm_retune = true; 909 mmc_retune_needed(host->mmc); 910 pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc)); 911 } 912 913 static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp) 914 { 915 if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 916 !chip->rpm_retune) 917 glk_rpm_retune_wa(chip, susp); 918 } 919 920 static int glk_runtime_suspend(struct sdhci_pci_chip *chip) 921 { 922 glk_rpm_retune_chk(chip, true); 923 924 return sdhci_cqhci_runtime_suspend(chip); 925 } 926 927 static int glk_runtime_resume(struct sdhci_pci_chip *chip) 928 { 929 glk_rpm_retune_chk(chip, false); 930 931 return sdhci_cqhci_runtime_resume(chip); 932 } 933 #endif 934 935 #ifdef CONFIG_ACPI 936 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 937 { 938 acpi_status status; 939 unsigned long long max_freq; 940 941 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 942 "MXFQ", NULL, &max_freq); 943 if (ACPI_FAILURE(status)) { 944 dev_err(&slot->chip->pdev->dev, 945 "MXFQ not found in acpi table\n"); 946 return -EINVAL; 947 } 948 949 slot->host->mmc->f_max = max_freq * 1000000; 950 951 return 0; 952 } 953 #else 954 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 955 { 956 return 0; 957 } 958 #endif 959 960 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 961 { 962 int err; 963 964 byt_probe_slot(slot); 965 966 err = ni_set_max_freq(slot); 967 if (err) 968 return err; 969 970 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 971 MMC_CAP_WAIT_WHILE_BUSY; 972 return 0; 973 } 974 975 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 976 { 977 byt_probe_slot(slot); 978 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 979 MMC_CAP_WAIT_WHILE_BUSY; 980 return 0; 981 } 982 983 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 984 { 985 byt_probe_slot(slot); 986 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | 987 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE; 988 slot->cd_idx = 0; 989 slot->cd_override_level = true; 990 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 991 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 992 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 993 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) 994 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 995 996 if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI && 997 slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3) 998 slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V; 999 1000 return 0; 1001 } 1002 1003 #ifdef CONFIG_PM_SLEEP 1004 1005 static int byt_resume(struct sdhci_pci_chip *chip) 1006 { 1007 byt_ocp_setting(chip->pdev); 1008 1009 return sdhci_pci_resume_host(chip); 1010 } 1011 1012 #endif 1013 1014 #ifdef CONFIG_PM 1015 1016 static int byt_runtime_resume(struct sdhci_pci_chip *chip) 1017 { 1018 byt_ocp_setting(chip->pdev); 1019 1020 return sdhci_pci_runtime_resume_host(chip); 1021 } 1022 1023 #endif 1024 1025 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 1026 #ifdef CONFIG_PM_SLEEP 1027 .resume = byt_resume, 1028 #endif 1029 #ifdef CONFIG_PM 1030 .runtime_resume = byt_runtime_resume, 1031 #endif 1032 .allow_runtime_pm = true, 1033 .probe_slot = byt_emmc_probe_slot, 1034 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1035 SDHCI_QUIRK_NO_LED, 1036 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1037 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1038 SDHCI_QUIRK2_STOP_WITH_TC, 1039 .ops = &sdhci_intel_byt_ops, 1040 .priv_size = sizeof(struct intel_host), 1041 }; 1042 1043 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = { 1044 .allow_runtime_pm = true, 1045 .probe_slot = glk_emmc_probe_slot, 1046 .add_host = glk_emmc_add_host, 1047 #ifdef CONFIG_PM_SLEEP 1048 .suspend = sdhci_cqhci_suspend, 1049 .resume = sdhci_cqhci_resume, 1050 #endif 1051 #ifdef CONFIG_PM 1052 .runtime_suspend = glk_runtime_suspend, 1053 .runtime_resume = glk_runtime_resume, 1054 #endif 1055 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1056 SDHCI_QUIRK_NO_LED, 1057 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1058 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1059 SDHCI_QUIRK2_STOP_WITH_TC, 1060 .ops = &sdhci_intel_glk_ops, 1061 .priv_size = sizeof(struct intel_host), 1062 }; 1063 1064 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 1065 #ifdef CONFIG_PM_SLEEP 1066 .resume = byt_resume, 1067 #endif 1068 #ifdef CONFIG_PM 1069 .runtime_resume = byt_runtime_resume, 1070 #endif 1071 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1072 SDHCI_QUIRK_NO_LED, 1073 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1074 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1075 .allow_runtime_pm = true, 1076 .probe_slot = ni_byt_sdio_probe_slot, 1077 .ops = &sdhci_intel_byt_ops, 1078 .priv_size = sizeof(struct intel_host), 1079 }; 1080 1081 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 1082 #ifdef CONFIG_PM_SLEEP 1083 .resume = byt_resume, 1084 #endif 1085 #ifdef CONFIG_PM 1086 .runtime_resume = byt_runtime_resume, 1087 #endif 1088 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1089 SDHCI_QUIRK_NO_LED, 1090 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1091 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1092 .allow_runtime_pm = true, 1093 .probe_slot = byt_sdio_probe_slot, 1094 .ops = &sdhci_intel_byt_ops, 1095 .priv_size = sizeof(struct intel_host), 1096 }; 1097 1098 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 1099 #ifdef CONFIG_PM_SLEEP 1100 .resume = byt_resume, 1101 #endif 1102 #ifdef CONFIG_PM 1103 .runtime_resume = byt_runtime_resume, 1104 #endif 1105 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1106 SDHCI_QUIRK_NO_LED, 1107 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 1108 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1109 SDHCI_QUIRK2_STOP_WITH_TC, 1110 .allow_runtime_pm = true, 1111 .own_cd_for_runtime_pm = true, 1112 .probe_slot = byt_sd_probe_slot, 1113 .ops = &sdhci_intel_byt_ops, 1114 .priv_size = sizeof(struct intel_host), 1115 }; 1116 1117 /* Define Host controllers for Intel Merrifield platform */ 1118 #define INTEL_MRFLD_EMMC_0 0 1119 #define INTEL_MRFLD_EMMC_1 1 1120 #define INTEL_MRFLD_SD 2 1121 #define INTEL_MRFLD_SDIO 3 1122 1123 #ifdef CONFIG_ACPI 1124 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) 1125 { 1126 struct acpi_device *device, *child; 1127 1128 device = ACPI_COMPANION(&slot->chip->pdev->dev); 1129 if (!device) 1130 return; 1131 1132 acpi_device_fix_up_power(device); 1133 list_for_each_entry(child, &device->children, node) 1134 if (child->status.present && child->status.enabled) 1135 acpi_device_fix_up_power(child); 1136 } 1137 #else 1138 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {} 1139 #endif 1140 1141 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 1142 { 1143 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 1144 1145 switch (func) { 1146 case INTEL_MRFLD_EMMC_0: 1147 case INTEL_MRFLD_EMMC_1: 1148 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1149 MMC_CAP_8_BIT_DATA | 1150 MMC_CAP_1_8V_DDR; 1151 break; 1152 case INTEL_MRFLD_SD: 1153 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1154 break; 1155 case INTEL_MRFLD_SDIO: 1156 /* Advertise 2.0v for compatibility with the SDIO card's OCR */ 1157 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195; 1158 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1159 MMC_CAP_POWER_OFF_CARD; 1160 break; 1161 default: 1162 return -ENODEV; 1163 } 1164 1165 intel_mrfld_mmc_fix_up_power_slot(slot); 1166 return 0; 1167 } 1168 1169 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 1170 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1171 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 1172 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1173 .allow_runtime_pm = true, 1174 .probe_slot = intel_mrfld_mmc_probe_slot, 1175 }; 1176 1177 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 1178 { 1179 u8 scratch; 1180 int ret; 1181 1182 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 1183 if (ret) 1184 return ret; 1185 1186 /* 1187 * Turn PMOS on [bit 0], set over current detection to 2.4 V 1188 * [bit 1:2] and enable over current debouncing [bit 6]. 1189 */ 1190 if (on) 1191 scratch |= 0x47; 1192 else 1193 scratch &= ~0x47; 1194 1195 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 1196 } 1197 1198 static int jmicron_probe(struct sdhci_pci_chip *chip) 1199 { 1200 int ret; 1201 u16 mmcdev = 0; 1202 1203 if (chip->pdev->revision == 0) { 1204 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 1205 SDHCI_QUIRK_32BIT_DMA_SIZE | 1206 SDHCI_QUIRK_32BIT_ADMA_SIZE | 1207 SDHCI_QUIRK_RESET_AFTER_REQUEST | 1208 SDHCI_QUIRK_BROKEN_SMALL_PIO; 1209 } 1210 1211 /* 1212 * JMicron chips can have two interfaces to the same hardware 1213 * in order to work around limitations in Microsoft's driver. 1214 * We need to make sure we only bind to one of them. 1215 * 1216 * This code assumes two things: 1217 * 1218 * 1. The PCI code adds subfunctions in order. 1219 * 1220 * 2. The MMC interface has a lower subfunction number 1221 * than the SD interface. 1222 */ 1223 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 1224 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 1225 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 1226 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 1227 1228 if (mmcdev) { 1229 struct pci_dev *sd_dev; 1230 1231 sd_dev = NULL; 1232 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 1233 mmcdev, sd_dev)) != NULL) { 1234 if ((PCI_SLOT(chip->pdev->devfn) == 1235 PCI_SLOT(sd_dev->devfn)) && 1236 (chip->pdev->bus == sd_dev->bus)) 1237 break; 1238 } 1239 1240 if (sd_dev) { 1241 pci_dev_put(sd_dev); 1242 dev_info(&chip->pdev->dev, "Refusing to bind to " 1243 "secondary interface.\n"); 1244 return -ENODEV; 1245 } 1246 } 1247 1248 /* 1249 * JMicron chips need a bit of a nudge to enable the power 1250 * output pins. 1251 */ 1252 ret = jmicron_pmos(chip, 1); 1253 if (ret) { 1254 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1255 return ret; 1256 } 1257 1258 /* quirk for unsable RO-detection on JM388 chips */ 1259 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 1260 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1261 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 1262 1263 return 0; 1264 } 1265 1266 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 1267 { 1268 u8 scratch; 1269 1270 scratch = readb(host->ioaddr + 0xC0); 1271 1272 if (on) 1273 scratch |= 0x01; 1274 else 1275 scratch &= ~0x01; 1276 1277 writeb(scratch, host->ioaddr + 0xC0); 1278 } 1279 1280 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 1281 { 1282 if (slot->chip->pdev->revision == 0) { 1283 u16 version; 1284 1285 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 1286 version = (version & SDHCI_VENDOR_VER_MASK) >> 1287 SDHCI_VENDOR_VER_SHIFT; 1288 1289 /* 1290 * Older versions of the chip have lots of nasty glitches 1291 * in the ADMA engine. It's best just to avoid it 1292 * completely. 1293 */ 1294 if (version < 0xAC) 1295 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 1296 } 1297 1298 /* JM388 MMC doesn't support 1.8V while SD supports it */ 1299 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1300 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 1301 MMC_VDD_29_30 | MMC_VDD_30_31 | 1302 MMC_VDD_165_195; /* allow 1.8V */ 1303 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 1304 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 1305 } 1306 1307 /* 1308 * The secondary interface requires a bit set to get the 1309 * interrupts. 1310 */ 1311 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1312 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1313 jmicron_enable_mmc(slot->host, 1); 1314 1315 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 1316 1317 return 0; 1318 } 1319 1320 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 1321 { 1322 if (dead) 1323 return; 1324 1325 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1326 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1327 jmicron_enable_mmc(slot->host, 0); 1328 } 1329 1330 #ifdef CONFIG_PM_SLEEP 1331 static int jmicron_suspend(struct sdhci_pci_chip *chip) 1332 { 1333 int i, ret; 1334 1335 ret = sdhci_pci_suspend_host(chip); 1336 if (ret) 1337 return ret; 1338 1339 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1340 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1341 for (i = 0; i < chip->num_slots; i++) 1342 jmicron_enable_mmc(chip->slots[i]->host, 0); 1343 } 1344 1345 return 0; 1346 } 1347 1348 static int jmicron_resume(struct sdhci_pci_chip *chip) 1349 { 1350 int ret, i; 1351 1352 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1353 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1354 for (i = 0; i < chip->num_slots; i++) 1355 jmicron_enable_mmc(chip->slots[i]->host, 1); 1356 } 1357 1358 ret = jmicron_pmos(chip, 1); 1359 if (ret) { 1360 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1361 return ret; 1362 } 1363 1364 return sdhci_pci_resume_host(chip); 1365 } 1366 #endif 1367 1368 static const struct sdhci_pci_fixes sdhci_jmicron = { 1369 .probe = jmicron_probe, 1370 1371 .probe_slot = jmicron_probe_slot, 1372 .remove_slot = jmicron_remove_slot, 1373 1374 #ifdef CONFIG_PM_SLEEP 1375 .suspend = jmicron_suspend, 1376 .resume = jmicron_resume, 1377 #endif 1378 }; 1379 1380 /* SysKonnect CardBus2SDIO extra registers */ 1381 #define SYSKT_CTRL 0x200 1382 #define SYSKT_RDFIFO_STAT 0x204 1383 #define SYSKT_WRFIFO_STAT 0x208 1384 #define SYSKT_POWER_DATA 0x20c 1385 #define SYSKT_POWER_330 0xef 1386 #define SYSKT_POWER_300 0xf8 1387 #define SYSKT_POWER_184 0xcc 1388 #define SYSKT_POWER_CMD 0x20d 1389 #define SYSKT_POWER_START (1 << 7) 1390 #define SYSKT_POWER_STATUS 0x20e 1391 #define SYSKT_POWER_STATUS_OK (1 << 0) 1392 #define SYSKT_BOARD_REV 0x210 1393 #define SYSKT_CHIP_REV 0x211 1394 #define SYSKT_CONF_DATA 0x212 1395 #define SYSKT_CONF_DATA_1V8 (1 << 2) 1396 #define SYSKT_CONF_DATA_2V5 (1 << 1) 1397 #define SYSKT_CONF_DATA_3V3 (1 << 0) 1398 1399 static int syskt_probe(struct sdhci_pci_chip *chip) 1400 { 1401 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1402 chip->pdev->class &= ~0x0000FF; 1403 chip->pdev->class |= PCI_SDHCI_IFDMA; 1404 } 1405 return 0; 1406 } 1407 1408 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 1409 { 1410 int tm, ps; 1411 1412 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 1413 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 1414 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 1415 "board rev %d.%d, chip rev %d.%d\n", 1416 board_rev >> 4, board_rev & 0xf, 1417 chip_rev >> 4, chip_rev & 0xf); 1418 if (chip_rev >= 0x20) 1419 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 1420 1421 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 1422 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 1423 udelay(50); 1424 tm = 10; /* Wait max 1 ms */ 1425 do { 1426 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 1427 if (ps & SYSKT_POWER_STATUS_OK) 1428 break; 1429 udelay(100); 1430 } while (--tm); 1431 if (!tm) { 1432 dev_err(&slot->chip->pdev->dev, 1433 "power regulator never stabilized"); 1434 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 1435 return -ENODEV; 1436 } 1437 1438 return 0; 1439 } 1440 1441 static const struct sdhci_pci_fixes sdhci_syskt = { 1442 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 1443 .probe = syskt_probe, 1444 .probe_slot = syskt_probe_slot, 1445 }; 1446 1447 static int via_probe(struct sdhci_pci_chip *chip) 1448 { 1449 if (chip->pdev->revision == 0x10) 1450 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 1451 1452 return 0; 1453 } 1454 1455 static const struct sdhci_pci_fixes sdhci_via = { 1456 .probe = via_probe, 1457 }; 1458 1459 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 1460 { 1461 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 1462 return 0; 1463 } 1464 1465 static const struct sdhci_pci_fixes sdhci_rtsx = { 1466 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1467 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 1468 SDHCI_QUIRK2_BROKEN_DDR50, 1469 .probe_slot = rtsx_probe_slot, 1470 }; 1471 1472 /*AMD chipset generation*/ 1473 enum amd_chipset_gen { 1474 AMD_CHIPSET_BEFORE_ML, 1475 AMD_CHIPSET_CZ, 1476 AMD_CHIPSET_NL, 1477 AMD_CHIPSET_UNKNOWN, 1478 }; 1479 1480 /* AMD registers */ 1481 #define AMD_SD_AUTO_PATTERN 0xB8 1482 #define AMD_MSLEEP_DURATION 4 1483 #define AMD_SD_MISC_CONTROL 0xD0 1484 #define AMD_MAX_TUNE_VALUE 0x0B 1485 #define AMD_AUTO_TUNE_SEL 0x10800 1486 #define AMD_FIFO_PTR 0x30 1487 #define AMD_BIT_MASK 0x1F 1488 1489 static void amd_tuning_reset(struct sdhci_host *host) 1490 { 1491 unsigned int val; 1492 1493 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1494 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 1495 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1496 1497 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1498 val &= ~SDHCI_CTRL_EXEC_TUNING; 1499 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1500 } 1501 1502 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 1503 { 1504 unsigned int val; 1505 1506 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 1507 val &= ~AMD_BIT_MASK; 1508 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 1509 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 1510 } 1511 1512 static void amd_enable_manual_tuning(struct pci_dev *pdev) 1513 { 1514 unsigned int val; 1515 1516 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 1517 val |= AMD_FIFO_PTR; 1518 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 1519 } 1520 1521 static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode) 1522 { 1523 struct sdhci_pci_slot *slot = sdhci_priv(host); 1524 struct pci_dev *pdev = slot->chip->pdev; 1525 u8 valid_win = 0; 1526 u8 valid_win_max = 0; 1527 u8 valid_win_end = 0; 1528 u8 ctrl, tune_around; 1529 1530 amd_tuning_reset(host); 1531 1532 for (tune_around = 0; tune_around < 12; tune_around++) { 1533 amd_config_tuning_phase(pdev, tune_around); 1534 1535 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1536 valid_win = 0; 1537 msleep(AMD_MSLEEP_DURATION); 1538 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 1539 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 1540 } else if (++valid_win > valid_win_max) { 1541 valid_win_max = valid_win; 1542 valid_win_end = tune_around; 1543 } 1544 } 1545 1546 if (!valid_win_max) { 1547 dev_err(&pdev->dev, "no tuning point found\n"); 1548 return -EIO; 1549 } 1550 1551 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 1552 1553 amd_enable_manual_tuning(pdev); 1554 1555 host->mmc->retune_period = 0; 1556 1557 return 0; 1558 } 1559 1560 static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode) 1561 { 1562 struct sdhci_host *host = mmc_priv(mmc); 1563 1564 /* AMD requires custom HS200 tuning */ 1565 if (host->timing == MMC_TIMING_MMC_HS200) 1566 return amd_execute_tuning_hs200(host, opcode); 1567 1568 /* Otherwise perform standard SDHCI tuning */ 1569 return sdhci_execute_tuning(mmc, opcode); 1570 } 1571 1572 static int amd_probe_slot(struct sdhci_pci_slot *slot) 1573 { 1574 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 1575 1576 ops->execute_tuning = amd_execute_tuning; 1577 1578 return 0; 1579 } 1580 1581 static int amd_probe(struct sdhci_pci_chip *chip) 1582 { 1583 struct pci_dev *smbus_dev; 1584 enum amd_chipset_gen gen; 1585 1586 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1587 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 1588 if (smbus_dev) { 1589 gen = AMD_CHIPSET_BEFORE_ML; 1590 } else { 1591 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1592 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1593 if (smbus_dev) { 1594 if (smbus_dev->revision < 0x51) 1595 gen = AMD_CHIPSET_CZ; 1596 else 1597 gen = AMD_CHIPSET_NL; 1598 } else { 1599 gen = AMD_CHIPSET_UNKNOWN; 1600 } 1601 } 1602 1603 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1604 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1605 1606 return 0; 1607 } 1608 1609 static u32 sdhci_read_present_state(struct sdhci_host *host) 1610 { 1611 return sdhci_readl(host, SDHCI_PRESENT_STATE); 1612 } 1613 1614 static void amd_sdhci_reset(struct sdhci_host *host, u8 mask) 1615 { 1616 struct sdhci_pci_slot *slot = sdhci_priv(host); 1617 struct pci_dev *pdev = slot->chip->pdev; 1618 u32 present_state; 1619 1620 /* 1621 * SDHC 0x7906 requires a hard reset to clear all internal state. 1622 * Otherwise it can get into a bad state where the DATA lines are always 1623 * read as zeros. 1624 */ 1625 if (pdev->device == 0x7906 && (mask & SDHCI_RESET_ALL)) { 1626 pci_clear_master(pdev); 1627 1628 pci_save_state(pdev); 1629 1630 pci_set_power_state(pdev, PCI_D3cold); 1631 pr_debug("%s: power_state=%u\n", mmc_hostname(host->mmc), 1632 pdev->current_state); 1633 pci_set_power_state(pdev, PCI_D0); 1634 1635 pci_restore_state(pdev); 1636 1637 /* 1638 * SDHCI_RESET_ALL says the card detect logic should not be 1639 * reset, but since we need to reset the entire controller 1640 * we should wait until the card detect logic has stabilized. 1641 * 1642 * This normally takes about 40ms. 1643 */ 1644 readx_poll_timeout( 1645 sdhci_read_present_state, 1646 host, 1647 present_state, 1648 present_state & SDHCI_CD_STABLE, 1649 10000, 1650 100000 1651 ); 1652 } 1653 1654 return sdhci_reset(host, mask); 1655 } 1656 1657 static const struct sdhci_ops amd_sdhci_pci_ops = { 1658 .set_clock = sdhci_set_clock, 1659 .enable_dma = sdhci_pci_enable_dma, 1660 .set_bus_width = sdhci_set_bus_width, 1661 .reset = amd_sdhci_reset, 1662 .set_uhs_signaling = sdhci_set_uhs_signaling, 1663 }; 1664 1665 static const struct sdhci_pci_fixes sdhci_amd = { 1666 .probe = amd_probe, 1667 .ops = &amd_sdhci_pci_ops, 1668 .probe_slot = amd_probe_slot, 1669 }; 1670 1671 static const struct pci_device_id pci_ids[] = { 1672 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh), 1673 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc), 1674 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc), 1675 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc), 1676 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712), 1677 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712), 1678 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714), 1679 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714), 1680 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe), 1681 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron), 1682 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron), 1683 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron), 1684 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron), 1685 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt), 1686 SDHCI_PCI_DEVICE(VIA, 95D0, via), 1687 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx), 1688 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk), 1689 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0), 1690 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2), 1691 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2), 1692 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd), 1693 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio), 1694 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio), 1695 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc), 1696 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc), 1697 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio), 1698 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio), 1699 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc), 1700 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio), 1701 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio), 1702 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd), 1703 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc), 1704 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc), 1705 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio), 1706 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd), 1707 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd), 1708 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio), 1709 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio), 1710 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc), 1711 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc), 1712 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc), 1713 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc), 1714 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio), 1715 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd), 1716 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc), 1717 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc), 1718 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc), 1719 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio), 1720 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd), 1721 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc), 1722 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio), 1723 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd), 1724 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc), 1725 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio), 1726 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd), 1727 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc), 1728 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio), 1729 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd), 1730 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc), 1731 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd), 1732 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd), 1733 SDHCI_PCI_DEVICE(INTEL, ICP_EMMC, intel_glk_emmc), 1734 SDHCI_PCI_DEVICE(INTEL, ICP_SD, intel_byt_sd), 1735 SDHCI_PCI_DEVICE(INTEL, EHL_EMMC, intel_glk_emmc), 1736 SDHCI_PCI_DEVICE(INTEL, EHL_SD, intel_byt_sd), 1737 SDHCI_PCI_DEVICE(INTEL, CML_EMMC, intel_glk_emmc), 1738 SDHCI_PCI_DEVICE(INTEL, CML_SD, intel_byt_sd), 1739 SDHCI_PCI_DEVICE(INTEL, CMLH_SD, intel_byt_sd), 1740 SDHCI_PCI_DEVICE(INTEL, JSL_EMMC, intel_glk_emmc), 1741 SDHCI_PCI_DEVICE(INTEL, JSL_SD, intel_byt_sd), 1742 SDHCI_PCI_DEVICE(O2, 8120, o2), 1743 SDHCI_PCI_DEVICE(O2, 8220, o2), 1744 SDHCI_PCI_DEVICE(O2, 8221, o2), 1745 SDHCI_PCI_DEVICE(O2, 8320, o2), 1746 SDHCI_PCI_DEVICE(O2, 8321, o2), 1747 SDHCI_PCI_DEVICE(O2, FUJIN2, o2), 1748 SDHCI_PCI_DEVICE(O2, SDS0, o2), 1749 SDHCI_PCI_DEVICE(O2, SDS1, o2), 1750 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2), 1751 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), 1752 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan), 1753 SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps), 1754 SDHCI_PCI_DEVICE(GLI, 9750, gl9750), 1755 SDHCI_PCI_DEVICE(GLI, 9755, gl9755), 1756 SDHCI_PCI_DEVICE(GLI, 9763E, gl9763e), 1757 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), 1758 /* Generic SD host controller */ 1759 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, 1760 { /* end: all zeroes */ }, 1761 }; 1762 1763 MODULE_DEVICE_TABLE(pci, pci_ids); 1764 1765 /*****************************************************************************\ 1766 * * 1767 * SDHCI core callbacks * 1768 * * 1769 \*****************************************************************************/ 1770 1771 int sdhci_pci_enable_dma(struct sdhci_host *host) 1772 { 1773 struct sdhci_pci_slot *slot; 1774 struct pci_dev *pdev; 1775 1776 slot = sdhci_priv(host); 1777 pdev = slot->chip->pdev; 1778 1779 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1780 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1781 (host->flags & SDHCI_USE_SDMA)) { 1782 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1783 "doesn't fully claim to support it.\n"); 1784 } 1785 1786 pci_set_master(pdev); 1787 1788 return 0; 1789 } 1790 1791 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1792 { 1793 struct sdhci_pci_slot *slot = sdhci_priv(host); 1794 int rst_n_gpio = slot->rst_n_gpio; 1795 1796 if (!gpio_is_valid(rst_n_gpio)) 1797 return; 1798 gpio_set_value_cansleep(rst_n_gpio, 0); 1799 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1800 udelay(10); 1801 gpio_set_value_cansleep(rst_n_gpio, 1); 1802 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1803 usleep_range(300, 1000); 1804 } 1805 1806 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1807 { 1808 struct sdhci_pci_slot *slot = sdhci_priv(host); 1809 1810 if (slot->hw_reset) 1811 slot->hw_reset(host); 1812 } 1813 1814 static const struct sdhci_ops sdhci_pci_ops = { 1815 .set_clock = sdhci_set_clock, 1816 .enable_dma = sdhci_pci_enable_dma, 1817 .set_bus_width = sdhci_set_bus_width, 1818 .reset = sdhci_reset, 1819 .set_uhs_signaling = sdhci_set_uhs_signaling, 1820 .hw_reset = sdhci_pci_hw_reset, 1821 }; 1822 1823 /*****************************************************************************\ 1824 * * 1825 * Suspend/resume * 1826 * * 1827 \*****************************************************************************/ 1828 1829 #ifdef CONFIG_PM_SLEEP 1830 static int sdhci_pci_suspend(struct device *dev) 1831 { 1832 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 1833 1834 if (!chip) 1835 return 0; 1836 1837 if (chip->fixes && chip->fixes->suspend) 1838 return chip->fixes->suspend(chip); 1839 1840 return sdhci_pci_suspend_host(chip); 1841 } 1842 1843 static int sdhci_pci_resume(struct device *dev) 1844 { 1845 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 1846 1847 if (!chip) 1848 return 0; 1849 1850 if (chip->fixes && chip->fixes->resume) 1851 return chip->fixes->resume(chip); 1852 1853 return sdhci_pci_resume_host(chip); 1854 } 1855 #endif 1856 1857 #ifdef CONFIG_PM 1858 static int sdhci_pci_runtime_suspend(struct device *dev) 1859 { 1860 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 1861 1862 if (!chip) 1863 return 0; 1864 1865 if (chip->fixes && chip->fixes->runtime_suspend) 1866 return chip->fixes->runtime_suspend(chip); 1867 1868 return sdhci_pci_runtime_suspend_host(chip); 1869 } 1870 1871 static int sdhci_pci_runtime_resume(struct device *dev) 1872 { 1873 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 1874 1875 if (!chip) 1876 return 0; 1877 1878 if (chip->fixes && chip->fixes->runtime_resume) 1879 return chip->fixes->runtime_resume(chip); 1880 1881 return sdhci_pci_runtime_resume_host(chip); 1882 } 1883 #endif 1884 1885 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1886 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1887 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1888 sdhci_pci_runtime_resume, NULL) 1889 }; 1890 1891 /*****************************************************************************\ 1892 * * 1893 * Device probing/removal * 1894 * * 1895 \*****************************************************************************/ 1896 1897 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1898 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1899 int slotno) 1900 { 1901 struct sdhci_pci_slot *slot; 1902 struct sdhci_host *host; 1903 int ret, bar = first_bar + slotno; 1904 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 1905 1906 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1907 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1908 return ERR_PTR(-ENODEV); 1909 } 1910 1911 if (pci_resource_len(pdev, bar) < 0x100) { 1912 dev_err(&pdev->dev, "Invalid iomem size. You may " 1913 "experience problems.\n"); 1914 } 1915 1916 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1917 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1918 return ERR_PTR(-ENODEV); 1919 } 1920 1921 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1922 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1923 return ERR_PTR(-ENODEV); 1924 } 1925 1926 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 1927 if (IS_ERR(host)) { 1928 dev_err(&pdev->dev, "cannot allocate host\n"); 1929 return ERR_CAST(host); 1930 } 1931 1932 slot = sdhci_priv(host); 1933 1934 slot->chip = chip; 1935 slot->host = host; 1936 slot->rst_n_gpio = -EINVAL; 1937 slot->cd_gpio = -EINVAL; 1938 slot->cd_idx = -1; 1939 1940 /* Retrieve platform data if there is any */ 1941 if (*sdhci_pci_get_data) 1942 slot->data = sdhci_pci_get_data(pdev, slotno); 1943 1944 if (slot->data) { 1945 if (slot->data->setup) { 1946 ret = slot->data->setup(slot->data); 1947 if (ret) { 1948 dev_err(&pdev->dev, "platform setup failed\n"); 1949 goto free; 1950 } 1951 } 1952 slot->rst_n_gpio = slot->data->rst_n_gpio; 1953 slot->cd_gpio = slot->data->cd_gpio; 1954 } 1955 1956 host->hw_name = "PCI"; 1957 host->ops = chip->fixes && chip->fixes->ops ? 1958 chip->fixes->ops : 1959 &sdhci_pci_ops; 1960 host->quirks = chip->quirks; 1961 host->quirks2 = chip->quirks2; 1962 1963 host->irq = pdev->irq; 1964 1965 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1966 if (ret) { 1967 dev_err(&pdev->dev, "cannot request region\n"); 1968 goto cleanup; 1969 } 1970 1971 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1972 1973 if (chip->fixes && chip->fixes->probe_slot) { 1974 ret = chip->fixes->probe_slot(slot); 1975 if (ret) 1976 goto cleanup; 1977 } 1978 1979 if (gpio_is_valid(slot->rst_n_gpio)) { 1980 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1981 gpio_direction_output(slot->rst_n_gpio, 1); 1982 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1983 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1984 } else { 1985 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1986 slot->rst_n_gpio = -EINVAL; 1987 } 1988 } 1989 1990 host->mmc->pm_caps = MMC_PM_KEEP_POWER; 1991 host->mmc->slotno = slotno; 1992 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1993 1994 if (device_can_wakeup(&pdev->dev)) 1995 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ; 1996 1997 if (host->mmc->caps & MMC_CAP_CD_WAKE) 1998 device_init_wakeup(&pdev->dev, true); 1999 2000 if (slot->cd_idx >= 0) { 2001 ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx, 2002 slot->cd_override_level, 0); 2003 if (ret && ret != -EPROBE_DEFER) 2004 ret = mmc_gpiod_request_cd(host->mmc, NULL, 2005 slot->cd_idx, 2006 slot->cd_override_level, 2007 0); 2008 if (ret == -EPROBE_DEFER) 2009 goto remove; 2010 2011 if (ret) { 2012 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 2013 slot->cd_idx = -1; 2014 } 2015 } 2016 2017 if (chip->fixes && chip->fixes->add_host) 2018 ret = chip->fixes->add_host(slot); 2019 else 2020 ret = sdhci_add_host(host); 2021 if (ret) 2022 goto remove; 2023 2024 sdhci_pci_add_own_cd(slot); 2025 2026 /* 2027 * Check if the chip needs a separate GPIO for card detect to wake up 2028 * from runtime suspend. If it is not there, don't allow runtime PM. 2029 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 2030 */ 2031 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 2032 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 2033 chip->allow_runtime_pm = false; 2034 2035 return slot; 2036 2037 remove: 2038 if (chip->fixes && chip->fixes->remove_slot) 2039 chip->fixes->remove_slot(slot, 0); 2040 2041 cleanup: 2042 if (slot->data && slot->data->cleanup) 2043 slot->data->cleanup(slot->data); 2044 2045 free: 2046 sdhci_free_host(host); 2047 2048 return ERR_PTR(ret); 2049 } 2050 2051 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 2052 { 2053 int dead; 2054 u32 scratch; 2055 2056 sdhci_pci_remove_own_cd(slot); 2057 2058 dead = 0; 2059 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 2060 if (scratch == (u32)-1) 2061 dead = 1; 2062 2063 sdhci_remove_host(slot->host, dead); 2064 2065 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 2066 slot->chip->fixes->remove_slot(slot, dead); 2067 2068 if (slot->data && slot->data->cleanup) 2069 slot->data->cleanup(slot->data); 2070 2071 sdhci_free_host(slot->host); 2072 } 2073 2074 static void sdhci_pci_runtime_pm_allow(struct device *dev) 2075 { 2076 pm_suspend_ignore_children(dev, 1); 2077 pm_runtime_set_autosuspend_delay(dev, 50); 2078 pm_runtime_use_autosuspend(dev); 2079 pm_runtime_allow(dev); 2080 /* Stay active until mmc core scans for a card */ 2081 pm_runtime_put_noidle(dev); 2082 } 2083 2084 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 2085 { 2086 pm_runtime_forbid(dev); 2087 pm_runtime_get_noresume(dev); 2088 } 2089 2090 static int sdhci_pci_probe(struct pci_dev *pdev, 2091 const struct pci_device_id *ent) 2092 { 2093 struct sdhci_pci_chip *chip; 2094 struct sdhci_pci_slot *slot; 2095 2096 u8 slots, first_bar; 2097 int ret, i; 2098 2099 BUG_ON(pdev == NULL); 2100 BUG_ON(ent == NULL); 2101 2102 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 2103 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 2104 2105 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 2106 if (ret) 2107 return ret; 2108 2109 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 2110 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 2111 2112 BUG_ON(slots > MAX_SLOTS); 2113 2114 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 2115 if (ret) 2116 return ret; 2117 2118 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 2119 2120 if (first_bar > 5) { 2121 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 2122 return -ENODEV; 2123 } 2124 2125 ret = pcim_enable_device(pdev); 2126 if (ret) 2127 return ret; 2128 2129 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 2130 if (!chip) 2131 return -ENOMEM; 2132 2133 chip->pdev = pdev; 2134 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 2135 if (chip->fixes) { 2136 chip->quirks = chip->fixes->quirks; 2137 chip->quirks2 = chip->fixes->quirks2; 2138 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 2139 } 2140 chip->num_slots = slots; 2141 chip->pm_retune = true; 2142 chip->rpm_retune = true; 2143 2144 pci_set_drvdata(pdev, chip); 2145 2146 if (chip->fixes && chip->fixes->probe) { 2147 ret = chip->fixes->probe(chip); 2148 if (ret) 2149 return ret; 2150 } 2151 2152 slots = chip->num_slots; /* Quirk may have changed this */ 2153 2154 for (i = 0; i < slots; i++) { 2155 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 2156 if (IS_ERR(slot)) { 2157 for (i--; i >= 0; i--) 2158 sdhci_pci_remove_slot(chip->slots[i]); 2159 return PTR_ERR(slot); 2160 } 2161 2162 chip->slots[i] = slot; 2163 } 2164 2165 if (chip->allow_runtime_pm) 2166 sdhci_pci_runtime_pm_allow(&pdev->dev); 2167 2168 return 0; 2169 } 2170 2171 static void sdhci_pci_remove(struct pci_dev *pdev) 2172 { 2173 int i; 2174 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 2175 2176 if (chip->allow_runtime_pm) 2177 sdhci_pci_runtime_pm_forbid(&pdev->dev); 2178 2179 for (i = 0; i < chip->num_slots; i++) 2180 sdhci_pci_remove_slot(chip->slots[i]); 2181 } 2182 2183 static struct pci_driver sdhci_driver = { 2184 .name = "sdhci-pci", 2185 .id_table = pci_ids, 2186 .probe = sdhci_pci_probe, 2187 .remove = sdhci_pci_remove, 2188 .driver = { 2189 .pm = &sdhci_pci_pm_ops 2190 }, 2191 }; 2192 2193 module_pci_driver(sdhci_driver); 2194 2195 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 2196 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 2197 MODULE_LICENSE("GPL"); 2198