1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 2 * 3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 * 10 * Thanks to the following companies for their support: 11 * 12 * - JMicron (hardware and technical support) 13 */ 14 15 #include <linux/string.h> 16 #include <linux/delay.h> 17 #include <linux/highmem.h> 18 #include <linux/module.h> 19 #include <linux/pci.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/slab.h> 22 #include <linux/device.h> 23 #include <linux/mmc/host.h> 24 #include <linux/mmc/mmc.h> 25 #include <linux/scatterlist.h> 26 #include <linux/io.h> 27 #include <linux/gpio.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/mmc/slot-gpio.h> 30 #include <linux/mmc/sdhci-pci-data.h> 31 #include <linux/acpi.h> 32 33 #include "sdhci.h" 34 #include "sdhci-pci.h" 35 #include "sdhci-pci-o2micro.h" 36 37 static int sdhci_pci_enable_dma(struct sdhci_host *host); 38 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width); 39 static void sdhci_pci_hw_reset(struct sdhci_host *host); 40 41 #ifdef CONFIG_PM_SLEEP 42 static int __sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 43 { 44 int i, ret; 45 46 for (i = 0; i < chip->num_slots; i++) { 47 struct sdhci_pci_slot *slot = chip->slots[i]; 48 struct sdhci_host *host; 49 50 if (!slot) 51 continue; 52 53 host = slot->host; 54 55 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 56 mmc_retune_needed(host->mmc); 57 58 ret = sdhci_suspend_host(host); 59 if (ret) 60 goto err_pci_suspend; 61 62 if (host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ) 63 sdhci_enable_irq_wakeups(host); 64 } 65 66 return 0; 67 68 err_pci_suspend: 69 while (--i >= 0) 70 sdhci_resume_host(chip->slots[i]->host); 71 return ret; 72 } 73 74 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip) 75 { 76 mmc_pm_flag_t pm_flags = 0; 77 int i; 78 79 for (i = 0; i < chip->num_slots; i++) { 80 struct sdhci_pci_slot *slot = chip->slots[i]; 81 82 if (slot) 83 pm_flags |= slot->host->mmc->pm_flags; 84 } 85 86 return device_init_wakeup(&chip->pdev->dev, 87 (pm_flags & MMC_PM_KEEP_POWER) && 88 (pm_flags & MMC_PM_WAKE_SDIO_IRQ)); 89 } 90 91 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 92 { 93 int ret; 94 95 ret = __sdhci_pci_suspend_host(chip); 96 if (ret) 97 return ret; 98 99 sdhci_pci_init_wakeup(chip); 100 101 return 0; 102 } 103 104 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip) 105 { 106 struct sdhci_pci_slot *slot; 107 int i, ret; 108 109 for (i = 0; i < chip->num_slots; i++) { 110 slot = chip->slots[i]; 111 if (!slot) 112 continue; 113 114 ret = sdhci_resume_host(slot->host); 115 if (ret) 116 return ret; 117 } 118 119 return 0; 120 } 121 #endif 122 123 #ifdef CONFIG_PM 124 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip) 125 { 126 struct sdhci_pci_slot *slot; 127 struct sdhci_host *host; 128 int i, ret; 129 130 for (i = 0; i < chip->num_slots; i++) { 131 slot = chip->slots[i]; 132 if (!slot) 133 continue; 134 135 host = slot->host; 136 137 ret = sdhci_runtime_suspend_host(host); 138 if (ret) 139 goto err_pci_runtime_suspend; 140 141 if (chip->rpm_retune && 142 host->tuning_mode != SDHCI_TUNING_MODE_3) 143 mmc_retune_needed(host->mmc); 144 } 145 146 return 0; 147 148 err_pci_runtime_suspend: 149 while (--i >= 0) 150 sdhci_runtime_resume_host(chip->slots[i]->host); 151 return ret; 152 } 153 154 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip) 155 { 156 struct sdhci_pci_slot *slot; 157 int i, ret; 158 159 for (i = 0; i < chip->num_slots; i++) { 160 slot = chip->slots[i]; 161 if (!slot) 162 continue; 163 164 ret = sdhci_runtime_resume_host(slot->host); 165 if (ret) 166 return ret; 167 } 168 169 return 0; 170 } 171 #endif 172 173 /*****************************************************************************\ 174 * * 175 * Hardware specific quirk handling * 176 * * 177 \*****************************************************************************/ 178 179 static int ricoh_probe(struct sdhci_pci_chip *chip) 180 { 181 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 182 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 183 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 184 return 0; 185 } 186 187 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 188 { 189 slot->host->caps = 190 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 191 & SDHCI_TIMEOUT_CLK_MASK) | 192 193 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 194 & SDHCI_CLOCK_BASE_MASK) | 195 196 SDHCI_TIMEOUT_CLK_UNIT | 197 SDHCI_CAN_VDD_330 | 198 SDHCI_CAN_DO_HISPD | 199 SDHCI_CAN_DO_SDMA; 200 return 0; 201 } 202 203 #ifdef CONFIG_PM_SLEEP 204 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 205 { 206 /* Apply a delay to allow controller to settle */ 207 /* Otherwise it becomes confused if card state changed 208 during suspend */ 209 msleep(500); 210 return sdhci_pci_resume_host(chip); 211 } 212 #endif 213 214 static const struct sdhci_pci_fixes sdhci_ricoh = { 215 .probe = ricoh_probe, 216 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 217 SDHCI_QUIRK_FORCE_DMA | 218 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 219 }; 220 221 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 222 .probe_slot = ricoh_mmc_probe_slot, 223 #ifdef CONFIG_PM_SLEEP 224 .resume = ricoh_mmc_resume, 225 #endif 226 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 227 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 228 SDHCI_QUIRK_NO_CARD_NO_RESET | 229 SDHCI_QUIRK_MISSING_CAPS 230 }; 231 232 static const struct sdhci_pci_fixes sdhci_ene_712 = { 233 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 234 SDHCI_QUIRK_BROKEN_DMA, 235 }; 236 237 static const struct sdhci_pci_fixes sdhci_ene_714 = { 238 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 239 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 240 SDHCI_QUIRK_BROKEN_DMA, 241 }; 242 243 static const struct sdhci_pci_fixes sdhci_cafe = { 244 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 245 SDHCI_QUIRK_NO_BUSY_IRQ | 246 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 247 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 248 }; 249 250 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 251 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 252 }; 253 254 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 255 { 256 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 257 return 0; 258 } 259 260 /* 261 * ADMA operation is disabled for Moorestown platform due to 262 * hardware bugs. 263 */ 264 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 265 { 266 /* 267 * slots number is fixed here for MRST as SDIO3/5 are never used and 268 * have hardware bugs. 269 */ 270 chip->num_slots = 1; 271 return 0; 272 } 273 274 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 275 { 276 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 277 return 0; 278 } 279 280 #ifdef CONFIG_PM 281 282 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 283 { 284 struct sdhci_pci_slot *slot = dev_id; 285 struct sdhci_host *host = slot->host; 286 287 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 288 return IRQ_HANDLED; 289 } 290 291 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 292 { 293 int err, irq, gpio = slot->cd_gpio; 294 295 slot->cd_gpio = -EINVAL; 296 slot->cd_irq = -EINVAL; 297 298 if (!gpio_is_valid(gpio)) 299 return; 300 301 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 302 if (err < 0) 303 goto out; 304 305 err = gpio_direction_input(gpio); 306 if (err < 0) 307 goto out_free; 308 309 irq = gpio_to_irq(gpio); 310 if (irq < 0) 311 goto out_free; 312 313 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 314 IRQF_TRIGGER_FALLING, "sd_cd", slot); 315 if (err) 316 goto out_free; 317 318 slot->cd_gpio = gpio; 319 slot->cd_irq = irq; 320 321 return; 322 323 out_free: 324 devm_gpio_free(&slot->chip->pdev->dev, gpio); 325 out: 326 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 327 } 328 329 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 330 { 331 if (slot->cd_irq >= 0) 332 free_irq(slot->cd_irq, slot); 333 } 334 335 #else 336 337 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 338 { 339 } 340 341 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 342 { 343 } 344 345 #endif 346 347 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 348 { 349 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 350 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC; 351 return 0; 352 } 353 354 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 355 { 356 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 357 return 0; 358 } 359 360 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 361 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 362 .probe_slot = mrst_hc_probe_slot, 363 }; 364 365 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 366 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 367 .probe = mrst_hc_probe, 368 }; 369 370 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 371 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 372 .allow_runtime_pm = true, 373 .own_cd_for_runtime_pm = true, 374 }; 375 376 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 377 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 378 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 379 .allow_runtime_pm = true, 380 .probe_slot = mfd_sdio_probe_slot, 381 }; 382 383 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 384 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 385 .allow_runtime_pm = true, 386 .probe_slot = mfd_emmc_probe_slot, 387 }; 388 389 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 390 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 391 .probe_slot = pch_hc_probe_slot, 392 }; 393 394 enum { 395 INTEL_DSM_FNS = 0, 396 INTEL_DSM_DRV_STRENGTH = 9, 397 INTEL_DSM_D3_RETUNE = 10, 398 }; 399 400 struct intel_host { 401 u32 dsm_fns; 402 int drv_strength; 403 bool d3_retune; 404 }; 405 406 static const guid_t intel_dsm_guid = 407 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F, 408 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61); 409 410 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 411 unsigned int fn, u32 *result) 412 { 413 union acpi_object *obj; 414 int err = 0; 415 size_t len; 416 417 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL); 418 if (!obj) 419 return -EOPNOTSUPP; 420 421 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { 422 err = -EINVAL; 423 goto out; 424 } 425 426 len = min_t(size_t, obj->buffer.length, 4); 427 428 *result = 0; 429 memcpy(result, obj->buffer.pointer, len); 430 out: 431 ACPI_FREE(obj); 432 433 return err; 434 } 435 436 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 437 unsigned int fn, u32 *result) 438 { 439 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 440 return -EOPNOTSUPP; 441 442 return __intel_dsm(intel_host, dev, fn, result); 443 } 444 445 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 446 struct mmc_host *mmc) 447 { 448 int err; 449 u32 val; 450 451 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 452 if (err) { 453 pr_debug("%s: DSM not supported, error %d\n", 454 mmc_hostname(mmc), err); 455 return; 456 } 457 458 pr_debug("%s: DSM function mask %#x\n", 459 mmc_hostname(mmc), intel_host->dsm_fns); 460 461 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 462 intel_host->drv_strength = err ? 0 : val; 463 464 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 465 intel_host->d3_retune = err ? true : !!val; 466 } 467 468 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 469 { 470 u8 reg; 471 472 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 473 reg |= 0x10; 474 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 475 /* For eMMC, minimum is 1us but give it 9us for good measure */ 476 udelay(9); 477 reg &= ~0x10; 478 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 479 /* For eMMC, minimum is 200us but give it 300us for good measure */ 480 usleep_range(300, 1000); 481 } 482 483 static int intel_select_drive_strength(struct mmc_card *card, 484 unsigned int max_dtr, int host_drv, 485 int card_drv, int *drv_type) 486 { 487 struct sdhci_host *host = mmc_priv(card->host); 488 struct sdhci_pci_slot *slot = sdhci_priv(host); 489 struct intel_host *intel_host = sdhci_pci_priv(slot); 490 491 return intel_host->drv_strength; 492 } 493 494 static int bxt_get_cd(struct mmc_host *mmc) 495 { 496 int gpio_cd = mmc_gpio_get_cd(mmc); 497 struct sdhci_host *host = mmc_priv(mmc); 498 unsigned long flags; 499 int ret = 0; 500 501 if (!gpio_cd) 502 return 0; 503 504 spin_lock_irqsave(&host->lock, flags); 505 506 if (host->flags & SDHCI_DEVICE_DEAD) 507 goto out; 508 509 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 510 out: 511 spin_unlock_irqrestore(&host->lock, flags); 512 513 return ret; 514 } 515 516 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 517 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 518 519 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 520 unsigned short vdd) 521 { 522 int cntr; 523 u8 reg; 524 525 sdhci_set_power(host, mode, vdd); 526 527 if (mode == MMC_POWER_OFF) 528 return; 529 530 /* 531 * Bus power might not enable after D3 -> D0 transition due to the 532 * present state not yet having propagated. Retry for up to 2ms. 533 */ 534 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 535 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 536 if (reg & SDHCI_POWER_ON) 537 break; 538 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 539 reg |= SDHCI_POWER_ON; 540 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 541 } 542 } 543 544 #define INTEL_HS400_ES_REG 0x78 545 #define INTEL_HS400_ES_BIT BIT(0) 546 547 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc, 548 struct mmc_ios *ios) 549 { 550 struct sdhci_host *host = mmc_priv(mmc); 551 u32 val; 552 553 val = sdhci_readl(host, INTEL_HS400_ES_REG); 554 if (ios->enhanced_strobe) 555 val |= INTEL_HS400_ES_BIT; 556 else 557 val &= ~INTEL_HS400_ES_BIT; 558 sdhci_writel(host, val, INTEL_HS400_ES_REG); 559 } 560 561 static const struct sdhci_ops sdhci_intel_byt_ops = { 562 .set_clock = sdhci_set_clock, 563 .set_power = sdhci_intel_set_power, 564 .enable_dma = sdhci_pci_enable_dma, 565 .set_bus_width = sdhci_pci_set_bus_width, 566 .reset = sdhci_reset, 567 .set_uhs_signaling = sdhci_set_uhs_signaling, 568 .hw_reset = sdhci_pci_hw_reset, 569 }; 570 571 static void byt_read_dsm(struct sdhci_pci_slot *slot) 572 { 573 struct intel_host *intel_host = sdhci_pci_priv(slot); 574 struct device *dev = &slot->chip->pdev->dev; 575 struct mmc_host *mmc = slot->host->mmc; 576 577 intel_dsm_init(intel_host, dev, mmc); 578 slot->chip->rpm_retune = intel_host->d3_retune; 579 } 580 581 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 582 { 583 byt_read_dsm(slot); 584 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 585 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 586 MMC_CAP_CMD_DURING_TFR | 587 MMC_CAP_WAIT_WHILE_BUSY; 588 slot->hw_reset = sdhci_pci_int_hw_reset; 589 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 590 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 591 slot->host->mmc_host_ops.select_drive_strength = 592 intel_select_drive_strength; 593 return 0; 594 } 595 596 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot) 597 { 598 int ret = byt_emmc_probe_slot(slot); 599 600 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) { 601 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES, 602 slot->host->mmc_host_ops.hs400_enhanced_strobe = 603 intel_hs400_enhanced_strobe; 604 } 605 606 return ret; 607 } 608 609 #ifdef CONFIG_ACPI 610 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 611 { 612 acpi_status status; 613 unsigned long long max_freq; 614 615 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 616 "MXFQ", NULL, &max_freq); 617 if (ACPI_FAILURE(status)) { 618 dev_err(&slot->chip->pdev->dev, 619 "MXFQ not found in acpi table\n"); 620 return -EINVAL; 621 } 622 623 slot->host->mmc->f_max = max_freq * 1000000; 624 625 return 0; 626 } 627 #else 628 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 629 { 630 return 0; 631 } 632 #endif 633 634 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 635 { 636 int err; 637 638 byt_read_dsm(slot); 639 640 err = ni_set_max_freq(slot); 641 if (err) 642 return err; 643 644 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 645 MMC_CAP_WAIT_WHILE_BUSY; 646 return 0; 647 } 648 649 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 650 { 651 byt_read_dsm(slot); 652 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 653 MMC_CAP_WAIT_WHILE_BUSY; 654 return 0; 655 } 656 657 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 658 { 659 byt_read_dsm(slot); 660 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | 661 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE; 662 slot->cd_idx = 0; 663 slot->cd_override_level = true; 664 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 665 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 666 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 667 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) 668 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 669 670 return 0; 671 } 672 673 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 674 .allow_runtime_pm = true, 675 .probe_slot = byt_emmc_probe_slot, 676 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 677 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 678 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 679 SDHCI_QUIRK2_STOP_WITH_TC, 680 .ops = &sdhci_intel_byt_ops, 681 .priv_size = sizeof(struct intel_host), 682 }; 683 684 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = { 685 .allow_runtime_pm = true, 686 .probe_slot = glk_emmc_probe_slot, 687 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 688 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 689 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 690 SDHCI_QUIRK2_STOP_WITH_TC, 691 .ops = &sdhci_intel_byt_ops, 692 .priv_size = sizeof(struct intel_host), 693 }; 694 695 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 696 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 697 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 698 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 699 .allow_runtime_pm = true, 700 .probe_slot = ni_byt_sdio_probe_slot, 701 .ops = &sdhci_intel_byt_ops, 702 .priv_size = sizeof(struct intel_host), 703 }; 704 705 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 706 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 707 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 708 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 709 .allow_runtime_pm = true, 710 .probe_slot = byt_sdio_probe_slot, 711 .ops = &sdhci_intel_byt_ops, 712 .priv_size = sizeof(struct intel_host), 713 }; 714 715 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 716 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 717 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 718 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 719 SDHCI_QUIRK2_STOP_WITH_TC, 720 .allow_runtime_pm = true, 721 .own_cd_for_runtime_pm = true, 722 .probe_slot = byt_sd_probe_slot, 723 .ops = &sdhci_intel_byt_ops, 724 .priv_size = sizeof(struct intel_host), 725 }; 726 727 /* Define Host controllers for Intel Merrifield platform */ 728 #define INTEL_MRFLD_EMMC_0 0 729 #define INTEL_MRFLD_EMMC_1 1 730 #define INTEL_MRFLD_SD 2 731 #define INTEL_MRFLD_SDIO 3 732 733 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 734 { 735 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 736 737 switch (func) { 738 case INTEL_MRFLD_EMMC_0: 739 case INTEL_MRFLD_EMMC_1: 740 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 741 MMC_CAP_8_BIT_DATA | 742 MMC_CAP_1_8V_DDR; 743 break; 744 case INTEL_MRFLD_SD: 745 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 746 break; 747 case INTEL_MRFLD_SDIO: 748 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 749 MMC_CAP_POWER_OFF_CARD; 750 break; 751 default: 752 return -ENODEV; 753 } 754 return 0; 755 } 756 757 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 758 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 759 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 760 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 761 .allow_runtime_pm = true, 762 .probe_slot = intel_mrfld_mmc_probe_slot, 763 }; 764 765 /* O2Micro extra registers */ 766 #define O2_SD_LOCK_WP 0xD3 767 #define O2_SD_MULTI_VCC3V 0xEE 768 #define O2_SD_CLKREQ 0xEC 769 #define O2_SD_CAPS 0xE0 770 #define O2_SD_ADMA1 0xE2 771 #define O2_SD_ADMA2 0xE7 772 #define O2_SD_INF_MOD 0xF1 773 774 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 775 { 776 u8 scratch; 777 int ret; 778 779 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 780 if (ret) 781 return ret; 782 783 /* 784 * Turn PMOS on [bit 0], set over current detection to 2.4 V 785 * [bit 1:2] and enable over current debouncing [bit 6]. 786 */ 787 if (on) 788 scratch |= 0x47; 789 else 790 scratch &= ~0x47; 791 792 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 793 } 794 795 static int jmicron_probe(struct sdhci_pci_chip *chip) 796 { 797 int ret; 798 u16 mmcdev = 0; 799 800 if (chip->pdev->revision == 0) { 801 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 802 SDHCI_QUIRK_32BIT_DMA_SIZE | 803 SDHCI_QUIRK_32BIT_ADMA_SIZE | 804 SDHCI_QUIRK_RESET_AFTER_REQUEST | 805 SDHCI_QUIRK_BROKEN_SMALL_PIO; 806 } 807 808 /* 809 * JMicron chips can have two interfaces to the same hardware 810 * in order to work around limitations in Microsoft's driver. 811 * We need to make sure we only bind to one of them. 812 * 813 * This code assumes two things: 814 * 815 * 1. The PCI code adds subfunctions in order. 816 * 817 * 2. The MMC interface has a lower subfunction number 818 * than the SD interface. 819 */ 820 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 821 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 822 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 823 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 824 825 if (mmcdev) { 826 struct pci_dev *sd_dev; 827 828 sd_dev = NULL; 829 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 830 mmcdev, sd_dev)) != NULL) { 831 if ((PCI_SLOT(chip->pdev->devfn) == 832 PCI_SLOT(sd_dev->devfn)) && 833 (chip->pdev->bus == sd_dev->bus)) 834 break; 835 } 836 837 if (sd_dev) { 838 pci_dev_put(sd_dev); 839 dev_info(&chip->pdev->dev, "Refusing to bind to " 840 "secondary interface.\n"); 841 return -ENODEV; 842 } 843 } 844 845 /* 846 * JMicron chips need a bit of a nudge to enable the power 847 * output pins. 848 */ 849 ret = jmicron_pmos(chip, 1); 850 if (ret) { 851 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 852 return ret; 853 } 854 855 /* quirk for unsable RO-detection on JM388 chips */ 856 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 857 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 858 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 859 860 return 0; 861 } 862 863 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 864 { 865 u8 scratch; 866 867 scratch = readb(host->ioaddr + 0xC0); 868 869 if (on) 870 scratch |= 0x01; 871 else 872 scratch &= ~0x01; 873 874 writeb(scratch, host->ioaddr + 0xC0); 875 } 876 877 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 878 { 879 if (slot->chip->pdev->revision == 0) { 880 u16 version; 881 882 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 883 version = (version & SDHCI_VENDOR_VER_MASK) >> 884 SDHCI_VENDOR_VER_SHIFT; 885 886 /* 887 * Older versions of the chip have lots of nasty glitches 888 * in the ADMA engine. It's best just to avoid it 889 * completely. 890 */ 891 if (version < 0xAC) 892 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 893 } 894 895 /* JM388 MMC doesn't support 1.8V while SD supports it */ 896 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 897 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 898 MMC_VDD_29_30 | MMC_VDD_30_31 | 899 MMC_VDD_165_195; /* allow 1.8V */ 900 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 901 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 902 } 903 904 /* 905 * The secondary interface requires a bit set to get the 906 * interrupts. 907 */ 908 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 909 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 910 jmicron_enable_mmc(slot->host, 1); 911 912 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 913 914 return 0; 915 } 916 917 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 918 { 919 if (dead) 920 return; 921 922 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 923 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 924 jmicron_enable_mmc(slot->host, 0); 925 } 926 927 #ifdef CONFIG_PM_SLEEP 928 static int jmicron_suspend(struct sdhci_pci_chip *chip) 929 { 930 int i, ret; 931 932 ret = __sdhci_pci_suspend_host(chip); 933 if (ret) 934 return ret; 935 936 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 937 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 938 for (i = 0; i < chip->num_slots; i++) 939 jmicron_enable_mmc(chip->slots[i]->host, 0); 940 } 941 942 sdhci_pci_init_wakeup(chip); 943 944 return 0; 945 } 946 947 static int jmicron_resume(struct sdhci_pci_chip *chip) 948 { 949 int ret, i; 950 951 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 952 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 953 for (i = 0; i < chip->num_slots; i++) 954 jmicron_enable_mmc(chip->slots[i]->host, 1); 955 } 956 957 ret = jmicron_pmos(chip, 1); 958 if (ret) { 959 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 960 return ret; 961 } 962 963 return sdhci_pci_resume_host(chip); 964 } 965 #endif 966 967 static const struct sdhci_pci_fixes sdhci_o2 = { 968 .probe = sdhci_pci_o2_probe, 969 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 970 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 971 .probe_slot = sdhci_pci_o2_probe_slot, 972 #ifdef CONFIG_PM_SLEEP 973 .resume = sdhci_pci_o2_resume, 974 #endif 975 }; 976 977 static const struct sdhci_pci_fixes sdhci_jmicron = { 978 .probe = jmicron_probe, 979 980 .probe_slot = jmicron_probe_slot, 981 .remove_slot = jmicron_remove_slot, 982 983 #ifdef CONFIG_PM_SLEEP 984 .suspend = jmicron_suspend, 985 .resume = jmicron_resume, 986 #endif 987 }; 988 989 /* SysKonnect CardBus2SDIO extra registers */ 990 #define SYSKT_CTRL 0x200 991 #define SYSKT_RDFIFO_STAT 0x204 992 #define SYSKT_WRFIFO_STAT 0x208 993 #define SYSKT_POWER_DATA 0x20c 994 #define SYSKT_POWER_330 0xef 995 #define SYSKT_POWER_300 0xf8 996 #define SYSKT_POWER_184 0xcc 997 #define SYSKT_POWER_CMD 0x20d 998 #define SYSKT_POWER_START (1 << 7) 999 #define SYSKT_POWER_STATUS 0x20e 1000 #define SYSKT_POWER_STATUS_OK (1 << 0) 1001 #define SYSKT_BOARD_REV 0x210 1002 #define SYSKT_CHIP_REV 0x211 1003 #define SYSKT_CONF_DATA 0x212 1004 #define SYSKT_CONF_DATA_1V8 (1 << 2) 1005 #define SYSKT_CONF_DATA_2V5 (1 << 1) 1006 #define SYSKT_CONF_DATA_3V3 (1 << 0) 1007 1008 static int syskt_probe(struct sdhci_pci_chip *chip) 1009 { 1010 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1011 chip->pdev->class &= ~0x0000FF; 1012 chip->pdev->class |= PCI_SDHCI_IFDMA; 1013 } 1014 return 0; 1015 } 1016 1017 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 1018 { 1019 int tm, ps; 1020 1021 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 1022 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 1023 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 1024 "board rev %d.%d, chip rev %d.%d\n", 1025 board_rev >> 4, board_rev & 0xf, 1026 chip_rev >> 4, chip_rev & 0xf); 1027 if (chip_rev >= 0x20) 1028 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 1029 1030 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 1031 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 1032 udelay(50); 1033 tm = 10; /* Wait max 1 ms */ 1034 do { 1035 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 1036 if (ps & SYSKT_POWER_STATUS_OK) 1037 break; 1038 udelay(100); 1039 } while (--tm); 1040 if (!tm) { 1041 dev_err(&slot->chip->pdev->dev, 1042 "power regulator never stabilized"); 1043 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 1044 return -ENODEV; 1045 } 1046 1047 return 0; 1048 } 1049 1050 static const struct sdhci_pci_fixes sdhci_syskt = { 1051 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 1052 .probe = syskt_probe, 1053 .probe_slot = syskt_probe_slot, 1054 }; 1055 1056 static int via_probe(struct sdhci_pci_chip *chip) 1057 { 1058 if (chip->pdev->revision == 0x10) 1059 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 1060 1061 return 0; 1062 } 1063 1064 static const struct sdhci_pci_fixes sdhci_via = { 1065 .probe = via_probe, 1066 }; 1067 1068 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 1069 { 1070 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 1071 return 0; 1072 } 1073 1074 static const struct sdhci_pci_fixes sdhci_rtsx = { 1075 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1076 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 1077 SDHCI_QUIRK2_BROKEN_DDR50, 1078 .probe_slot = rtsx_probe_slot, 1079 }; 1080 1081 /*AMD chipset generation*/ 1082 enum amd_chipset_gen { 1083 AMD_CHIPSET_BEFORE_ML, 1084 AMD_CHIPSET_CZ, 1085 AMD_CHIPSET_NL, 1086 AMD_CHIPSET_UNKNOWN, 1087 }; 1088 1089 /* AMD registers */ 1090 #define AMD_SD_AUTO_PATTERN 0xB8 1091 #define AMD_MSLEEP_DURATION 4 1092 #define AMD_SD_MISC_CONTROL 0xD0 1093 #define AMD_MAX_TUNE_VALUE 0x0B 1094 #define AMD_AUTO_TUNE_SEL 0x10800 1095 #define AMD_FIFO_PTR 0x30 1096 #define AMD_BIT_MASK 0x1F 1097 1098 static void amd_tuning_reset(struct sdhci_host *host) 1099 { 1100 unsigned int val; 1101 1102 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1103 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 1104 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1105 1106 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1107 val &= ~SDHCI_CTRL_EXEC_TUNING; 1108 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1109 } 1110 1111 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 1112 { 1113 unsigned int val; 1114 1115 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 1116 val &= ~AMD_BIT_MASK; 1117 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 1118 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 1119 } 1120 1121 static void amd_enable_manual_tuning(struct pci_dev *pdev) 1122 { 1123 unsigned int val; 1124 1125 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 1126 val |= AMD_FIFO_PTR; 1127 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 1128 } 1129 1130 static int amd_execute_tuning(struct sdhci_host *host, u32 opcode) 1131 { 1132 struct sdhci_pci_slot *slot = sdhci_priv(host); 1133 struct pci_dev *pdev = slot->chip->pdev; 1134 u8 valid_win = 0; 1135 u8 valid_win_max = 0; 1136 u8 valid_win_end = 0; 1137 u8 ctrl, tune_around; 1138 1139 amd_tuning_reset(host); 1140 1141 for (tune_around = 0; tune_around < 12; tune_around++) { 1142 amd_config_tuning_phase(pdev, tune_around); 1143 1144 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1145 valid_win = 0; 1146 msleep(AMD_MSLEEP_DURATION); 1147 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 1148 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 1149 } else if (++valid_win > valid_win_max) { 1150 valid_win_max = valid_win; 1151 valid_win_end = tune_around; 1152 } 1153 } 1154 1155 if (!valid_win_max) { 1156 dev_err(&pdev->dev, "no tuning point found\n"); 1157 return -EIO; 1158 } 1159 1160 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 1161 1162 amd_enable_manual_tuning(pdev); 1163 1164 host->mmc->retune_period = 0; 1165 1166 return 0; 1167 } 1168 1169 static int amd_probe(struct sdhci_pci_chip *chip) 1170 { 1171 struct pci_dev *smbus_dev; 1172 enum amd_chipset_gen gen; 1173 1174 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1175 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 1176 if (smbus_dev) { 1177 gen = AMD_CHIPSET_BEFORE_ML; 1178 } else { 1179 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1180 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1181 if (smbus_dev) { 1182 if (smbus_dev->revision < 0x51) 1183 gen = AMD_CHIPSET_CZ; 1184 else 1185 gen = AMD_CHIPSET_NL; 1186 } else { 1187 gen = AMD_CHIPSET_UNKNOWN; 1188 } 1189 } 1190 1191 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1192 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1193 1194 return 0; 1195 } 1196 1197 static const struct sdhci_ops amd_sdhci_pci_ops = { 1198 .set_clock = sdhci_set_clock, 1199 .enable_dma = sdhci_pci_enable_dma, 1200 .set_bus_width = sdhci_pci_set_bus_width, 1201 .reset = sdhci_reset, 1202 .set_uhs_signaling = sdhci_set_uhs_signaling, 1203 .platform_execute_tuning = amd_execute_tuning, 1204 }; 1205 1206 static const struct sdhci_pci_fixes sdhci_amd = { 1207 .probe = amd_probe, 1208 .ops = &amd_sdhci_pci_ops, 1209 }; 1210 1211 static const struct pci_device_id pci_ids[] = { 1212 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh), 1213 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc), 1214 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc), 1215 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc), 1216 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712), 1217 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712), 1218 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714), 1219 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714), 1220 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe), 1221 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron), 1222 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron), 1223 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron), 1224 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron), 1225 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt), 1226 SDHCI_PCI_DEVICE(VIA, 95D0, via), 1227 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx), 1228 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk), 1229 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0), 1230 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2), 1231 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2), 1232 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd), 1233 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio), 1234 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio), 1235 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc), 1236 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc), 1237 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio), 1238 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio), 1239 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc), 1240 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio), 1241 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio), 1242 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd), 1243 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc), 1244 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc), 1245 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio), 1246 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd), 1247 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd), 1248 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio), 1249 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio), 1250 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc), 1251 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc), 1252 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc), 1253 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc), 1254 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio), 1255 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd), 1256 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc), 1257 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc), 1258 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio), 1259 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd), 1260 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc), 1261 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio), 1262 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd), 1263 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc), 1264 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio), 1265 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd), 1266 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc), 1267 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio), 1268 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd), 1269 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc), 1270 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd), 1271 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd), 1272 SDHCI_PCI_DEVICE(O2, 8120, o2), 1273 SDHCI_PCI_DEVICE(O2, 8220, o2), 1274 SDHCI_PCI_DEVICE(O2, 8221, o2), 1275 SDHCI_PCI_DEVICE(O2, 8320, o2), 1276 SDHCI_PCI_DEVICE(O2, 8321, o2), 1277 SDHCI_PCI_DEVICE(O2, FUJIN2, o2), 1278 SDHCI_PCI_DEVICE(O2, SDS0, o2), 1279 SDHCI_PCI_DEVICE(O2, SDS1, o2), 1280 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2), 1281 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), 1282 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), 1283 /* Generic SD host controller */ 1284 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, 1285 { /* end: all zeroes */ }, 1286 }; 1287 1288 MODULE_DEVICE_TABLE(pci, pci_ids); 1289 1290 /*****************************************************************************\ 1291 * * 1292 * SDHCI core callbacks * 1293 * * 1294 \*****************************************************************************/ 1295 1296 static int sdhci_pci_enable_dma(struct sdhci_host *host) 1297 { 1298 struct sdhci_pci_slot *slot; 1299 struct pci_dev *pdev; 1300 1301 slot = sdhci_priv(host); 1302 pdev = slot->chip->pdev; 1303 1304 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1305 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1306 (host->flags & SDHCI_USE_SDMA)) { 1307 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1308 "doesn't fully claim to support it.\n"); 1309 } 1310 1311 pci_set_master(pdev); 1312 1313 return 0; 1314 } 1315 1316 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width) 1317 { 1318 u8 ctrl; 1319 1320 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1321 1322 switch (width) { 1323 case MMC_BUS_WIDTH_8: 1324 ctrl |= SDHCI_CTRL_8BITBUS; 1325 ctrl &= ~SDHCI_CTRL_4BITBUS; 1326 break; 1327 case MMC_BUS_WIDTH_4: 1328 ctrl |= SDHCI_CTRL_4BITBUS; 1329 ctrl &= ~SDHCI_CTRL_8BITBUS; 1330 break; 1331 default: 1332 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS); 1333 break; 1334 } 1335 1336 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1337 } 1338 1339 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1340 { 1341 struct sdhci_pci_slot *slot = sdhci_priv(host); 1342 int rst_n_gpio = slot->rst_n_gpio; 1343 1344 if (!gpio_is_valid(rst_n_gpio)) 1345 return; 1346 gpio_set_value_cansleep(rst_n_gpio, 0); 1347 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1348 udelay(10); 1349 gpio_set_value_cansleep(rst_n_gpio, 1); 1350 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1351 usleep_range(300, 1000); 1352 } 1353 1354 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1355 { 1356 struct sdhci_pci_slot *slot = sdhci_priv(host); 1357 1358 if (slot->hw_reset) 1359 slot->hw_reset(host); 1360 } 1361 1362 static const struct sdhci_ops sdhci_pci_ops = { 1363 .set_clock = sdhci_set_clock, 1364 .enable_dma = sdhci_pci_enable_dma, 1365 .set_bus_width = sdhci_pci_set_bus_width, 1366 .reset = sdhci_reset, 1367 .set_uhs_signaling = sdhci_set_uhs_signaling, 1368 .hw_reset = sdhci_pci_hw_reset, 1369 }; 1370 1371 /*****************************************************************************\ 1372 * * 1373 * Suspend/resume * 1374 * * 1375 \*****************************************************************************/ 1376 1377 #ifdef CONFIG_PM_SLEEP 1378 static int sdhci_pci_suspend(struct device *dev) 1379 { 1380 struct pci_dev *pdev = to_pci_dev(dev); 1381 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1382 1383 if (!chip) 1384 return 0; 1385 1386 if (chip->fixes && chip->fixes->suspend) 1387 return chip->fixes->suspend(chip); 1388 1389 return sdhci_pci_suspend_host(chip); 1390 } 1391 1392 static int sdhci_pci_resume(struct device *dev) 1393 { 1394 struct pci_dev *pdev = to_pci_dev(dev); 1395 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1396 1397 if (!chip) 1398 return 0; 1399 1400 if (chip->fixes && chip->fixes->resume) 1401 return chip->fixes->resume(chip); 1402 1403 return sdhci_pci_resume_host(chip); 1404 } 1405 #endif 1406 1407 #ifdef CONFIG_PM 1408 static int sdhci_pci_runtime_suspend(struct device *dev) 1409 { 1410 struct pci_dev *pdev = to_pci_dev(dev); 1411 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1412 1413 if (!chip) 1414 return 0; 1415 1416 if (chip->fixes && chip->fixes->runtime_suspend) 1417 return chip->fixes->runtime_suspend(chip); 1418 1419 return sdhci_pci_runtime_suspend_host(chip); 1420 } 1421 1422 static int sdhci_pci_runtime_resume(struct device *dev) 1423 { 1424 struct pci_dev *pdev = to_pci_dev(dev); 1425 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1426 1427 if (!chip) 1428 return 0; 1429 1430 if (chip->fixes && chip->fixes->runtime_resume) 1431 return chip->fixes->runtime_resume(chip); 1432 1433 return sdhci_pci_runtime_resume_host(chip); 1434 } 1435 #endif 1436 1437 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1438 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1439 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1440 sdhci_pci_runtime_resume, NULL) 1441 }; 1442 1443 /*****************************************************************************\ 1444 * * 1445 * Device probing/removal * 1446 * * 1447 \*****************************************************************************/ 1448 1449 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1450 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1451 int slotno) 1452 { 1453 struct sdhci_pci_slot *slot; 1454 struct sdhci_host *host; 1455 int ret, bar = first_bar + slotno; 1456 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 1457 1458 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1459 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1460 return ERR_PTR(-ENODEV); 1461 } 1462 1463 if (pci_resource_len(pdev, bar) < 0x100) { 1464 dev_err(&pdev->dev, "Invalid iomem size. You may " 1465 "experience problems.\n"); 1466 } 1467 1468 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1469 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1470 return ERR_PTR(-ENODEV); 1471 } 1472 1473 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1474 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1475 return ERR_PTR(-ENODEV); 1476 } 1477 1478 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 1479 if (IS_ERR(host)) { 1480 dev_err(&pdev->dev, "cannot allocate host\n"); 1481 return ERR_CAST(host); 1482 } 1483 1484 slot = sdhci_priv(host); 1485 1486 slot->chip = chip; 1487 slot->host = host; 1488 slot->rst_n_gpio = -EINVAL; 1489 slot->cd_gpio = -EINVAL; 1490 slot->cd_idx = -1; 1491 1492 /* Retrieve platform data if there is any */ 1493 if (*sdhci_pci_get_data) 1494 slot->data = sdhci_pci_get_data(pdev, slotno); 1495 1496 if (slot->data) { 1497 if (slot->data->setup) { 1498 ret = slot->data->setup(slot->data); 1499 if (ret) { 1500 dev_err(&pdev->dev, "platform setup failed\n"); 1501 goto free; 1502 } 1503 } 1504 slot->rst_n_gpio = slot->data->rst_n_gpio; 1505 slot->cd_gpio = slot->data->cd_gpio; 1506 } 1507 1508 host->hw_name = "PCI"; 1509 host->ops = chip->fixes && chip->fixes->ops ? 1510 chip->fixes->ops : 1511 &sdhci_pci_ops; 1512 host->quirks = chip->quirks; 1513 host->quirks2 = chip->quirks2; 1514 1515 host->irq = pdev->irq; 1516 1517 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1518 if (ret) { 1519 dev_err(&pdev->dev, "cannot request region\n"); 1520 goto cleanup; 1521 } 1522 1523 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1524 1525 if (chip->fixes && chip->fixes->probe_slot) { 1526 ret = chip->fixes->probe_slot(slot); 1527 if (ret) 1528 goto cleanup; 1529 } 1530 1531 if (gpio_is_valid(slot->rst_n_gpio)) { 1532 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1533 gpio_direction_output(slot->rst_n_gpio, 1); 1534 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1535 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1536 } else { 1537 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1538 slot->rst_n_gpio = -EINVAL; 1539 } 1540 } 1541 1542 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; 1543 host->mmc->slotno = slotno; 1544 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1545 1546 if (slot->cd_idx >= 0) { 1547 ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx, 1548 slot->cd_override_level, 0, NULL); 1549 if (ret == -EPROBE_DEFER) 1550 goto remove; 1551 1552 if (ret) { 1553 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 1554 slot->cd_idx = -1; 1555 } 1556 } 1557 1558 if (chip->fixes && chip->fixes->add_host) 1559 ret = chip->fixes->add_host(slot); 1560 else 1561 ret = sdhci_add_host(host); 1562 if (ret) 1563 goto remove; 1564 1565 sdhci_pci_add_own_cd(slot); 1566 1567 /* 1568 * Check if the chip needs a separate GPIO for card detect to wake up 1569 * from runtime suspend. If it is not there, don't allow runtime PM. 1570 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 1571 */ 1572 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 1573 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 1574 chip->allow_runtime_pm = false; 1575 1576 return slot; 1577 1578 remove: 1579 if (chip->fixes && chip->fixes->remove_slot) 1580 chip->fixes->remove_slot(slot, 0); 1581 1582 cleanup: 1583 if (slot->data && slot->data->cleanup) 1584 slot->data->cleanup(slot->data); 1585 1586 free: 1587 sdhci_free_host(host); 1588 1589 return ERR_PTR(ret); 1590 } 1591 1592 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 1593 { 1594 int dead; 1595 u32 scratch; 1596 1597 sdhci_pci_remove_own_cd(slot); 1598 1599 dead = 0; 1600 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 1601 if (scratch == (u32)-1) 1602 dead = 1; 1603 1604 sdhci_remove_host(slot->host, dead); 1605 1606 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 1607 slot->chip->fixes->remove_slot(slot, dead); 1608 1609 if (slot->data && slot->data->cleanup) 1610 slot->data->cleanup(slot->data); 1611 1612 sdhci_free_host(slot->host); 1613 } 1614 1615 static void sdhci_pci_runtime_pm_allow(struct device *dev) 1616 { 1617 pm_suspend_ignore_children(dev, 1); 1618 pm_runtime_set_autosuspend_delay(dev, 50); 1619 pm_runtime_use_autosuspend(dev); 1620 pm_runtime_allow(dev); 1621 /* Stay active until mmc core scans for a card */ 1622 pm_runtime_put_noidle(dev); 1623 } 1624 1625 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 1626 { 1627 pm_runtime_forbid(dev); 1628 pm_runtime_get_noresume(dev); 1629 } 1630 1631 static int sdhci_pci_probe(struct pci_dev *pdev, 1632 const struct pci_device_id *ent) 1633 { 1634 struct sdhci_pci_chip *chip; 1635 struct sdhci_pci_slot *slot; 1636 1637 u8 slots, first_bar; 1638 int ret, i; 1639 1640 BUG_ON(pdev == NULL); 1641 BUG_ON(ent == NULL); 1642 1643 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 1644 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 1645 1646 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 1647 if (ret) 1648 return ret; 1649 1650 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 1651 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 1652 if (slots == 0) 1653 return -ENODEV; 1654 1655 BUG_ON(slots > MAX_SLOTS); 1656 1657 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 1658 if (ret) 1659 return ret; 1660 1661 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 1662 1663 if (first_bar > 5) { 1664 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 1665 return -ENODEV; 1666 } 1667 1668 ret = pcim_enable_device(pdev); 1669 if (ret) 1670 return ret; 1671 1672 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 1673 if (!chip) 1674 return -ENOMEM; 1675 1676 chip->pdev = pdev; 1677 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 1678 if (chip->fixes) { 1679 chip->quirks = chip->fixes->quirks; 1680 chip->quirks2 = chip->fixes->quirks2; 1681 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 1682 } 1683 chip->num_slots = slots; 1684 chip->pm_retune = true; 1685 chip->rpm_retune = true; 1686 1687 pci_set_drvdata(pdev, chip); 1688 1689 if (chip->fixes && chip->fixes->probe) { 1690 ret = chip->fixes->probe(chip); 1691 if (ret) 1692 return ret; 1693 } 1694 1695 slots = chip->num_slots; /* Quirk may have changed this */ 1696 1697 for (i = 0; i < slots; i++) { 1698 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 1699 if (IS_ERR(slot)) { 1700 for (i--; i >= 0; i--) 1701 sdhci_pci_remove_slot(chip->slots[i]); 1702 return PTR_ERR(slot); 1703 } 1704 1705 chip->slots[i] = slot; 1706 } 1707 1708 if (chip->allow_runtime_pm) 1709 sdhci_pci_runtime_pm_allow(&pdev->dev); 1710 1711 return 0; 1712 } 1713 1714 static void sdhci_pci_remove(struct pci_dev *pdev) 1715 { 1716 int i; 1717 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1718 1719 if (chip->allow_runtime_pm) 1720 sdhci_pci_runtime_pm_forbid(&pdev->dev); 1721 1722 for (i = 0; i < chip->num_slots; i++) 1723 sdhci_pci_remove_slot(chip->slots[i]); 1724 } 1725 1726 static struct pci_driver sdhci_driver = { 1727 .name = "sdhci-pci", 1728 .id_table = pci_ids, 1729 .probe = sdhci_pci_probe, 1730 .remove = sdhci_pci_remove, 1731 .driver = { 1732 .pm = &sdhci_pci_pm_ops 1733 }, 1734 }; 1735 1736 module_pci_driver(sdhci_driver); 1737 1738 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 1739 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 1740 MODULE_LICENSE("GPL"); 1741