1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 2 * 3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 * 10 * Thanks to the following companies for their support: 11 * 12 * - JMicron (hardware and technical support) 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/highmem.h> 17 #include <linux/module.h> 18 #include <linux/pci.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/slab.h> 21 #include <linux/device.h> 22 #include <linux/mmc/host.h> 23 #include <linux/mmc/mmc.h> 24 #include <linux/scatterlist.h> 25 #include <linux/io.h> 26 #include <linux/gpio.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/mmc/slot-gpio.h> 29 #include <linux/mmc/sdhci-pci-data.h> 30 #include <linux/acpi.h> 31 32 #include "sdhci.h" 33 #include "sdhci-pci.h" 34 #include "sdhci-pci-o2micro.h" 35 36 static int sdhci_pci_enable_dma(struct sdhci_host *host); 37 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width); 38 static void sdhci_pci_hw_reset(struct sdhci_host *host); 39 static int sdhci_pci_select_drive_strength(struct sdhci_host *host, 40 struct mmc_card *card, 41 unsigned int max_dtr, int host_drv, 42 int card_drv, int *drv_type); 43 44 /*****************************************************************************\ 45 * * 46 * Hardware specific quirk handling * 47 * * 48 \*****************************************************************************/ 49 50 static int ricoh_probe(struct sdhci_pci_chip *chip) 51 { 52 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 53 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 54 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 55 return 0; 56 } 57 58 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 59 { 60 slot->host->caps = 61 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 62 & SDHCI_TIMEOUT_CLK_MASK) | 63 64 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 65 & SDHCI_CLOCK_BASE_MASK) | 66 67 SDHCI_TIMEOUT_CLK_UNIT | 68 SDHCI_CAN_VDD_330 | 69 SDHCI_CAN_DO_HISPD | 70 SDHCI_CAN_DO_SDMA; 71 return 0; 72 } 73 74 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 75 { 76 /* Apply a delay to allow controller to settle */ 77 /* Otherwise it becomes confused if card state changed 78 during suspend */ 79 msleep(500); 80 return 0; 81 } 82 83 static const struct sdhci_pci_fixes sdhci_ricoh = { 84 .probe = ricoh_probe, 85 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 86 SDHCI_QUIRK_FORCE_DMA | 87 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 88 }; 89 90 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 91 .probe_slot = ricoh_mmc_probe_slot, 92 .resume = ricoh_mmc_resume, 93 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 94 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 95 SDHCI_QUIRK_NO_CARD_NO_RESET | 96 SDHCI_QUIRK_MISSING_CAPS 97 }; 98 99 static const struct sdhci_pci_fixes sdhci_ene_712 = { 100 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 101 SDHCI_QUIRK_BROKEN_DMA, 102 }; 103 104 static const struct sdhci_pci_fixes sdhci_ene_714 = { 105 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 106 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 107 SDHCI_QUIRK_BROKEN_DMA, 108 }; 109 110 static const struct sdhci_pci_fixes sdhci_cafe = { 111 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 112 SDHCI_QUIRK_NO_BUSY_IRQ | 113 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 114 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 115 }; 116 117 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 118 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 119 }; 120 121 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 122 { 123 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 124 return 0; 125 } 126 127 /* 128 * ADMA operation is disabled for Moorestown platform due to 129 * hardware bugs. 130 */ 131 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 132 { 133 /* 134 * slots number is fixed here for MRST as SDIO3/5 are never used and 135 * have hardware bugs. 136 */ 137 chip->num_slots = 1; 138 return 0; 139 } 140 141 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 142 { 143 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 144 return 0; 145 } 146 147 #ifdef CONFIG_PM 148 149 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 150 { 151 struct sdhci_pci_slot *slot = dev_id; 152 struct sdhci_host *host = slot->host; 153 154 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 155 return IRQ_HANDLED; 156 } 157 158 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 159 { 160 int err, irq, gpio = slot->cd_gpio; 161 162 slot->cd_gpio = -EINVAL; 163 slot->cd_irq = -EINVAL; 164 165 if (!gpio_is_valid(gpio)) 166 return; 167 168 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 169 if (err < 0) 170 goto out; 171 172 err = gpio_direction_input(gpio); 173 if (err < 0) 174 goto out_free; 175 176 irq = gpio_to_irq(gpio); 177 if (irq < 0) 178 goto out_free; 179 180 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 181 IRQF_TRIGGER_FALLING, "sd_cd", slot); 182 if (err) 183 goto out_free; 184 185 slot->cd_gpio = gpio; 186 slot->cd_irq = irq; 187 188 return; 189 190 out_free: 191 devm_gpio_free(&slot->chip->pdev->dev, gpio); 192 out: 193 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 194 } 195 196 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 197 { 198 if (slot->cd_irq >= 0) 199 free_irq(slot->cd_irq, slot); 200 } 201 202 #else 203 204 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 205 { 206 } 207 208 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 209 { 210 } 211 212 #endif 213 214 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 215 { 216 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 217 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC | 218 MMC_CAP2_HC_ERASE_SZ; 219 return 0; 220 } 221 222 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 223 { 224 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 225 return 0; 226 } 227 228 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 229 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 230 .probe_slot = mrst_hc_probe_slot, 231 }; 232 233 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 234 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 235 .probe = mrst_hc_probe, 236 }; 237 238 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 239 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 240 .allow_runtime_pm = true, 241 .own_cd_for_runtime_pm = true, 242 }; 243 244 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 245 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 246 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 247 .allow_runtime_pm = true, 248 .probe_slot = mfd_sdio_probe_slot, 249 }; 250 251 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 252 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 253 .allow_runtime_pm = true, 254 .probe_slot = mfd_emmc_probe_slot, 255 }; 256 257 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 258 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 259 .probe_slot = pch_hc_probe_slot, 260 }; 261 262 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 263 { 264 u8 reg; 265 266 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 267 reg |= 0x10; 268 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 269 /* For eMMC, minimum is 1us but give it 9us for good measure */ 270 udelay(9); 271 reg &= ~0x10; 272 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 273 /* For eMMC, minimum is 200us but give it 300us for good measure */ 274 usleep_range(300, 1000); 275 } 276 277 static int spt_select_drive_strength(struct sdhci_host *host, 278 struct mmc_card *card, 279 unsigned int max_dtr, 280 int host_drv, int card_drv, int *drv_type) 281 { 282 int drive_strength; 283 284 if (sdhci_pci_spt_drive_strength > 0) 285 drive_strength = sdhci_pci_spt_drive_strength & 0xf; 286 else 287 drive_strength = 0; /* Default 50-ohm */ 288 289 if ((mmc_driver_type_mask(drive_strength) & card_drv) == 0) 290 drive_strength = 0; /* Default 50-ohm */ 291 292 return drive_strength; 293 } 294 295 /* Try to read the drive strength from the card */ 296 static void spt_read_drive_strength(struct sdhci_host *host) 297 { 298 u32 val, i, t; 299 u16 m; 300 301 if (sdhci_pci_spt_drive_strength) 302 return; 303 304 sdhci_pci_spt_drive_strength = -1; 305 306 m = sdhci_readw(host, SDHCI_HOST_CONTROL2) & 0x7; 307 if (m != 3 && m != 5) 308 return; 309 val = sdhci_readl(host, SDHCI_PRESENT_STATE); 310 if (val & 0x3) 311 return; 312 sdhci_writel(host, 0x007f0023, SDHCI_INT_ENABLE); 313 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 314 sdhci_writew(host, 0x10, SDHCI_TRANSFER_MODE); 315 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 316 sdhci_writew(host, 512, SDHCI_BLOCK_SIZE); 317 sdhci_writew(host, 1, SDHCI_BLOCK_COUNT); 318 sdhci_writel(host, 0, SDHCI_ARGUMENT); 319 sdhci_writew(host, 0x83b, SDHCI_COMMAND); 320 for (i = 0; i < 1000; i++) { 321 val = sdhci_readl(host, SDHCI_INT_STATUS); 322 if (val & 0xffff8000) 323 return; 324 if (val & 0x20) 325 break; 326 udelay(1); 327 } 328 val = sdhci_readl(host, SDHCI_PRESENT_STATE); 329 if (!(val & 0x800)) 330 return; 331 for (i = 0; i < 47; i++) 332 val = sdhci_readl(host, SDHCI_BUFFER); 333 t = val & 0xf00; 334 if (t != 0x200 && t != 0x300) 335 return; 336 337 sdhci_pci_spt_drive_strength = 0x10 | ((val >> 12) & 0xf); 338 } 339 340 static int bxt_get_cd(struct mmc_host *mmc) 341 { 342 int gpio_cd = mmc_gpio_get_cd(mmc); 343 struct sdhci_host *host = mmc_priv(mmc); 344 unsigned long flags; 345 int ret = 0; 346 347 if (!gpio_cd) 348 return 0; 349 350 spin_lock_irqsave(&host->lock, flags); 351 352 if (host->flags & SDHCI_DEVICE_DEAD) 353 goto out; 354 355 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 356 out: 357 spin_unlock_irqrestore(&host->lock, flags); 358 359 return ret; 360 } 361 362 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 363 { 364 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 365 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 366 MMC_CAP_CMD_DURING_TFR | 367 MMC_CAP_WAIT_WHILE_BUSY; 368 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ; 369 slot->hw_reset = sdhci_pci_int_hw_reset; 370 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 371 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 372 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_SPT_EMMC) { 373 spt_read_drive_strength(slot->host); 374 slot->select_drive_strength = spt_select_drive_strength; 375 } 376 return 0; 377 } 378 379 #ifdef CONFIG_ACPI 380 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 381 { 382 acpi_status status; 383 unsigned long long max_freq; 384 385 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 386 "MXFQ", NULL, &max_freq); 387 if (ACPI_FAILURE(status)) { 388 dev_err(&slot->chip->pdev->dev, 389 "MXFQ not found in acpi table\n"); 390 return -EINVAL; 391 } 392 393 slot->host->mmc->f_max = max_freq * 1000000; 394 395 return 0; 396 } 397 #else 398 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 399 { 400 return 0; 401 } 402 #endif 403 404 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 405 { 406 int err; 407 408 err = ni_set_max_freq(slot); 409 if (err) 410 return err; 411 412 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 413 MMC_CAP_WAIT_WHILE_BUSY; 414 return 0; 415 } 416 417 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 418 { 419 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 420 MMC_CAP_WAIT_WHILE_BUSY; 421 return 0; 422 } 423 424 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 425 { 426 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 427 slot->cd_idx = 0; 428 slot->cd_override_level = true; 429 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 430 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 431 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 432 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) { 433 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 434 slot->host->mmc->caps |= MMC_CAP_AGGRESSIVE_PM; 435 } 436 437 return 0; 438 } 439 440 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 441 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 442 443 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 444 unsigned short vdd) 445 { 446 int cntr; 447 u8 reg; 448 449 sdhci_set_power(host, mode, vdd); 450 451 if (mode == MMC_POWER_OFF) 452 return; 453 454 spin_unlock_irq(&host->lock); 455 456 /* 457 * Bus power might not enable after D3 -> D0 transition due to the 458 * present state not yet having propagated. Retry for up to 2ms. 459 */ 460 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 461 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 462 if (reg & SDHCI_POWER_ON) 463 break; 464 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 465 reg |= SDHCI_POWER_ON; 466 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 467 } 468 469 spin_lock_irq(&host->lock); 470 } 471 472 static const struct sdhci_ops sdhci_intel_byt_ops = { 473 .set_clock = sdhci_set_clock, 474 .set_power = sdhci_intel_set_power, 475 .enable_dma = sdhci_pci_enable_dma, 476 .set_bus_width = sdhci_pci_set_bus_width, 477 .reset = sdhci_reset, 478 .set_uhs_signaling = sdhci_set_uhs_signaling, 479 .hw_reset = sdhci_pci_hw_reset, 480 .select_drive_strength = sdhci_pci_select_drive_strength, 481 }; 482 483 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 484 .allow_runtime_pm = true, 485 .probe_slot = byt_emmc_probe_slot, 486 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 487 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 488 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 489 SDHCI_QUIRK2_STOP_WITH_TC, 490 .ops = &sdhci_intel_byt_ops, 491 }; 492 493 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 494 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 495 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 496 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 497 .allow_runtime_pm = true, 498 .probe_slot = ni_byt_sdio_probe_slot, 499 .ops = &sdhci_intel_byt_ops, 500 }; 501 502 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 503 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 504 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 505 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 506 .allow_runtime_pm = true, 507 .probe_slot = byt_sdio_probe_slot, 508 .ops = &sdhci_intel_byt_ops, 509 }; 510 511 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 512 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 513 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 514 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 515 SDHCI_QUIRK2_STOP_WITH_TC, 516 .allow_runtime_pm = true, 517 .own_cd_for_runtime_pm = true, 518 .probe_slot = byt_sd_probe_slot, 519 .ops = &sdhci_intel_byt_ops, 520 }; 521 522 /* Define Host controllers for Intel Merrifield platform */ 523 #define INTEL_MRFLD_EMMC_0 0 524 #define INTEL_MRFLD_EMMC_1 1 525 #define INTEL_MRFLD_SD 2 526 #define INTEL_MRFLD_SDIO 3 527 528 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 529 { 530 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 531 532 switch (func) { 533 case INTEL_MRFLD_EMMC_0: 534 case INTEL_MRFLD_EMMC_1: 535 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 536 MMC_CAP_8_BIT_DATA | 537 MMC_CAP_1_8V_DDR; 538 break; 539 case INTEL_MRFLD_SD: 540 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 541 break; 542 case INTEL_MRFLD_SDIO: 543 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 544 MMC_CAP_POWER_OFF_CARD; 545 break; 546 default: 547 return -ENODEV; 548 } 549 return 0; 550 } 551 552 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 553 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 554 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 555 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 556 .allow_runtime_pm = true, 557 .probe_slot = intel_mrfld_mmc_probe_slot, 558 }; 559 560 /* O2Micro extra registers */ 561 #define O2_SD_LOCK_WP 0xD3 562 #define O2_SD_MULTI_VCC3V 0xEE 563 #define O2_SD_CLKREQ 0xEC 564 #define O2_SD_CAPS 0xE0 565 #define O2_SD_ADMA1 0xE2 566 #define O2_SD_ADMA2 0xE7 567 #define O2_SD_INF_MOD 0xF1 568 569 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 570 { 571 u8 scratch; 572 int ret; 573 574 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 575 if (ret) 576 return ret; 577 578 /* 579 * Turn PMOS on [bit 0], set over current detection to 2.4 V 580 * [bit 1:2] and enable over current debouncing [bit 6]. 581 */ 582 if (on) 583 scratch |= 0x47; 584 else 585 scratch &= ~0x47; 586 587 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 588 } 589 590 static int jmicron_probe(struct sdhci_pci_chip *chip) 591 { 592 int ret; 593 u16 mmcdev = 0; 594 595 if (chip->pdev->revision == 0) { 596 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 597 SDHCI_QUIRK_32BIT_DMA_SIZE | 598 SDHCI_QUIRK_32BIT_ADMA_SIZE | 599 SDHCI_QUIRK_RESET_AFTER_REQUEST | 600 SDHCI_QUIRK_BROKEN_SMALL_PIO; 601 } 602 603 /* 604 * JMicron chips can have two interfaces to the same hardware 605 * in order to work around limitations in Microsoft's driver. 606 * We need to make sure we only bind to one of them. 607 * 608 * This code assumes two things: 609 * 610 * 1. The PCI code adds subfunctions in order. 611 * 612 * 2. The MMC interface has a lower subfunction number 613 * than the SD interface. 614 */ 615 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 616 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 617 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 618 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 619 620 if (mmcdev) { 621 struct pci_dev *sd_dev; 622 623 sd_dev = NULL; 624 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 625 mmcdev, sd_dev)) != NULL) { 626 if ((PCI_SLOT(chip->pdev->devfn) == 627 PCI_SLOT(sd_dev->devfn)) && 628 (chip->pdev->bus == sd_dev->bus)) 629 break; 630 } 631 632 if (sd_dev) { 633 pci_dev_put(sd_dev); 634 dev_info(&chip->pdev->dev, "Refusing to bind to " 635 "secondary interface.\n"); 636 return -ENODEV; 637 } 638 } 639 640 /* 641 * JMicron chips need a bit of a nudge to enable the power 642 * output pins. 643 */ 644 ret = jmicron_pmos(chip, 1); 645 if (ret) { 646 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 647 return ret; 648 } 649 650 /* quirk for unsable RO-detection on JM388 chips */ 651 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 652 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 653 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 654 655 return 0; 656 } 657 658 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 659 { 660 u8 scratch; 661 662 scratch = readb(host->ioaddr + 0xC0); 663 664 if (on) 665 scratch |= 0x01; 666 else 667 scratch &= ~0x01; 668 669 writeb(scratch, host->ioaddr + 0xC0); 670 } 671 672 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 673 { 674 if (slot->chip->pdev->revision == 0) { 675 u16 version; 676 677 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 678 version = (version & SDHCI_VENDOR_VER_MASK) >> 679 SDHCI_VENDOR_VER_SHIFT; 680 681 /* 682 * Older versions of the chip have lots of nasty glitches 683 * in the ADMA engine. It's best just to avoid it 684 * completely. 685 */ 686 if (version < 0xAC) 687 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 688 } 689 690 /* JM388 MMC doesn't support 1.8V while SD supports it */ 691 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 692 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 693 MMC_VDD_29_30 | MMC_VDD_30_31 | 694 MMC_VDD_165_195; /* allow 1.8V */ 695 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 696 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 697 } 698 699 /* 700 * The secondary interface requires a bit set to get the 701 * interrupts. 702 */ 703 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 704 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 705 jmicron_enable_mmc(slot->host, 1); 706 707 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 708 709 return 0; 710 } 711 712 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 713 { 714 if (dead) 715 return; 716 717 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 718 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 719 jmicron_enable_mmc(slot->host, 0); 720 } 721 722 static int jmicron_suspend(struct sdhci_pci_chip *chip) 723 { 724 int i; 725 726 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 727 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 728 for (i = 0; i < chip->num_slots; i++) 729 jmicron_enable_mmc(chip->slots[i]->host, 0); 730 } 731 732 return 0; 733 } 734 735 static int jmicron_resume(struct sdhci_pci_chip *chip) 736 { 737 int ret, i; 738 739 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 740 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 741 for (i = 0; i < chip->num_slots; i++) 742 jmicron_enable_mmc(chip->slots[i]->host, 1); 743 } 744 745 ret = jmicron_pmos(chip, 1); 746 if (ret) { 747 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 748 return ret; 749 } 750 751 return 0; 752 } 753 754 static const struct sdhci_pci_fixes sdhci_o2 = { 755 .probe = sdhci_pci_o2_probe, 756 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 757 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 758 .probe_slot = sdhci_pci_o2_probe_slot, 759 .resume = sdhci_pci_o2_resume, 760 }; 761 762 static const struct sdhci_pci_fixes sdhci_jmicron = { 763 .probe = jmicron_probe, 764 765 .probe_slot = jmicron_probe_slot, 766 .remove_slot = jmicron_remove_slot, 767 768 .suspend = jmicron_suspend, 769 .resume = jmicron_resume, 770 }; 771 772 /* SysKonnect CardBus2SDIO extra registers */ 773 #define SYSKT_CTRL 0x200 774 #define SYSKT_RDFIFO_STAT 0x204 775 #define SYSKT_WRFIFO_STAT 0x208 776 #define SYSKT_POWER_DATA 0x20c 777 #define SYSKT_POWER_330 0xef 778 #define SYSKT_POWER_300 0xf8 779 #define SYSKT_POWER_184 0xcc 780 #define SYSKT_POWER_CMD 0x20d 781 #define SYSKT_POWER_START (1 << 7) 782 #define SYSKT_POWER_STATUS 0x20e 783 #define SYSKT_POWER_STATUS_OK (1 << 0) 784 #define SYSKT_BOARD_REV 0x210 785 #define SYSKT_CHIP_REV 0x211 786 #define SYSKT_CONF_DATA 0x212 787 #define SYSKT_CONF_DATA_1V8 (1 << 2) 788 #define SYSKT_CONF_DATA_2V5 (1 << 1) 789 #define SYSKT_CONF_DATA_3V3 (1 << 0) 790 791 static int syskt_probe(struct sdhci_pci_chip *chip) 792 { 793 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 794 chip->pdev->class &= ~0x0000FF; 795 chip->pdev->class |= PCI_SDHCI_IFDMA; 796 } 797 return 0; 798 } 799 800 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 801 { 802 int tm, ps; 803 804 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 805 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 806 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 807 "board rev %d.%d, chip rev %d.%d\n", 808 board_rev >> 4, board_rev & 0xf, 809 chip_rev >> 4, chip_rev & 0xf); 810 if (chip_rev >= 0x20) 811 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 812 813 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 814 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 815 udelay(50); 816 tm = 10; /* Wait max 1 ms */ 817 do { 818 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 819 if (ps & SYSKT_POWER_STATUS_OK) 820 break; 821 udelay(100); 822 } while (--tm); 823 if (!tm) { 824 dev_err(&slot->chip->pdev->dev, 825 "power regulator never stabilized"); 826 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 827 return -ENODEV; 828 } 829 830 return 0; 831 } 832 833 static const struct sdhci_pci_fixes sdhci_syskt = { 834 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 835 .probe = syskt_probe, 836 .probe_slot = syskt_probe_slot, 837 }; 838 839 static int via_probe(struct sdhci_pci_chip *chip) 840 { 841 if (chip->pdev->revision == 0x10) 842 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 843 844 return 0; 845 } 846 847 static const struct sdhci_pci_fixes sdhci_via = { 848 .probe = via_probe, 849 }; 850 851 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 852 { 853 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 854 return 0; 855 } 856 857 static const struct sdhci_pci_fixes sdhci_rtsx = { 858 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 859 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 860 SDHCI_QUIRK2_BROKEN_DDR50, 861 .probe_slot = rtsx_probe_slot, 862 }; 863 864 /*AMD chipset generation*/ 865 enum amd_chipset_gen { 866 AMD_CHIPSET_BEFORE_ML, 867 AMD_CHIPSET_CZ, 868 AMD_CHIPSET_NL, 869 AMD_CHIPSET_UNKNOWN, 870 }; 871 872 /* AMD registers */ 873 #define AMD_SD_AUTO_PATTERN 0xB8 874 #define AMD_MSLEEP_DURATION 4 875 #define AMD_SD_MISC_CONTROL 0xD0 876 #define AMD_MAX_TUNE_VALUE 0x0B 877 #define AMD_AUTO_TUNE_SEL 0x10800 878 #define AMD_FIFO_PTR 0x30 879 #define AMD_BIT_MASK 0x1F 880 881 static void amd_tuning_reset(struct sdhci_host *host) 882 { 883 unsigned int val; 884 885 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 886 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 887 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 888 889 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 890 val &= ~SDHCI_CTRL_EXEC_TUNING; 891 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 892 } 893 894 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 895 { 896 unsigned int val; 897 898 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 899 val &= ~AMD_BIT_MASK; 900 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 901 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 902 } 903 904 static void amd_enable_manual_tuning(struct pci_dev *pdev) 905 { 906 unsigned int val; 907 908 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 909 val |= AMD_FIFO_PTR; 910 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 911 } 912 913 static int amd_execute_tuning(struct sdhci_host *host, u32 opcode) 914 { 915 struct sdhci_pci_slot *slot = sdhci_priv(host); 916 struct pci_dev *pdev = slot->chip->pdev; 917 u8 valid_win = 0; 918 u8 valid_win_max = 0; 919 u8 valid_win_end = 0; 920 u8 ctrl, tune_around; 921 922 amd_tuning_reset(host); 923 924 for (tune_around = 0; tune_around < 12; tune_around++) { 925 amd_config_tuning_phase(pdev, tune_around); 926 927 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 928 valid_win = 0; 929 msleep(AMD_MSLEEP_DURATION); 930 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 931 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 932 } else if (++valid_win > valid_win_max) { 933 valid_win_max = valid_win; 934 valid_win_end = tune_around; 935 } 936 } 937 938 if (!valid_win_max) { 939 dev_err(&pdev->dev, "no tuning point found\n"); 940 return -EIO; 941 } 942 943 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 944 945 amd_enable_manual_tuning(pdev); 946 947 host->mmc->retune_period = 0; 948 949 return 0; 950 } 951 952 static int amd_probe(struct sdhci_pci_chip *chip) 953 { 954 struct pci_dev *smbus_dev; 955 enum amd_chipset_gen gen; 956 957 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 958 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 959 if (smbus_dev) { 960 gen = AMD_CHIPSET_BEFORE_ML; 961 } else { 962 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 963 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 964 if (smbus_dev) { 965 if (smbus_dev->revision < 0x51) 966 gen = AMD_CHIPSET_CZ; 967 else 968 gen = AMD_CHIPSET_NL; 969 } else { 970 gen = AMD_CHIPSET_UNKNOWN; 971 } 972 } 973 974 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 975 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 976 977 return 0; 978 } 979 980 static const struct sdhci_ops amd_sdhci_pci_ops = { 981 .set_clock = sdhci_set_clock, 982 .enable_dma = sdhci_pci_enable_dma, 983 .set_bus_width = sdhci_pci_set_bus_width, 984 .reset = sdhci_reset, 985 .set_uhs_signaling = sdhci_set_uhs_signaling, 986 .platform_execute_tuning = amd_execute_tuning, 987 }; 988 989 static const struct sdhci_pci_fixes sdhci_amd = { 990 .probe = amd_probe, 991 .ops = &amd_sdhci_pci_ops, 992 }; 993 994 static const struct pci_device_id pci_ids[] = { 995 { 996 .vendor = PCI_VENDOR_ID_RICOH, 997 .device = PCI_DEVICE_ID_RICOH_R5C822, 998 .subvendor = PCI_ANY_ID, 999 .subdevice = PCI_ANY_ID, 1000 .driver_data = (kernel_ulong_t)&sdhci_ricoh, 1001 }, 1002 1003 { 1004 .vendor = PCI_VENDOR_ID_RICOH, 1005 .device = 0x843, 1006 .subvendor = PCI_ANY_ID, 1007 .subdevice = PCI_ANY_ID, 1008 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 1009 }, 1010 1011 { 1012 .vendor = PCI_VENDOR_ID_RICOH, 1013 .device = 0xe822, 1014 .subvendor = PCI_ANY_ID, 1015 .subdevice = PCI_ANY_ID, 1016 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 1017 }, 1018 1019 { 1020 .vendor = PCI_VENDOR_ID_RICOH, 1021 .device = 0xe823, 1022 .subvendor = PCI_ANY_ID, 1023 .subdevice = PCI_ANY_ID, 1024 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 1025 }, 1026 1027 { 1028 .vendor = PCI_VENDOR_ID_ENE, 1029 .device = PCI_DEVICE_ID_ENE_CB712_SD, 1030 .subvendor = PCI_ANY_ID, 1031 .subdevice = PCI_ANY_ID, 1032 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 1033 }, 1034 1035 { 1036 .vendor = PCI_VENDOR_ID_ENE, 1037 .device = PCI_DEVICE_ID_ENE_CB712_SD_2, 1038 .subvendor = PCI_ANY_ID, 1039 .subdevice = PCI_ANY_ID, 1040 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 1041 }, 1042 1043 { 1044 .vendor = PCI_VENDOR_ID_ENE, 1045 .device = PCI_DEVICE_ID_ENE_CB714_SD, 1046 .subvendor = PCI_ANY_ID, 1047 .subdevice = PCI_ANY_ID, 1048 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 1049 }, 1050 1051 { 1052 .vendor = PCI_VENDOR_ID_ENE, 1053 .device = PCI_DEVICE_ID_ENE_CB714_SD_2, 1054 .subvendor = PCI_ANY_ID, 1055 .subdevice = PCI_ANY_ID, 1056 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 1057 }, 1058 1059 { 1060 .vendor = PCI_VENDOR_ID_MARVELL, 1061 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD, 1062 .subvendor = PCI_ANY_ID, 1063 .subdevice = PCI_ANY_ID, 1064 .driver_data = (kernel_ulong_t)&sdhci_cafe, 1065 }, 1066 1067 { 1068 .vendor = PCI_VENDOR_ID_JMICRON, 1069 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD, 1070 .subvendor = PCI_ANY_ID, 1071 .subdevice = PCI_ANY_ID, 1072 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1073 }, 1074 1075 { 1076 .vendor = PCI_VENDOR_ID_JMICRON, 1077 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC, 1078 .subvendor = PCI_ANY_ID, 1079 .subdevice = PCI_ANY_ID, 1080 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1081 }, 1082 1083 { 1084 .vendor = PCI_VENDOR_ID_JMICRON, 1085 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD, 1086 .subvendor = PCI_ANY_ID, 1087 .subdevice = PCI_ANY_ID, 1088 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1089 }, 1090 1091 { 1092 .vendor = PCI_VENDOR_ID_JMICRON, 1093 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD, 1094 .subvendor = PCI_ANY_ID, 1095 .subdevice = PCI_ANY_ID, 1096 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1097 }, 1098 1099 { 1100 .vendor = PCI_VENDOR_ID_SYSKONNECT, 1101 .device = 0x8000, 1102 .subvendor = PCI_ANY_ID, 1103 .subdevice = PCI_ANY_ID, 1104 .driver_data = (kernel_ulong_t)&sdhci_syskt, 1105 }, 1106 1107 { 1108 .vendor = PCI_VENDOR_ID_VIA, 1109 .device = 0x95d0, 1110 .subvendor = PCI_ANY_ID, 1111 .subdevice = PCI_ANY_ID, 1112 .driver_data = (kernel_ulong_t)&sdhci_via, 1113 }, 1114 1115 { 1116 .vendor = PCI_VENDOR_ID_REALTEK, 1117 .device = 0x5250, 1118 .subvendor = PCI_ANY_ID, 1119 .subdevice = PCI_ANY_ID, 1120 .driver_data = (kernel_ulong_t)&sdhci_rtsx, 1121 }, 1122 1123 { 1124 .vendor = PCI_VENDOR_ID_INTEL, 1125 .device = PCI_DEVICE_ID_INTEL_QRK_SD, 1126 .subvendor = PCI_ANY_ID, 1127 .subdevice = PCI_ANY_ID, 1128 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk, 1129 }, 1130 1131 { 1132 .vendor = PCI_VENDOR_ID_INTEL, 1133 .device = PCI_DEVICE_ID_INTEL_MRST_SD0, 1134 .subvendor = PCI_ANY_ID, 1135 .subdevice = PCI_ANY_ID, 1136 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0, 1137 }, 1138 1139 { 1140 .vendor = PCI_VENDOR_ID_INTEL, 1141 .device = PCI_DEVICE_ID_INTEL_MRST_SD1, 1142 .subvendor = PCI_ANY_ID, 1143 .subdevice = PCI_ANY_ID, 1144 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 1145 }, 1146 1147 { 1148 .vendor = PCI_VENDOR_ID_INTEL, 1149 .device = PCI_DEVICE_ID_INTEL_MRST_SD2, 1150 .subvendor = PCI_ANY_ID, 1151 .subdevice = PCI_ANY_ID, 1152 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 1153 }, 1154 1155 { 1156 .vendor = PCI_VENDOR_ID_INTEL, 1157 .device = PCI_DEVICE_ID_INTEL_MFD_SD, 1158 .subvendor = PCI_ANY_ID, 1159 .subdevice = PCI_ANY_ID, 1160 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1161 }, 1162 1163 { 1164 .vendor = PCI_VENDOR_ID_INTEL, 1165 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1, 1166 .subvendor = PCI_ANY_ID, 1167 .subdevice = PCI_ANY_ID, 1168 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1169 }, 1170 1171 { 1172 .vendor = PCI_VENDOR_ID_INTEL, 1173 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2, 1174 .subvendor = PCI_ANY_ID, 1175 .subdevice = PCI_ANY_ID, 1176 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1177 }, 1178 1179 { 1180 .vendor = PCI_VENDOR_ID_INTEL, 1181 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0, 1182 .subvendor = PCI_ANY_ID, 1183 .subdevice = PCI_ANY_ID, 1184 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1185 }, 1186 1187 { 1188 .vendor = PCI_VENDOR_ID_INTEL, 1189 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1, 1190 .subvendor = PCI_ANY_ID, 1191 .subdevice = PCI_ANY_ID, 1192 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1193 }, 1194 1195 { 1196 .vendor = PCI_VENDOR_ID_INTEL, 1197 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0, 1198 .subvendor = PCI_ANY_ID, 1199 .subdevice = PCI_ANY_ID, 1200 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1201 }, 1202 1203 { 1204 .vendor = PCI_VENDOR_ID_INTEL, 1205 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1, 1206 .subvendor = PCI_ANY_ID, 1207 .subdevice = PCI_ANY_ID, 1208 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1209 }, 1210 1211 { 1212 .vendor = PCI_VENDOR_ID_INTEL, 1213 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC, 1214 .subvendor = PCI_ANY_ID, 1215 .subdevice = PCI_ANY_ID, 1216 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1217 }, 1218 1219 { 1220 .vendor = PCI_VENDOR_ID_INTEL, 1221 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, 1222 .subvendor = PCI_VENDOR_ID_NI, 1223 .subdevice = 0x7884, 1224 .driver_data = (kernel_ulong_t)&sdhci_ni_byt_sdio, 1225 }, 1226 1227 { 1228 .vendor = PCI_VENDOR_ID_INTEL, 1229 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, 1230 .subvendor = PCI_ANY_ID, 1231 .subdevice = PCI_ANY_ID, 1232 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1233 }, 1234 1235 { 1236 .vendor = PCI_VENDOR_ID_INTEL, 1237 .device = PCI_DEVICE_ID_INTEL_BYT_SD, 1238 .subvendor = PCI_ANY_ID, 1239 .subdevice = PCI_ANY_ID, 1240 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1241 }, 1242 1243 { 1244 .vendor = PCI_VENDOR_ID_INTEL, 1245 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2, 1246 .subvendor = PCI_ANY_ID, 1247 .subdevice = PCI_ANY_ID, 1248 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1249 }, 1250 1251 { 1252 .vendor = PCI_VENDOR_ID_INTEL, 1253 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC, 1254 .subvendor = PCI_ANY_ID, 1255 .subdevice = PCI_ANY_ID, 1256 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1257 }, 1258 1259 { 1260 .vendor = PCI_VENDOR_ID_INTEL, 1261 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO, 1262 .subvendor = PCI_ANY_ID, 1263 .subdevice = PCI_ANY_ID, 1264 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1265 }, 1266 1267 { 1268 .vendor = PCI_VENDOR_ID_INTEL, 1269 .device = PCI_DEVICE_ID_INTEL_BSW_SD, 1270 .subvendor = PCI_ANY_ID, 1271 .subdevice = PCI_ANY_ID, 1272 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1273 }, 1274 1275 { 1276 .vendor = PCI_VENDOR_ID_INTEL, 1277 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0, 1278 .subvendor = PCI_ANY_ID, 1279 .subdevice = PCI_ANY_ID, 1280 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1281 }, 1282 1283 { 1284 .vendor = PCI_VENDOR_ID_INTEL, 1285 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1, 1286 .subvendor = PCI_ANY_ID, 1287 .subdevice = PCI_ANY_ID, 1288 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1289 }, 1290 1291 { 1292 .vendor = PCI_VENDOR_ID_INTEL, 1293 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2, 1294 .subvendor = PCI_ANY_ID, 1295 .subdevice = PCI_ANY_ID, 1296 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1297 }, 1298 1299 { 1300 .vendor = PCI_VENDOR_ID_INTEL, 1301 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0, 1302 .subvendor = PCI_ANY_ID, 1303 .subdevice = PCI_ANY_ID, 1304 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1305 }, 1306 1307 { 1308 .vendor = PCI_VENDOR_ID_INTEL, 1309 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1, 1310 .subvendor = PCI_ANY_ID, 1311 .subdevice = PCI_ANY_ID, 1312 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1313 }, 1314 1315 { 1316 .vendor = PCI_VENDOR_ID_INTEL, 1317 .device = PCI_DEVICE_ID_INTEL_MRFLD_MMC, 1318 .subvendor = PCI_ANY_ID, 1319 .subdevice = PCI_ANY_ID, 1320 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfld_mmc, 1321 }, 1322 1323 { 1324 .vendor = PCI_VENDOR_ID_INTEL, 1325 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC, 1326 .subvendor = PCI_ANY_ID, 1327 .subdevice = PCI_ANY_ID, 1328 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1329 }, 1330 1331 { 1332 .vendor = PCI_VENDOR_ID_INTEL, 1333 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO, 1334 .subvendor = PCI_ANY_ID, 1335 .subdevice = PCI_ANY_ID, 1336 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1337 }, 1338 1339 { 1340 .vendor = PCI_VENDOR_ID_INTEL, 1341 .device = PCI_DEVICE_ID_INTEL_SPT_SD, 1342 .subvendor = PCI_ANY_ID, 1343 .subdevice = PCI_ANY_ID, 1344 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1345 }, 1346 1347 { 1348 .vendor = PCI_VENDOR_ID_INTEL, 1349 .device = PCI_DEVICE_ID_INTEL_DNV_EMMC, 1350 .subvendor = PCI_ANY_ID, 1351 .subdevice = PCI_ANY_ID, 1352 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1353 }, 1354 1355 { 1356 .vendor = PCI_VENDOR_ID_INTEL, 1357 .device = PCI_DEVICE_ID_INTEL_BXT_EMMC, 1358 .subvendor = PCI_ANY_ID, 1359 .subdevice = PCI_ANY_ID, 1360 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1361 }, 1362 1363 { 1364 .vendor = PCI_VENDOR_ID_INTEL, 1365 .device = PCI_DEVICE_ID_INTEL_BXT_SDIO, 1366 .subvendor = PCI_ANY_ID, 1367 .subdevice = PCI_ANY_ID, 1368 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1369 }, 1370 1371 { 1372 .vendor = PCI_VENDOR_ID_INTEL, 1373 .device = PCI_DEVICE_ID_INTEL_BXT_SD, 1374 .subvendor = PCI_ANY_ID, 1375 .subdevice = PCI_ANY_ID, 1376 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1377 }, 1378 1379 { 1380 .vendor = PCI_VENDOR_ID_INTEL, 1381 .device = PCI_DEVICE_ID_INTEL_BXTM_EMMC, 1382 .subvendor = PCI_ANY_ID, 1383 .subdevice = PCI_ANY_ID, 1384 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1385 }, 1386 1387 { 1388 .vendor = PCI_VENDOR_ID_INTEL, 1389 .device = PCI_DEVICE_ID_INTEL_BXTM_SDIO, 1390 .subvendor = PCI_ANY_ID, 1391 .subdevice = PCI_ANY_ID, 1392 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1393 }, 1394 1395 { 1396 .vendor = PCI_VENDOR_ID_INTEL, 1397 .device = PCI_DEVICE_ID_INTEL_BXTM_SD, 1398 .subvendor = PCI_ANY_ID, 1399 .subdevice = PCI_ANY_ID, 1400 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1401 }, 1402 1403 { 1404 .vendor = PCI_VENDOR_ID_INTEL, 1405 .device = PCI_DEVICE_ID_INTEL_APL_EMMC, 1406 .subvendor = PCI_ANY_ID, 1407 .subdevice = PCI_ANY_ID, 1408 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1409 }, 1410 1411 { 1412 .vendor = PCI_VENDOR_ID_INTEL, 1413 .device = PCI_DEVICE_ID_INTEL_APL_SDIO, 1414 .subvendor = PCI_ANY_ID, 1415 .subdevice = PCI_ANY_ID, 1416 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1417 }, 1418 1419 { 1420 .vendor = PCI_VENDOR_ID_INTEL, 1421 .device = PCI_DEVICE_ID_INTEL_APL_SD, 1422 .subvendor = PCI_ANY_ID, 1423 .subdevice = PCI_ANY_ID, 1424 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1425 }, 1426 1427 { 1428 .vendor = PCI_VENDOR_ID_INTEL, 1429 .device = PCI_DEVICE_ID_INTEL_GLK_EMMC, 1430 .subvendor = PCI_ANY_ID, 1431 .subdevice = PCI_ANY_ID, 1432 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1433 }, 1434 1435 { 1436 .vendor = PCI_VENDOR_ID_INTEL, 1437 .device = PCI_DEVICE_ID_INTEL_GLK_SDIO, 1438 .subvendor = PCI_ANY_ID, 1439 .subdevice = PCI_ANY_ID, 1440 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1441 }, 1442 1443 { 1444 .vendor = PCI_VENDOR_ID_INTEL, 1445 .device = PCI_DEVICE_ID_INTEL_GLK_SD, 1446 .subvendor = PCI_ANY_ID, 1447 .subdevice = PCI_ANY_ID, 1448 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1449 }, 1450 1451 { 1452 .vendor = PCI_VENDOR_ID_O2, 1453 .device = PCI_DEVICE_ID_O2_8120, 1454 .subvendor = PCI_ANY_ID, 1455 .subdevice = PCI_ANY_ID, 1456 .driver_data = (kernel_ulong_t)&sdhci_o2, 1457 }, 1458 1459 { 1460 .vendor = PCI_VENDOR_ID_O2, 1461 .device = PCI_DEVICE_ID_O2_8220, 1462 .subvendor = PCI_ANY_ID, 1463 .subdevice = PCI_ANY_ID, 1464 .driver_data = (kernel_ulong_t)&sdhci_o2, 1465 }, 1466 1467 { 1468 .vendor = PCI_VENDOR_ID_O2, 1469 .device = PCI_DEVICE_ID_O2_8221, 1470 .subvendor = PCI_ANY_ID, 1471 .subdevice = PCI_ANY_ID, 1472 .driver_data = (kernel_ulong_t)&sdhci_o2, 1473 }, 1474 1475 { 1476 .vendor = PCI_VENDOR_ID_O2, 1477 .device = PCI_DEVICE_ID_O2_8320, 1478 .subvendor = PCI_ANY_ID, 1479 .subdevice = PCI_ANY_ID, 1480 .driver_data = (kernel_ulong_t)&sdhci_o2, 1481 }, 1482 1483 { 1484 .vendor = PCI_VENDOR_ID_O2, 1485 .device = PCI_DEVICE_ID_O2_8321, 1486 .subvendor = PCI_ANY_ID, 1487 .subdevice = PCI_ANY_ID, 1488 .driver_data = (kernel_ulong_t)&sdhci_o2, 1489 }, 1490 1491 { 1492 .vendor = PCI_VENDOR_ID_O2, 1493 .device = PCI_DEVICE_ID_O2_FUJIN2, 1494 .subvendor = PCI_ANY_ID, 1495 .subdevice = PCI_ANY_ID, 1496 .driver_data = (kernel_ulong_t)&sdhci_o2, 1497 }, 1498 1499 { 1500 .vendor = PCI_VENDOR_ID_O2, 1501 .device = PCI_DEVICE_ID_O2_SDS0, 1502 .subvendor = PCI_ANY_ID, 1503 .subdevice = PCI_ANY_ID, 1504 .driver_data = (kernel_ulong_t)&sdhci_o2, 1505 }, 1506 1507 { 1508 .vendor = PCI_VENDOR_ID_O2, 1509 .device = PCI_DEVICE_ID_O2_SDS1, 1510 .subvendor = PCI_ANY_ID, 1511 .subdevice = PCI_ANY_ID, 1512 .driver_data = (kernel_ulong_t)&sdhci_o2, 1513 }, 1514 1515 { 1516 .vendor = PCI_VENDOR_ID_O2, 1517 .device = PCI_DEVICE_ID_O2_SEABIRD0, 1518 .subvendor = PCI_ANY_ID, 1519 .subdevice = PCI_ANY_ID, 1520 .driver_data = (kernel_ulong_t)&sdhci_o2, 1521 }, 1522 1523 { 1524 .vendor = PCI_VENDOR_ID_O2, 1525 .device = PCI_DEVICE_ID_O2_SEABIRD1, 1526 .subvendor = PCI_ANY_ID, 1527 .subdevice = PCI_ANY_ID, 1528 .driver_data = (kernel_ulong_t)&sdhci_o2, 1529 }, 1530 { 1531 .vendor = PCI_VENDOR_ID_AMD, 1532 .device = PCI_ANY_ID, 1533 .class = PCI_CLASS_SYSTEM_SDHCI << 8, 1534 .class_mask = 0xFFFF00, 1535 .subvendor = PCI_ANY_ID, 1536 .subdevice = PCI_ANY_ID, 1537 .driver_data = (kernel_ulong_t)&sdhci_amd, 1538 }, 1539 { /* Generic SD host controller */ 1540 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) 1541 }, 1542 1543 { /* end: all zeroes */ }, 1544 }; 1545 1546 MODULE_DEVICE_TABLE(pci, pci_ids); 1547 1548 /*****************************************************************************\ 1549 * * 1550 * SDHCI core callbacks * 1551 * * 1552 \*****************************************************************************/ 1553 1554 static int sdhci_pci_enable_dma(struct sdhci_host *host) 1555 { 1556 struct sdhci_pci_slot *slot; 1557 struct pci_dev *pdev; 1558 1559 slot = sdhci_priv(host); 1560 pdev = slot->chip->pdev; 1561 1562 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1563 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1564 (host->flags & SDHCI_USE_SDMA)) { 1565 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1566 "doesn't fully claim to support it.\n"); 1567 } 1568 1569 pci_set_master(pdev); 1570 1571 return 0; 1572 } 1573 1574 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width) 1575 { 1576 u8 ctrl; 1577 1578 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1579 1580 switch (width) { 1581 case MMC_BUS_WIDTH_8: 1582 ctrl |= SDHCI_CTRL_8BITBUS; 1583 ctrl &= ~SDHCI_CTRL_4BITBUS; 1584 break; 1585 case MMC_BUS_WIDTH_4: 1586 ctrl |= SDHCI_CTRL_4BITBUS; 1587 ctrl &= ~SDHCI_CTRL_8BITBUS; 1588 break; 1589 default: 1590 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS); 1591 break; 1592 } 1593 1594 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1595 } 1596 1597 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1598 { 1599 struct sdhci_pci_slot *slot = sdhci_priv(host); 1600 int rst_n_gpio = slot->rst_n_gpio; 1601 1602 if (!gpio_is_valid(rst_n_gpio)) 1603 return; 1604 gpio_set_value_cansleep(rst_n_gpio, 0); 1605 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1606 udelay(10); 1607 gpio_set_value_cansleep(rst_n_gpio, 1); 1608 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1609 usleep_range(300, 1000); 1610 } 1611 1612 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1613 { 1614 struct sdhci_pci_slot *slot = sdhci_priv(host); 1615 1616 if (slot->hw_reset) 1617 slot->hw_reset(host); 1618 } 1619 1620 static int sdhci_pci_select_drive_strength(struct sdhci_host *host, 1621 struct mmc_card *card, 1622 unsigned int max_dtr, int host_drv, 1623 int card_drv, int *drv_type) 1624 { 1625 struct sdhci_pci_slot *slot = sdhci_priv(host); 1626 1627 if (!slot->select_drive_strength) 1628 return 0; 1629 1630 return slot->select_drive_strength(host, card, max_dtr, host_drv, 1631 card_drv, drv_type); 1632 } 1633 1634 static const struct sdhci_ops sdhci_pci_ops = { 1635 .set_clock = sdhci_set_clock, 1636 .enable_dma = sdhci_pci_enable_dma, 1637 .set_bus_width = sdhci_pci_set_bus_width, 1638 .reset = sdhci_reset, 1639 .set_uhs_signaling = sdhci_set_uhs_signaling, 1640 .hw_reset = sdhci_pci_hw_reset, 1641 .select_drive_strength = sdhci_pci_select_drive_strength, 1642 }; 1643 1644 /*****************************************************************************\ 1645 * * 1646 * Suspend/resume * 1647 * * 1648 \*****************************************************************************/ 1649 1650 #ifdef CONFIG_PM_SLEEP 1651 static int sdhci_pci_suspend(struct device *dev) 1652 { 1653 struct pci_dev *pdev = to_pci_dev(dev); 1654 struct sdhci_pci_chip *chip; 1655 struct sdhci_pci_slot *slot; 1656 struct sdhci_host *host; 1657 mmc_pm_flag_t slot_pm_flags; 1658 mmc_pm_flag_t pm_flags = 0; 1659 int i, ret; 1660 1661 chip = pci_get_drvdata(pdev); 1662 if (!chip) 1663 return 0; 1664 1665 for (i = 0; i < chip->num_slots; i++) { 1666 slot = chip->slots[i]; 1667 if (!slot) 1668 continue; 1669 1670 host = slot->host; 1671 1672 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 1673 mmc_retune_needed(host->mmc); 1674 1675 ret = sdhci_suspend_host(host); 1676 1677 if (ret) 1678 goto err_pci_suspend; 1679 1680 slot_pm_flags = host->mmc->pm_flags; 1681 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1682 sdhci_enable_irq_wakeups(host); 1683 1684 pm_flags |= slot_pm_flags; 1685 } 1686 1687 if (chip->fixes && chip->fixes->suspend) { 1688 ret = chip->fixes->suspend(chip); 1689 if (ret) 1690 goto err_pci_suspend; 1691 } 1692 1693 if (pm_flags & MMC_PM_KEEP_POWER) { 1694 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1695 device_init_wakeup(dev, true); 1696 else 1697 device_init_wakeup(dev, false); 1698 } else 1699 device_init_wakeup(dev, false); 1700 1701 return 0; 1702 1703 err_pci_suspend: 1704 while (--i >= 0) 1705 sdhci_resume_host(chip->slots[i]->host); 1706 return ret; 1707 } 1708 1709 static int sdhci_pci_resume(struct device *dev) 1710 { 1711 struct pci_dev *pdev = to_pci_dev(dev); 1712 struct sdhci_pci_chip *chip; 1713 struct sdhci_pci_slot *slot; 1714 int i, ret; 1715 1716 chip = pci_get_drvdata(pdev); 1717 if (!chip) 1718 return 0; 1719 1720 if (chip->fixes && chip->fixes->resume) { 1721 ret = chip->fixes->resume(chip); 1722 if (ret) 1723 return ret; 1724 } 1725 1726 for (i = 0; i < chip->num_slots; i++) { 1727 slot = chip->slots[i]; 1728 if (!slot) 1729 continue; 1730 1731 ret = sdhci_resume_host(slot->host); 1732 if (ret) 1733 return ret; 1734 } 1735 1736 return 0; 1737 } 1738 #endif 1739 1740 #ifdef CONFIG_PM 1741 static int sdhci_pci_runtime_suspend(struct device *dev) 1742 { 1743 struct pci_dev *pdev = to_pci_dev(dev); 1744 struct sdhci_pci_chip *chip; 1745 struct sdhci_pci_slot *slot; 1746 struct sdhci_host *host; 1747 int i, ret; 1748 1749 chip = pci_get_drvdata(pdev); 1750 if (!chip) 1751 return 0; 1752 1753 for (i = 0; i < chip->num_slots; i++) { 1754 slot = chip->slots[i]; 1755 if (!slot) 1756 continue; 1757 1758 host = slot->host; 1759 1760 ret = sdhci_runtime_suspend_host(host); 1761 if (ret) 1762 goto err_pci_runtime_suspend; 1763 1764 if (chip->rpm_retune && 1765 host->tuning_mode != SDHCI_TUNING_MODE_3) 1766 mmc_retune_needed(host->mmc); 1767 } 1768 1769 if (chip->fixes && chip->fixes->suspend) { 1770 ret = chip->fixes->suspend(chip); 1771 if (ret) 1772 goto err_pci_runtime_suspend; 1773 } 1774 1775 return 0; 1776 1777 err_pci_runtime_suspend: 1778 while (--i >= 0) 1779 sdhci_runtime_resume_host(chip->slots[i]->host); 1780 return ret; 1781 } 1782 1783 static int sdhci_pci_runtime_resume(struct device *dev) 1784 { 1785 struct pci_dev *pdev = to_pci_dev(dev); 1786 struct sdhci_pci_chip *chip; 1787 struct sdhci_pci_slot *slot; 1788 int i, ret; 1789 1790 chip = pci_get_drvdata(pdev); 1791 if (!chip) 1792 return 0; 1793 1794 if (chip->fixes && chip->fixes->resume) { 1795 ret = chip->fixes->resume(chip); 1796 if (ret) 1797 return ret; 1798 } 1799 1800 for (i = 0; i < chip->num_slots; i++) { 1801 slot = chip->slots[i]; 1802 if (!slot) 1803 continue; 1804 1805 ret = sdhci_runtime_resume_host(slot->host); 1806 if (ret) 1807 return ret; 1808 } 1809 1810 return 0; 1811 } 1812 #endif 1813 1814 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1815 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1816 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1817 sdhci_pci_runtime_resume, NULL) 1818 }; 1819 1820 /*****************************************************************************\ 1821 * * 1822 * Device probing/removal * 1823 * * 1824 \*****************************************************************************/ 1825 1826 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1827 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1828 int slotno) 1829 { 1830 struct sdhci_pci_slot *slot; 1831 struct sdhci_host *host; 1832 int ret, bar = first_bar + slotno; 1833 1834 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1835 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1836 return ERR_PTR(-ENODEV); 1837 } 1838 1839 if (pci_resource_len(pdev, bar) < 0x100) { 1840 dev_err(&pdev->dev, "Invalid iomem size. You may " 1841 "experience problems.\n"); 1842 } 1843 1844 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1845 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1846 return ERR_PTR(-ENODEV); 1847 } 1848 1849 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1850 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1851 return ERR_PTR(-ENODEV); 1852 } 1853 1854 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot)); 1855 if (IS_ERR(host)) { 1856 dev_err(&pdev->dev, "cannot allocate host\n"); 1857 return ERR_CAST(host); 1858 } 1859 1860 slot = sdhci_priv(host); 1861 1862 slot->chip = chip; 1863 slot->host = host; 1864 slot->rst_n_gpio = -EINVAL; 1865 slot->cd_gpio = -EINVAL; 1866 slot->cd_idx = -1; 1867 1868 /* Retrieve platform data if there is any */ 1869 if (*sdhci_pci_get_data) 1870 slot->data = sdhci_pci_get_data(pdev, slotno); 1871 1872 if (slot->data) { 1873 if (slot->data->setup) { 1874 ret = slot->data->setup(slot->data); 1875 if (ret) { 1876 dev_err(&pdev->dev, "platform setup failed\n"); 1877 goto free; 1878 } 1879 } 1880 slot->rst_n_gpio = slot->data->rst_n_gpio; 1881 slot->cd_gpio = slot->data->cd_gpio; 1882 } 1883 1884 host->hw_name = "PCI"; 1885 host->ops = chip->fixes && chip->fixes->ops ? 1886 chip->fixes->ops : 1887 &sdhci_pci_ops; 1888 host->quirks = chip->quirks; 1889 host->quirks2 = chip->quirks2; 1890 1891 host->irq = pdev->irq; 1892 1893 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1894 if (ret) { 1895 dev_err(&pdev->dev, "cannot request region\n"); 1896 goto cleanup; 1897 } 1898 1899 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1900 1901 if (chip->fixes && chip->fixes->probe_slot) { 1902 ret = chip->fixes->probe_slot(slot); 1903 if (ret) 1904 goto cleanup; 1905 } 1906 1907 if (gpio_is_valid(slot->rst_n_gpio)) { 1908 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1909 gpio_direction_output(slot->rst_n_gpio, 1); 1910 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1911 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1912 } else { 1913 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1914 slot->rst_n_gpio = -EINVAL; 1915 } 1916 } 1917 1918 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; 1919 host->mmc->slotno = slotno; 1920 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1921 1922 if (slot->cd_idx >= 0) { 1923 ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx, 1924 slot->cd_override_level, 0, NULL); 1925 if (ret == -EPROBE_DEFER) 1926 goto remove; 1927 1928 if (ret) { 1929 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 1930 slot->cd_idx = -1; 1931 } 1932 } 1933 1934 ret = sdhci_add_host(host); 1935 if (ret) 1936 goto remove; 1937 1938 sdhci_pci_add_own_cd(slot); 1939 1940 /* 1941 * Check if the chip needs a separate GPIO for card detect to wake up 1942 * from runtime suspend. If it is not there, don't allow runtime PM. 1943 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 1944 */ 1945 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 1946 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 1947 chip->allow_runtime_pm = false; 1948 1949 return slot; 1950 1951 remove: 1952 if (chip->fixes && chip->fixes->remove_slot) 1953 chip->fixes->remove_slot(slot, 0); 1954 1955 cleanup: 1956 if (slot->data && slot->data->cleanup) 1957 slot->data->cleanup(slot->data); 1958 1959 free: 1960 sdhci_free_host(host); 1961 1962 return ERR_PTR(ret); 1963 } 1964 1965 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 1966 { 1967 int dead; 1968 u32 scratch; 1969 1970 sdhci_pci_remove_own_cd(slot); 1971 1972 dead = 0; 1973 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 1974 if (scratch == (u32)-1) 1975 dead = 1; 1976 1977 sdhci_remove_host(slot->host, dead); 1978 1979 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 1980 slot->chip->fixes->remove_slot(slot, dead); 1981 1982 if (slot->data && slot->data->cleanup) 1983 slot->data->cleanup(slot->data); 1984 1985 sdhci_free_host(slot->host); 1986 } 1987 1988 static void sdhci_pci_runtime_pm_allow(struct device *dev) 1989 { 1990 pm_suspend_ignore_children(dev, 1); 1991 pm_runtime_set_autosuspend_delay(dev, 50); 1992 pm_runtime_use_autosuspend(dev); 1993 pm_runtime_allow(dev); 1994 /* Stay active until mmc core scans for a card */ 1995 pm_runtime_put_noidle(dev); 1996 } 1997 1998 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 1999 { 2000 pm_runtime_forbid(dev); 2001 pm_runtime_get_noresume(dev); 2002 } 2003 2004 static int sdhci_pci_probe(struct pci_dev *pdev, 2005 const struct pci_device_id *ent) 2006 { 2007 struct sdhci_pci_chip *chip; 2008 struct sdhci_pci_slot *slot; 2009 2010 u8 slots, first_bar; 2011 int ret, i; 2012 2013 BUG_ON(pdev == NULL); 2014 BUG_ON(ent == NULL); 2015 2016 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 2017 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 2018 2019 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 2020 if (ret) 2021 return ret; 2022 2023 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 2024 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 2025 if (slots == 0) 2026 return -ENODEV; 2027 2028 BUG_ON(slots > MAX_SLOTS); 2029 2030 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 2031 if (ret) 2032 return ret; 2033 2034 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 2035 2036 if (first_bar > 5) { 2037 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 2038 return -ENODEV; 2039 } 2040 2041 ret = pcim_enable_device(pdev); 2042 if (ret) 2043 return ret; 2044 2045 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 2046 if (!chip) 2047 return -ENOMEM; 2048 2049 chip->pdev = pdev; 2050 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 2051 if (chip->fixes) { 2052 chip->quirks = chip->fixes->quirks; 2053 chip->quirks2 = chip->fixes->quirks2; 2054 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 2055 } 2056 chip->num_slots = slots; 2057 chip->pm_retune = true; 2058 chip->rpm_retune = true; 2059 2060 pci_set_drvdata(pdev, chip); 2061 2062 if (chip->fixes && chip->fixes->probe) { 2063 ret = chip->fixes->probe(chip); 2064 if (ret) 2065 return ret; 2066 } 2067 2068 slots = chip->num_slots; /* Quirk may have changed this */ 2069 2070 for (i = 0; i < slots; i++) { 2071 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 2072 if (IS_ERR(slot)) { 2073 for (i--; i >= 0; i--) 2074 sdhci_pci_remove_slot(chip->slots[i]); 2075 return PTR_ERR(slot); 2076 } 2077 2078 chip->slots[i] = slot; 2079 } 2080 2081 if (chip->allow_runtime_pm) 2082 sdhci_pci_runtime_pm_allow(&pdev->dev); 2083 2084 return 0; 2085 } 2086 2087 static void sdhci_pci_remove(struct pci_dev *pdev) 2088 { 2089 int i; 2090 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 2091 2092 if (chip->allow_runtime_pm) 2093 sdhci_pci_runtime_pm_forbid(&pdev->dev); 2094 2095 for (i = 0; i < chip->num_slots; i++) 2096 sdhci_pci_remove_slot(chip->slots[i]); 2097 } 2098 2099 static struct pci_driver sdhci_driver = { 2100 .name = "sdhci-pci", 2101 .id_table = pci_ids, 2102 .probe = sdhci_pci_probe, 2103 .remove = sdhci_pci_remove, 2104 .driver = { 2105 .pm = &sdhci_pci_pm_ops 2106 }, 2107 }; 2108 2109 module_pci_driver(sdhci_driver); 2110 2111 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 2112 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 2113 MODULE_LICENSE("GPL"); 2114