1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 2 * 3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 * 10 * Thanks to the following companies for their support: 11 * 12 * - JMicron (hardware and technical support) 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/highmem.h> 17 #include <linux/module.h> 18 #include <linux/pci.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/slab.h> 21 #include <linux/device.h> 22 #include <linux/mmc/host.h> 23 #include <linux/mmc/mmc.h> 24 #include <linux/scatterlist.h> 25 #include <linux/io.h> 26 #include <linux/gpio.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/mmc/slot-gpio.h> 29 #include <linux/mmc/sdhci-pci-data.h> 30 #include <linux/acpi.h> 31 32 #include "sdhci.h" 33 #include "sdhci-pci.h" 34 #include "sdhci-pci-o2micro.h" 35 36 static int sdhci_pci_enable_dma(struct sdhci_host *host); 37 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width); 38 static void sdhci_pci_hw_reset(struct sdhci_host *host); 39 40 /*****************************************************************************\ 41 * * 42 * Hardware specific quirk handling * 43 * * 44 \*****************************************************************************/ 45 46 static int ricoh_probe(struct sdhci_pci_chip *chip) 47 { 48 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 49 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 50 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 51 return 0; 52 } 53 54 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 55 { 56 slot->host->caps = 57 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 58 & SDHCI_TIMEOUT_CLK_MASK) | 59 60 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 61 & SDHCI_CLOCK_BASE_MASK) | 62 63 SDHCI_TIMEOUT_CLK_UNIT | 64 SDHCI_CAN_VDD_330 | 65 SDHCI_CAN_DO_HISPD | 66 SDHCI_CAN_DO_SDMA; 67 return 0; 68 } 69 70 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 71 { 72 /* Apply a delay to allow controller to settle */ 73 /* Otherwise it becomes confused if card state changed 74 during suspend */ 75 msleep(500); 76 return 0; 77 } 78 79 static const struct sdhci_pci_fixes sdhci_ricoh = { 80 .probe = ricoh_probe, 81 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 82 SDHCI_QUIRK_FORCE_DMA | 83 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 84 }; 85 86 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 87 .probe_slot = ricoh_mmc_probe_slot, 88 .resume = ricoh_mmc_resume, 89 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 90 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 91 SDHCI_QUIRK_NO_CARD_NO_RESET | 92 SDHCI_QUIRK_MISSING_CAPS 93 }; 94 95 static const struct sdhci_pci_fixes sdhci_ene_712 = { 96 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 97 SDHCI_QUIRK_BROKEN_DMA, 98 }; 99 100 static const struct sdhci_pci_fixes sdhci_ene_714 = { 101 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 102 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 103 SDHCI_QUIRK_BROKEN_DMA, 104 }; 105 106 static const struct sdhci_pci_fixes sdhci_cafe = { 107 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 108 SDHCI_QUIRK_NO_BUSY_IRQ | 109 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 110 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 111 }; 112 113 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 114 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 115 }; 116 117 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 118 { 119 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 120 return 0; 121 } 122 123 /* 124 * ADMA operation is disabled for Moorestown platform due to 125 * hardware bugs. 126 */ 127 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 128 { 129 /* 130 * slots number is fixed here for MRST as SDIO3/5 are never used and 131 * have hardware bugs. 132 */ 133 chip->num_slots = 1; 134 return 0; 135 } 136 137 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 138 { 139 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 140 return 0; 141 } 142 143 #ifdef CONFIG_PM 144 145 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 146 { 147 struct sdhci_pci_slot *slot = dev_id; 148 struct sdhci_host *host = slot->host; 149 150 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 151 return IRQ_HANDLED; 152 } 153 154 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 155 { 156 int err, irq, gpio = slot->cd_gpio; 157 158 slot->cd_gpio = -EINVAL; 159 slot->cd_irq = -EINVAL; 160 161 if (!gpio_is_valid(gpio)) 162 return; 163 164 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 165 if (err < 0) 166 goto out; 167 168 err = gpio_direction_input(gpio); 169 if (err < 0) 170 goto out_free; 171 172 irq = gpio_to_irq(gpio); 173 if (irq < 0) 174 goto out_free; 175 176 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 177 IRQF_TRIGGER_FALLING, "sd_cd", slot); 178 if (err) 179 goto out_free; 180 181 slot->cd_gpio = gpio; 182 slot->cd_irq = irq; 183 184 return; 185 186 out_free: 187 devm_gpio_free(&slot->chip->pdev->dev, gpio); 188 out: 189 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 190 } 191 192 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 193 { 194 if (slot->cd_irq >= 0) 195 free_irq(slot->cd_irq, slot); 196 } 197 198 #else 199 200 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 201 { 202 } 203 204 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 205 { 206 } 207 208 #endif 209 210 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 211 { 212 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 213 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC | 214 MMC_CAP2_HC_ERASE_SZ; 215 return 0; 216 } 217 218 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 219 { 220 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 221 return 0; 222 } 223 224 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 225 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 226 .probe_slot = mrst_hc_probe_slot, 227 }; 228 229 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 230 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 231 .probe = mrst_hc_probe, 232 }; 233 234 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 235 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 236 .allow_runtime_pm = true, 237 .own_cd_for_runtime_pm = true, 238 }; 239 240 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 241 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 242 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 243 .allow_runtime_pm = true, 244 .probe_slot = mfd_sdio_probe_slot, 245 }; 246 247 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 248 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 249 .allow_runtime_pm = true, 250 .probe_slot = mfd_emmc_probe_slot, 251 }; 252 253 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 254 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 255 .probe_slot = pch_hc_probe_slot, 256 }; 257 258 enum { 259 INTEL_DSM_FNS = 0, 260 INTEL_DSM_DRV_STRENGTH = 9, 261 INTEL_DSM_D3_RETUNE = 10, 262 }; 263 264 struct intel_host { 265 u32 dsm_fns; 266 int drv_strength; 267 bool d3_retune; 268 }; 269 270 const u8 intel_dsm_uuid[] = { 271 0xA5, 0x3E, 0xC1, 0xF6, 0xCD, 0x65, 0x1F, 0x46, 272 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61, 273 }; 274 275 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 276 unsigned int fn, u32 *result) 277 { 278 union acpi_object *obj; 279 int err = 0; 280 281 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), intel_dsm_uuid, 0, fn, NULL); 282 if (!obj) 283 return -EOPNOTSUPP; 284 285 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { 286 err = -EINVAL; 287 goto out; 288 } 289 290 if (obj->buffer.length >= 4) 291 *result = *(u32 *)obj->buffer.pointer; 292 else if (obj->buffer.length >= 2) 293 *result = *(u16 *)obj->buffer.pointer; 294 else 295 *result = *(u8 *)obj->buffer.pointer; 296 out: 297 ACPI_FREE(obj); 298 299 return err; 300 } 301 302 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 303 unsigned int fn, u32 *result) 304 { 305 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 306 return -EOPNOTSUPP; 307 308 return __intel_dsm(intel_host, dev, fn, result); 309 } 310 311 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 312 struct mmc_host *mmc) 313 { 314 int err; 315 u32 val; 316 317 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 318 if (err) { 319 pr_debug("%s: DSM not supported, error %d\n", 320 mmc_hostname(mmc), err); 321 return; 322 } 323 324 pr_debug("%s: DSM function mask %#x\n", 325 mmc_hostname(mmc), intel_host->dsm_fns); 326 327 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 328 intel_host->drv_strength = err ? 0 : val; 329 330 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 331 intel_host->d3_retune = err ? true : !!val; 332 } 333 334 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 335 { 336 u8 reg; 337 338 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 339 reg |= 0x10; 340 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 341 /* For eMMC, minimum is 1us but give it 9us for good measure */ 342 udelay(9); 343 reg &= ~0x10; 344 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 345 /* For eMMC, minimum is 200us but give it 300us for good measure */ 346 usleep_range(300, 1000); 347 } 348 349 static int intel_select_drive_strength(struct mmc_card *card, 350 unsigned int max_dtr, int host_drv, 351 int card_drv, int *drv_type) 352 { 353 struct sdhci_host *host = mmc_priv(card->host); 354 struct sdhci_pci_slot *slot = sdhci_priv(host); 355 struct intel_host *intel_host = sdhci_pci_priv(slot); 356 357 return intel_host->drv_strength; 358 } 359 360 static int bxt_get_cd(struct mmc_host *mmc) 361 { 362 int gpio_cd = mmc_gpio_get_cd(mmc); 363 struct sdhci_host *host = mmc_priv(mmc); 364 unsigned long flags; 365 int ret = 0; 366 367 if (!gpio_cd) 368 return 0; 369 370 spin_lock_irqsave(&host->lock, flags); 371 372 if (host->flags & SDHCI_DEVICE_DEAD) 373 goto out; 374 375 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 376 out: 377 spin_unlock_irqrestore(&host->lock, flags); 378 379 return ret; 380 } 381 382 static void byt_read_dsm(struct sdhci_pci_slot *slot) 383 { 384 struct intel_host *intel_host = sdhci_pci_priv(slot); 385 struct device *dev = &slot->chip->pdev->dev; 386 struct mmc_host *mmc = slot->host->mmc; 387 388 intel_dsm_init(intel_host, dev, mmc); 389 slot->chip->rpm_retune = intel_host->d3_retune; 390 } 391 392 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 393 { 394 byt_read_dsm(slot); 395 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 396 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 397 MMC_CAP_CMD_DURING_TFR | 398 MMC_CAP_WAIT_WHILE_BUSY; 399 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ; 400 slot->hw_reset = sdhci_pci_int_hw_reset; 401 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 402 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 403 slot->host->mmc_host_ops.select_drive_strength = 404 intel_select_drive_strength; 405 return 0; 406 } 407 408 #ifdef CONFIG_ACPI 409 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 410 { 411 acpi_status status; 412 unsigned long long max_freq; 413 414 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 415 "MXFQ", NULL, &max_freq); 416 if (ACPI_FAILURE(status)) { 417 dev_err(&slot->chip->pdev->dev, 418 "MXFQ not found in acpi table\n"); 419 return -EINVAL; 420 } 421 422 slot->host->mmc->f_max = max_freq * 1000000; 423 424 return 0; 425 } 426 #else 427 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 428 { 429 return 0; 430 } 431 #endif 432 433 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 434 { 435 int err; 436 437 byt_read_dsm(slot); 438 439 err = ni_set_max_freq(slot); 440 if (err) 441 return err; 442 443 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 444 MMC_CAP_WAIT_WHILE_BUSY; 445 return 0; 446 } 447 448 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 449 { 450 byt_read_dsm(slot); 451 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 452 MMC_CAP_WAIT_WHILE_BUSY; 453 return 0; 454 } 455 456 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 457 { 458 byt_read_dsm(slot); 459 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 460 slot->cd_idx = 0; 461 slot->cd_override_level = true; 462 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 463 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 464 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 465 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) { 466 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 467 slot->host->mmc->caps |= MMC_CAP_AGGRESSIVE_PM; 468 } 469 470 return 0; 471 } 472 473 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 474 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 475 476 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 477 unsigned short vdd) 478 { 479 int cntr; 480 u8 reg; 481 482 sdhci_set_power(host, mode, vdd); 483 484 if (mode == MMC_POWER_OFF) 485 return; 486 487 /* 488 * Bus power might not enable after D3 -> D0 transition due to the 489 * present state not yet having propagated. Retry for up to 2ms. 490 */ 491 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 492 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 493 if (reg & SDHCI_POWER_ON) 494 break; 495 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 496 reg |= SDHCI_POWER_ON; 497 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 498 } 499 } 500 501 static const struct sdhci_ops sdhci_intel_byt_ops = { 502 .set_clock = sdhci_set_clock, 503 .set_power = sdhci_intel_set_power, 504 .enable_dma = sdhci_pci_enable_dma, 505 .set_bus_width = sdhci_pci_set_bus_width, 506 .reset = sdhci_reset, 507 .set_uhs_signaling = sdhci_set_uhs_signaling, 508 .hw_reset = sdhci_pci_hw_reset, 509 }; 510 511 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 512 .allow_runtime_pm = true, 513 .probe_slot = byt_emmc_probe_slot, 514 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 515 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 516 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 517 SDHCI_QUIRK2_STOP_WITH_TC, 518 .ops = &sdhci_intel_byt_ops, 519 .priv_size = sizeof(struct intel_host), 520 }; 521 522 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 523 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 524 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 525 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 526 .allow_runtime_pm = true, 527 .probe_slot = ni_byt_sdio_probe_slot, 528 .ops = &sdhci_intel_byt_ops, 529 .priv_size = sizeof(struct intel_host), 530 }; 531 532 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 533 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 534 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 535 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 536 .allow_runtime_pm = true, 537 .probe_slot = byt_sdio_probe_slot, 538 .ops = &sdhci_intel_byt_ops, 539 .priv_size = sizeof(struct intel_host), 540 }; 541 542 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 543 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 544 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 545 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 546 SDHCI_QUIRK2_STOP_WITH_TC, 547 .allow_runtime_pm = true, 548 .own_cd_for_runtime_pm = true, 549 .probe_slot = byt_sd_probe_slot, 550 .ops = &sdhci_intel_byt_ops, 551 .priv_size = sizeof(struct intel_host), 552 }; 553 554 /* Define Host controllers for Intel Merrifield platform */ 555 #define INTEL_MRFLD_EMMC_0 0 556 #define INTEL_MRFLD_EMMC_1 1 557 #define INTEL_MRFLD_SD 2 558 #define INTEL_MRFLD_SDIO 3 559 560 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 561 { 562 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 563 564 switch (func) { 565 case INTEL_MRFLD_EMMC_0: 566 case INTEL_MRFLD_EMMC_1: 567 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 568 MMC_CAP_8_BIT_DATA | 569 MMC_CAP_1_8V_DDR; 570 break; 571 case INTEL_MRFLD_SD: 572 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 573 break; 574 case INTEL_MRFLD_SDIO: 575 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 576 MMC_CAP_POWER_OFF_CARD; 577 break; 578 default: 579 return -ENODEV; 580 } 581 return 0; 582 } 583 584 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 585 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 586 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 587 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 588 .allow_runtime_pm = true, 589 .probe_slot = intel_mrfld_mmc_probe_slot, 590 }; 591 592 /* O2Micro extra registers */ 593 #define O2_SD_LOCK_WP 0xD3 594 #define O2_SD_MULTI_VCC3V 0xEE 595 #define O2_SD_CLKREQ 0xEC 596 #define O2_SD_CAPS 0xE0 597 #define O2_SD_ADMA1 0xE2 598 #define O2_SD_ADMA2 0xE7 599 #define O2_SD_INF_MOD 0xF1 600 601 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 602 { 603 u8 scratch; 604 int ret; 605 606 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 607 if (ret) 608 return ret; 609 610 /* 611 * Turn PMOS on [bit 0], set over current detection to 2.4 V 612 * [bit 1:2] and enable over current debouncing [bit 6]. 613 */ 614 if (on) 615 scratch |= 0x47; 616 else 617 scratch &= ~0x47; 618 619 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 620 } 621 622 static int jmicron_probe(struct sdhci_pci_chip *chip) 623 { 624 int ret; 625 u16 mmcdev = 0; 626 627 if (chip->pdev->revision == 0) { 628 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 629 SDHCI_QUIRK_32BIT_DMA_SIZE | 630 SDHCI_QUIRK_32BIT_ADMA_SIZE | 631 SDHCI_QUIRK_RESET_AFTER_REQUEST | 632 SDHCI_QUIRK_BROKEN_SMALL_PIO; 633 } 634 635 /* 636 * JMicron chips can have two interfaces to the same hardware 637 * in order to work around limitations in Microsoft's driver. 638 * We need to make sure we only bind to one of them. 639 * 640 * This code assumes two things: 641 * 642 * 1. The PCI code adds subfunctions in order. 643 * 644 * 2. The MMC interface has a lower subfunction number 645 * than the SD interface. 646 */ 647 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 648 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 649 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 650 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 651 652 if (mmcdev) { 653 struct pci_dev *sd_dev; 654 655 sd_dev = NULL; 656 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 657 mmcdev, sd_dev)) != NULL) { 658 if ((PCI_SLOT(chip->pdev->devfn) == 659 PCI_SLOT(sd_dev->devfn)) && 660 (chip->pdev->bus == sd_dev->bus)) 661 break; 662 } 663 664 if (sd_dev) { 665 pci_dev_put(sd_dev); 666 dev_info(&chip->pdev->dev, "Refusing to bind to " 667 "secondary interface.\n"); 668 return -ENODEV; 669 } 670 } 671 672 /* 673 * JMicron chips need a bit of a nudge to enable the power 674 * output pins. 675 */ 676 ret = jmicron_pmos(chip, 1); 677 if (ret) { 678 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 679 return ret; 680 } 681 682 /* quirk for unsable RO-detection on JM388 chips */ 683 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 684 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 685 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 686 687 return 0; 688 } 689 690 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 691 { 692 u8 scratch; 693 694 scratch = readb(host->ioaddr + 0xC0); 695 696 if (on) 697 scratch |= 0x01; 698 else 699 scratch &= ~0x01; 700 701 writeb(scratch, host->ioaddr + 0xC0); 702 } 703 704 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 705 { 706 if (slot->chip->pdev->revision == 0) { 707 u16 version; 708 709 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 710 version = (version & SDHCI_VENDOR_VER_MASK) >> 711 SDHCI_VENDOR_VER_SHIFT; 712 713 /* 714 * Older versions of the chip have lots of nasty glitches 715 * in the ADMA engine. It's best just to avoid it 716 * completely. 717 */ 718 if (version < 0xAC) 719 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 720 } 721 722 /* JM388 MMC doesn't support 1.8V while SD supports it */ 723 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 724 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 725 MMC_VDD_29_30 | MMC_VDD_30_31 | 726 MMC_VDD_165_195; /* allow 1.8V */ 727 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 728 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 729 } 730 731 /* 732 * The secondary interface requires a bit set to get the 733 * interrupts. 734 */ 735 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 736 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 737 jmicron_enable_mmc(slot->host, 1); 738 739 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 740 741 return 0; 742 } 743 744 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 745 { 746 if (dead) 747 return; 748 749 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 750 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 751 jmicron_enable_mmc(slot->host, 0); 752 } 753 754 static int jmicron_suspend(struct sdhci_pci_chip *chip) 755 { 756 int i; 757 758 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 759 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 760 for (i = 0; i < chip->num_slots; i++) 761 jmicron_enable_mmc(chip->slots[i]->host, 0); 762 } 763 764 return 0; 765 } 766 767 static int jmicron_resume(struct sdhci_pci_chip *chip) 768 { 769 int ret, i; 770 771 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 772 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 773 for (i = 0; i < chip->num_slots; i++) 774 jmicron_enable_mmc(chip->slots[i]->host, 1); 775 } 776 777 ret = jmicron_pmos(chip, 1); 778 if (ret) { 779 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 780 return ret; 781 } 782 783 return 0; 784 } 785 786 static const struct sdhci_pci_fixes sdhci_o2 = { 787 .probe = sdhci_pci_o2_probe, 788 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 789 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 790 .probe_slot = sdhci_pci_o2_probe_slot, 791 .resume = sdhci_pci_o2_resume, 792 }; 793 794 static const struct sdhci_pci_fixes sdhci_jmicron = { 795 .probe = jmicron_probe, 796 797 .probe_slot = jmicron_probe_slot, 798 .remove_slot = jmicron_remove_slot, 799 800 .suspend = jmicron_suspend, 801 .resume = jmicron_resume, 802 }; 803 804 /* SysKonnect CardBus2SDIO extra registers */ 805 #define SYSKT_CTRL 0x200 806 #define SYSKT_RDFIFO_STAT 0x204 807 #define SYSKT_WRFIFO_STAT 0x208 808 #define SYSKT_POWER_DATA 0x20c 809 #define SYSKT_POWER_330 0xef 810 #define SYSKT_POWER_300 0xf8 811 #define SYSKT_POWER_184 0xcc 812 #define SYSKT_POWER_CMD 0x20d 813 #define SYSKT_POWER_START (1 << 7) 814 #define SYSKT_POWER_STATUS 0x20e 815 #define SYSKT_POWER_STATUS_OK (1 << 0) 816 #define SYSKT_BOARD_REV 0x210 817 #define SYSKT_CHIP_REV 0x211 818 #define SYSKT_CONF_DATA 0x212 819 #define SYSKT_CONF_DATA_1V8 (1 << 2) 820 #define SYSKT_CONF_DATA_2V5 (1 << 1) 821 #define SYSKT_CONF_DATA_3V3 (1 << 0) 822 823 static int syskt_probe(struct sdhci_pci_chip *chip) 824 { 825 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 826 chip->pdev->class &= ~0x0000FF; 827 chip->pdev->class |= PCI_SDHCI_IFDMA; 828 } 829 return 0; 830 } 831 832 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 833 { 834 int tm, ps; 835 836 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 837 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 838 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 839 "board rev %d.%d, chip rev %d.%d\n", 840 board_rev >> 4, board_rev & 0xf, 841 chip_rev >> 4, chip_rev & 0xf); 842 if (chip_rev >= 0x20) 843 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 844 845 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 846 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 847 udelay(50); 848 tm = 10; /* Wait max 1 ms */ 849 do { 850 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 851 if (ps & SYSKT_POWER_STATUS_OK) 852 break; 853 udelay(100); 854 } while (--tm); 855 if (!tm) { 856 dev_err(&slot->chip->pdev->dev, 857 "power regulator never stabilized"); 858 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 859 return -ENODEV; 860 } 861 862 return 0; 863 } 864 865 static const struct sdhci_pci_fixes sdhci_syskt = { 866 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 867 .probe = syskt_probe, 868 .probe_slot = syskt_probe_slot, 869 }; 870 871 static int via_probe(struct sdhci_pci_chip *chip) 872 { 873 if (chip->pdev->revision == 0x10) 874 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 875 876 return 0; 877 } 878 879 static const struct sdhci_pci_fixes sdhci_via = { 880 .probe = via_probe, 881 }; 882 883 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 884 { 885 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 886 return 0; 887 } 888 889 static const struct sdhci_pci_fixes sdhci_rtsx = { 890 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 891 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 892 SDHCI_QUIRK2_BROKEN_DDR50, 893 .probe_slot = rtsx_probe_slot, 894 }; 895 896 /*AMD chipset generation*/ 897 enum amd_chipset_gen { 898 AMD_CHIPSET_BEFORE_ML, 899 AMD_CHIPSET_CZ, 900 AMD_CHIPSET_NL, 901 AMD_CHIPSET_UNKNOWN, 902 }; 903 904 /* AMD registers */ 905 #define AMD_SD_AUTO_PATTERN 0xB8 906 #define AMD_MSLEEP_DURATION 4 907 #define AMD_SD_MISC_CONTROL 0xD0 908 #define AMD_MAX_TUNE_VALUE 0x0B 909 #define AMD_AUTO_TUNE_SEL 0x10800 910 #define AMD_FIFO_PTR 0x30 911 #define AMD_BIT_MASK 0x1F 912 913 static void amd_tuning_reset(struct sdhci_host *host) 914 { 915 unsigned int val; 916 917 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 918 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 919 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 920 921 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 922 val &= ~SDHCI_CTRL_EXEC_TUNING; 923 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 924 } 925 926 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 927 { 928 unsigned int val; 929 930 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 931 val &= ~AMD_BIT_MASK; 932 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 933 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 934 } 935 936 static void amd_enable_manual_tuning(struct pci_dev *pdev) 937 { 938 unsigned int val; 939 940 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 941 val |= AMD_FIFO_PTR; 942 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 943 } 944 945 static int amd_execute_tuning(struct sdhci_host *host, u32 opcode) 946 { 947 struct sdhci_pci_slot *slot = sdhci_priv(host); 948 struct pci_dev *pdev = slot->chip->pdev; 949 u8 valid_win = 0; 950 u8 valid_win_max = 0; 951 u8 valid_win_end = 0; 952 u8 ctrl, tune_around; 953 954 amd_tuning_reset(host); 955 956 for (tune_around = 0; tune_around < 12; tune_around++) { 957 amd_config_tuning_phase(pdev, tune_around); 958 959 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 960 valid_win = 0; 961 msleep(AMD_MSLEEP_DURATION); 962 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 963 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 964 } else if (++valid_win > valid_win_max) { 965 valid_win_max = valid_win; 966 valid_win_end = tune_around; 967 } 968 } 969 970 if (!valid_win_max) { 971 dev_err(&pdev->dev, "no tuning point found\n"); 972 return -EIO; 973 } 974 975 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 976 977 amd_enable_manual_tuning(pdev); 978 979 host->mmc->retune_period = 0; 980 981 return 0; 982 } 983 984 static int amd_probe(struct sdhci_pci_chip *chip) 985 { 986 struct pci_dev *smbus_dev; 987 enum amd_chipset_gen gen; 988 989 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 990 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 991 if (smbus_dev) { 992 gen = AMD_CHIPSET_BEFORE_ML; 993 } else { 994 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 995 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 996 if (smbus_dev) { 997 if (smbus_dev->revision < 0x51) 998 gen = AMD_CHIPSET_CZ; 999 else 1000 gen = AMD_CHIPSET_NL; 1001 } else { 1002 gen = AMD_CHIPSET_UNKNOWN; 1003 } 1004 } 1005 1006 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1007 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1008 1009 return 0; 1010 } 1011 1012 static const struct sdhci_ops amd_sdhci_pci_ops = { 1013 .set_clock = sdhci_set_clock, 1014 .enable_dma = sdhci_pci_enable_dma, 1015 .set_bus_width = sdhci_pci_set_bus_width, 1016 .reset = sdhci_reset, 1017 .set_uhs_signaling = sdhci_set_uhs_signaling, 1018 .platform_execute_tuning = amd_execute_tuning, 1019 }; 1020 1021 static const struct sdhci_pci_fixes sdhci_amd = { 1022 .probe = amd_probe, 1023 .ops = &amd_sdhci_pci_ops, 1024 }; 1025 1026 static const struct pci_device_id pci_ids[] = { 1027 { 1028 .vendor = PCI_VENDOR_ID_RICOH, 1029 .device = PCI_DEVICE_ID_RICOH_R5C822, 1030 .subvendor = PCI_ANY_ID, 1031 .subdevice = PCI_ANY_ID, 1032 .driver_data = (kernel_ulong_t)&sdhci_ricoh, 1033 }, 1034 1035 { 1036 .vendor = PCI_VENDOR_ID_RICOH, 1037 .device = 0x843, 1038 .subvendor = PCI_ANY_ID, 1039 .subdevice = PCI_ANY_ID, 1040 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 1041 }, 1042 1043 { 1044 .vendor = PCI_VENDOR_ID_RICOH, 1045 .device = 0xe822, 1046 .subvendor = PCI_ANY_ID, 1047 .subdevice = PCI_ANY_ID, 1048 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 1049 }, 1050 1051 { 1052 .vendor = PCI_VENDOR_ID_RICOH, 1053 .device = 0xe823, 1054 .subvendor = PCI_ANY_ID, 1055 .subdevice = PCI_ANY_ID, 1056 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 1057 }, 1058 1059 { 1060 .vendor = PCI_VENDOR_ID_ENE, 1061 .device = PCI_DEVICE_ID_ENE_CB712_SD, 1062 .subvendor = PCI_ANY_ID, 1063 .subdevice = PCI_ANY_ID, 1064 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 1065 }, 1066 1067 { 1068 .vendor = PCI_VENDOR_ID_ENE, 1069 .device = PCI_DEVICE_ID_ENE_CB712_SD_2, 1070 .subvendor = PCI_ANY_ID, 1071 .subdevice = PCI_ANY_ID, 1072 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 1073 }, 1074 1075 { 1076 .vendor = PCI_VENDOR_ID_ENE, 1077 .device = PCI_DEVICE_ID_ENE_CB714_SD, 1078 .subvendor = PCI_ANY_ID, 1079 .subdevice = PCI_ANY_ID, 1080 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 1081 }, 1082 1083 { 1084 .vendor = PCI_VENDOR_ID_ENE, 1085 .device = PCI_DEVICE_ID_ENE_CB714_SD_2, 1086 .subvendor = PCI_ANY_ID, 1087 .subdevice = PCI_ANY_ID, 1088 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 1089 }, 1090 1091 { 1092 .vendor = PCI_VENDOR_ID_MARVELL, 1093 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD, 1094 .subvendor = PCI_ANY_ID, 1095 .subdevice = PCI_ANY_ID, 1096 .driver_data = (kernel_ulong_t)&sdhci_cafe, 1097 }, 1098 1099 { 1100 .vendor = PCI_VENDOR_ID_JMICRON, 1101 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD, 1102 .subvendor = PCI_ANY_ID, 1103 .subdevice = PCI_ANY_ID, 1104 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1105 }, 1106 1107 { 1108 .vendor = PCI_VENDOR_ID_JMICRON, 1109 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC, 1110 .subvendor = PCI_ANY_ID, 1111 .subdevice = PCI_ANY_ID, 1112 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1113 }, 1114 1115 { 1116 .vendor = PCI_VENDOR_ID_JMICRON, 1117 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD, 1118 .subvendor = PCI_ANY_ID, 1119 .subdevice = PCI_ANY_ID, 1120 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1121 }, 1122 1123 { 1124 .vendor = PCI_VENDOR_ID_JMICRON, 1125 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD, 1126 .subvendor = PCI_ANY_ID, 1127 .subdevice = PCI_ANY_ID, 1128 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1129 }, 1130 1131 { 1132 .vendor = PCI_VENDOR_ID_SYSKONNECT, 1133 .device = 0x8000, 1134 .subvendor = PCI_ANY_ID, 1135 .subdevice = PCI_ANY_ID, 1136 .driver_data = (kernel_ulong_t)&sdhci_syskt, 1137 }, 1138 1139 { 1140 .vendor = PCI_VENDOR_ID_VIA, 1141 .device = 0x95d0, 1142 .subvendor = PCI_ANY_ID, 1143 .subdevice = PCI_ANY_ID, 1144 .driver_data = (kernel_ulong_t)&sdhci_via, 1145 }, 1146 1147 { 1148 .vendor = PCI_VENDOR_ID_REALTEK, 1149 .device = 0x5250, 1150 .subvendor = PCI_ANY_ID, 1151 .subdevice = PCI_ANY_ID, 1152 .driver_data = (kernel_ulong_t)&sdhci_rtsx, 1153 }, 1154 1155 { 1156 .vendor = PCI_VENDOR_ID_INTEL, 1157 .device = PCI_DEVICE_ID_INTEL_QRK_SD, 1158 .subvendor = PCI_ANY_ID, 1159 .subdevice = PCI_ANY_ID, 1160 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk, 1161 }, 1162 1163 { 1164 .vendor = PCI_VENDOR_ID_INTEL, 1165 .device = PCI_DEVICE_ID_INTEL_MRST_SD0, 1166 .subvendor = PCI_ANY_ID, 1167 .subdevice = PCI_ANY_ID, 1168 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0, 1169 }, 1170 1171 { 1172 .vendor = PCI_VENDOR_ID_INTEL, 1173 .device = PCI_DEVICE_ID_INTEL_MRST_SD1, 1174 .subvendor = PCI_ANY_ID, 1175 .subdevice = PCI_ANY_ID, 1176 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 1177 }, 1178 1179 { 1180 .vendor = PCI_VENDOR_ID_INTEL, 1181 .device = PCI_DEVICE_ID_INTEL_MRST_SD2, 1182 .subvendor = PCI_ANY_ID, 1183 .subdevice = PCI_ANY_ID, 1184 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 1185 }, 1186 1187 { 1188 .vendor = PCI_VENDOR_ID_INTEL, 1189 .device = PCI_DEVICE_ID_INTEL_MFD_SD, 1190 .subvendor = PCI_ANY_ID, 1191 .subdevice = PCI_ANY_ID, 1192 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1193 }, 1194 1195 { 1196 .vendor = PCI_VENDOR_ID_INTEL, 1197 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1, 1198 .subvendor = PCI_ANY_ID, 1199 .subdevice = PCI_ANY_ID, 1200 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1201 }, 1202 1203 { 1204 .vendor = PCI_VENDOR_ID_INTEL, 1205 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2, 1206 .subvendor = PCI_ANY_ID, 1207 .subdevice = PCI_ANY_ID, 1208 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1209 }, 1210 1211 { 1212 .vendor = PCI_VENDOR_ID_INTEL, 1213 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0, 1214 .subvendor = PCI_ANY_ID, 1215 .subdevice = PCI_ANY_ID, 1216 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1217 }, 1218 1219 { 1220 .vendor = PCI_VENDOR_ID_INTEL, 1221 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1, 1222 .subvendor = PCI_ANY_ID, 1223 .subdevice = PCI_ANY_ID, 1224 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1225 }, 1226 1227 { 1228 .vendor = PCI_VENDOR_ID_INTEL, 1229 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0, 1230 .subvendor = PCI_ANY_ID, 1231 .subdevice = PCI_ANY_ID, 1232 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1233 }, 1234 1235 { 1236 .vendor = PCI_VENDOR_ID_INTEL, 1237 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1, 1238 .subvendor = PCI_ANY_ID, 1239 .subdevice = PCI_ANY_ID, 1240 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1241 }, 1242 1243 { 1244 .vendor = PCI_VENDOR_ID_INTEL, 1245 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC, 1246 .subvendor = PCI_ANY_ID, 1247 .subdevice = PCI_ANY_ID, 1248 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1249 }, 1250 1251 { 1252 .vendor = PCI_VENDOR_ID_INTEL, 1253 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, 1254 .subvendor = PCI_VENDOR_ID_NI, 1255 .subdevice = 0x7884, 1256 .driver_data = (kernel_ulong_t)&sdhci_ni_byt_sdio, 1257 }, 1258 1259 { 1260 .vendor = PCI_VENDOR_ID_INTEL, 1261 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, 1262 .subvendor = PCI_ANY_ID, 1263 .subdevice = PCI_ANY_ID, 1264 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1265 }, 1266 1267 { 1268 .vendor = PCI_VENDOR_ID_INTEL, 1269 .device = PCI_DEVICE_ID_INTEL_BYT_SD, 1270 .subvendor = PCI_ANY_ID, 1271 .subdevice = PCI_ANY_ID, 1272 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1273 }, 1274 1275 { 1276 .vendor = PCI_VENDOR_ID_INTEL, 1277 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2, 1278 .subvendor = PCI_ANY_ID, 1279 .subdevice = PCI_ANY_ID, 1280 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1281 }, 1282 1283 { 1284 .vendor = PCI_VENDOR_ID_INTEL, 1285 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC, 1286 .subvendor = PCI_ANY_ID, 1287 .subdevice = PCI_ANY_ID, 1288 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1289 }, 1290 1291 { 1292 .vendor = PCI_VENDOR_ID_INTEL, 1293 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO, 1294 .subvendor = PCI_ANY_ID, 1295 .subdevice = PCI_ANY_ID, 1296 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1297 }, 1298 1299 { 1300 .vendor = PCI_VENDOR_ID_INTEL, 1301 .device = PCI_DEVICE_ID_INTEL_BSW_SD, 1302 .subvendor = PCI_ANY_ID, 1303 .subdevice = PCI_ANY_ID, 1304 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1305 }, 1306 1307 { 1308 .vendor = PCI_VENDOR_ID_INTEL, 1309 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0, 1310 .subvendor = PCI_ANY_ID, 1311 .subdevice = PCI_ANY_ID, 1312 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1313 }, 1314 1315 { 1316 .vendor = PCI_VENDOR_ID_INTEL, 1317 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1, 1318 .subvendor = PCI_ANY_ID, 1319 .subdevice = PCI_ANY_ID, 1320 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1321 }, 1322 1323 { 1324 .vendor = PCI_VENDOR_ID_INTEL, 1325 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2, 1326 .subvendor = PCI_ANY_ID, 1327 .subdevice = PCI_ANY_ID, 1328 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1329 }, 1330 1331 { 1332 .vendor = PCI_VENDOR_ID_INTEL, 1333 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0, 1334 .subvendor = PCI_ANY_ID, 1335 .subdevice = PCI_ANY_ID, 1336 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1337 }, 1338 1339 { 1340 .vendor = PCI_VENDOR_ID_INTEL, 1341 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1, 1342 .subvendor = PCI_ANY_ID, 1343 .subdevice = PCI_ANY_ID, 1344 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1345 }, 1346 1347 { 1348 .vendor = PCI_VENDOR_ID_INTEL, 1349 .device = PCI_DEVICE_ID_INTEL_MRFLD_MMC, 1350 .subvendor = PCI_ANY_ID, 1351 .subdevice = PCI_ANY_ID, 1352 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfld_mmc, 1353 }, 1354 1355 { 1356 .vendor = PCI_VENDOR_ID_INTEL, 1357 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC, 1358 .subvendor = PCI_ANY_ID, 1359 .subdevice = PCI_ANY_ID, 1360 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1361 }, 1362 1363 { 1364 .vendor = PCI_VENDOR_ID_INTEL, 1365 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO, 1366 .subvendor = PCI_ANY_ID, 1367 .subdevice = PCI_ANY_ID, 1368 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1369 }, 1370 1371 { 1372 .vendor = PCI_VENDOR_ID_INTEL, 1373 .device = PCI_DEVICE_ID_INTEL_SPT_SD, 1374 .subvendor = PCI_ANY_ID, 1375 .subdevice = PCI_ANY_ID, 1376 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1377 }, 1378 1379 { 1380 .vendor = PCI_VENDOR_ID_INTEL, 1381 .device = PCI_DEVICE_ID_INTEL_DNV_EMMC, 1382 .subvendor = PCI_ANY_ID, 1383 .subdevice = PCI_ANY_ID, 1384 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1385 }, 1386 1387 { 1388 .vendor = PCI_VENDOR_ID_INTEL, 1389 .device = PCI_DEVICE_ID_INTEL_BXT_EMMC, 1390 .subvendor = PCI_ANY_ID, 1391 .subdevice = PCI_ANY_ID, 1392 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1393 }, 1394 1395 { 1396 .vendor = PCI_VENDOR_ID_INTEL, 1397 .device = PCI_DEVICE_ID_INTEL_BXT_SDIO, 1398 .subvendor = PCI_ANY_ID, 1399 .subdevice = PCI_ANY_ID, 1400 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1401 }, 1402 1403 { 1404 .vendor = PCI_VENDOR_ID_INTEL, 1405 .device = PCI_DEVICE_ID_INTEL_BXT_SD, 1406 .subvendor = PCI_ANY_ID, 1407 .subdevice = PCI_ANY_ID, 1408 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1409 }, 1410 1411 { 1412 .vendor = PCI_VENDOR_ID_INTEL, 1413 .device = PCI_DEVICE_ID_INTEL_BXTM_EMMC, 1414 .subvendor = PCI_ANY_ID, 1415 .subdevice = PCI_ANY_ID, 1416 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1417 }, 1418 1419 { 1420 .vendor = PCI_VENDOR_ID_INTEL, 1421 .device = PCI_DEVICE_ID_INTEL_BXTM_SDIO, 1422 .subvendor = PCI_ANY_ID, 1423 .subdevice = PCI_ANY_ID, 1424 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1425 }, 1426 1427 { 1428 .vendor = PCI_VENDOR_ID_INTEL, 1429 .device = PCI_DEVICE_ID_INTEL_BXTM_SD, 1430 .subvendor = PCI_ANY_ID, 1431 .subdevice = PCI_ANY_ID, 1432 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1433 }, 1434 1435 { 1436 .vendor = PCI_VENDOR_ID_INTEL, 1437 .device = PCI_DEVICE_ID_INTEL_APL_EMMC, 1438 .subvendor = PCI_ANY_ID, 1439 .subdevice = PCI_ANY_ID, 1440 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1441 }, 1442 1443 { 1444 .vendor = PCI_VENDOR_ID_INTEL, 1445 .device = PCI_DEVICE_ID_INTEL_APL_SDIO, 1446 .subvendor = PCI_ANY_ID, 1447 .subdevice = PCI_ANY_ID, 1448 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1449 }, 1450 1451 { 1452 .vendor = PCI_VENDOR_ID_INTEL, 1453 .device = PCI_DEVICE_ID_INTEL_APL_SD, 1454 .subvendor = PCI_ANY_ID, 1455 .subdevice = PCI_ANY_ID, 1456 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1457 }, 1458 1459 { 1460 .vendor = PCI_VENDOR_ID_INTEL, 1461 .device = PCI_DEVICE_ID_INTEL_GLK_EMMC, 1462 .subvendor = PCI_ANY_ID, 1463 .subdevice = PCI_ANY_ID, 1464 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1465 }, 1466 1467 { 1468 .vendor = PCI_VENDOR_ID_INTEL, 1469 .device = PCI_DEVICE_ID_INTEL_GLK_SDIO, 1470 .subvendor = PCI_ANY_ID, 1471 .subdevice = PCI_ANY_ID, 1472 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1473 }, 1474 1475 { 1476 .vendor = PCI_VENDOR_ID_INTEL, 1477 .device = PCI_DEVICE_ID_INTEL_GLK_SD, 1478 .subvendor = PCI_ANY_ID, 1479 .subdevice = PCI_ANY_ID, 1480 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1481 }, 1482 1483 { 1484 .vendor = PCI_VENDOR_ID_O2, 1485 .device = PCI_DEVICE_ID_O2_8120, 1486 .subvendor = PCI_ANY_ID, 1487 .subdevice = PCI_ANY_ID, 1488 .driver_data = (kernel_ulong_t)&sdhci_o2, 1489 }, 1490 1491 { 1492 .vendor = PCI_VENDOR_ID_O2, 1493 .device = PCI_DEVICE_ID_O2_8220, 1494 .subvendor = PCI_ANY_ID, 1495 .subdevice = PCI_ANY_ID, 1496 .driver_data = (kernel_ulong_t)&sdhci_o2, 1497 }, 1498 1499 { 1500 .vendor = PCI_VENDOR_ID_O2, 1501 .device = PCI_DEVICE_ID_O2_8221, 1502 .subvendor = PCI_ANY_ID, 1503 .subdevice = PCI_ANY_ID, 1504 .driver_data = (kernel_ulong_t)&sdhci_o2, 1505 }, 1506 1507 { 1508 .vendor = PCI_VENDOR_ID_O2, 1509 .device = PCI_DEVICE_ID_O2_8320, 1510 .subvendor = PCI_ANY_ID, 1511 .subdevice = PCI_ANY_ID, 1512 .driver_data = (kernel_ulong_t)&sdhci_o2, 1513 }, 1514 1515 { 1516 .vendor = PCI_VENDOR_ID_O2, 1517 .device = PCI_DEVICE_ID_O2_8321, 1518 .subvendor = PCI_ANY_ID, 1519 .subdevice = PCI_ANY_ID, 1520 .driver_data = (kernel_ulong_t)&sdhci_o2, 1521 }, 1522 1523 { 1524 .vendor = PCI_VENDOR_ID_O2, 1525 .device = PCI_DEVICE_ID_O2_FUJIN2, 1526 .subvendor = PCI_ANY_ID, 1527 .subdevice = PCI_ANY_ID, 1528 .driver_data = (kernel_ulong_t)&sdhci_o2, 1529 }, 1530 1531 { 1532 .vendor = PCI_VENDOR_ID_O2, 1533 .device = PCI_DEVICE_ID_O2_SDS0, 1534 .subvendor = PCI_ANY_ID, 1535 .subdevice = PCI_ANY_ID, 1536 .driver_data = (kernel_ulong_t)&sdhci_o2, 1537 }, 1538 1539 { 1540 .vendor = PCI_VENDOR_ID_O2, 1541 .device = PCI_DEVICE_ID_O2_SDS1, 1542 .subvendor = PCI_ANY_ID, 1543 .subdevice = PCI_ANY_ID, 1544 .driver_data = (kernel_ulong_t)&sdhci_o2, 1545 }, 1546 1547 { 1548 .vendor = PCI_VENDOR_ID_O2, 1549 .device = PCI_DEVICE_ID_O2_SEABIRD0, 1550 .subvendor = PCI_ANY_ID, 1551 .subdevice = PCI_ANY_ID, 1552 .driver_data = (kernel_ulong_t)&sdhci_o2, 1553 }, 1554 1555 { 1556 .vendor = PCI_VENDOR_ID_O2, 1557 .device = PCI_DEVICE_ID_O2_SEABIRD1, 1558 .subvendor = PCI_ANY_ID, 1559 .subdevice = PCI_ANY_ID, 1560 .driver_data = (kernel_ulong_t)&sdhci_o2, 1561 }, 1562 { 1563 .vendor = PCI_VENDOR_ID_AMD, 1564 .device = PCI_ANY_ID, 1565 .class = PCI_CLASS_SYSTEM_SDHCI << 8, 1566 .class_mask = 0xFFFF00, 1567 .subvendor = PCI_ANY_ID, 1568 .subdevice = PCI_ANY_ID, 1569 .driver_data = (kernel_ulong_t)&sdhci_amd, 1570 }, 1571 { /* Generic SD host controller */ 1572 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) 1573 }, 1574 1575 { /* end: all zeroes */ }, 1576 }; 1577 1578 MODULE_DEVICE_TABLE(pci, pci_ids); 1579 1580 /*****************************************************************************\ 1581 * * 1582 * SDHCI core callbacks * 1583 * * 1584 \*****************************************************************************/ 1585 1586 static int sdhci_pci_enable_dma(struct sdhci_host *host) 1587 { 1588 struct sdhci_pci_slot *slot; 1589 struct pci_dev *pdev; 1590 1591 slot = sdhci_priv(host); 1592 pdev = slot->chip->pdev; 1593 1594 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1595 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1596 (host->flags & SDHCI_USE_SDMA)) { 1597 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1598 "doesn't fully claim to support it.\n"); 1599 } 1600 1601 pci_set_master(pdev); 1602 1603 return 0; 1604 } 1605 1606 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width) 1607 { 1608 u8 ctrl; 1609 1610 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1611 1612 switch (width) { 1613 case MMC_BUS_WIDTH_8: 1614 ctrl |= SDHCI_CTRL_8BITBUS; 1615 ctrl &= ~SDHCI_CTRL_4BITBUS; 1616 break; 1617 case MMC_BUS_WIDTH_4: 1618 ctrl |= SDHCI_CTRL_4BITBUS; 1619 ctrl &= ~SDHCI_CTRL_8BITBUS; 1620 break; 1621 default: 1622 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS); 1623 break; 1624 } 1625 1626 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1627 } 1628 1629 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1630 { 1631 struct sdhci_pci_slot *slot = sdhci_priv(host); 1632 int rst_n_gpio = slot->rst_n_gpio; 1633 1634 if (!gpio_is_valid(rst_n_gpio)) 1635 return; 1636 gpio_set_value_cansleep(rst_n_gpio, 0); 1637 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1638 udelay(10); 1639 gpio_set_value_cansleep(rst_n_gpio, 1); 1640 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1641 usleep_range(300, 1000); 1642 } 1643 1644 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1645 { 1646 struct sdhci_pci_slot *slot = sdhci_priv(host); 1647 1648 if (slot->hw_reset) 1649 slot->hw_reset(host); 1650 } 1651 1652 static const struct sdhci_ops sdhci_pci_ops = { 1653 .set_clock = sdhci_set_clock, 1654 .enable_dma = sdhci_pci_enable_dma, 1655 .set_bus_width = sdhci_pci_set_bus_width, 1656 .reset = sdhci_reset, 1657 .set_uhs_signaling = sdhci_set_uhs_signaling, 1658 .hw_reset = sdhci_pci_hw_reset, 1659 }; 1660 1661 /*****************************************************************************\ 1662 * * 1663 * Suspend/resume * 1664 * * 1665 \*****************************************************************************/ 1666 1667 #ifdef CONFIG_PM_SLEEP 1668 static int sdhci_pci_suspend(struct device *dev) 1669 { 1670 struct pci_dev *pdev = to_pci_dev(dev); 1671 struct sdhci_pci_chip *chip; 1672 struct sdhci_pci_slot *slot; 1673 struct sdhci_host *host; 1674 mmc_pm_flag_t slot_pm_flags; 1675 mmc_pm_flag_t pm_flags = 0; 1676 int i, ret; 1677 1678 chip = pci_get_drvdata(pdev); 1679 if (!chip) 1680 return 0; 1681 1682 for (i = 0; i < chip->num_slots; i++) { 1683 slot = chip->slots[i]; 1684 if (!slot) 1685 continue; 1686 1687 host = slot->host; 1688 1689 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 1690 mmc_retune_needed(host->mmc); 1691 1692 ret = sdhci_suspend_host(host); 1693 1694 if (ret) 1695 goto err_pci_suspend; 1696 1697 slot_pm_flags = host->mmc->pm_flags; 1698 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1699 sdhci_enable_irq_wakeups(host); 1700 1701 pm_flags |= slot_pm_flags; 1702 } 1703 1704 if (chip->fixes && chip->fixes->suspend) { 1705 ret = chip->fixes->suspend(chip); 1706 if (ret) 1707 goto err_pci_suspend; 1708 } 1709 1710 if (pm_flags & MMC_PM_KEEP_POWER) { 1711 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1712 device_init_wakeup(dev, true); 1713 else 1714 device_init_wakeup(dev, false); 1715 } else 1716 device_init_wakeup(dev, false); 1717 1718 return 0; 1719 1720 err_pci_suspend: 1721 while (--i >= 0) 1722 sdhci_resume_host(chip->slots[i]->host); 1723 return ret; 1724 } 1725 1726 static int sdhci_pci_resume(struct device *dev) 1727 { 1728 struct pci_dev *pdev = to_pci_dev(dev); 1729 struct sdhci_pci_chip *chip; 1730 struct sdhci_pci_slot *slot; 1731 int i, ret; 1732 1733 chip = pci_get_drvdata(pdev); 1734 if (!chip) 1735 return 0; 1736 1737 if (chip->fixes && chip->fixes->resume) { 1738 ret = chip->fixes->resume(chip); 1739 if (ret) 1740 return ret; 1741 } 1742 1743 for (i = 0; i < chip->num_slots; i++) { 1744 slot = chip->slots[i]; 1745 if (!slot) 1746 continue; 1747 1748 ret = sdhci_resume_host(slot->host); 1749 if (ret) 1750 return ret; 1751 } 1752 1753 return 0; 1754 } 1755 #endif 1756 1757 #ifdef CONFIG_PM 1758 static int sdhci_pci_runtime_suspend(struct device *dev) 1759 { 1760 struct pci_dev *pdev = to_pci_dev(dev); 1761 struct sdhci_pci_chip *chip; 1762 struct sdhci_pci_slot *slot; 1763 struct sdhci_host *host; 1764 int i, ret; 1765 1766 chip = pci_get_drvdata(pdev); 1767 if (!chip) 1768 return 0; 1769 1770 for (i = 0; i < chip->num_slots; i++) { 1771 slot = chip->slots[i]; 1772 if (!slot) 1773 continue; 1774 1775 host = slot->host; 1776 1777 ret = sdhci_runtime_suspend_host(host); 1778 if (ret) 1779 goto err_pci_runtime_suspend; 1780 1781 if (chip->rpm_retune && 1782 host->tuning_mode != SDHCI_TUNING_MODE_3) 1783 mmc_retune_needed(host->mmc); 1784 } 1785 1786 if (chip->fixes && chip->fixes->suspend) { 1787 ret = chip->fixes->suspend(chip); 1788 if (ret) 1789 goto err_pci_runtime_suspend; 1790 } 1791 1792 return 0; 1793 1794 err_pci_runtime_suspend: 1795 while (--i >= 0) 1796 sdhci_runtime_resume_host(chip->slots[i]->host); 1797 return ret; 1798 } 1799 1800 static int sdhci_pci_runtime_resume(struct device *dev) 1801 { 1802 struct pci_dev *pdev = to_pci_dev(dev); 1803 struct sdhci_pci_chip *chip; 1804 struct sdhci_pci_slot *slot; 1805 int i, ret; 1806 1807 chip = pci_get_drvdata(pdev); 1808 if (!chip) 1809 return 0; 1810 1811 if (chip->fixes && chip->fixes->resume) { 1812 ret = chip->fixes->resume(chip); 1813 if (ret) 1814 return ret; 1815 } 1816 1817 for (i = 0; i < chip->num_slots; i++) { 1818 slot = chip->slots[i]; 1819 if (!slot) 1820 continue; 1821 1822 ret = sdhci_runtime_resume_host(slot->host); 1823 if (ret) 1824 return ret; 1825 } 1826 1827 return 0; 1828 } 1829 #endif 1830 1831 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1832 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1833 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1834 sdhci_pci_runtime_resume, NULL) 1835 }; 1836 1837 /*****************************************************************************\ 1838 * * 1839 * Device probing/removal * 1840 * * 1841 \*****************************************************************************/ 1842 1843 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1844 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1845 int slotno) 1846 { 1847 struct sdhci_pci_slot *slot; 1848 struct sdhci_host *host; 1849 int ret, bar = first_bar + slotno; 1850 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 1851 1852 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1853 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1854 return ERR_PTR(-ENODEV); 1855 } 1856 1857 if (pci_resource_len(pdev, bar) < 0x100) { 1858 dev_err(&pdev->dev, "Invalid iomem size. You may " 1859 "experience problems.\n"); 1860 } 1861 1862 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1863 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1864 return ERR_PTR(-ENODEV); 1865 } 1866 1867 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1868 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1869 return ERR_PTR(-ENODEV); 1870 } 1871 1872 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 1873 if (IS_ERR(host)) { 1874 dev_err(&pdev->dev, "cannot allocate host\n"); 1875 return ERR_CAST(host); 1876 } 1877 1878 slot = sdhci_priv(host); 1879 1880 slot->chip = chip; 1881 slot->host = host; 1882 slot->rst_n_gpio = -EINVAL; 1883 slot->cd_gpio = -EINVAL; 1884 slot->cd_idx = -1; 1885 1886 /* Retrieve platform data if there is any */ 1887 if (*sdhci_pci_get_data) 1888 slot->data = sdhci_pci_get_data(pdev, slotno); 1889 1890 if (slot->data) { 1891 if (slot->data->setup) { 1892 ret = slot->data->setup(slot->data); 1893 if (ret) { 1894 dev_err(&pdev->dev, "platform setup failed\n"); 1895 goto free; 1896 } 1897 } 1898 slot->rst_n_gpio = slot->data->rst_n_gpio; 1899 slot->cd_gpio = slot->data->cd_gpio; 1900 } 1901 1902 host->hw_name = "PCI"; 1903 host->ops = chip->fixes && chip->fixes->ops ? 1904 chip->fixes->ops : 1905 &sdhci_pci_ops; 1906 host->quirks = chip->quirks; 1907 host->quirks2 = chip->quirks2; 1908 1909 host->irq = pdev->irq; 1910 1911 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1912 if (ret) { 1913 dev_err(&pdev->dev, "cannot request region\n"); 1914 goto cleanup; 1915 } 1916 1917 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1918 1919 if (chip->fixes && chip->fixes->probe_slot) { 1920 ret = chip->fixes->probe_slot(slot); 1921 if (ret) 1922 goto cleanup; 1923 } 1924 1925 if (gpio_is_valid(slot->rst_n_gpio)) { 1926 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1927 gpio_direction_output(slot->rst_n_gpio, 1); 1928 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1929 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1930 } else { 1931 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1932 slot->rst_n_gpio = -EINVAL; 1933 } 1934 } 1935 1936 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; 1937 host->mmc->slotno = slotno; 1938 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1939 1940 if (slot->cd_idx >= 0) { 1941 ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx, 1942 slot->cd_override_level, 0, NULL); 1943 if (ret == -EPROBE_DEFER) 1944 goto remove; 1945 1946 if (ret) { 1947 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 1948 slot->cd_idx = -1; 1949 } 1950 } 1951 1952 ret = sdhci_add_host(host); 1953 if (ret) 1954 goto remove; 1955 1956 sdhci_pci_add_own_cd(slot); 1957 1958 /* 1959 * Check if the chip needs a separate GPIO for card detect to wake up 1960 * from runtime suspend. If it is not there, don't allow runtime PM. 1961 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 1962 */ 1963 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 1964 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 1965 chip->allow_runtime_pm = false; 1966 1967 return slot; 1968 1969 remove: 1970 if (chip->fixes && chip->fixes->remove_slot) 1971 chip->fixes->remove_slot(slot, 0); 1972 1973 cleanup: 1974 if (slot->data && slot->data->cleanup) 1975 slot->data->cleanup(slot->data); 1976 1977 free: 1978 sdhci_free_host(host); 1979 1980 return ERR_PTR(ret); 1981 } 1982 1983 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 1984 { 1985 int dead; 1986 u32 scratch; 1987 1988 sdhci_pci_remove_own_cd(slot); 1989 1990 dead = 0; 1991 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 1992 if (scratch == (u32)-1) 1993 dead = 1; 1994 1995 sdhci_remove_host(slot->host, dead); 1996 1997 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 1998 slot->chip->fixes->remove_slot(slot, dead); 1999 2000 if (slot->data && slot->data->cleanup) 2001 slot->data->cleanup(slot->data); 2002 2003 sdhci_free_host(slot->host); 2004 } 2005 2006 static void sdhci_pci_runtime_pm_allow(struct device *dev) 2007 { 2008 pm_suspend_ignore_children(dev, 1); 2009 pm_runtime_set_autosuspend_delay(dev, 50); 2010 pm_runtime_use_autosuspend(dev); 2011 pm_runtime_allow(dev); 2012 /* Stay active until mmc core scans for a card */ 2013 pm_runtime_put_noidle(dev); 2014 } 2015 2016 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 2017 { 2018 pm_runtime_forbid(dev); 2019 pm_runtime_get_noresume(dev); 2020 } 2021 2022 static int sdhci_pci_probe(struct pci_dev *pdev, 2023 const struct pci_device_id *ent) 2024 { 2025 struct sdhci_pci_chip *chip; 2026 struct sdhci_pci_slot *slot; 2027 2028 u8 slots, first_bar; 2029 int ret, i; 2030 2031 BUG_ON(pdev == NULL); 2032 BUG_ON(ent == NULL); 2033 2034 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 2035 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 2036 2037 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 2038 if (ret) 2039 return ret; 2040 2041 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 2042 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 2043 if (slots == 0) 2044 return -ENODEV; 2045 2046 BUG_ON(slots > MAX_SLOTS); 2047 2048 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 2049 if (ret) 2050 return ret; 2051 2052 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 2053 2054 if (first_bar > 5) { 2055 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 2056 return -ENODEV; 2057 } 2058 2059 ret = pcim_enable_device(pdev); 2060 if (ret) 2061 return ret; 2062 2063 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 2064 if (!chip) 2065 return -ENOMEM; 2066 2067 chip->pdev = pdev; 2068 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 2069 if (chip->fixes) { 2070 chip->quirks = chip->fixes->quirks; 2071 chip->quirks2 = chip->fixes->quirks2; 2072 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 2073 } 2074 chip->num_slots = slots; 2075 chip->pm_retune = true; 2076 chip->rpm_retune = true; 2077 2078 pci_set_drvdata(pdev, chip); 2079 2080 if (chip->fixes && chip->fixes->probe) { 2081 ret = chip->fixes->probe(chip); 2082 if (ret) 2083 return ret; 2084 } 2085 2086 slots = chip->num_slots; /* Quirk may have changed this */ 2087 2088 for (i = 0; i < slots; i++) { 2089 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 2090 if (IS_ERR(slot)) { 2091 for (i--; i >= 0; i--) 2092 sdhci_pci_remove_slot(chip->slots[i]); 2093 return PTR_ERR(slot); 2094 } 2095 2096 chip->slots[i] = slot; 2097 } 2098 2099 if (chip->allow_runtime_pm) 2100 sdhci_pci_runtime_pm_allow(&pdev->dev); 2101 2102 return 0; 2103 } 2104 2105 static void sdhci_pci_remove(struct pci_dev *pdev) 2106 { 2107 int i; 2108 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 2109 2110 if (chip->allow_runtime_pm) 2111 sdhci_pci_runtime_pm_forbid(&pdev->dev); 2112 2113 for (i = 0; i < chip->num_slots; i++) 2114 sdhci_pci_remove_slot(chip->slots[i]); 2115 } 2116 2117 static struct pci_driver sdhci_driver = { 2118 .name = "sdhci-pci", 2119 .id_table = pci_ids, 2120 .probe = sdhci_pci_probe, 2121 .remove = sdhci_pci_remove, 2122 .driver = { 2123 .pm = &sdhci_pci_pm_ops 2124 }, 2125 }; 2126 2127 module_pci_driver(sdhci_driver); 2128 2129 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 2130 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 2131 MODULE_LICENSE("GPL"); 2132