1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 3 * 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 5 * 6 * Thanks to the following companies for their support: 7 * 8 * - JMicron (hardware and technical support) 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/string.h> 13 #include <linux/delay.h> 14 #include <linux/highmem.h> 15 #include <linux/module.h> 16 #include <linux/pci.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/slab.h> 19 #include <linux/device.h> 20 #include <linux/mmc/host.h> 21 #include <linux/mmc/mmc.h> 22 #include <linux/scatterlist.h> 23 #include <linux/io.h> 24 #include <linux/gpio.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/mmc/slot-gpio.h> 27 #include <linux/mmc/sdhci-pci-data.h> 28 #include <linux/acpi.h> 29 30 #ifdef CONFIG_X86 31 #include <asm/iosf_mbi.h> 32 #endif 33 34 #include "cqhci.h" 35 36 #include "sdhci.h" 37 #include "sdhci-pci.h" 38 39 static void sdhci_pci_hw_reset(struct sdhci_host *host); 40 41 #ifdef CONFIG_PM_SLEEP 42 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip) 43 { 44 mmc_pm_flag_t pm_flags = 0; 45 bool cap_cd_wake = false; 46 int i; 47 48 for (i = 0; i < chip->num_slots; i++) { 49 struct sdhci_pci_slot *slot = chip->slots[i]; 50 51 if (slot) { 52 pm_flags |= slot->host->mmc->pm_flags; 53 if (slot->host->mmc->caps & MMC_CAP_CD_WAKE) 54 cap_cd_wake = true; 55 } 56 } 57 58 if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ)) 59 return device_wakeup_enable(&chip->pdev->dev); 60 else if (!cap_cd_wake) 61 return device_wakeup_disable(&chip->pdev->dev); 62 63 return 0; 64 } 65 66 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 67 { 68 int i, ret; 69 70 sdhci_pci_init_wakeup(chip); 71 72 for (i = 0; i < chip->num_slots; i++) { 73 struct sdhci_pci_slot *slot = chip->slots[i]; 74 struct sdhci_host *host; 75 76 if (!slot) 77 continue; 78 79 host = slot->host; 80 81 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 82 mmc_retune_needed(host->mmc); 83 84 ret = sdhci_suspend_host(host); 85 if (ret) 86 goto err_pci_suspend; 87 88 if (device_may_wakeup(&chip->pdev->dev)) 89 mmc_gpio_set_cd_wake(host->mmc, true); 90 } 91 92 return 0; 93 94 err_pci_suspend: 95 while (--i >= 0) 96 sdhci_resume_host(chip->slots[i]->host); 97 return ret; 98 } 99 100 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip) 101 { 102 struct sdhci_pci_slot *slot; 103 int i, ret; 104 105 for (i = 0; i < chip->num_slots; i++) { 106 slot = chip->slots[i]; 107 if (!slot) 108 continue; 109 110 ret = sdhci_resume_host(slot->host); 111 if (ret) 112 return ret; 113 114 mmc_gpio_set_cd_wake(slot->host->mmc, false); 115 } 116 117 return 0; 118 } 119 120 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip) 121 { 122 int ret; 123 124 ret = cqhci_suspend(chip->slots[0]->host->mmc); 125 if (ret) 126 return ret; 127 128 return sdhci_pci_suspend_host(chip); 129 } 130 131 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip) 132 { 133 int ret; 134 135 ret = sdhci_pci_resume_host(chip); 136 if (ret) 137 return ret; 138 139 return cqhci_resume(chip->slots[0]->host->mmc); 140 } 141 #endif 142 143 #ifdef CONFIG_PM 144 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip) 145 { 146 struct sdhci_pci_slot *slot; 147 struct sdhci_host *host; 148 int i, ret; 149 150 for (i = 0; i < chip->num_slots; i++) { 151 slot = chip->slots[i]; 152 if (!slot) 153 continue; 154 155 host = slot->host; 156 157 ret = sdhci_runtime_suspend_host(host); 158 if (ret) 159 goto err_pci_runtime_suspend; 160 161 if (chip->rpm_retune && 162 host->tuning_mode != SDHCI_TUNING_MODE_3) 163 mmc_retune_needed(host->mmc); 164 } 165 166 return 0; 167 168 err_pci_runtime_suspend: 169 while (--i >= 0) 170 sdhci_runtime_resume_host(chip->slots[i]->host); 171 return ret; 172 } 173 174 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip) 175 { 176 struct sdhci_pci_slot *slot; 177 int i, ret; 178 179 for (i = 0; i < chip->num_slots; i++) { 180 slot = chip->slots[i]; 181 if (!slot) 182 continue; 183 184 ret = sdhci_runtime_resume_host(slot->host); 185 if (ret) 186 return ret; 187 } 188 189 return 0; 190 } 191 192 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip) 193 { 194 int ret; 195 196 ret = cqhci_suspend(chip->slots[0]->host->mmc); 197 if (ret) 198 return ret; 199 200 return sdhci_pci_runtime_suspend_host(chip); 201 } 202 203 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip) 204 { 205 int ret; 206 207 ret = sdhci_pci_runtime_resume_host(chip); 208 if (ret) 209 return ret; 210 211 return cqhci_resume(chip->slots[0]->host->mmc); 212 } 213 #endif 214 215 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask) 216 { 217 int cmd_error = 0; 218 int data_error = 0; 219 220 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 221 return intmask; 222 223 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 224 225 return 0; 226 } 227 228 static void sdhci_pci_dumpregs(struct mmc_host *mmc) 229 { 230 sdhci_dumpregs(mmc_priv(mmc)); 231 } 232 233 /*****************************************************************************\ 234 * * 235 * Hardware specific quirk handling * 236 * * 237 \*****************************************************************************/ 238 239 static int ricoh_probe(struct sdhci_pci_chip *chip) 240 { 241 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 242 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 243 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 244 return 0; 245 } 246 247 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 248 { 249 slot->host->caps = 250 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 251 & SDHCI_TIMEOUT_CLK_MASK) | 252 253 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 254 & SDHCI_CLOCK_BASE_MASK) | 255 256 SDHCI_TIMEOUT_CLK_UNIT | 257 SDHCI_CAN_VDD_330 | 258 SDHCI_CAN_DO_HISPD | 259 SDHCI_CAN_DO_SDMA; 260 return 0; 261 } 262 263 #ifdef CONFIG_PM_SLEEP 264 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 265 { 266 /* Apply a delay to allow controller to settle */ 267 /* Otherwise it becomes confused if card state changed 268 during suspend */ 269 msleep(500); 270 return sdhci_pci_resume_host(chip); 271 } 272 #endif 273 274 static const struct sdhci_pci_fixes sdhci_ricoh = { 275 .probe = ricoh_probe, 276 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 277 SDHCI_QUIRK_FORCE_DMA | 278 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 279 }; 280 281 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 282 .probe_slot = ricoh_mmc_probe_slot, 283 #ifdef CONFIG_PM_SLEEP 284 .resume = ricoh_mmc_resume, 285 #endif 286 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 287 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 288 SDHCI_QUIRK_NO_CARD_NO_RESET | 289 SDHCI_QUIRK_MISSING_CAPS 290 }; 291 292 static const struct sdhci_pci_fixes sdhci_ene_712 = { 293 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 294 SDHCI_QUIRK_BROKEN_DMA, 295 }; 296 297 static const struct sdhci_pci_fixes sdhci_ene_714 = { 298 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 299 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 300 SDHCI_QUIRK_BROKEN_DMA, 301 }; 302 303 static const struct sdhci_pci_fixes sdhci_cafe = { 304 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 305 SDHCI_QUIRK_NO_BUSY_IRQ | 306 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 307 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 308 }; 309 310 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 311 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 312 }; 313 314 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 315 { 316 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 317 return 0; 318 } 319 320 /* 321 * ADMA operation is disabled for Moorestown platform due to 322 * hardware bugs. 323 */ 324 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 325 { 326 /* 327 * slots number is fixed here for MRST as SDIO3/5 are never used and 328 * have hardware bugs. 329 */ 330 chip->num_slots = 1; 331 return 0; 332 } 333 334 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 335 { 336 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 337 return 0; 338 } 339 340 #ifdef CONFIG_PM 341 342 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 343 { 344 struct sdhci_pci_slot *slot = dev_id; 345 struct sdhci_host *host = slot->host; 346 347 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 348 return IRQ_HANDLED; 349 } 350 351 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 352 { 353 int err, irq, gpio = slot->cd_gpio; 354 355 slot->cd_gpio = -EINVAL; 356 slot->cd_irq = -EINVAL; 357 358 if (!gpio_is_valid(gpio)) 359 return; 360 361 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 362 if (err < 0) 363 goto out; 364 365 err = gpio_direction_input(gpio); 366 if (err < 0) 367 goto out_free; 368 369 irq = gpio_to_irq(gpio); 370 if (irq < 0) 371 goto out_free; 372 373 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 374 IRQF_TRIGGER_FALLING, "sd_cd", slot); 375 if (err) 376 goto out_free; 377 378 slot->cd_gpio = gpio; 379 slot->cd_irq = irq; 380 381 return; 382 383 out_free: 384 devm_gpio_free(&slot->chip->pdev->dev, gpio); 385 out: 386 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 387 } 388 389 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 390 { 391 if (slot->cd_irq >= 0) 392 free_irq(slot->cd_irq, slot); 393 } 394 395 #else 396 397 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 398 { 399 } 400 401 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 402 { 403 } 404 405 #endif 406 407 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 408 { 409 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 410 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC; 411 return 0; 412 } 413 414 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 415 { 416 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 417 return 0; 418 } 419 420 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 421 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 422 .probe_slot = mrst_hc_probe_slot, 423 }; 424 425 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 426 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 427 .probe = mrst_hc_probe, 428 }; 429 430 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 431 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 432 .allow_runtime_pm = true, 433 .own_cd_for_runtime_pm = true, 434 }; 435 436 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 437 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 438 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 439 .allow_runtime_pm = true, 440 .probe_slot = mfd_sdio_probe_slot, 441 }; 442 443 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 444 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 445 .allow_runtime_pm = true, 446 .probe_slot = mfd_emmc_probe_slot, 447 }; 448 449 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 450 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 451 .probe_slot = pch_hc_probe_slot, 452 }; 453 454 #ifdef CONFIG_X86 455 456 #define BYT_IOSF_SCCEP 0x63 457 #define BYT_IOSF_OCP_NETCTRL0 0x1078 458 #define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8) 459 460 static void byt_ocp_setting(struct pci_dev *pdev) 461 { 462 u32 val = 0; 463 464 if (pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC && 465 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SDIO && 466 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SD && 467 pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC2) 468 return; 469 470 if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0, 471 &val)) { 472 dev_err(&pdev->dev, "%s read error\n", __func__); 473 return; 474 } 475 476 if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE)) 477 return; 478 479 val &= ~BYT_IOSF_OCP_TIMEOUT_BASE; 480 481 if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0, 482 val)) { 483 dev_err(&pdev->dev, "%s write error\n", __func__); 484 return; 485 } 486 487 dev_dbg(&pdev->dev, "%s completed\n", __func__); 488 } 489 490 #else 491 492 static inline void byt_ocp_setting(struct pci_dev *pdev) 493 { 494 } 495 496 #endif 497 498 enum { 499 INTEL_DSM_FNS = 0, 500 INTEL_DSM_V18_SWITCH = 3, 501 INTEL_DSM_V33_SWITCH = 4, 502 INTEL_DSM_DRV_STRENGTH = 9, 503 INTEL_DSM_D3_RETUNE = 10, 504 }; 505 506 struct intel_host { 507 u32 dsm_fns; 508 int drv_strength; 509 bool d3_retune; 510 bool rpm_retune_ok; 511 u32 glk_rx_ctrl1; 512 u32 glk_tun_val; 513 }; 514 515 static const guid_t intel_dsm_guid = 516 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F, 517 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61); 518 519 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 520 unsigned int fn, u32 *result) 521 { 522 union acpi_object *obj; 523 int err = 0; 524 size_t len; 525 526 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL); 527 if (!obj) 528 return -EOPNOTSUPP; 529 530 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { 531 err = -EINVAL; 532 goto out; 533 } 534 535 len = min_t(size_t, obj->buffer.length, 4); 536 537 *result = 0; 538 memcpy(result, obj->buffer.pointer, len); 539 out: 540 ACPI_FREE(obj); 541 542 return err; 543 } 544 545 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 546 unsigned int fn, u32 *result) 547 { 548 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 549 return -EOPNOTSUPP; 550 551 return __intel_dsm(intel_host, dev, fn, result); 552 } 553 554 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 555 struct mmc_host *mmc) 556 { 557 int err; 558 u32 val; 559 560 intel_host->d3_retune = true; 561 562 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 563 if (err) { 564 pr_debug("%s: DSM not supported, error %d\n", 565 mmc_hostname(mmc), err); 566 return; 567 } 568 569 pr_debug("%s: DSM function mask %#x\n", 570 mmc_hostname(mmc), intel_host->dsm_fns); 571 572 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 573 intel_host->drv_strength = err ? 0 : val; 574 575 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 576 intel_host->d3_retune = err ? true : !!val; 577 } 578 579 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 580 { 581 u8 reg; 582 583 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 584 reg |= 0x10; 585 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 586 /* For eMMC, minimum is 1us but give it 9us for good measure */ 587 udelay(9); 588 reg &= ~0x10; 589 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 590 /* For eMMC, minimum is 200us but give it 300us for good measure */ 591 usleep_range(300, 1000); 592 } 593 594 static int intel_select_drive_strength(struct mmc_card *card, 595 unsigned int max_dtr, int host_drv, 596 int card_drv, int *drv_type) 597 { 598 struct sdhci_host *host = mmc_priv(card->host); 599 struct sdhci_pci_slot *slot = sdhci_priv(host); 600 struct intel_host *intel_host = sdhci_pci_priv(slot); 601 602 return intel_host->drv_strength; 603 } 604 605 static int bxt_get_cd(struct mmc_host *mmc) 606 { 607 int gpio_cd = mmc_gpio_get_cd(mmc); 608 struct sdhci_host *host = mmc_priv(mmc); 609 unsigned long flags; 610 int ret = 0; 611 612 if (!gpio_cd) 613 return 0; 614 615 spin_lock_irqsave(&host->lock, flags); 616 617 if (host->flags & SDHCI_DEVICE_DEAD) 618 goto out; 619 620 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 621 out: 622 spin_unlock_irqrestore(&host->lock, flags); 623 624 return ret; 625 } 626 627 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 628 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 629 630 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 631 unsigned short vdd) 632 { 633 int cntr; 634 u8 reg; 635 636 sdhci_set_power(host, mode, vdd); 637 638 if (mode == MMC_POWER_OFF) 639 return; 640 641 /* 642 * Bus power might not enable after D3 -> D0 transition due to the 643 * present state not yet having propagated. Retry for up to 2ms. 644 */ 645 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 646 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 647 if (reg & SDHCI_POWER_ON) 648 break; 649 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 650 reg |= SDHCI_POWER_ON; 651 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 652 } 653 } 654 655 #define INTEL_HS400_ES_REG 0x78 656 #define INTEL_HS400_ES_BIT BIT(0) 657 658 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc, 659 struct mmc_ios *ios) 660 { 661 struct sdhci_host *host = mmc_priv(mmc); 662 u32 val; 663 664 val = sdhci_readl(host, INTEL_HS400_ES_REG); 665 if (ios->enhanced_strobe) 666 val |= INTEL_HS400_ES_BIT; 667 else 668 val &= ~INTEL_HS400_ES_BIT; 669 sdhci_writel(host, val, INTEL_HS400_ES_REG); 670 } 671 672 static int intel_start_signal_voltage_switch(struct mmc_host *mmc, 673 struct mmc_ios *ios) 674 { 675 struct device *dev = mmc_dev(mmc); 676 struct sdhci_host *host = mmc_priv(mmc); 677 struct sdhci_pci_slot *slot = sdhci_priv(host); 678 struct intel_host *intel_host = sdhci_pci_priv(slot); 679 unsigned int fn; 680 u32 result = 0; 681 int err; 682 683 err = sdhci_start_signal_voltage_switch(mmc, ios); 684 if (err) 685 return err; 686 687 switch (ios->signal_voltage) { 688 case MMC_SIGNAL_VOLTAGE_330: 689 fn = INTEL_DSM_V33_SWITCH; 690 break; 691 case MMC_SIGNAL_VOLTAGE_180: 692 fn = INTEL_DSM_V18_SWITCH; 693 break; 694 default: 695 return 0; 696 } 697 698 err = intel_dsm(intel_host, dev, fn, &result); 699 pr_debug("%s: %s DSM fn %u error %d result %u\n", 700 mmc_hostname(mmc), __func__, fn, err, result); 701 702 return 0; 703 } 704 705 static const struct sdhci_ops sdhci_intel_byt_ops = { 706 .set_clock = sdhci_set_clock, 707 .set_power = sdhci_intel_set_power, 708 .enable_dma = sdhci_pci_enable_dma, 709 .set_bus_width = sdhci_set_bus_width, 710 .reset = sdhci_reset, 711 .set_uhs_signaling = sdhci_set_uhs_signaling, 712 .hw_reset = sdhci_pci_hw_reset, 713 }; 714 715 static const struct sdhci_ops sdhci_intel_glk_ops = { 716 .set_clock = sdhci_set_clock, 717 .set_power = sdhci_intel_set_power, 718 .enable_dma = sdhci_pci_enable_dma, 719 .set_bus_width = sdhci_set_bus_width, 720 .reset = sdhci_reset, 721 .set_uhs_signaling = sdhci_set_uhs_signaling, 722 .hw_reset = sdhci_pci_hw_reset, 723 .irq = sdhci_cqhci_irq, 724 }; 725 726 static void byt_read_dsm(struct sdhci_pci_slot *slot) 727 { 728 struct intel_host *intel_host = sdhci_pci_priv(slot); 729 struct device *dev = &slot->chip->pdev->dev; 730 struct mmc_host *mmc = slot->host->mmc; 731 732 intel_dsm_init(intel_host, dev, mmc); 733 slot->chip->rpm_retune = intel_host->d3_retune; 734 } 735 736 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode) 737 { 738 int err = sdhci_execute_tuning(mmc, opcode); 739 struct sdhci_host *host = mmc_priv(mmc); 740 741 if (err) 742 return err; 743 744 /* 745 * Tuning can leave the IP in an active state (Buffer Read Enable bit 746 * set) which prevents the entry to low power states (i.e. S0i3). Data 747 * reset will clear it. 748 */ 749 sdhci_reset(host, SDHCI_RESET_DATA); 750 751 return 0; 752 } 753 754 static void byt_probe_slot(struct sdhci_pci_slot *slot) 755 { 756 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 757 struct device *dev = &slot->chip->pdev->dev; 758 struct mmc_host *mmc = slot->host->mmc; 759 760 byt_read_dsm(slot); 761 762 byt_ocp_setting(slot->chip->pdev); 763 764 ops->execute_tuning = intel_execute_tuning; 765 ops->start_signal_voltage_switch = intel_start_signal_voltage_switch; 766 767 device_property_read_u32(dev, "max-frequency", &mmc->f_max); 768 } 769 770 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 771 { 772 byt_probe_slot(slot); 773 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 774 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 775 MMC_CAP_CMD_DURING_TFR | 776 MMC_CAP_WAIT_WHILE_BUSY; 777 slot->hw_reset = sdhci_pci_int_hw_reset; 778 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 779 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 780 slot->host->mmc_host_ops.select_drive_strength = 781 intel_select_drive_strength; 782 return 0; 783 } 784 785 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot) 786 { 787 int ret = byt_emmc_probe_slot(slot); 788 789 slot->host->mmc->caps2 |= MMC_CAP2_CQE; 790 791 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) { 792 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES, 793 slot->host->mmc_host_ops.hs400_enhanced_strobe = 794 intel_hs400_enhanced_strobe; 795 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; 796 } 797 798 return ret; 799 } 800 801 static const struct cqhci_host_ops glk_cqhci_ops = { 802 .enable = sdhci_cqe_enable, 803 .disable = sdhci_cqe_disable, 804 .dumpregs = sdhci_pci_dumpregs, 805 }; 806 807 static int glk_emmc_add_host(struct sdhci_pci_slot *slot) 808 { 809 struct device *dev = &slot->chip->pdev->dev; 810 struct sdhci_host *host = slot->host; 811 struct cqhci_host *cq_host; 812 bool dma64; 813 int ret; 814 815 ret = sdhci_setup_host(host); 816 if (ret) 817 return ret; 818 819 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); 820 if (!cq_host) { 821 ret = -ENOMEM; 822 goto cleanup; 823 } 824 825 cq_host->mmio = host->ioaddr + 0x200; 826 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 827 cq_host->ops = &glk_cqhci_ops; 828 829 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 830 if (dma64) 831 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 832 833 ret = cqhci_init(cq_host, host->mmc, dma64); 834 if (ret) 835 goto cleanup; 836 837 ret = __sdhci_add_host(host); 838 if (ret) 839 goto cleanup; 840 841 return 0; 842 843 cleanup: 844 sdhci_cleanup_host(host); 845 return ret; 846 } 847 848 #ifdef CONFIG_PM 849 #define GLK_RX_CTRL1 0x834 850 #define GLK_TUN_VAL 0x840 851 #define GLK_PATH_PLL GENMASK(13, 8) 852 #define GLK_DLY GENMASK(6, 0) 853 /* Workaround firmware failing to restore the tuning value */ 854 static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp) 855 { 856 struct sdhci_pci_slot *slot = chip->slots[0]; 857 struct intel_host *intel_host = sdhci_pci_priv(slot); 858 struct sdhci_host *host = slot->host; 859 u32 glk_rx_ctrl1; 860 u32 glk_tun_val; 861 u32 dly; 862 863 if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc)) 864 return; 865 866 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1); 867 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL); 868 869 if (susp) { 870 intel_host->glk_rx_ctrl1 = glk_rx_ctrl1; 871 intel_host->glk_tun_val = glk_tun_val; 872 return; 873 } 874 875 if (!intel_host->glk_tun_val) 876 return; 877 878 if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) { 879 intel_host->rpm_retune_ok = true; 880 return; 881 } 882 883 dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) + 884 (intel_host->glk_tun_val << 1)); 885 if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1)) 886 return; 887 888 glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly; 889 sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1); 890 891 intel_host->rpm_retune_ok = true; 892 chip->rpm_retune = true; 893 mmc_retune_needed(host->mmc); 894 pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc)); 895 } 896 897 static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp) 898 { 899 if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 900 !chip->rpm_retune) 901 glk_rpm_retune_wa(chip, susp); 902 } 903 904 static int glk_runtime_suspend(struct sdhci_pci_chip *chip) 905 { 906 glk_rpm_retune_chk(chip, true); 907 908 return sdhci_cqhci_runtime_suspend(chip); 909 } 910 911 static int glk_runtime_resume(struct sdhci_pci_chip *chip) 912 { 913 glk_rpm_retune_chk(chip, false); 914 915 return sdhci_cqhci_runtime_resume(chip); 916 } 917 #endif 918 919 #ifdef CONFIG_ACPI 920 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 921 { 922 acpi_status status; 923 unsigned long long max_freq; 924 925 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 926 "MXFQ", NULL, &max_freq); 927 if (ACPI_FAILURE(status)) { 928 dev_err(&slot->chip->pdev->dev, 929 "MXFQ not found in acpi table\n"); 930 return -EINVAL; 931 } 932 933 slot->host->mmc->f_max = max_freq * 1000000; 934 935 return 0; 936 } 937 #else 938 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 939 { 940 return 0; 941 } 942 #endif 943 944 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 945 { 946 int err; 947 948 byt_probe_slot(slot); 949 950 err = ni_set_max_freq(slot); 951 if (err) 952 return err; 953 954 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 955 MMC_CAP_WAIT_WHILE_BUSY; 956 return 0; 957 } 958 959 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 960 { 961 byt_probe_slot(slot); 962 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 963 MMC_CAP_WAIT_WHILE_BUSY; 964 return 0; 965 } 966 967 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 968 { 969 byt_probe_slot(slot); 970 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | 971 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE; 972 slot->cd_idx = 0; 973 slot->cd_override_level = true; 974 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 975 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 976 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 977 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) 978 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 979 980 if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI && 981 slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3) 982 slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V; 983 984 return 0; 985 } 986 987 #ifdef CONFIG_PM_SLEEP 988 989 static int byt_resume(struct sdhci_pci_chip *chip) 990 { 991 byt_ocp_setting(chip->pdev); 992 993 return sdhci_pci_resume_host(chip); 994 } 995 996 #endif 997 998 #ifdef CONFIG_PM 999 1000 static int byt_runtime_resume(struct sdhci_pci_chip *chip) 1001 { 1002 byt_ocp_setting(chip->pdev); 1003 1004 return sdhci_pci_runtime_resume_host(chip); 1005 } 1006 1007 #endif 1008 1009 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 1010 #ifdef CONFIG_PM_SLEEP 1011 .resume = byt_resume, 1012 #endif 1013 #ifdef CONFIG_PM 1014 .runtime_resume = byt_runtime_resume, 1015 #endif 1016 .allow_runtime_pm = true, 1017 .probe_slot = byt_emmc_probe_slot, 1018 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1019 SDHCI_QUIRK_NO_LED, 1020 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1021 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1022 SDHCI_QUIRK2_STOP_WITH_TC, 1023 .ops = &sdhci_intel_byt_ops, 1024 .priv_size = sizeof(struct intel_host), 1025 }; 1026 1027 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = { 1028 .allow_runtime_pm = true, 1029 .probe_slot = glk_emmc_probe_slot, 1030 .add_host = glk_emmc_add_host, 1031 #ifdef CONFIG_PM_SLEEP 1032 .suspend = sdhci_cqhci_suspend, 1033 .resume = sdhci_cqhci_resume, 1034 #endif 1035 #ifdef CONFIG_PM 1036 .runtime_suspend = glk_runtime_suspend, 1037 .runtime_resume = glk_runtime_resume, 1038 #endif 1039 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1040 SDHCI_QUIRK_NO_LED, 1041 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1042 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1043 SDHCI_QUIRK2_STOP_WITH_TC, 1044 .ops = &sdhci_intel_glk_ops, 1045 .priv_size = sizeof(struct intel_host), 1046 }; 1047 1048 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 1049 #ifdef CONFIG_PM_SLEEP 1050 .resume = byt_resume, 1051 #endif 1052 #ifdef CONFIG_PM 1053 .runtime_resume = byt_runtime_resume, 1054 #endif 1055 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1056 SDHCI_QUIRK_NO_LED, 1057 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1058 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1059 .allow_runtime_pm = true, 1060 .probe_slot = ni_byt_sdio_probe_slot, 1061 .ops = &sdhci_intel_byt_ops, 1062 .priv_size = sizeof(struct intel_host), 1063 }; 1064 1065 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 1066 #ifdef CONFIG_PM_SLEEP 1067 .resume = byt_resume, 1068 #endif 1069 #ifdef CONFIG_PM 1070 .runtime_resume = byt_runtime_resume, 1071 #endif 1072 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1073 SDHCI_QUIRK_NO_LED, 1074 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1075 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1076 .allow_runtime_pm = true, 1077 .probe_slot = byt_sdio_probe_slot, 1078 .ops = &sdhci_intel_byt_ops, 1079 .priv_size = sizeof(struct intel_host), 1080 }; 1081 1082 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 1083 #ifdef CONFIG_PM_SLEEP 1084 .resume = byt_resume, 1085 #endif 1086 #ifdef CONFIG_PM 1087 .runtime_resume = byt_runtime_resume, 1088 #endif 1089 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1090 SDHCI_QUIRK_NO_LED, 1091 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 1092 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1093 SDHCI_QUIRK2_STOP_WITH_TC, 1094 .allow_runtime_pm = true, 1095 .own_cd_for_runtime_pm = true, 1096 .probe_slot = byt_sd_probe_slot, 1097 .ops = &sdhci_intel_byt_ops, 1098 .priv_size = sizeof(struct intel_host), 1099 }; 1100 1101 /* Define Host controllers for Intel Merrifield platform */ 1102 #define INTEL_MRFLD_EMMC_0 0 1103 #define INTEL_MRFLD_EMMC_1 1 1104 #define INTEL_MRFLD_SD 2 1105 #define INTEL_MRFLD_SDIO 3 1106 1107 #ifdef CONFIG_ACPI 1108 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) 1109 { 1110 struct acpi_device *device, *child; 1111 1112 device = ACPI_COMPANION(&slot->chip->pdev->dev); 1113 if (!device) 1114 return; 1115 1116 acpi_device_fix_up_power(device); 1117 list_for_each_entry(child, &device->children, node) 1118 if (child->status.present && child->status.enabled) 1119 acpi_device_fix_up_power(child); 1120 } 1121 #else 1122 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {} 1123 #endif 1124 1125 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 1126 { 1127 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 1128 1129 switch (func) { 1130 case INTEL_MRFLD_EMMC_0: 1131 case INTEL_MRFLD_EMMC_1: 1132 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1133 MMC_CAP_8_BIT_DATA | 1134 MMC_CAP_1_8V_DDR; 1135 break; 1136 case INTEL_MRFLD_SD: 1137 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1138 break; 1139 case INTEL_MRFLD_SDIO: 1140 /* Advertise 2.0v for compatibility with the SDIO card's OCR */ 1141 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195; 1142 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1143 MMC_CAP_POWER_OFF_CARD; 1144 break; 1145 default: 1146 return -ENODEV; 1147 } 1148 1149 intel_mrfld_mmc_fix_up_power_slot(slot); 1150 return 0; 1151 } 1152 1153 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 1154 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1155 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 1156 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1157 .allow_runtime_pm = true, 1158 .probe_slot = intel_mrfld_mmc_probe_slot, 1159 }; 1160 1161 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 1162 { 1163 u8 scratch; 1164 int ret; 1165 1166 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 1167 if (ret) 1168 return ret; 1169 1170 /* 1171 * Turn PMOS on [bit 0], set over current detection to 2.4 V 1172 * [bit 1:2] and enable over current debouncing [bit 6]. 1173 */ 1174 if (on) 1175 scratch |= 0x47; 1176 else 1177 scratch &= ~0x47; 1178 1179 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 1180 } 1181 1182 static int jmicron_probe(struct sdhci_pci_chip *chip) 1183 { 1184 int ret; 1185 u16 mmcdev = 0; 1186 1187 if (chip->pdev->revision == 0) { 1188 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 1189 SDHCI_QUIRK_32BIT_DMA_SIZE | 1190 SDHCI_QUIRK_32BIT_ADMA_SIZE | 1191 SDHCI_QUIRK_RESET_AFTER_REQUEST | 1192 SDHCI_QUIRK_BROKEN_SMALL_PIO; 1193 } 1194 1195 /* 1196 * JMicron chips can have two interfaces to the same hardware 1197 * in order to work around limitations in Microsoft's driver. 1198 * We need to make sure we only bind to one of them. 1199 * 1200 * This code assumes two things: 1201 * 1202 * 1. The PCI code adds subfunctions in order. 1203 * 1204 * 2. The MMC interface has a lower subfunction number 1205 * than the SD interface. 1206 */ 1207 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 1208 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 1209 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 1210 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 1211 1212 if (mmcdev) { 1213 struct pci_dev *sd_dev; 1214 1215 sd_dev = NULL; 1216 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 1217 mmcdev, sd_dev)) != NULL) { 1218 if ((PCI_SLOT(chip->pdev->devfn) == 1219 PCI_SLOT(sd_dev->devfn)) && 1220 (chip->pdev->bus == sd_dev->bus)) 1221 break; 1222 } 1223 1224 if (sd_dev) { 1225 pci_dev_put(sd_dev); 1226 dev_info(&chip->pdev->dev, "Refusing to bind to " 1227 "secondary interface.\n"); 1228 return -ENODEV; 1229 } 1230 } 1231 1232 /* 1233 * JMicron chips need a bit of a nudge to enable the power 1234 * output pins. 1235 */ 1236 ret = jmicron_pmos(chip, 1); 1237 if (ret) { 1238 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1239 return ret; 1240 } 1241 1242 /* quirk for unsable RO-detection on JM388 chips */ 1243 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 1244 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1245 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 1246 1247 return 0; 1248 } 1249 1250 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 1251 { 1252 u8 scratch; 1253 1254 scratch = readb(host->ioaddr + 0xC0); 1255 1256 if (on) 1257 scratch |= 0x01; 1258 else 1259 scratch &= ~0x01; 1260 1261 writeb(scratch, host->ioaddr + 0xC0); 1262 } 1263 1264 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 1265 { 1266 if (slot->chip->pdev->revision == 0) { 1267 u16 version; 1268 1269 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 1270 version = (version & SDHCI_VENDOR_VER_MASK) >> 1271 SDHCI_VENDOR_VER_SHIFT; 1272 1273 /* 1274 * Older versions of the chip have lots of nasty glitches 1275 * in the ADMA engine. It's best just to avoid it 1276 * completely. 1277 */ 1278 if (version < 0xAC) 1279 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 1280 } 1281 1282 /* JM388 MMC doesn't support 1.8V while SD supports it */ 1283 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1284 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 1285 MMC_VDD_29_30 | MMC_VDD_30_31 | 1286 MMC_VDD_165_195; /* allow 1.8V */ 1287 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 1288 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 1289 } 1290 1291 /* 1292 * The secondary interface requires a bit set to get the 1293 * interrupts. 1294 */ 1295 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1296 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1297 jmicron_enable_mmc(slot->host, 1); 1298 1299 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 1300 1301 return 0; 1302 } 1303 1304 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 1305 { 1306 if (dead) 1307 return; 1308 1309 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1310 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1311 jmicron_enable_mmc(slot->host, 0); 1312 } 1313 1314 #ifdef CONFIG_PM_SLEEP 1315 static int jmicron_suspend(struct sdhci_pci_chip *chip) 1316 { 1317 int i, ret; 1318 1319 ret = sdhci_pci_suspend_host(chip); 1320 if (ret) 1321 return ret; 1322 1323 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1324 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1325 for (i = 0; i < chip->num_slots; i++) 1326 jmicron_enable_mmc(chip->slots[i]->host, 0); 1327 } 1328 1329 return 0; 1330 } 1331 1332 static int jmicron_resume(struct sdhci_pci_chip *chip) 1333 { 1334 int ret, i; 1335 1336 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1337 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1338 for (i = 0; i < chip->num_slots; i++) 1339 jmicron_enable_mmc(chip->slots[i]->host, 1); 1340 } 1341 1342 ret = jmicron_pmos(chip, 1); 1343 if (ret) { 1344 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1345 return ret; 1346 } 1347 1348 return sdhci_pci_resume_host(chip); 1349 } 1350 #endif 1351 1352 static const struct sdhci_pci_fixes sdhci_jmicron = { 1353 .probe = jmicron_probe, 1354 1355 .probe_slot = jmicron_probe_slot, 1356 .remove_slot = jmicron_remove_slot, 1357 1358 #ifdef CONFIG_PM_SLEEP 1359 .suspend = jmicron_suspend, 1360 .resume = jmicron_resume, 1361 #endif 1362 }; 1363 1364 /* SysKonnect CardBus2SDIO extra registers */ 1365 #define SYSKT_CTRL 0x200 1366 #define SYSKT_RDFIFO_STAT 0x204 1367 #define SYSKT_WRFIFO_STAT 0x208 1368 #define SYSKT_POWER_DATA 0x20c 1369 #define SYSKT_POWER_330 0xef 1370 #define SYSKT_POWER_300 0xf8 1371 #define SYSKT_POWER_184 0xcc 1372 #define SYSKT_POWER_CMD 0x20d 1373 #define SYSKT_POWER_START (1 << 7) 1374 #define SYSKT_POWER_STATUS 0x20e 1375 #define SYSKT_POWER_STATUS_OK (1 << 0) 1376 #define SYSKT_BOARD_REV 0x210 1377 #define SYSKT_CHIP_REV 0x211 1378 #define SYSKT_CONF_DATA 0x212 1379 #define SYSKT_CONF_DATA_1V8 (1 << 2) 1380 #define SYSKT_CONF_DATA_2V5 (1 << 1) 1381 #define SYSKT_CONF_DATA_3V3 (1 << 0) 1382 1383 static int syskt_probe(struct sdhci_pci_chip *chip) 1384 { 1385 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1386 chip->pdev->class &= ~0x0000FF; 1387 chip->pdev->class |= PCI_SDHCI_IFDMA; 1388 } 1389 return 0; 1390 } 1391 1392 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 1393 { 1394 int tm, ps; 1395 1396 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 1397 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 1398 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 1399 "board rev %d.%d, chip rev %d.%d\n", 1400 board_rev >> 4, board_rev & 0xf, 1401 chip_rev >> 4, chip_rev & 0xf); 1402 if (chip_rev >= 0x20) 1403 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 1404 1405 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 1406 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 1407 udelay(50); 1408 tm = 10; /* Wait max 1 ms */ 1409 do { 1410 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 1411 if (ps & SYSKT_POWER_STATUS_OK) 1412 break; 1413 udelay(100); 1414 } while (--tm); 1415 if (!tm) { 1416 dev_err(&slot->chip->pdev->dev, 1417 "power regulator never stabilized"); 1418 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 1419 return -ENODEV; 1420 } 1421 1422 return 0; 1423 } 1424 1425 static const struct sdhci_pci_fixes sdhci_syskt = { 1426 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 1427 .probe = syskt_probe, 1428 .probe_slot = syskt_probe_slot, 1429 }; 1430 1431 static int via_probe(struct sdhci_pci_chip *chip) 1432 { 1433 if (chip->pdev->revision == 0x10) 1434 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 1435 1436 return 0; 1437 } 1438 1439 static const struct sdhci_pci_fixes sdhci_via = { 1440 .probe = via_probe, 1441 }; 1442 1443 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 1444 { 1445 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 1446 return 0; 1447 } 1448 1449 static const struct sdhci_pci_fixes sdhci_rtsx = { 1450 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1451 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 1452 SDHCI_QUIRK2_BROKEN_DDR50, 1453 .probe_slot = rtsx_probe_slot, 1454 }; 1455 1456 /*AMD chipset generation*/ 1457 enum amd_chipset_gen { 1458 AMD_CHIPSET_BEFORE_ML, 1459 AMD_CHIPSET_CZ, 1460 AMD_CHIPSET_NL, 1461 AMD_CHIPSET_UNKNOWN, 1462 }; 1463 1464 /* AMD registers */ 1465 #define AMD_SD_AUTO_PATTERN 0xB8 1466 #define AMD_MSLEEP_DURATION 4 1467 #define AMD_SD_MISC_CONTROL 0xD0 1468 #define AMD_MAX_TUNE_VALUE 0x0B 1469 #define AMD_AUTO_TUNE_SEL 0x10800 1470 #define AMD_FIFO_PTR 0x30 1471 #define AMD_BIT_MASK 0x1F 1472 1473 static void amd_tuning_reset(struct sdhci_host *host) 1474 { 1475 unsigned int val; 1476 1477 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1478 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 1479 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1480 1481 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1482 val &= ~SDHCI_CTRL_EXEC_TUNING; 1483 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1484 } 1485 1486 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 1487 { 1488 unsigned int val; 1489 1490 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 1491 val &= ~AMD_BIT_MASK; 1492 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 1493 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 1494 } 1495 1496 static void amd_enable_manual_tuning(struct pci_dev *pdev) 1497 { 1498 unsigned int val; 1499 1500 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 1501 val |= AMD_FIFO_PTR; 1502 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 1503 } 1504 1505 static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode) 1506 { 1507 struct sdhci_pci_slot *slot = sdhci_priv(host); 1508 struct pci_dev *pdev = slot->chip->pdev; 1509 u8 valid_win = 0; 1510 u8 valid_win_max = 0; 1511 u8 valid_win_end = 0; 1512 u8 ctrl, tune_around; 1513 1514 amd_tuning_reset(host); 1515 1516 for (tune_around = 0; tune_around < 12; tune_around++) { 1517 amd_config_tuning_phase(pdev, tune_around); 1518 1519 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1520 valid_win = 0; 1521 msleep(AMD_MSLEEP_DURATION); 1522 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 1523 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 1524 } else if (++valid_win > valid_win_max) { 1525 valid_win_max = valid_win; 1526 valid_win_end = tune_around; 1527 } 1528 } 1529 1530 if (!valid_win_max) { 1531 dev_err(&pdev->dev, "no tuning point found\n"); 1532 return -EIO; 1533 } 1534 1535 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 1536 1537 amd_enable_manual_tuning(pdev); 1538 1539 host->mmc->retune_period = 0; 1540 1541 return 0; 1542 } 1543 1544 static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode) 1545 { 1546 struct sdhci_host *host = mmc_priv(mmc); 1547 1548 /* AMD requires custom HS200 tuning */ 1549 if (host->timing == MMC_TIMING_MMC_HS200) 1550 return amd_execute_tuning_hs200(host, opcode); 1551 1552 /* Otherwise perform standard SDHCI tuning */ 1553 return sdhci_execute_tuning(mmc, opcode); 1554 } 1555 1556 static int amd_probe_slot(struct sdhci_pci_slot *slot) 1557 { 1558 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 1559 1560 ops->execute_tuning = amd_execute_tuning; 1561 1562 return 0; 1563 } 1564 1565 static int amd_probe(struct sdhci_pci_chip *chip) 1566 { 1567 struct pci_dev *smbus_dev; 1568 enum amd_chipset_gen gen; 1569 1570 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1571 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 1572 if (smbus_dev) { 1573 gen = AMD_CHIPSET_BEFORE_ML; 1574 } else { 1575 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1576 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1577 if (smbus_dev) { 1578 if (smbus_dev->revision < 0x51) 1579 gen = AMD_CHIPSET_CZ; 1580 else 1581 gen = AMD_CHIPSET_NL; 1582 } else { 1583 gen = AMD_CHIPSET_UNKNOWN; 1584 } 1585 } 1586 1587 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1588 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1589 1590 return 0; 1591 } 1592 1593 static const struct sdhci_ops amd_sdhci_pci_ops = { 1594 .set_clock = sdhci_set_clock, 1595 .enable_dma = sdhci_pci_enable_dma, 1596 .set_bus_width = sdhci_set_bus_width, 1597 .reset = sdhci_reset, 1598 .set_uhs_signaling = sdhci_set_uhs_signaling, 1599 }; 1600 1601 static const struct sdhci_pci_fixes sdhci_amd = { 1602 .probe = amd_probe, 1603 .ops = &amd_sdhci_pci_ops, 1604 .probe_slot = amd_probe_slot, 1605 }; 1606 1607 static const struct pci_device_id pci_ids[] = { 1608 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh), 1609 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc), 1610 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc), 1611 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc), 1612 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712), 1613 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712), 1614 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714), 1615 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714), 1616 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe), 1617 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron), 1618 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron), 1619 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron), 1620 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron), 1621 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt), 1622 SDHCI_PCI_DEVICE(VIA, 95D0, via), 1623 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx), 1624 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk), 1625 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0), 1626 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2), 1627 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2), 1628 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd), 1629 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio), 1630 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio), 1631 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc), 1632 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc), 1633 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio), 1634 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio), 1635 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc), 1636 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio), 1637 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio), 1638 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd), 1639 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc), 1640 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc), 1641 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio), 1642 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd), 1643 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd), 1644 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio), 1645 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio), 1646 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc), 1647 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc), 1648 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc), 1649 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc), 1650 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio), 1651 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd), 1652 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc), 1653 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc), 1654 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc), 1655 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio), 1656 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd), 1657 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc), 1658 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio), 1659 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd), 1660 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc), 1661 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio), 1662 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd), 1663 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc), 1664 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio), 1665 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd), 1666 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc), 1667 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd), 1668 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd), 1669 SDHCI_PCI_DEVICE(INTEL, ICP_EMMC, intel_glk_emmc), 1670 SDHCI_PCI_DEVICE(INTEL, ICP_SD, intel_byt_sd), 1671 SDHCI_PCI_DEVICE(INTEL, EHL_EMMC, intel_glk_emmc), 1672 SDHCI_PCI_DEVICE(INTEL, EHL_SD, intel_byt_sd), 1673 SDHCI_PCI_DEVICE(INTEL, CML_EMMC, intel_glk_emmc), 1674 SDHCI_PCI_DEVICE(INTEL, CML_SD, intel_byt_sd), 1675 SDHCI_PCI_DEVICE(O2, 8120, o2), 1676 SDHCI_PCI_DEVICE(O2, 8220, o2), 1677 SDHCI_PCI_DEVICE(O2, 8221, o2), 1678 SDHCI_PCI_DEVICE(O2, 8320, o2), 1679 SDHCI_PCI_DEVICE(O2, 8321, o2), 1680 SDHCI_PCI_DEVICE(O2, FUJIN2, o2), 1681 SDHCI_PCI_DEVICE(O2, SDS0, o2), 1682 SDHCI_PCI_DEVICE(O2, SDS1, o2), 1683 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2), 1684 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), 1685 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan), 1686 SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps), 1687 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), 1688 /* Generic SD host controller */ 1689 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, 1690 { /* end: all zeroes */ }, 1691 }; 1692 1693 MODULE_DEVICE_TABLE(pci, pci_ids); 1694 1695 /*****************************************************************************\ 1696 * * 1697 * SDHCI core callbacks * 1698 * * 1699 \*****************************************************************************/ 1700 1701 int sdhci_pci_enable_dma(struct sdhci_host *host) 1702 { 1703 struct sdhci_pci_slot *slot; 1704 struct pci_dev *pdev; 1705 1706 slot = sdhci_priv(host); 1707 pdev = slot->chip->pdev; 1708 1709 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1710 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1711 (host->flags & SDHCI_USE_SDMA)) { 1712 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1713 "doesn't fully claim to support it.\n"); 1714 } 1715 1716 pci_set_master(pdev); 1717 1718 return 0; 1719 } 1720 1721 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1722 { 1723 struct sdhci_pci_slot *slot = sdhci_priv(host); 1724 int rst_n_gpio = slot->rst_n_gpio; 1725 1726 if (!gpio_is_valid(rst_n_gpio)) 1727 return; 1728 gpio_set_value_cansleep(rst_n_gpio, 0); 1729 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1730 udelay(10); 1731 gpio_set_value_cansleep(rst_n_gpio, 1); 1732 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1733 usleep_range(300, 1000); 1734 } 1735 1736 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1737 { 1738 struct sdhci_pci_slot *slot = sdhci_priv(host); 1739 1740 if (slot->hw_reset) 1741 slot->hw_reset(host); 1742 } 1743 1744 static const struct sdhci_ops sdhci_pci_ops = { 1745 .set_clock = sdhci_set_clock, 1746 .enable_dma = sdhci_pci_enable_dma, 1747 .set_bus_width = sdhci_set_bus_width, 1748 .reset = sdhci_reset, 1749 .set_uhs_signaling = sdhci_set_uhs_signaling, 1750 .hw_reset = sdhci_pci_hw_reset, 1751 }; 1752 1753 /*****************************************************************************\ 1754 * * 1755 * Suspend/resume * 1756 * * 1757 \*****************************************************************************/ 1758 1759 #ifdef CONFIG_PM_SLEEP 1760 static int sdhci_pci_suspend(struct device *dev) 1761 { 1762 struct pci_dev *pdev = to_pci_dev(dev); 1763 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1764 1765 if (!chip) 1766 return 0; 1767 1768 if (chip->fixes && chip->fixes->suspend) 1769 return chip->fixes->suspend(chip); 1770 1771 return sdhci_pci_suspend_host(chip); 1772 } 1773 1774 static int sdhci_pci_resume(struct device *dev) 1775 { 1776 struct pci_dev *pdev = to_pci_dev(dev); 1777 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1778 1779 if (!chip) 1780 return 0; 1781 1782 if (chip->fixes && chip->fixes->resume) 1783 return chip->fixes->resume(chip); 1784 1785 return sdhci_pci_resume_host(chip); 1786 } 1787 #endif 1788 1789 #ifdef CONFIG_PM 1790 static int sdhci_pci_runtime_suspend(struct device *dev) 1791 { 1792 struct pci_dev *pdev = to_pci_dev(dev); 1793 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1794 1795 if (!chip) 1796 return 0; 1797 1798 if (chip->fixes && chip->fixes->runtime_suspend) 1799 return chip->fixes->runtime_suspend(chip); 1800 1801 return sdhci_pci_runtime_suspend_host(chip); 1802 } 1803 1804 static int sdhci_pci_runtime_resume(struct device *dev) 1805 { 1806 struct pci_dev *pdev = to_pci_dev(dev); 1807 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1808 1809 if (!chip) 1810 return 0; 1811 1812 if (chip->fixes && chip->fixes->runtime_resume) 1813 return chip->fixes->runtime_resume(chip); 1814 1815 return sdhci_pci_runtime_resume_host(chip); 1816 } 1817 #endif 1818 1819 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1820 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1821 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1822 sdhci_pci_runtime_resume, NULL) 1823 }; 1824 1825 /*****************************************************************************\ 1826 * * 1827 * Device probing/removal * 1828 * * 1829 \*****************************************************************************/ 1830 1831 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1832 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1833 int slotno) 1834 { 1835 struct sdhci_pci_slot *slot; 1836 struct sdhci_host *host; 1837 int ret, bar = first_bar + slotno; 1838 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 1839 1840 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1841 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1842 return ERR_PTR(-ENODEV); 1843 } 1844 1845 if (pci_resource_len(pdev, bar) < 0x100) { 1846 dev_err(&pdev->dev, "Invalid iomem size. You may " 1847 "experience problems.\n"); 1848 } 1849 1850 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1851 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1852 return ERR_PTR(-ENODEV); 1853 } 1854 1855 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1856 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1857 return ERR_PTR(-ENODEV); 1858 } 1859 1860 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 1861 if (IS_ERR(host)) { 1862 dev_err(&pdev->dev, "cannot allocate host\n"); 1863 return ERR_CAST(host); 1864 } 1865 1866 slot = sdhci_priv(host); 1867 1868 slot->chip = chip; 1869 slot->host = host; 1870 slot->rst_n_gpio = -EINVAL; 1871 slot->cd_gpio = -EINVAL; 1872 slot->cd_idx = -1; 1873 1874 /* Retrieve platform data if there is any */ 1875 if (*sdhci_pci_get_data) 1876 slot->data = sdhci_pci_get_data(pdev, slotno); 1877 1878 if (slot->data) { 1879 if (slot->data->setup) { 1880 ret = slot->data->setup(slot->data); 1881 if (ret) { 1882 dev_err(&pdev->dev, "platform setup failed\n"); 1883 goto free; 1884 } 1885 } 1886 slot->rst_n_gpio = slot->data->rst_n_gpio; 1887 slot->cd_gpio = slot->data->cd_gpio; 1888 } 1889 1890 host->hw_name = "PCI"; 1891 host->ops = chip->fixes && chip->fixes->ops ? 1892 chip->fixes->ops : 1893 &sdhci_pci_ops; 1894 host->quirks = chip->quirks; 1895 host->quirks2 = chip->quirks2; 1896 1897 host->irq = pdev->irq; 1898 1899 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1900 if (ret) { 1901 dev_err(&pdev->dev, "cannot request region\n"); 1902 goto cleanup; 1903 } 1904 1905 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1906 1907 if (chip->fixes && chip->fixes->probe_slot) { 1908 ret = chip->fixes->probe_slot(slot); 1909 if (ret) 1910 goto cleanup; 1911 } 1912 1913 if (gpio_is_valid(slot->rst_n_gpio)) { 1914 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1915 gpio_direction_output(slot->rst_n_gpio, 1); 1916 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1917 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1918 } else { 1919 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1920 slot->rst_n_gpio = -EINVAL; 1921 } 1922 } 1923 1924 host->mmc->pm_caps = MMC_PM_KEEP_POWER; 1925 host->mmc->slotno = slotno; 1926 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1927 1928 if (device_can_wakeup(&pdev->dev)) 1929 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ; 1930 1931 if (host->mmc->caps & MMC_CAP_CD_WAKE) 1932 device_init_wakeup(&pdev->dev, true); 1933 1934 if (slot->cd_idx >= 0) { 1935 ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx, 1936 slot->cd_override_level, 0, NULL); 1937 if (ret && ret != -EPROBE_DEFER) 1938 ret = mmc_gpiod_request_cd(host->mmc, NULL, 1939 slot->cd_idx, 1940 slot->cd_override_level, 1941 0, NULL); 1942 if (ret == -EPROBE_DEFER) 1943 goto remove; 1944 1945 if (ret) { 1946 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 1947 slot->cd_idx = -1; 1948 } 1949 } 1950 1951 if (chip->fixes && chip->fixes->add_host) 1952 ret = chip->fixes->add_host(slot); 1953 else 1954 ret = sdhci_add_host(host); 1955 if (ret) 1956 goto remove; 1957 1958 sdhci_pci_add_own_cd(slot); 1959 1960 /* 1961 * Check if the chip needs a separate GPIO for card detect to wake up 1962 * from runtime suspend. If it is not there, don't allow runtime PM. 1963 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 1964 */ 1965 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 1966 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 1967 chip->allow_runtime_pm = false; 1968 1969 return slot; 1970 1971 remove: 1972 if (chip->fixes && chip->fixes->remove_slot) 1973 chip->fixes->remove_slot(slot, 0); 1974 1975 cleanup: 1976 if (slot->data && slot->data->cleanup) 1977 slot->data->cleanup(slot->data); 1978 1979 free: 1980 sdhci_free_host(host); 1981 1982 return ERR_PTR(ret); 1983 } 1984 1985 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 1986 { 1987 int dead; 1988 u32 scratch; 1989 1990 sdhci_pci_remove_own_cd(slot); 1991 1992 dead = 0; 1993 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 1994 if (scratch == (u32)-1) 1995 dead = 1; 1996 1997 sdhci_remove_host(slot->host, dead); 1998 1999 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 2000 slot->chip->fixes->remove_slot(slot, dead); 2001 2002 if (slot->data && slot->data->cleanup) 2003 slot->data->cleanup(slot->data); 2004 2005 sdhci_free_host(slot->host); 2006 } 2007 2008 static void sdhci_pci_runtime_pm_allow(struct device *dev) 2009 { 2010 pm_suspend_ignore_children(dev, 1); 2011 pm_runtime_set_autosuspend_delay(dev, 50); 2012 pm_runtime_use_autosuspend(dev); 2013 pm_runtime_allow(dev); 2014 /* Stay active until mmc core scans for a card */ 2015 pm_runtime_put_noidle(dev); 2016 } 2017 2018 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 2019 { 2020 pm_runtime_forbid(dev); 2021 pm_runtime_get_noresume(dev); 2022 } 2023 2024 static int sdhci_pci_probe(struct pci_dev *pdev, 2025 const struct pci_device_id *ent) 2026 { 2027 struct sdhci_pci_chip *chip; 2028 struct sdhci_pci_slot *slot; 2029 2030 u8 slots, first_bar; 2031 int ret, i; 2032 2033 BUG_ON(pdev == NULL); 2034 BUG_ON(ent == NULL); 2035 2036 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 2037 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 2038 2039 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 2040 if (ret) 2041 return ret; 2042 2043 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 2044 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 2045 2046 BUG_ON(slots > MAX_SLOTS); 2047 2048 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 2049 if (ret) 2050 return ret; 2051 2052 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 2053 2054 if (first_bar > 5) { 2055 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 2056 return -ENODEV; 2057 } 2058 2059 ret = pcim_enable_device(pdev); 2060 if (ret) 2061 return ret; 2062 2063 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 2064 if (!chip) 2065 return -ENOMEM; 2066 2067 chip->pdev = pdev; 2068 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 2069 if (chip->fixes) { 2070 chip->quirks = chip->fixes->quirks; 2071 chip->quirks2 = chip->fixes->quirks2; 2072 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 2073 } 2074 chip->num_slots = slots; 2075 chip->pm_retune = true; 2076 chip->rpm_retune = true; 2077 2078 pci_set_drvdata(pdev, chip); 2079 2080 if (chip->fixes && chip->fixes->probe) { 2081 ret = chip->fixes->probe(chip); 2082 if (ret) 2083 return ret; 2084 } 2085 2086 slots = chip->num_slots; /* Quirk may have changed this */ 2087 2088 for (i = 0; i < slots; i++) { 2089 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 2090 if (IS_ERR(slot)) { 2091 for (i--; i >= 0; i--) 2092 sdhci_pci_remove_slot(chip->slots[i]); 2093 return PTR_ERR(slot); 2094 } 2095 2096 chip->slots[i] = slot; 2097 } 2098 2099 if (chip->allow_runtime_pm) 2100 sdhci_pci_runtime_pm_allow(&pdev->dev); 2101 2102 return 0; 2103 } 2104 2105 static void sdhci_pci_remove(struct pci_dev *pdev) 2106 { 2107 int i; 2108 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 2109 2110 if (chip->allow_runtime_pm) 2111 sdhci_pci_runtime_pm_forbid(&pdev->dev); 2112 2113 for (i = 0; i < chip->num_slots; i++) 2114 sdhci_pci_remove_slot(chip->slots[i]); 2115 } 2116 2117 static struct pci_driver sdhci_driver = { 2118 .name = "sdhci-pci", 2119 .id_table = pci_ids, 2120 .probe = sdhci_pci_probe, 2121 .remove = sdhci_pci_remove, 2122 .driver = { 2123 .pm = &sdhci_pci_pm_ops 2124 }, 2125 }; 2126 2127 module_pci_driver(sdhci_driver); 2128 2129 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 2130 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 2131 MODULE_LICENSE("GPL"); 2132