1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 2 * 3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 * 10 * Thanks to the following companies for their support: 11 * 12 * - JMicron (hardware and technical support) 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/highmem.h> 17 #include <linux/module.h> 18 #include <linux/pci.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/slab.h> 21 #include <linux/device.h> 22 #include <linux/mmc/host.h> 23 #include <linux/mmc/mmc.h> 24 #include <linux/scatterlist.h> 25 #include <linux/io.h> 26 #include <linux/gpio.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/mmc/slot-gpio.h> 29 #include <linux/mmc/sdhci-pci-data.h> 30 #include <linux/acpi.h> 31 32 #include "sdhci.h" 33 #include "sdhci-pci.h" 34 #include "sdhci-pci-o2micro.h" 35 36 static int sdhci_pci_enable_dma(struct sdhci_host *host); 37 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width); 38 static void sdhci_pci_hw_reset(struct sdhci_host *host); 39 static int sdhci_pci_select_drive_strength(struct sdhci_host *host, 40 struct mmc_card *card, 41 unsigned int max_dtr, int host_drv, 42 int card_drv, int *drv_type); 43 44 /*****************************************************************************\ 45 * * 46 * Hardware specific quirk handling * 47 * * 48 \*****************************************************************************/ 49 50 static int ricoh_probe(struct sdhci_pci_chip *chip) 51 { 52 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 53 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 54 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 55 return 0; 56 } 57 58 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 59 { 60 slot->host->caps = 61 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 62 & SDHCI_TIMEOUT_CLK_MASK) | 63 64 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 65 & SDHCI_CLOCK_BASE_MASK) | 66 67 SDHCI_TIMEOUT_CLK_UNIT | 68 SDHCI_CAN_VDD_330 | 69 SDHCI_CAN_DO_HISPD | 70 SDHCI_CAN_DO_SDMA; 71 return 0; 72 } 73 74 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 75 { 76 /* Apply a delay to allow controller to settle */ 77 /* Otherwise it becomes confused if card state changed 78 during suspend */ 79 msleep(500); 80 return 0; 81 } 82 83 static const struct sdhci_pci_fixes sdhci_ricoh = { 84 .probe = ricoh_probe, 85 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 86 SDHCI_QUIRK_FORCE_DMA | 87 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 88 }; 89 90 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 91 .probe_slot = ricoh_mmc_probe_slot, 92 .resume = ricoh_mmc_resume, 93 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 94 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 95 SDHCI_QUIRK_NO_CARD_NO_RESET | 96 SDHCI_QUIRK_MISSING_CAPS 97 }; 98 99 static const struct sdhci_pci_fixes sdhci_ene_712 = { 100 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 101 SDHCI_QUIRK_BROKEN_DMA, 102 }; 103 104 static const struct sdhci_pci_fixes sdhci_ene_714 = { 105 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 106 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 107 SDHCI_QUIRK_BROKEN_DMA, 108 }; 109 110 static const struct sdhci_pci_fixes sdhci_cafe = { 111 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 112 SDHCI_QUIRK_NO_BUSY_IRQ | 113 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 114 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 115 }; 116 117 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 118 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 119 }; 120 121 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 122 { 123 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 124 return 0; 125 } 126 127 /* 128 * ADMA operation is disabled for Moorestown platform due to 129 * hardware bugs. 130 */ 131 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 132 { 133 /* 134 * slots number is fixed here for MRST as SDIO3/5 are never used and 135 * have hardware bugs. 136 */ 137 chip->num_slots = 1; 138 return 0; 139 } 140 141 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 142 { 143 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 144 return 0; 145 } 146 147 #ifdef CONFIG_PM 148 149 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 150 { 151 struct sdhci_pci_slot *slot = dev_id; 152 struct sdhci_host *host = slot->host; 153 154 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 155 return IRQ_HANDLED; 156 } 157 158 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 159 { 160 int err, irq, gpio = slot->cd_gpio; 161 162 slot->cd_gpio = -EINVAL; 163 slot->cd_irq = -EINVAL; 164 165 if (!gpio_is_valid(gpio)) 166 return; 167 168 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 169 if (err < 0) 170 goto out; 171 172 err = gpio_direction_input(gpio); 173 if (err < 0) 174 goto out_free; 175 176 irq = gpio_to_irq(gpio); 177 if (irq < 0) 178 goto out_free; 179 180 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 181 IRQF_TRIGGER_FALLING, "sd_cd", slot); 182 if (err) 183 goto out_free; 184 185 slot->cd_gpio = gpio; 186 slot->cd_irq = irq; 187 188 return; 189 190 out_free: 191 devm_gpio_free(&slot->chip->pdev->dev, gpio); 192 out: 193 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 194 } 195 196 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 197 { 198 if (slot->cd_irq >= 0) 199 free_irq(slot->cd_irq, slot); 200 } 201 202 #else 203 204 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 205 { 206 } 207 208 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 209 { 210 } 211 212 #endif 213 214 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 215 { 216 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 217 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC | 218 MMC_CAP2_HC_ERASE_SZ; 219 return 0; 220 } 221 222 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 223 { 224 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 225 return 0; 226 } 227 228 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 229 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 230 .probe_slot = mrst_hc_probe_slot, 231 }; 232 233 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 234 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 235 .probe = mrst_hc_probe, 236 }; 237 238 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 239 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 240 .allow_runtime_pm = true, 241 .own_cd_for_runtime_pm = true, 242 }; 243 244 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 245 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 246 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 247 .allow_runtime_pm = true, 248 .probe_slot = mfd_sdio_probe_slot, 249 }; 250 251 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 252 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 253 .allow_runtime_pm = true, 254 .probe_slot = mfd_emmc_probe_slot, 255 }; 256 257 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 258 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 259 .probe_slot = pch_hc_probe_slot, 260 }; 261 262 enum { 263 INTEL_DSM_FNS = 0, 264 INTEL_DSM_D3_RETUNE = 10, 265 }; 266 267 struct intel_host { 268 u32 dsm_fns; 269 bool d3_retune; 270 }; 271 272 const u8 intel_dsm_uuid[] = { 273 0xA5, 0x3E, 0xC1, 0xF6, 0xCD, 0x65, 0x1F, 0x46, 274 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61, 275 }; 276 277 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 278 unsigned int fn, u32 *result) 279 { 280 union acpi_object *obj; 281 int err = 0; 282 283 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), intel_dsm_uuid, 0, fn, NULL); 284 if (!obj) 285 return -EOPNOTSUPP; 286 287 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { 288 err = -EINVAL; 289 goto out; 290 } 291 292 if (obj->buffer.length >= 4) 293 *result = *(u32 *)obj->buffer.pointer; 294 else if (obj->buffer.length >= 2) 295 *result = *(u16 *)obj->buffer.pointer; 296 else 297 *result = *(u8 *)obj->buffer.pointer; 298 out: 299 ACPI_FREE(obj); 300 301 return err; 302 } 303 304 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 305 unsigned int fn, u32 *result) 306 { 307 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 308 return -EOPNOTSUPP; 309 310 return __intel_dsm(intel_host, dev, fn, result); 311 } 312 313 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 314 struct mmc_host *mmc) 315 { 316 int err; 317 u32 val; 318 319 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 320 if (err) { 321 pr_debug("%s: DSM not supported, error %d\n", 322 mmc_hostname(mmc), err); 323 return; 324 } 325 326 pr_debug("%s: DSM function mask %#x\n", 327 mmc_hostname(mmc), intel_host->dsm_fns); 328 329 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 330 intel_host->d3_retune = err ? true : !!val; 331 } 332 333 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 334 { 335 u8 reg; 336 337 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 338 reg |= 0x10; 339 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 340 /* For eMMC, minimum is 1us but give it 9us for good measure */ 341 udelay(9); 342 reg &= ~0x10; 343 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 344 /* For eMMC, minimum is 200us but give it 300us for good measure */ 345 usleep_range(300, 1000); 346 } 347 348 static int spt_select_drive_strength(struct sdhci_host *host, 349 struct mmc_card *card, 350 unsigned int max_dtr, 351 int host_drv, int card_drv, int *drv_type) 352 { 353 int drive_strength; 354 355 if (sdhci_pci_spt_drive_strength > 0) 356 drive_strength = sdhci_pci_spt_drive_strength & 0xf; 357 else 358 drive_strength = 0; /* Default 50-ohm */ 359 360 if ((mmc_driver_type_mask(drive_strength) & card_drv) == 0) 361 drive_strength = 0; /* Default 50-ohm */ 362 363 return drive_strength; 364 } 365 366 /* Try to read the drive strength from the card */ 367 static void spt_read_drive_strength(struct sdhci_host *host) 368 { 369 u32 val, i, t; 370 u16 m; 371 372 if (sdhci_pci_spt_drive_strength) 373 return; 374 375 sdhci_pci_spt_drive_strength = -1; 376 377 m = sdhci_readw(host, SDHCI_HOST_CONTROL2) & 0x7; 378 if (m != 3 && m != 5) 379 return; 380 val = sdhci_readl(host, SDHCI_PRESENT_STATE); 381 if (val & 0x3) 382 return; 383 sdhci_writel(host, 0x007f0023, SDHCI_INT_ENABLE); 384 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 385 sdhci_writew(host, 0x10, SDHCI_TRANSFER_MODE); 386 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 387 sdhci_writew(host, 512, SDHCI_BLOCK_SIZE); 388 sdhci_writew(host, 1, SDHCI_BLOCK_COUNT); 389 sdhci_writel(host, 0, SDHCI_ARGUMENT); 390 sdhci_writew(host, 0x83b, SDHCI_COMMAND); 391 for (i = 0; i < 1000; i++) { 392 val = sdhci_readl(host, SDHCI_INT_STATUS); 393 if (val & 0xffff8000) 394 return; 395 if (val & 0x20) 396 break; 397 udelay(1); 398 } 399 val = sdhci_readl(host, SDHCI_PRESENT_STATE); 400 if (!(val & 0x800)) 401 return; 402 for (i = 0; i < 47; i++) 403 val = sdhci_readl(host, SDHCI_BUFFER); 404 t = val & 0xf00; 405 if (t != 0x200 && t != 0x300) 406 return; 407 408 sdhci_pci_spt_drive_strength = 0x10 | ((val >> 12) & 0xf); 409 } 410 411 static int bxt_get_cd(struct mmc_host *mmc) 412 { 413 int gpio_cd = mmc_gpio_get_cd(mmc); 414 struct sdhci_host *host = mmc_priv(mmc); 415 unsigned long flags; 416 int ret = 0; 417 418 if (!gpio_cd) 419 return 0; 420 421 spin_lock_irqsave(&host->lock, flags); 422 423 if (host->flags & SDHCI_DEVICE_DEAD) 424 goto out; 425 426 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 427 out: 428 spin_unlock_irqrestore(&host->lock, flags); 429 430 return ret; 431 } 432 433 static void byt_read_dsm(struct sdhci_pci_slot *slot) 434 { 435 struct intel_host *intel_host = sdhci_pci_priv(slot); 436 struct device *dev = &slot->chip->pdev->dev; 437 struct mmc_host *mmc = slot->host->mmc; 438 439 intel_dsm_init(intel_host, dev, mmc); 440 slot->chip->rpm_retune = intel_host->d3_retune; 441 } 442 443 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 444 { 445 byt_read_dsm(slot); 446 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 447 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 448 MMC_CAP_CMD_DURING_TFR | 449 MMC_CAP_WAIT_WHILE_BUSY; 450 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ; 451 slot->hw_reset = sdhci_pci_int_hw_reset; 452 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 453 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 454 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_SPT_EMMC) { 455 spt_read_drive_strength(slot->host); 456 slot->select_drive_strength = spt_select_drive_strength; 457 } 458 return 0; 459 } 460 461 #ifdef CONFIG_ACPI 462 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 463 { 464 acpi_status status; 465 unsigned long long max_freq; 466 467 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 468 "MXFQ", NULL, &max_freq); 469 if (ACPI_FAILURE(status)) { 470 dev_err(&slot->chip->pdev->dev, 471 "MXFQ not found in acpi table\n"); 472 return -EINVAL; 473 } 474 475 slot->host->mmc->f_max = max_freq * 1000000; 476 477 return 0; 478 } 479 #else 480 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 481 { 482 return 0; 483 } 484 #endif 485 486 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 487 { 488 int err; 489 490 byt_read_dsm(slot); 491 492 err = ni_set_max_freq(slot); 493 if (err) 494 return err; 495 496 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 497 MMC_CAP_WAIT_WHILE_BUSY; 498 return 0; 499 } 500 501 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 502 { 503 byt_read_dsm(slot); 504 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 505 MMC_CAP_WAIT_WHILE_BUSY; 506 return 0; 507 } 508 509 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 510 { 511 byt_read_dsm(slot); 512 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 513 slot->cd_idx = 0; 514 slot->cd_override_level = true; 515 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 516 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 517 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 518 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) { 519 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 520 slot->host->mmc->caps |= MMC_CAP_AGGRESSIVE_PM; 521 } 522 523 return 0; 524 } 525 526 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 527 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 528 529 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 530 unsigned short vdd) 531 { 532 int cntr; 533 u8 reg; 534 535 sdhci_set_power(host, mode, vdd); 536 537 if (mode == MMC_POWER_OFF) 538 return; 539 540 spin_unlock_irq(&host->lock); 541 542 /* 543 * Bus power might not enable after D3 -> D0 transition due to the 544 * present state not yet having propagated. Retry for up to 2ms. 545 */ 546 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 547 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 548 if (reg & SDHCI_POWER_ON) 549 break; 550 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 551 reg |= SDHCI_POWER_ON; 552 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 553 } 554 555 spin_lock_irq(&host->lock); 556 } 557 558 static const struct sdhci_ops sdhci_intel_byt_ops = { 559 .set_clock = sdhci_set_clock, 560 .set_power = sdhci_intel_set_power, 561 .enable_dma = sdhci_pci_enable_dma, 562 .set_bus_width = sdhci_pci_set_bus_width, 563 .reset = sdhci_reset, 564 .set_uhs_signaling = sdhci_set_uhs_signaling, 565 .hw_reset = sdhci_pci_hw_reset, 566 .select_drive_strength = sdhci_pci_select_drive_strength, 567 }; 568 569 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 570 .allow_runtime_pm = true, 571 .probe_slot = byt_emmc_probe_slot, 572 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 573 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 574 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 575 SDHCI_QUIRK2_STOP_WITH_TC, 576 .ops = &sdhci_intel_byt_ops, 577 .priv_size = sizeof(struct intel_host), 578 }; 579 580 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 581 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 582 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 583 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 584 .allow_runtime_pm = true, 585 .probe_slot = ni_byt_sdio_probe_slot, 586 .ops = &sdhci_intel_byt_ops, 587 .priv_size = sizeof(struct intel_host), 588 }; 589 590 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 591 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 592 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 593 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 594 .allow_runtime_pm = true, 595 .probe_slot = byt_sdio_probe_slot, 596 .ops = &sdhci_intel_byt_ops, 597 .priv_size = sizeof(struct intel_host), 598 }; 599 600 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 601 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 602 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 603 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 604 SDHCI_QUIRK2_STOP_WITH_TC, 605 .allow_runtime_pm = true, 606 .own_cd_for_runtime_pm = true, 607 .probe_slot = byt_sd_probe_slot, 608 .ops = &sdhci_intel_byt_ops, 609 .priv_size = sizeof(struct intel_host), 610 }; 611 612 /* Define Host controllers for Intel Merrifield platform */ 613 #define INTEL_MRFLD_EMMC_0 0 614 #define INTEL_MRFLD_EMMC_1 1 615 #define INTEL_MRFLD_SD 2 616 #define INTEL_MRFLD_SDIO 3 617 618 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 619 { 620 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 621 622 switch (func) { 623 case INTEL_MRFLD_EMMC_0: 624 case INTEL_MRFLD_EMMC_1: 625 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 626 MMC_CAP_8_BIT_DATA | 627 MMC_CAP_1_8V_DDR; 628 break; 629 case INTEL_MRFLD_SD: 630 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 631 break; 632 case INTEL_MRFLD_SDIO: 633 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 634 MMC_CAP_POWER_OFF_CARD; 635 break; 636 default: 637 return -ENODEV; 638 } 639 return 0; 640 } 641 642 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 643 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 644 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 645 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 646 .allow_runtime_pm = true, 647 .probe_slot = intel_mrfld_mmc_probe_slot, 648 }; 649 650 /* O2Micro extra registers */ 651 #define O2_SD_LOCK_WP 0xD3 652 #define O2_SD_MULTI_VCC3V 0xEE 653 #define O2_SD_CLKREQ 0xEC 654 #define O2_SD_CAPS 0xE0 655 #define O2_SD_ADMA1 0xE2 656 #define O2_SD_ADMA2 0xE7 657 #define O2_SD_INF_MOD 0xF1 658 659 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 660 { 661 u8 scratch; 662 int ret; 663 664 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 665 if (ret) 666 return ret; 667 668 /* 669 * Turn PMOS on [bit 0], set over current detection to 2.4 V 670 * [bit 1:2] and enable over current debouncing [bit 6]. 671 */ 672 if (on) 673 scratch |= 0x47; 674 else 675 scratch &= ~0x47; 676 677 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 678 } 679 680 static int jmicron_probe(struct sdhci_pci_chip *chip) 681 { 682 int ret; 683 u16 mmcdev = 0; 684 685 if (chip->pdev->revision == 0) { 686 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 687 SDHCI_QUIRK_32BIT_DMA_SIZE | 688 SDHCI_QUIRK_32BIT_ADMA_SIZE | 689 SDHCI_QUIRK_RESET_AFTER_REQUEST | 690 SDHCI_QUIRK_BROKEN_SMALL_PIO; 691 } 692 693 /* 694 * JMicron chips can have two interfaces to the same hardware 695 * in order to work around limitations in Microsoft's driver. 696 * We need to make sure we only bind to one of them. 697 * 698 * This code assumes two things: 699 * 700 * 1. The PCI code adds subfunctions in order. 701 * 702 * 2. The MMC interface has a lower subfunction number 703 * than the SD interface. 704 */ 705 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 706 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 707 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 708 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 709 710 if (mmcdev) { 711 struct pci_dev *sd_dev; 712 713 sd_dev = NULL; 714 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 715 mmcdev, sd_dev)) != NULL) { 716 if ((PCI_SLOT(chip->pdev->devfn) == 717 PCI_SLOT(sd_dev->devfn)) && 718 (chip->pdev->bus == sd_dev->bus)) 719 break; 720 } 721 722 if (sd_dev) { 723 pci_dev_put(sd_dev); 724 dev_info(&chip->pdev->dev, "Refusing to bind to " 725 "secondary interface.\n"); 726 return -ENODEV; 727 } 728 } 729 730 /* 731 * JMicron chips need a bit of a nudge to enable the power 732 * output pins. 733 */ 734 ret = jmicron_pmos(chip, 1); 735 if (ret) { 736 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 737 return ret; 738 } 739 740 /* quirk for unsable RO-detection on JM388 chips */ 741 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 742 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 743 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 744 745 return 0; 746 } 747 748 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 749 { 750 u8 scratch; 751 752 scratch = readb(host->ioaddr + 0xC0); 753 754 if (on) 755 scratch |= 0x01; 756 else 757 scratch &= ~0x01; 758 759 writeb(scratch, host->ioaddr + 0xC0); 760 } 761 762 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 763 { 764 if (slot->chip->pdev->revision == 0) { 765 u16 version; 766 767 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 768 version = (version & SDHCI_VENDOR_VER_MASK) >> 769 SDHCI_VENDOR_VER_SHIFT; 770 771 /* 772 * Older versions of the chip have lots of nasty glitches 773 * in the ADMA engine. It's best just to avoid it 774 * completely. 775 */ 776 if (version < 0xAC) 777 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 778 } 779 780 /* JM388 MMC doesn't support 1.8V while SD supports it */ 781 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 782 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 783 MMC_VDD_29_30 | MMC_VDD_30_31 | 784 MMC_VDD_165_195; /* allow 1.8V */ 785 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 786 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 787 } 788 789 /* 790 * The secondary interface requires a bit set to get the 791 * interrupts. 792 */ 793 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 794 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 795 jmicron_enable_mmc(slot->host, 1); 796 797 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 798 799 return 0; 800 } 801 802 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 803 { 804 if (dead) 805 return; 806 807 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 808 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 809 jmicron_enable_mmc(slot->host, 0); 810 } 811 812 static int jmicron_suspend(struct sdhci_pci_chip *chip) 813 { 814 int i; 815 816 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 817 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 818 for (i = 0; i < chip->num_slots; i++) 819 jmicron_enable_mmc(chip->slots[i]->host, 0); 820 } 821 822 return 0; 823 } 824 825 static int jmicron_resume(struct sdhci_pci_chip *chip) 826 { 827 int ret, i; 828 829 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 830 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 831 for (i = 0; i < chip->num_slots; i++) 832 jmicron_enable_mmc(chip->slots[i]->host, 1); 833 } 834 835 ret = jmicron_pmos(chip, 1); 836 if (ret) { 837 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 838 return ret; 839 } 840 841 return 0; 842 } 843 844 static const struct sdhci_pci_fixes sdhci_o2 = { 845 .probe = sdhci_pci_o2_probe, 846 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 847 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 848 .probe_slot = sdhci_pci_o2_probe_slot, 849 .resume = sdhci_pci_o2_resume, 850 }; 851 852 static const struct sdhci_pci_fixes sdhci_jmicron = { 853 .probe = jmicron_probe, 854 855 .probe_slot = jmicron_probe_slot, 856 .remove_slot = jmicron_remove_slot, 857 858 .suspend = jmicron_suspend, 859 .resume = jmicron_resume, 860 }; 861 862 /* SysKonnect CardBus2SDIO extra registers */ 863 #define SYSKT_CTRL 0x200 864 #define SYSKT_RDFIFO_STAT 0x204 865 #define SYSKT_WRFIFO_STAT 0x208 866 #define SYSKT_POWER_DATA 0x20c 867 #define SYSKT_POWER_330 0xef 868 #define SYSKT_POWER_300 0xf8 869 #define SYSKT_POWER_184 0xcc 870 #define SYSKT_POWER_CMD 0x20d 871 #define SYSKT_POWER_START (1 << 7) 872 #define SYSKT_POWER_STATUS 0x20e 873 #define SYSKT_POWER_STATUS_OK (1 << 0) 874 #define SYSKT_BOARD_REV 0x210 875 #define SYSKT_CHIP_REV 0x211 876 #define SYSKT_CONF_DATA 0x212 877 #define SYSKT_CONF_DATA_1V8 (1 << 2) 878 #define SYSKT_CONF_DATA_2V5 (1 << 1) 879 #define SYSKT_CONF_DATA_3V3 (1 << 0) 880 881 static int syskt_probe(struct sdhci_pci_chip *chip) 882 { 883 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 884 chip->pdev->class &= ~0x0000FF; 885 chip->pdev->class |= PCI_SDHCI_IFDMA; 886 } 887 return 0; 888 } 889 890 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 891 { 892 int tm, ps; 893 894 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 895 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 896 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 897 "board rev %d.%d, chip rev %d.%d\n", 898 board_rev >> 4, board_rev & 0xf, 899 chip_rev >> 4, chip_rev & 0xf); 900 if (chip_rev >= 0x20) 901 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 902 903 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 904 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 905 udelay(50); 906 tm = 10; /* Wait max 1 ms */ 907 do { 908 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 909 if (ps & SYSKT_POWER_STATUS_OK) 910 break; 911 udelay(100); 912 } while (--tm); 913 if (!tm) { 914 dev_err(&slot->chip->pdev->dev, 915 "power regulator never stabilized"); 916 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 917 return -ENODEV; 918 } 919 920 return 0; 921 } 922 923 static const struct sdhci_pci_fixes sdhci_syskt = { 924 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 925 .probe = syskt_probe, 926 .probe_slot = syskt_probe_slot, 927 }; 928 929 static int via_probe(struct sdhci_pci_chip *chip) 930 { 931 if (chip->pdev->revision == 0x10) 932 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 933 934 return 0; 935 } 936 937 static const struct sdhci_pci_fixes sdhci_via = { 938 .probe = via_probe, 939 }; 940 941 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 942 { 943 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 944 return 0; 945 } 946 947 static const struct sdhci_pci_fixes sdhci_rtsx = { 948 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 949 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 950 SDHCI_QUIRK2_BROKEN_DDR50, 951 .probe_slot = rtsx_probe_slot, 952 }; 953 954 /*AMD chipset generation*/ 955 enum amd_chipset_gen { 956 AMD_CHIPSET_BEFORE_ML, 957 AMD_CHIPSET_CZ, 958 AMD_CHIPSET_NL, 959 AMD_CHIPSET_UNKNOWN, 960 }; 961 962 /* AMD registers */ 963 #define AMD_SD_AUTO_PATTERN 0xB8 964 #define AMD_MSLEEP_DURATION 4 965 #define AMD_SD_MISC_CONTROL 0xD0 966 #define AMD_MAX_TUNE_VALUE 0x0B 967 #define AMD_AUTO_TUNE_SEL 0x10800 968 #define AMD_FIFO_PTR 0x30 969 #define AMD_BIT_MASK 0x1F 970 971 static void amd_tuning_reset(struct sdhci_host *host) 972 { 973 unsigned int val; 974 975 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 976 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 977 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 978 979 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 980 val &= ~SDHCI_CTRL_EXEC_TUNING; 981 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 982 } 983 984 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 985 { 986 unsigned int val; 987 988 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 989 val &= ~AMD_BIT_MASK; 990 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 991 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 992 } 993 994 static void amd_enable_manual_tuning(struct pci_dev *pdev) 995 { 996 unsigned int val; 997 998 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 999 val |= AMD_FIFO_PTR; 1000 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 1001 } 1002 1003 static int amd_execute_tuning(struct sdhci_host *host, u32 opcode) 1004 { 1005 struct sdhci_pci_slot *slot = sdhci_priv(host); 1006 struct pci_dev *pdev = slot->chip->pdev; 1007 u8 valid_win = 0; 1008 u8 valid_win_max = 0; 1009 u8 valid_win_end = 0; 1010 u8 ctrl, tune_around; 1011 1012 amd_tuning_reset(host); 1013 1014 for (tune_around = 0; tune_around < 12; tune_around++) { 1015 amd_config_tuning_phase(pdev, tune_around); 1016 1017 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1018 valid_win = 0; 1019 msleep(AMD_MSLEEP_DURATION); 1020 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 1021 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 1022 } else if (++valid_win > valid_win_max) { 1023 valid_win_max = valid_win; 1024 valid_win_end = tune_around; 1025 } 1026 } 1027 1028 if (!valid_win_max) { 1029 dev_err(&pdev->dev, "no tuning point found\n"); 1030 return -EIO; 1031 } 1032 1033 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 1034 1035 amd_enable_manual_tuning(pdev); 1036 1037 host->mmc->retune_period = 0; 1038 1039 return 0; 1040 } 1041 1042 static int amd_probe(struct sdhci_pci_chip *chip) 1043 { 1044 struct pci_dev *smbus_dev; 1045 enum amd_chipset_gen gen; 1046 1047 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1048 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 1049 if (smbus_dev) { 1050 gen = AMD_CHIPSET_BEFORE_ML; 1051 } else { 1052 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1053 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1054 if (smbus_dev) { 1055 if (smbus_dev->revision < 0x51) 1056 gen = AMD_CHIPSET_CZ; 1057 else 1058 gen = AMD_CHIPSET_NL; 1059 } else { 1060 gen = AMD_CHIPSET_UNKNOWN; 1061 } 1062 } 1063 1064 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1065 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1066 1067 return 0; 1068 } 1069 1070 static const struct sdhci_ops amd_sdhci_pci_ops = { 1071 .set_clock = sdhci_set_clock, 1072 .enable_dma = sdhci_pci_enable_dma, 1073 .set_bus_width = sdhci_pci_set_bus_width, 1074 .reset = sdhci_reset, 1075 .set_uhs_signaling = sdhci_set_uhs_signaling, 1076 .platform_execute_tuning = amd_execute_tuning, 1077 }; 1078 1079 static const struct sdhci_pci_fixes sdhci_amd = { 1080 .probe = amd_probe, 1081 .ops = &amd_sdhci_pci_ops, 1082 }; 1083 1084 static const struct pci_device_id pci_ids[] = { 1085 { 1086 .vendor = PCI_VENDOR_ID_RICOH, 1087 .device = PCI_DEVICE_ID_RICOH_R5C822, 1088 .subvendor = PCI_ANY_ID, 1089 .subdevice = PCI_ANY_ID, 1090 .driver_data = (kernel_ulong_t)&sdhci_ricoh, 1091 }, 1092 1093 { 1094 .vendor = PCI_VENDOR_ID_RICOH, 1095 .device = 0x843, 1096 .subvendor = PCI_ANY_ID, 1097 .subdevice = PCI_ANY_ID, 1098 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 1099 }, 1100 1101 { 1102 .vendor = PCI_VENDOR_ID_RICOH, 1103 .device = 0xe822, 1104 .subvendor = PCI_ANY_ID, 1105 .subdevice = PCI_ANY_ID, 1106 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 1107 }, 1108 1109 { 1110 .vendor = PCI_VENDOR_ID_RICOH, 1111 .device = 0xe823, 1112 .subvendor = PCI_ANY_ID, 1113 .subdevice = PCI_ANY_ID, 1114 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 1115 }, 1116 1117 { 1118 .vendor = PCI_VENDOR_ID_ENE, 1119 .device = PCI_DEVICE_ID_ENE_CB712_SD, 1120 .subvendor = PCI_ANY_ID, 1121 .subdevice = PCI_ANY_ID, 1122 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 1123 }, 1124 1125 { 1126 .vendor = PCI_VENDOR_ID_ENE, 1127 .device = PCI_DEVICE_ID_ENE_CB712_SD_2, 1128 .subvendor = PCI_ANY_ID, 1129 .subdevice = PCI_ANY_ID, 1130 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 1131 }, 1132 1133 { 1134 .vendor = PCI_VENDOR_ID_ENE, 1135 .device = PCI_DEVICE_ID_ENE_CB714_SD, 1136 .subvendor = PCI_ANY_ID, 1137 .subdevice = PCI_ANY_ID, 1138 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 1139 }, 1140 1141 { 1142 .vendor = PCI_VENDOR_ID_ENE, 1143 .device = PCI_DEVICE_ID_ENE_CB714_SD_2, 1144 .subvendor = PCI_ANY_ID, 1145 .subdevice = PCI_ANY_ID, 1146 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 1147 }, 1148 1149 { 1150 .vendor = PCI_VENDOR_ID_MARVELL, 1151 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD, 1152 .subvendor = PCI_ANY_ID, 1153 .subdevice = PCI_ANY_ID, 1154 .driver_data = (kernel_ulong_t)&sdhci_cafe, 1155 }, 1156 1157 { 1158 .vendor = PCI_VENDOR_ID_JMICRON, 1159 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD, 1160 .subvendor = PCI_ANY_ID, 1161 .subdevice = PCI_ANY_ID, 1162 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1163 }, 1164 1165 { 1166 .vendor = PCI_VENDOR_ID_JMICRON, 1167 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC, 1168 .subvendor = PCI_ANY_ID, 1169 .subdevice = PCI_ANY_ID, 1170 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1171 }, 1172 1173 { 1174 .vendor = PCI_VENDOR_ID_JMICRON, 1175 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD, 1176 .subvendor = PCI_ANY_ID, 1177 .subdevice = PCI_ANY_ID, 1178 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1179 }, 1180 1181 { 1182 .vendor = PCI_VENDOR_ID_JMICRON, 1183 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD, 1184 .subvendor = PCI_ANY_ID, 1185 .subdevice = PCI_ANY_ID, 1186 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1187 }, 1188 1189 { 1190 .vendor = PCI_VENDOR_ID_SYSKONNECT, 1191 .device = 0x8000, 1192 .subvendor = PCI_ANY_ID, 1193 .subdevice = PCI_ANY_ID, 1194 .driver_data = (kernel_ulong_t)&sdhci_syskt, 1195 }, 1196 1197 { 1198 .vendor = PCI_VENDOR_ID_VIA, 1199 .device = 0x95d0, 1200 .subvendor = PCI_ANY_ID, 1201 .subdevice = PCI_ANY_ID, 1202 .driver_data = (kernel_ulong_t)&sdhci_via, 1203 }, 1204 1205 { 1206 .vendor = PCI_VENDOR_ID_REALTEK, 1207 .device = 0x5250, 1208 .subvendor = PCI_ANY_ID, 1209 .subdevice = PCI_ANY_ID, 1210 .driver_data = (kernel_ulong_t)&sdhci_rtsx, 1211 }, 1212 1213 { 1214 .vendor = PCI_VENDOR_ID_INTEL, 1215 .device = PCI_DEVICE_ID_INTEL_QRK_SD, 1216 .subvendor = PCI_ANY_ID, 1217 .subdevice = PCI_ANY_ID, 1218 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk, 1219 }, 1220 1221 { 1222 .vendor = PCI_VENDOR_ID_INTEL, 1223 .device = PCI_DEVICE_ID_INTEL_MRST_SD0, 1224 .subvendor = PCI_ANY_ID, 1225 .subdevice = PCI_ANY_ID, 1226 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0, 1227 }, 1228 1229 { 1230 .vendor = PCI_VENDOR_ID_INTEL, 1231 .device = PCI_DEVICE_ID_INTEL_MRST_SD1, 1232 .subvendor = PCI_ANY_ID, 1233 .subdevice = PCI_ANY_ID, 1234 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 1235 }, 1236 1237 { 1238 .vendor = PCI_VENDOR_ID_INTEL, 1239 .device = PCI_DEVICE_ID_INTEL_MRST_SD2, 1240 .subvendor = PCI_ANY_ID, 1241 .subdevice = PCI_ANY_ID, 1242 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 1243 }, 1244 1245 { 1246 .vendor = PCI_VENDOR_ID_INTEL, 1247 .device = PCI_DEVICE_ID_INTEL_MFD_SD, 1248 .subvendor = PCI_ANY_ID, 1249 .subdevice = PCI_ANY_ID, 1250 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1251 }, 1252 1253 { 1254 .vendor = PCI_VENDOR_ID_INTEL, 1255 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1, 1256 .subvendor = PCI_ANY_ID, 1257 .subdevice = PCI_ANY_ID, 1258 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1259 }, 1260 1261 { 1262 .vendor = PCI_VENDOR_ID_INTEL, 1263 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2, 1264 .subvendor = PCI_ANY_ID, 1265 .subdevice = PCI_ANY_ID, 1266 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1267 }, 1268 1269 { 1270 .vendor = PCI_VENDOR_ID_INTEL, 1271 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0, 1272 .subvendor = PCI_ANY_ID, 1273 .subdevice = PCI_ANY_ID, 1274 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1275 }, 1276 1277 { 1278 .vendor = PCI_VENDOR_ID_INTEL, 1279 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1, 1280 .subvendor = PCI_ANY_ID, 1281 .subdevice = PCI_ANY_ID, 1282 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1283 }, 1284 1285 { 1286 .vendor = PCI_VENDOR_ID_INTEL, 1287 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0, 1288 .subvendor = PCI_ANY_ID, 1289 .subdevice = PCI_ANY_ID, 1290 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1291 }, 1292 1293 { 1294 .vendor = PCI_VENDOR_ID_INTEL, 1295 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1, 1296 .subvendor = PCI_ANY_ID, 1297 .subdevice = PCI_ANY_ID, 1298 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1299 }, 1300 1301 { 1302 .vendor = PCI_VENDOR_ID_INTEL, 1303 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC, 1304 .subvendor = PCI_ANY_ID, 1305 .subdevice = PCI_ANY_ID, 1306 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1307 }, 1308 1309 { 1310 .vendor = PCI_VENDOR_ID_INTEL, 1311 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, 1312 .subvendor = PCI_VENDOR_ID_NI, 1313 .subdevice = 0x7884, 1314 .driver_data = (kernel_ulong_t)&sdhci_ni_byt_sdio, 1315 }, 1316 1317 { 1318 .vendor = PCI_VENDOR_ID_INTEL, 1319 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, 1320 .subvendor = PCI_ANY_ID, 1321 .subdevice = PCI_ANY_ID, 1322 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1323 }, 1324 1325 { 1326 .vendor = PCI_VENDOR_ID_INTEL, 1327 .device = PCI_DEVICE_ID_INTEL_BYT_SD, 1328 .subvendor = PCI_ANY_ID, 1329 .subdevice = PCI_ANY_ID, 1330 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1331 }, 1332 1333 { 1334 .vendor = PCI_VENDOR_ID_INTEL, 1335 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2, 1336 .subvendor = PCI_ANY_ID, 1337 .subdevice = PCI_ANY_ID, 1338 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1339 }, 1340 1341 { 1342 .vendor = PCI_VENDOR_ID_INTEL, 1343 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC, 1344 .subvendor = PCI_ANY_ID, 1345 .subdevice = PCI_ANY_ID, 1346 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1347 }, 1348 1349 { 1350 .vendor = PCI_VENDOR_ID_INTEL, 1351 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO, 1352 .subvendor = PCI_ANY_ID, 1353 .subdevice = PCI_ANY_ID, 1354 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1355 }, 1356 1357 { 1358 .vendor = PCI_VENDOR_ID_INTEL, 1359 .device = PCI_DEVICE_ID_INTEL_BSW_SD, 1360 .subvendor = PCI_ANY_ID, 1361 .subdevice = PCI_ANY_ID, 1362 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1363 }, 1364 1365 { 1366 .vendor = PCI_VENDOR_ID_INTEL, 1367 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0, 1368 .subvendor = PCI_ANY_ID, 1369 .subdevice = PCI_ANY_ID, 1370 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1371 }, 1372 1373 { 1374 .vendor = PCI_VENDOR_ID_INTEL, 1375 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1, 1376 .subvendor = PCI_ANY_ID, 1377 .subdevice = PCI_ANY_ID, 1378 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1379 }, 1380 1381 { 1382 .vendor = PCI_VENDOR_ID_INTEL, 1383 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2, 1384 .subvendor = PCI_ANY_ID, 1385 .subdevice = PCI_ANY_ID, 1386 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1387 }, 1388 1389 { 1390 .vendor = PCI_VENDOR_ID_INTEL, 1391 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0, 1392 .subvendor = PCI_ANY_ID, 1393 .subdevice = PCI_ANY_ID, 1394 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1395 }, 1396 1397 { 1398 .vendor = PCI_VENDOR_ID_INTEL, 1399 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1, 1400 .subvendor = PCI_ANY_ID, 1401 .subdevice = PCI_ANY_ID, 1402 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1403 }, 1404 1405 { 1406 .vendor = PCI_VENDOR_ID_INTEL, 1407 .device = PCI_DEVICE_ID_INTEL_MRFLD_MMC, 1408 .subvendor = PCI_ANY_ID, 1409 .subdevice = PCI_ANY_ID, 1410 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfld_mmc, 1411 }, 1412 1413 { 1414 .vendor = PCI_VENDOR_ID_INTEL, 1415 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC, 1416 .subvendor = PCI_ANY_ID, 1417 .subdevice = PCI_ANY_ID, 1418 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1419 }, 1420 1421 { 1422 .vendor = PCI_VENDOR_ID_INTEL, 1423 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO, 1424 .subvendor = PCI_ANY_ID, 1425 .subdevice = PCI_ANY_ID, 1426 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1427 }, 1428 1429 { 1430 .vendor = PCI_VENDOR_ID_INTEL, 1431 .device = PCI_DEVICE_ID_INTEL_SPT_SD, 1432 .subvendor = PCI_ANY_ID, 1433 .subdevice = PCI_ANY_ID, 1434 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1435 }, 1436 1437 { 1438 .vendor = PCI_VENDOR_ID_INTEL, 1439 .device = PCI_DEVICE_ID_INTEL_DNV_EMMC, 1440 .subvendor = PCI_ANY_ID, 1441 .subdevice = PCI_ANY_ID, 1442 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1443 }, 1444 1445 { 1446 .vendor = PCI_VENDOR_ID_INTEL, 1447 .device = PCI_DEVICE_ID_INTEL_BXT_EMMC, 1448 .subvendor = PCI_ANY_ID, 1449 .subdevice = PCI_ANY_ID, 1450 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1451 }, 1452 1453 { 1454 .vendor = PCI_VENDOR_ID_INTEL, 1455 .device = PCI_DEVICE_ID_INTEL_BXT_SDIO, 1456 .subvendor = PCI_ANY_ID, 1457 .subdevice = PCI_ANY_ID, 1458 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1459 }, 1460 1461 { 1462 .vendor = PCI_VENDOR_ID_INTEL, 1463 .device = PCI_DEVICE_ID_INTEL_BXT_SD, 1464 .subvendor = PCI_ANY_ID, 1465 .subdevice = PCI_ANY_ID, 1466 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1467 }, 1468 1469 { 1470 .vendor = PCI_VENDOR_ID_INTEL, 1471 .device = PCI_DEVICE_ID_INTEL_BXTM_EMMC, 1472 .subvendor = PCI_ANY_ID, 1473 .subdevice = PCI_ANY_ID, 1474 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1475 }, 1476 1477 { 1478 .vendor = PCI_VENDOR_ID_INTEL, 1479 .device = PCI_DEVICE_ID_INTEL_BXTM_SDIO, 1480 .subvendor = PCI_ANY_ID, 1481 .subdevice = PCI_ANY_ID, 1482 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1483 }, 1484 1485 { 1486 .vendor = PCI_VENDOR_ID_INTEL, 1487 .device = PCI_DEVICE_ID_INTEL_BXTM_SD, 1488 .subvendor = PCI_ANY_ID, 1489 .subdevice = PCI_ANY_ID, 1490 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1491 }, 1492 1493 { 1494 .vendor = PCI_VENDOR_ID_INTEL, 1495 .device = PCI_DEVICE_ID_INTEL_APL_EMMC, 1496 .subvendor = PCI_ANY_ID, 1497 .subdevice = PCI_ANY_ID, 1498 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1499 }, 1500 1501 { 1502 .vendor = PCI_VENDOR_ID_INTEL, 1503 .device = PCI_DEVICE_ID_INTEL_APL_SDIO, 1504 .subvendor = PCI_ANY_ID, 1505 .subdevice = PCI_ANY_ID, 1506 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1507 }, 1508 1509 { 1510 .vendor = PCI_VENDOR_ID_INTEL, 1511 .device = PCI_DEVICE_ID_INTEL_APL_SD, 1512 .subvendor = PCI_ANY_ID, 1513 .subdevice = PCI_ANY_ID, 1514 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1515 }, 1516 1517 { 1518 .vendor = PCI_VENDOR_ID_INTEL, 1519 .device = PCI_DEVICE_ID_INTEL_GLK_EMMC, 1520 .subvendor = PCI_ANY_ID, 1521 .subdevice = PCI_ANY_ID, 1522 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1523 }, 1524 1525 { 1526 .vendor = PCI_VENDOR_ID_INTEL, 1527 .device = PCI_DEVICE_ID_INTEL_GLK_SDIO, 1528 .subvendor = PCI_ANY_ID, 1529 .subdevice = PCI_ANY_ID, 1530 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1531 }, 1532 1533 { 1534 .vendor = PCI_VENDOR_ID_INTEL, 1535 .device = PCI_DEVICE_ID_INTEL_GLK_SD, 1536 .subvendor = PCI_ANY_ID, 1537 .subdevice = PCI_ANY_ID, 1538 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1539 }, 1540 1541 { 1542 .vendor = PCI_VENDOR_ID_O2, 1543 .device = PCI_DEVICE_ID_O2_8120, 1544 .subvendor = PCI_ANY_ID, 1545 .subdevice = PCI_ANY_ID, 1546 .driver_data = (kernel_ulong_t)&sdhci_o2, 1547 }, 1548 1549 { 1550 .vendor = PCI_VENDOR_ID_O2, 1551 .device = PCI_DEVICE_ID_O2_8220, 1552 .subvendor = PCI_ANY_ID, 1553 .subdevice = PCI_ANY_ID, 1554 .driver_data = (kernel_ulong_t)&sdhci_o2, 1555 }, 1556 1557 { 1558 .vendor = PCI_VENDOR_ID_O2, 1559 .device = PCI_DEVICE_ID_O2_8221, 1560 .subvendor = PCI_ANY_ID, 1561 .subdevice = PCI_ANY_ID, 1562 .driver_data = (kernel_ulong_t)&sdhci_o2, 1563 }, 1564 1565 { 1566 .vendor = PCI_VENDOR_ID_O2, 1567 .device = PCI_DEVICE_ID_O2_8320, 1568 .subvendor = PCI_ANY_ID, 1569 .subdevice = PCI_ANY_ID, 1570 .driver_data = (kernel_ulong_t)&sdhci_o2, 1571 }, 1572 1573 { 1574 .vendor = PCI_VENDOR_ID_O2, 1575 .device = PCI_DEVICE_ID_O2_8321, 1576 .subvendor = PCI_ANY_ID, 1577 .subdevice = PCI_ANY_ID, 1578 .driver_data = (kernel_ulong_t)&sdhci_o2, 1579 }, 1580 1581 { 1582 .vendor = PCI_VENDOR_ID_O2, 1583 .device = PCI_DEVICE_ID_O2_FUJIN2, 1584 .subvendor = PCI_ANY_ID, 1585 .subdevice = PCI_ANY_ID, 1586 .driver_data = (kernel_ulong_t)&sdhci_o2, 1587 }, 1588 1589 { 1590 .vendor = PCI_VENDOR_ID_O2, 1591 .device = PCI_DEVICE_ID_O2_SDS0, 1592 .subvendor = PCI_ANY_ID, 1593 .subdevice = PCI_ANY_ID, 1594 .driver_data = (kernel_ulong_t)&sdhci_o2, 1595 }, 1596 1597 { 1598 .vendor = PCI_VENDOR_ID_O2, 1599 .device = PCI_DEVICE_ID_O2_SDS1, 1600 .subvendor = PCI_ANY_ID, 1601 .subdevice = PCI_ANY_ID, 1602 .driver_data = (kernel_ulong_t)&sdhci_o2, 1603 }, 1604 1605 { 1606 .vendor = PCI_VENDOR_ID_O2, 1607 .device = PCI_DEVICE_ID_O2_SEABIRD0, 1608 .subvendor = PCI_ANY_ID, 1609 .subdevice = PCI_ANY_ID, 1610 .driver_data = (kernel_ulong_t)&sdhci_o2, 1611 }, 1612 1613 { 1614 .vendor = PCI_VENDOR_ID_O2, 1615 .device = PCI_DEVICE_ID_O2_SEABIRD1, 1616 .subvendor = PCI_ANY_ID, 1617 .subdevice = PCI_ANY_ID, 1618 .driver_data = (kernel_ulong_t)&sdhci_o2, 1619 }, 1620 { 1621 .vendor = PCI_VENDOR_ID_AMD, 1622 .device = PCI_ANY_ID, 1623 .class = PCI_CLASS_SYSTEM_SDHCI << 8, 1624 .class_mask = 0xFFFF00, 1625 .subvendor = PCI_ANY_ID, 1626 .subdevice = PCI_ANY_ID, 1627 .driver_data = (kernel_ulong_t)&sdhci_amd, 1628 }, 1629 { /* Generic SD host controller */ 1630 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) 1631 }, 1632 1633 { /* end: all zeroes */ }, 1634 }; 1635 1636 MODULE_DEVICE_TABLE(pci, pci_ids); 1637 1638 /*****************************************************************************\ 1639 * * 1640 * SDHCI core callbacks * 1641 * * 1642 \*****************************************************************************/ 1643 1644 static int sdhci_pci_enable_dma(struct sdhci_host *host) 1645 { 1646 struct sdhci_pci_slot *slot; 1647 struct pci_dev *pdev; 1648 1649 slot = sdhci_priv(host); 1650 pdev = slot->chip->pdev; 1651 1652 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1653 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1654 (host->flags & SDHCI_USE_SDMA)) { 1655 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1656 "doesn't fully claim to support it.\n"); 1657 } 1658 1659 pci_set_master(pdev); 1660 1661 return 0; 1662 } 1663 1664 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width) 1665 { 1666 u8 ctrl; 1667 1668 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1669 1670 switch (width) { 1671 case MMC_BUS_WIDTH_8: 1672 ctrl |= SDHCI_CTRL_8BITBUS; 1673 ctrl &= ~SDHCI_CTRL_4BITBUS; 1674 break; 1675 case MMC_BUS_WIDTH_4: 1676 ctrl |= SDHCI_CTRL_4BITBUS; 1677 ctrl &= ~SDHCI_CTRL_8BITBUS; 1678 break; 1679 default: 1680 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS); 1681 break; 1682 } 1683 1684 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1685 } 1686 1687 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1688 { 1689 struct sdhci_pci_slot *slot = sdhci_priv(host); 1690 int rst_n_gpio = slot->rst_n_gpio; 1691 1692 if (!gpio_is_valid(rst_n_gpio)) 1693 return; 1694 gpio_set_value_cansleep(rst_n_gpio, 0); 1695 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1696 udelay(10); 1697 gpio_set_value_cansleep(rst_n_gpio, 1); 1698 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1699 usleep_range(300, 1000); 1700 } 1701 1702 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1703 { 1704 struct sdhci_pci_slot *slot = sdhci_priv(host); 1705 1706 if (slot->hw_reset) 1707 slot->hw_reset(host); 1708 } 1709 1710 static int sdhci_pci_select_drive_strength(struct sdhci_host *host, 1711 struct mmc_card *card, 1712 unsigned int max_dtr, int host_drv, 1713 int card_drv, int *drv_type) 1714 { 1715 struct sdhci_pci_slot *slot = sdhci_priv(host); 1716 1717 if (!slot->select_drive_strength) 1718 return 0; 1719 1720 return slot->select_drive_strength(host, card, max_dtr, host_drv, 1721 card_drv, drv_type); 1722 } 1723 1724 static const struct sdhci_ops sdhci_pci_ops = { 1725 .set_clock = sdhci_set_clock, 1726 .enable_dma = sdhci_pci_enable_dma, 1727 .set_bus_width = sdhci_pci_set_bus_width, 1728 .reset = sdhci_reset, 1729 .set_uhs_signaling = sdhci_set_uhs_signaling, 1730 .hw_reset = sdhci_pci_hw_reset, 1731 .select_drive_strength = sdhci_pci_select_drive_strength, 1732 }; 1733 1734 /*****************************************************************************\ 1735 * * 1736 * Suspend/resume * 1737 * * 1738 \*****************************************************************************/ 1739 1740 #ifdef CONFIG_PM_SLEEP 1741 static int sdhci_pci_suspend(struct device *dev) 1742 { 1743 struct pci_dev *pdev = to_pci_dev(dev); 1744 struct sdhci_pci_chip *chip; 1745 struct sdhci_pci_slot *slot; 1746 struct sdhci_host *host; 1747 mmc_pm_flag_t slot_pm_flags; 1748 mmc_pm_flag_t pm_flags = 0; 1749 int i, ret; 1750 1751 chip = pci_get_drvdata(pdev); 1752 if (!chip) 1753 return 0; 1754 1755 for (i = 0; i < chip->num_slots; i++) { 1756 slot = chip->slots[i]; 1757 if (!slot) 1758 continue; 1759 1760 host = slot->host; 1761 1762 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 1763 mmc_retune_needed(host->mmc); 1764 1765 ret = sdhci_suspend_host(host); 1766 1767 if (ret) 1768 goto err_pci_suspend; 1769 1770 slot_pm_flags = host->mmc->pm_flags; 1771 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1772 sdhci_enable_irq_wakeups(host); 1773 1774 pm_flags |= slot_pm_flags; 1775 } 1776 1777 if (chip->fixes && chip->fixes->suspend) { 1778 ret = chip->fixes->suspend(chip); 1779 if (ret) 1780 goto err_pci_suspend; 1781 } 1782 1783 if (pm_flags & MMC_PM_KEEP_POWER) { 1784 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1785 device_init_wakeup(dev, true); 1786 else 1787 device_init_wakeup(dev, false); 1788 } else 1789 device_init_wakeup(dev, false); 1790 1791 return 0; 1792 1793 err_pci_suspend: 1794 while (--i >= 0) 1795 sdhci_resume_host(chip->slots[i]->host); 1796 return ret; 1797 } 1798 1799 static int sdhci_pci_resume(struct device *dev) 1800 { 1801 struct pci_dev *pdev = to_pci_dev(dev); 1802 struct sdhci_pci_chip *chip; 1803 struct sdhci_pci_slot *slot; 1804 int i, ret; 1805 1806 chip = pci_get_drvdata(pdev); 1807 if (!chip) 1808 return 0; 1809 1810 if (chip->fixes && chip->fixes->resume) { 1811 ret = chip->fixes->resume(chip); 1812 if (ret) 1813 return ret; 1814 } 1815 1816 for (i = 0; i < chip->num_slots; i++) { 1817 slot = chip->slots[i]; 1818 if (!slot) 1819 continue; 1820 1821 ret = sdhci_resume_host(slot->host); 1822 if (ret) 1823 return ret; 1824 } 1825 1826 return 0; 1827 } 1828 #endif 1829 1830 #ifdef CONFIG_PM 1831 static int sdhci_pci_runtime_suspend(struct device *dev) 1832 { 1833 struct pci_dev *pdev = to_pci_dev(dev); 1834 struct sdhci_pci_chip *chip; 1835 struct sdhci_pci_slot *slot; 1836 struct sdhci_host *host; 1837 int i, ret; 1838 1839 chip = pci_get_drvdata(pdev); 1840 if (!chip) 1841 return 0; 1842 1843 for (i = 0; i < chip->num_slots; i++) { 1844 slot = chip->slots[i]; 1845 if (!slot) 1846 continue; 1847 1848 host = slot->host; 1849 1850 ret = sdhci_runtime_suspend_host(host); 1851 if (ret) 1852 goto err_pci_runtime_suspend; 1853 1854 if (chip->rpm_retune && 1855 host->tuning_mode != SDHCI_TUNING_MODE_3) 1856 mmc_retune_needed(host->mmc); 1857 } 1858 1859 if (chip->fixes && chip->fixes->suspend) { 1860 ret = chip->fixes->suspend(chip); 1861 if (ret) 1862 goto err_pci_runtime_suspend; 1863 } 1864 1865 return 0; 1866 1867 err_pci_runtime_suspend: 1868 while (--i >= 0) 1869 sdhci_runtime_resume_host(chip->slots[i]->host); 1870 return ret; 1871 } 1872 1873 static int sdhci_pci_runtime_resume(struct device *dev) 1874 { 1875 struct pci_dev *pdev = to_pci_dev(dev); 1876 struct sdhci_pci_chip *chip; 1877 struct sdhci_pci_slot *slot; 1878 int i, ret; 1879 1880 chip = pci_get_drvdata(pdev); 1881 if (!chip) 1882 return 0; 1883 1884 if (chip->fixes && chip->fixes->resume) { 1885 ret = chip->fixes->resume(chip); 1886 if (ret) 1887 return ret; 1888 } 1889 1890 for (i = 0; i < chip->num_slots; i++) { 1891 slot = chip->slots[i]; 1892 if (!slot) 1893 continue; 1894 1895 ret = sdhci_runtime_resume_host(slot->host); 1896 if (ret) 1897 return ret; 1898 } 1899 1900 return 0; 1901 } 1902 #endif 1903 1904 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1905 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1906 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1907 sdhci_pci_runtime_resume, NULL) 1908 }; 1909 1910 /*****************************************************************************\ 1911 * * 1912 * Device probing/removal * 1913 * * 1914 \*****************************************************************************/ 1915 1916 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1917 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1918 int slotno) 1919 { 1920 struct sdhci_pci_slot *slot; 1921 struct sdhci_host *host; 1922 int ret, bar = first_bar + slotno; 1923 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 1924 1925 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1926 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1927 return ERR_PTR(-ENODEV); 1928 } 1929 1930 if (pci_resource_len(pdev, bar) < 0x100) { 1931 dev_err(&pdev->dev, "Invalid iomem size. You may " 1932 "experience problems.\n"); 1933 } 1934 1935 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1936 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1937 return ERR_PTR(-ENODEV); 1938 } 1939 1940 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1941 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1942 return ERR_PTR(-ENODEV); 1943 } 1944 1945 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 1946 if (IS_ERR(host)) { 1947 dev_err(&pdev->dev, "cannot allocate host\n"); 1948 return ERR_CAST(host); 1949 } 1950 1951 slot = sdhci_priv(host); 1952 1953 slot->chip = chip; 1954 slot->host = host; 1955 slot->rst_n_gpio = -EINVAL; 1956 slot->cd_gpio = -EINVAL; 1957 slot->cd_idx = -1; 1958 1959 /* Retrieve platform data if there is any */ 1960 if (*sdhci_pci_get_data) 1961 slot->data = sdhci_pci_get_data(pdev, slotno); 1962 1963 if (slot->data) { 1964 if (slot->data->setup) { 1965 ret = slot->data->setup(slot->data); 1966 if (ret) { 1967 dev_err(&pdev->dev, "platform setup failed\n"); 1968 goto free; 1969 } 1970 } 1971 slot->rst_n_gpio = slot->data->rst_n_gpio; 1972 slot->cd_gpio = slot->data->cd_gpio; 1973 } 1974 1975 host->hw_name = "PCI"; 1976 host->ops = chip->fixes && chip->fixes->ops ? 1977 chip->fixes->ops : 1978 &sdhci_pci_ops; 1979 host->quirks = chip->quirks; 1980 host->quirks2 = chip->quirks2; 1981 1982 host->irq = pdev->irq; 1983 1984 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1985 if (ret) { 1986 dev_err(&pdev->dev, "cannot request region\n"); 1987 goto cleanup; 1988 } 1989 1990 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1991 1992 if (chip->fixes && chip->fixes->probe_slot) { 1993 ret = chip->fixes->probe_slot(slot); 1994 if (ret) 1995 goto cleanup; 1996 } 1997 1998 if (gpio_is_valid(slot->rst_n_gpio)) { 1999 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 2000 gpio_direction_output(slot->rst_n_gpio, 1); 2001 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 2002 slot->hw_reset = sdhci_pci_gpio_hw_reset; 2003 } else { 2004 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 2005 slot->rst_n_gpio = -EINVAL; 2006 } 2007 } 2008 2009 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; 2010 host->mmc->slotno = slotno; 2011 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 2012 2013 if (slot->cd_idx >= 0) { 2014 ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx, 2015 slot->cd_override_level, 0, NULL); 2016 if (ret == -EPROBE_DEFER) 2017 goto remove; 2018 2019 if (ret) { 2020 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 2021 slot->cd_idx = -1; 2022 } 2023 } 2024 2025 ret = sdhci_add_host(host); 2026 if (ret) 2027 goto remove; 2028 2029 sdhci_pci_add_own_cd(slot); 2030 2031 /* 2032 * Check if the chip needs a separate GPIO for card detect to wake up 2033 * from runtime suspend. If it is not there, don't allow runtime PM. 2034 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 2035 */ 2036 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 2037 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 2038 chip->allow_runtime_pm = false; 2039 2040 return slot; 2041 2042 remove: 2043 if (chip->fixes && chip->fixes->remove_slot) 2044 chip->fixes->remove_slot(slot, 0); 2045 2046 cleanup: 2047 if (slot->data && slot->data->cleanup) 2048 slot->data->cleanup(slot->data); 2049 2050 free: 2051 sdhci_free_host(host); 2052 2053 return ERR_PTR(ret); 2054 } 2055 2056 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 2057 { 2058 int dead; 2059 u32 scratch; 2060 2061 sdhci_pci_remove_own_cd(slot); 2062 2063 dead = 0; 2064 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 2065 if (scratch == (u32)-1) 2066 dead = 1; 2067 2068 sdhci_remove_host(slot->host, dead); 2069 2070 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 2071 slot->chip->fixes->remove_slot(slot, dead); 2072 2073 if (slot->data && slot->data->cleanup) 2074 slot->data->cleanup(slot->data); 2075 2076 sdhci_free_host(slot->host); 2077 } 2078 2079 static void sdhci_pci_runtime_pm_allow(struct device *dev) 2080 { 2081 pm_suspend_ignore_children(dev, 1); 2082 pm_runtime_set_autosuspend_delay(dev, 50); 2083 pm_runtime_use_autosuspend(dev); 2084 pm_runtime_allow(dev); 2085 /* Stay active until mmc core scans for a card */ 2086 pm_runtime_put_noidle(dev); 2087 } 2088 2089 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 2090 { 2091 pm_runtime_forbid(dev); 2092 pm_runtime_get_noresume(dev); 2093 } 2094 2095 static int sdhci_pci_probe(struct pci_dev *pdev, 2096 const struct pci_device_id *ent) 2097 { 2098 struct sdhci_pci_chip *chip; 2099 struct sdhci_pci_slot *slot; 2100 2101 u8 slots, first_bar; 2102 int ret, i; 2103 2104 BUG_ON(pdev == NULL); 2105 BUG_ON(ent == NULL); 2106 2107 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 2108 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 2109 2110 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 2111 if (ret) 2112 return ret; 2113 2114 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 2115 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 2116 if (slots == 0) 2117 return -ENODEV; 2118 2119 BUG_ON(slots > MAX_SLOTS); 2120 2121 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 2122 if (ret) 2123 return ret; 2124 2125 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 2126 2127 if (first_bar > 5) { 2128 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 2129 return -ENODEV; 2130 } 2131 2132 ret = pcim_enable_device(pdev); 2133 if (ret) 2134 return ret; 2135 2136 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 2137 if (!chip) 2138 return -ENOMEM; 2139 2140 chip->pdev = pdev; 2141 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 2142 if (chip->fixes) { 2143 chip->quirks = chip->fixes->quirks; 2144 chip->quirks2 = chip->fixes->quirks2; 2145 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 2146 } 2147 chip->num_slots = slots; 2148 chip->pm_retune = true; 2149 chip->rpm_retune = true; 2150 2151 pci_set_drvdata(pdev, chip); 2152 2153 if (chip->fixes && chip->fixes->probe) { 2154 ret = chip->fixes->probe(chip); 2155 if (ret) 2156 return ret; 2157 } 2158 2159 slots = chip->num_slots; /* Quirk may have changed this */ 2160 2161 for (i = 0; i < slots; i++) { 2162 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 2163 if (IS_ERR(slot)) { 2164 for (i--; i >= 0; i--) 2165 sdhci_pci_remove_slot(chip->slots[i]); 2166 return PTR_ERR(slot); 2167 } 2168 2169 chip->slots[i] = slot; 2170 } 2171 2172 if (chip->allow_runtime_pm) 2173 sdhci_pci_runtime_pm_allow(&pdev->dev); 2174 2175 return 0; 2176 } 2177 2178 static void sdhci_pci_remove(struct pci_dev *pdev) 2179 { 2180 int i; 2181 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 2182 2183 if (chip->allow_runtime_pm) 2184 sdhci_pci_runtime_pm_forbid(&pdev->dev); 2185 2186 for (i = 0; i < chip->num_slots; i++) 2187 sdhci_pci_remove_slot(chip->slots[i]); 2188 } 2189 2190 static struct pci_driver sdhci_driver = { 2191 .name = "sdhci-pci", 2192 .id_table = pci_ids, 2193 .probe = sdhci_pci_probe, 2194 .remove = sdhci_pci_remove, 2195 .driver = { 2196 .pm = &sdhci_pci_pm_ops 2197 }, 2198 }; 2199 2200 module_pci_driver(sdhci_driver); 2201 2202 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 2203 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 2204 MODULE_LICENSE("GPL"); 2205