1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 2 * 3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 * 10 * Thanks to the following companies for their support: 11 * 12 * - JMicron (hardware and technical support) 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/highmem.h> 17 #include <linux/module.h> 18 #include <linux/pci.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/slab.h> 21 #include <linux/device.h> 22 #include <linux/mmc/host.h> 23 #include <linux/mmc/mmc.h> 24 #include <linux/scatterlist.h> 25 #include <linux/io.h> 26 #include <linux/gpio.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/mmc/slot-gpio.h> 29 #include <linux/mmc/sdhci-pci-data.h> 30 31 #include "sdhci.h" 32 #include "sdhci-pci.h" 33 #include "sdhci-pci-o2micro.h" 34 35 /*****************************************************************************\ 36 * * 37 * Hardware specific quirk handling * 38 * * 39 \*****************************************************************************/ 40 41 static int ricoh_probe(struct sdhci_pci_chip *chip) 42 { 43 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 44 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 45 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 46 return 0; 47 } 48 49 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 50 { 51 slot->host->caps = 52 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 53 & SDHCI_TIMEOUT_CLK_MASK) | 54 55 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 56 & SDHCI_CLOCK_BASE_MASK) | 57 58 SDHCI_TIMEOUT_CLK_UNIT | 59 SDHCI_CAN_VDD_330 | 60 SDHCI_CAN_DO_HISPD | 61 SDHCI_CAN_DO_SDMA; 62 return 0; 63 } 64 65 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 66 { 67 /* Apply a delay to allow controller to settle */ 68 /* Otherwise it becomes confused if card state changed 69 during suspend */ 70 msleep(500); 71 return 0; 72 } 73 74 static const struct sdhci_pci_fixes sdhci_ricoh = { 75 .probe = ricoh_probe, 76 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 77 SDHCI_QUIRK_FORCE_DMA | 78 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 79 }; 80 81 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 82 .probe_slot = ricoh_mmc_probe_slot, 83 .resume = ricoh_mmc_resume, 84 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 85 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 86 SDHCI_QUIRK_NO_CARD_NO_RESET | 87 SDHCI_QUIRK_MISSING_CAPS 88 }; 89 90 static const struct sdhci_pci_fixes sdhci_ene_712 = { 91 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 92 SDHCI_QUIRK_BROKEN_DMA, 93 }; 94 95 static const struct sdhci_pci_fixes sdhci_ene_714 = { 96 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 97 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 98 SDHCI_QUIRK_BROKEN_DMA, 99 }; 100 101 static const struct sdhci_pci_fixes sdhci_cafe = { 102 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 103 SDHCI_QUIRK_NO_BUSY_IRQ | 104 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 105 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 106 }; 107 108 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 109 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 110 }; 111 112 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 113 { 114 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 115 return 0; 116 } 117 118 /* 119 * ADMA operation is disabled for Moorestown platform due to 120 * hardware bugs. 121 */ 122 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 123 { 124 /* 125 * slots number is fixed here for MRST as SDIO3/5 are never used and 126 * have hardware bugs. 127 */ 128 chip->num_slots = 1; 129 return 0; 130 } 131 132 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 133 { 134 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 135 return 0; 136 } 137 138 #ifdef CONFIG_PM 139 140 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 141 { 142 struct sdhci_pci_slot *slot = dev_id; 143 struct sdhci_host *host = slot->host; 144 145 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 146 return IRQ_HANDLED; 147 } 148 149 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 150 { 151 int err, irq, gpio = slot->cd_gpio; 152 153 slot->cd_gpio = -EINVAL; 154 slot->cd_irq = -EINVAL; 155 156 if (!gpio_is_valid(gpio)) 157 return; 158 159 err = gpio_request(gpio, "sd_cd"); 160 if (err < 0) 161 goto out; 162 163 err = gpio_direction_input(gpio); 164 if (err < 0) 165 goto out_free; 166 167 irq = gpio_to_irq(gpio); 168 if (irq < 0) 169 goto out_free; 170 171 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 172 IRQF_TRIGGER_FALLING, "sd_cd", slot); 173 if (err) 174 goto out_free; 175 176 slot->cd_gpio = gpio; 177 slot->cd_irq = irq; 178 179 return; 180 181 out_free: 182 gpio_free(gpio); 183 out: 184 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 185 } 186 187 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 188 { 189 if (slot->cd_irq >= 0) 190 free_irq(slot->cd_irq, slot); 191 if (gpio_is_valid(slot->cd_gpio)) 192 gpio_free(slot->cd_gpio); 193 } 194 195 #else 196 197 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 198 { 199 } 200 201 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 202 { 203 } 204 205 #endif 206 207 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 208 { 209 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 210 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC | 211 MMC_CAP2_HC_ERASE_SZ; 212 return 0; 213 } 214 215 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 216 { 217 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 218 return 0; 219 } 220 221 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 222 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 223 .probe_slot = mrst_hc_probe_slot, 224 }; 225 226 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 227 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 228 .probe = mrst_hc_probe, 229 }; 230 231 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 232 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 233 .allow_runtime_pm = true, 234 .own_cd_for_runtime_pm = true, 235 }; 236 237 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 238 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 239 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 240 .allow_runtime_pm = true, 241 .probe_slot = mfd_sdio_probe_slot, 242 }; 243 244 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 245 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 246 .allow_runtime_pm = true, 247 .probe_slot = mfd_emmc_probe_slot, 248 }; 249 250 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 251 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 252 .probe_slot = pch_hc_probe_slot, 253 }; 254 255 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 256 { 257 u8 reg; 258 259 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 260 reg |= 0x10; 261 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 262 /* For eMMC, minimum is 1us but give it 9us for good measure */ 263 udelay(9); 264 reg &= ~0x10; 265 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 266 /* For eMMC, minimum is 200us but give it 300us for good measure */ 267 usleep_range(300, 1000); 268 } 269 270 static int spt_select_drive_strength(struct sdhci_host *host, 271 struct mmc_card *card, 272 unsigned int max_dtr, 273 int host_drv, int card_drv, int *drv_type) 274 { 275 int drive_strength; 276 277 if (sdhci_pci_spt_drive_strength > 0) 278 drive_strength = sdhci_pci_spt_drive_strength & 0xf; 279 else 280 drive_strength = 0; /* Default 50-ohm */ 281 282 if ((mmc_driver_type_mask(drive_strength) & card_drv) == 0) 283 drive_strength = 0; /* Default 50-ohm */ 284 285 return drive_strength; 286 } 287 288 /* Try to read the drive strength from the card */ 289 static void spt_read_drive_strength(struct sdhci_host *host) 290 { 291 u32 val, i, t; 292 u16 m; 293 294 if (sdhci_pci_spt_drive_strength) 295 return; 296 297 sdhci_pci_spt_drive_strength = -1; 298 299 m = sdhci_readw(host, SDHCI_HOST_CONTROL2) & 0x7; 300 if (m != 3 && m != 5) 301 return; 302 val = sdhci_readl(host, SDHCI_PRESENT_STATE); 303 if (val & 0x3) 304 return; 305 sdhci_writel(host, 0x007f0023, SDHCI_INT_ENABLE); 306 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 307 sdhci_writew(host, 0x10, SDHCI_TRANSFER_MODE); 308 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 309 sdhci_writew(host, 512, SDHCI_BLOCK_SIZE); 310 sdhci_writew(host, 1, SDHCI_BLOCK_COUNT); 311 sdhci_writel(host, 0, SDHCI_ARGUMENT); 312 sdhci_writew(host, 0x83b, SDHCI_COMMAND); 313 for (i = 0; i < 1000; i++) { 314 val = sdhci_readl(host, SDHCI_INT_STATUS); 315 if (val & 0xffff8000) 316 return; 317 if (val & 0x20) 318 break; 319 udelay(1); 320 } 321 val = sdhci_readl(host, SDHCI_PRESENT_STATE); 322 if (!(val & 0x800)) 323 return; 324 for (i = 0; i < 47; i++) 325 val = sdhci_readl(host, SDHCI_BUFFER); 326 t = val & 0xf00; 327 if (t != 0x200 && t != 0x300) 328 return; 329 330 sdhci_pci_spt_drive_strength = 0x10 | ((val >> 12) & 0xf); 331 } 332 333 static int bxt_get_cd(struct mmc_host *mmc) 334 { 335 int gpio_cd = mmc_gpio_get_cd(mmc); 336 struct sdhci_host *host = mmc_priv(mmc); 337 unsigned long flags; 338 int ret = 0; 339 340 if (!gpio_cd) 341 return 0; 342 343 spin_lock_irqsave(&host->lock, flags); 344 345 if (host->flags & SDHCI_DEVICE_DEAD) 346 goto out; 347 348 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 349 out: 350 spin_unlock_irqrestore(&host->lock, flags); 351 352 return ret; 353 } 354 355 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 356 { 357 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 358 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 359 MMC_CAP_BUS_WIDTH_TEST | 360 MMC_CAP_WAIT_WHILE_BUSY; 361 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ; 362 slot->hw_reset = sdhci_pci_int_hw_reset; 363 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 364 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 365 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_SPT_EMMC) { 366 spt_read_drive_strength(slot->host); 367 slot->select_drive_strength = spt_select_drive_strength; 368 } 369 return 0; 370 } 371 372 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 373 { 374 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 375 MMC_CAP_BUS_WIDTH_TEST | 376 MMC_CAP_WAIT_WHILE_BUSY; 377 return 0; 378 } 379 380 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 381 { 382 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST | 383 MMC_CAP_WAIT_WHILE_BUSY; 384 slot->cd_con_id = NULL; 385 slot->cd_idx = 0; 386 slot->cd_override_level = true; 387 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 388 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 389 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD) 390 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 391 392 return 0; 393 } 394 395 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 396 .allow_runtime_pm = true, 397 .probe_slot = byt_emmc_probe_slot, 398 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 399 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 400 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 401 SDHCI_QUIRK2_STOP_WITH_TC, 402 }; 403 404 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 405 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 406 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 407 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 408 .allow_runtime_pm = true, 409 .probe_slot = byt_sdio_probe_slot, 410 }; 411 412 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 413 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 414 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 415 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 416 SDHCI_QUIRK2_STOP_WITH_TC, 417 .allow_runtime_pm = true, 418 .own_cd_for_runtime_pm = true, 419 .probe_slot = byt_sd_probe_slot, 420 }; 421 422 /* Define Host controllers for Intel Merrifield platform */ 423 #define INTEL_MRFL_EMMC_0 0 424 #define INTEL_MRFL_EMMC_1 1 425 426 static int intel_mrfl_mmc_probe_slot(struct sdhci_pci_slot *slot) 427 { 428 if ((PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_0) && 429 (PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_1)) 430 /* SD support is not ready yet */ 431 return -ENODEV; 432 433 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 434 MMC_CAP_1_8V_DDR; 435 436 return 0; 437 } 438 439 static const struct sdhci_pci_fixes sdhci_intel_mrfl_mmc = { 440 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 441 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 442 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 443 .allow_runtime_pm = true, 444 .probe_slot = intel_mrfl_mmc_probe_slot, 445 }; 446 447 /* O2Micro extra registers */ 448 #define O2_SD_LOCK_WP 0xD3 449 #define O2_SD_MULTI_VCC3V 0xEE 450 #define O2_SD_CLKREQ 0xEC 451 #define O2_SD_CAPS 0xE0 452 #define O2_SD_ADMA1 0xE2 453 #define O2_SD_ADMA2 0xE7 454 #define O2_SD_INF_MOD 0xF1 455 456 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 457 { 458 u8 scratch; 459 int ret; 460 461 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 462 if (ret) 463 return ret; 464 465 /* 466 * Turn PMOS on [bit 0], set over current detection to 2.4 V 467 * [bit 1:2] and enable over current debouncing [bit 6]. 468 */ 469 if (on) 470 scratch |= 0x47; 471 else 472 scratch &= ~0x47; 473 474 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 475 } 476 477 static int jmicron_probe(struct sdhci_pci_chip *chip) 478 { 479 int ret; 480 u16 mmcdev = 0; 481 482 if (chip->pdev->revision == 0) { 483 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 484 SDHCI_QUIRK_32BIT_DMA_SIZE | 485 SDHCI_QUIRK_32BIT_ADMA_SIZE | 486 SDHCI_QUIRK_RESET_AFTER_REQUEST | 487 SDHCI_QUIRK_BROKEN_SMALL_PIO; 488 } 489 490 /* 491 * JMicron chips can have two interfaces to the same hardware 492 * in order to work around limitations in Microsoft's driver. 493 * We need to make sure we only bind to one of them. 494 * 495 * This code assumes two things: 496 * 497 * 1. The PCI code adds subfunctions in order. 498 * 499 * 2. The MMC interface has a lower subfunction number 500 * than the SD interface. 501 */ 502 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 503 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 504 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 505 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 506 507 if (mmcdev) { 508 struct pci_dev *sd_dev; 509 510 sd_dev = NULL; 511 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 512 mmcdev, sd_dev)) != NULL) { 513 if ((PCI_SLOT(chip->pdev->devfn) == 514 PCI_SLOT(sd_dev->devfn)) && 515 (chip->pdev->bus == sd_dev->bus)) 516 break; 517 } 518 519 if (sd_dev) { 520 pci_dev_put(sd_dev); 521 dev_info(&chip->pdev->dev, "Refusing to bind to " 522 "secondary interface.\n"); 523 return -ENODEV; 524 } 525 } 526 527 /* 528 * JMicron chips need a bit of a nudge to enable the power 529 * output pins. 530 */ 531 ret = jmicron_pmos(chip, 1); 532 if (ret) { 533 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 534 return ret; 535 } 536 537 /* quirk for unsable RO-detection on JM388 chips */ 538 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 539 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 540 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 541 542 return 0; 543 } 544 545 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 546 { 547 u8 scratch; 548 549 scratch = readb(host->ioaddr + 0xC0); 550 551 if (on) 552 scratch |= 0x01; 553 else 554 scratch &= ~0x01; 555 556 writeb(scratch, host->ioaddr + 0xC0); 557 } 558 559 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 560 { 561 if (slot->chip->pdev->revision == 0) { 562 u16 version; 563 564 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 565 version = (version & SDHCI_VENDOR_VER_MASK) >> 566 SDHCI_VENDOR_VER_SHIFT; 567 568 /* 569 * Older versions of the chip have lots of nasty glitches 570 * in the ADMA engine. It's best just to avoid it 571 * completely. 572 */ 573 if (version < 0xAC) 574 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 575 } 576 577 /* JM388 MMC doesn't support 1.8V while SD supports it */ 578 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 579 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 580 MMC_VDD_29_30 | MMC_VDD_30_31 | 581 MMC_VDD_165_195; /* allow 1.8V */ 582 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 583 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 584 } 585 586 /* 587 * The secondary interface requires a bit set to get the 588 * interrupts. 589 */ 590 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 591 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 592 jmicron_enable_mmc(slot->host, 1); 593 594 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 595 596 return 0; 597 } 598 599 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 600 { 601 if (dead) 602 return; 603 604 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 605 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 606 jmicron_enable_mmc(slot->host, 0); 607 } 608 609 static int jmicron_suspend(struct sdhci_pci_chip *chip) 610 { 611 int i; 612 613 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 614 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 615 for (i = 0; i < chip->num_slots; i++) 616 jmicron_enable_mmc(chip->slots[i]->host, 0); 617 } 618 619 return 0; 620 } 621 622 static int jmicron_resume(struct sdhci_pci_chip *chip) 623 { 624 int ret, i; 625 626 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 627 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 628 for (i = 0; i < chip->num_slots; i++) 629 jmicron_enable_mmc(chip->slots[i]->host, 1); 630 } 631 632 ret = jmicron_pmos(chip, 1); 633 if (ret) { 634 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 635 return ret; 636 } 637 638 return 0; 639 } 640 641 static const struct sdhci_pci_fixes sdhci_o2 = { 642 .probe = sdhci_pci_o2_probe, 643 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 644 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 645 .probe_slot = sdhci_pci_o2_probe_slot, 646 .resume = sdhci_pci_o2_resume, 647 }; 648 649 static const struct sdhci_pci_fixes sdhci_jmicron = { 650 .probe = jmicron_probe, 651 652 .probe_slot = jmicron_probe_slot, 653 .remove_slot = jmicron_remove_slot, 654 655 .suspend = jmicron_suspend, 656 .resume = jmicron_resume, 657 }; 658 659 /* SysKonnect CardBus2SDIO extra registers */ 660 #define SYSKT_CTRL 0x200 661 #define SYSKT_RDFIFO_STAT 0x204 662 #define SYSKT_WRFIFO_STAT 0x208 663 #define SYSKT_POWER_DATA 0x20c 664 #define SYSKT_POWER_330 0xef 665 #define SYSKT_POWER_300 0xf8 666 #define SYSKT_POWER_184 0xcc 667 #define SYSKT_POWER_CMD 0x20d 668 #define SYSKT_POWER_START (1 << 7) 669 #define SYSKT_POWER_STATUS 0x20e 670 #define SYSKT_POWER_STATUS_OK (1 << 0) 671 #define SYSKT_BOARD_REV 0x210 672 #define SYSKT_CHIP_REV 0x211 673 #define SYSKT_CONF_DATA 0x212 674 #define SYSKT_CONF_DATA_1V8 (1 << 2) 675 #define SYSKT_CONF_DATA_2V5 (1 << 1) 676 #define SYSKT_CONF_DATA_3V3 (1 << 0) 677 678 static int syskt_probe(struct sdhci_pci_chip *chip) 679 { 680 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 681 chip->pdev->class &= ~0x0000FF; 682 chip->pdev->class |= PCI_SDHCI_IFDMA; 683 } 684 return 0; 685 } 686 687 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 688 { 689 int tm, ps; 690 691 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 692 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 693 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 694 "board rev %d.%d, chip rev %d.%d\n", 695 board_rev >> 4, board_rev & 0xf, 696 chip_rev >> 4, chip_rev & 0xf); 697 if (chip_rev >= 0x20) 698 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 699 700 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 701 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 702 udelay(50); 703 tm = 10; /* Wait max 1 ms */ 704 do { 705 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 706 if (ps & SYSKT_POWER_STATUS_OK) 707 break; 708 udelay(100); 709 } while (--tm); 710 if (!tm) { 711 dev_err(&slot->chip->pdev->dev, 712 "power regulator never stabilized"); 713 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 714 return -ENODEV; 715 } 716 717 return 0; 718 } 719 720 static const struct sdhci_pci_fixes sdhci_syskt = { 721 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 722 .probe = syskt_probe, 723 .probe_slot = syskt_probe_slot, 724 }; 725 726 static int via_probe(struct sdhci_pci_chip *chip) 727 { 728 if (chip->pdev->revision == 0x10) 729 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 730 731 return 0; 732 } 733 734 static const struct sdhci_pci_fixes sdhci_via = { 735 .probe = via_probe, 736 }; 737 738 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 739 { 740 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 741 return 0; 742 } 743 744 static const struct sdhci_pci_fixes sdhci_rtsx = { 745 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 746 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 747 SDHCI_QUIRK2_BROKEN_DDR50, 748 .probe_slot = rtsx_probe_slot, 749 }; 750 751 /*AMD chipset generation*/ 752 enum amd_chipset_gen { 753 AMD_CHIPSET_BEFORE_ML, 754 AMD_CHIPSET_CZ, 755 AMD_CHIPSET_NL, 756 AMD_CHIPSET_UNKNOWN, 757 }; 758 759 static int amd_probe(struct sdhci_pci_chip *chip) 760 { 761 struct pci_dev *smbus_dev; 762 enum amd_chipset_gen gen; 763 764 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 765 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 766 if (smbus_dev) { 767 gen = AMD_CHIPSET_BEFORE_ML; 768 } else { 769 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 770 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 771 if (smbus_dev) { 772 if (smbus_dev->revision < 0x51) 773 gen = AMD_CHIPSET_CZ; 774 else 775 gen = AMD_CHIPSET_NL; 776 } else { 777 gen = AMD_CHIPSET_UNKNOWN; 778 } 779 } 780 781 if ((gen == AMD_CHIPSET_BEFORE_ML) || (gen == AMD_CHIPSET_CZ)) { 782 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 783 chip->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 784 } 785 786 return 0; 787 } 788 789 static const struct sdhci_pci_fixes sdhci_amd = { 790 .probe = amd_probe, 791 }; 792 793 static const struct pci_device_id pci_ids[] = { 794 { 795 .vendor = PCI_VENDOR_ID_RICOH, 796 .device = PCI_DEVICE_ID_RICOH_R5C822, 797 .subvendor = PCI_ANY_ID, 798 .subdevice = PCI_ANY_ID, 799 .driver_data = (kernel_ulong_t)&sdhci_ricoh, 800 }, 801 802 { 803 .vendor = PCI_VENDOR_ID_RICOH, 804 .device = 0x843, 805 .subvendor = PCI_ANY_ID, 806 .subdevice = PCI_ANY_ID, 807 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 808 }, 809 810 { 811 .vendor = PCI_VENDOR_ID_RICOH, 812 .device = 0xe822, 813 .subvendor = PCI_ANY_ID, 814 .subdevice = PCI_ANY_ID, 815 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 816 }, 817 818 { 819 .vendor = PCI_VENDOR_ID_RICOH, 820 .device = 0xe823, 821 .subvendor = PCI_ANY_ID, 822 .subdevice = PCI_ANY_ID, 823 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 824 }, 825 826 { 827 .vendor = PCI_VENDOR_ID_ENE, 828 .device = PCI_DEVICE_ID_ENE_CB712_SD, 829 .subvendor = PCI_ANY_ID, 830 .subdevice = PCI_ANY_ID, 831 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 832 }, 833 834 { 835 .vendor = PCI_VENDOR_ID_ENE, 836 .device = PCI_DEVICE_ID_ENE_CB712_SD_2, 837 .subvendor = PCI_ANY_ID, 838 .subdevice = PCI_ANY_ID, 839 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 840 }, 841 842 { 843 .vendor = PCI_VENDOR_ID_ENE, 844 .device = PCI_DEVICE_ID_ENE_CB714_SD, 845 .subvendor = PCI_ANY_ID, 846 .subdevice = PCI_ANY_ID, 847 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 848 }, 849 850 { 851 .vendor = PCI_VENDOR_ID_ENE, 852 .device = PCI_DEVICE_ID_ENE_CB714_SD_2, 853 .subvendor = PCI_ANY_ID, 854 .subdevice = PCI_ANY_ID, 855 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 856 }, 857 858 { 859 .vendor = PCI_VENDOR_ID_MARVELL, 860 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD, 861 .subvendor = PCI_ANY_ID, 862 .subdevice = PCI_ANY_ID, 863 .driver_data = (kernel_ulong_t)&sdhci_cafe, 864 }, 865 866 { 867 .vendor = PCI_VENDOR_ID_JMICRON, 868 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD, 869 .subvendor = PCI_ANY_ID, 870 .subdevice = PCI_ANY_ID, 871 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 872 }, 873 874 { 875 .vendor = PCI_VENDOR_ID_JMICRON, 876 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC, 877 .subvendor = PCI_ANY_ID, 878 .subdevice = PCI_ANY_ID, 879 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 880 }, 881 882 { 883 .vendor = PCI_VENDOR_ID_JMICRON, 884 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD, 885 .subvendor = PCI_ANY_ID, 886 .subdevice = PCI_ANY_ID, 887 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 888 }, 889 890 { 891 .vendor = PCI_VENDOR_ID_JMICRON, 892 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD, 893 .subvendor = PCI_ANY_ID, 894 .subdevice = PCI_ANY_ID, 895 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 896 }, 897 898 { 899 .vendor = PCI_VENDOR_ID_SYSKONNECT, 900 .device = 0x8000, 901 .subvendor = PCI_ANY_ID, 902 .subdevice = PCI_ANY_ID, 903 .driver_data = (kernel_ulong_t)&sdhci_syskt, 904 }, 905 906 { 907 .vendor = PCI_VENDOR_ID_VIA, 908 .device = 0x95d0, 909 .subvendor = PCI_ANY_ID, 910 .subdevice = PCI_ANY_ID, 911 .driver_data = (kernel_ulong_t)&sdhci_via, 912 }, 913 914 { 915 .vendor = PCI_VENDOR_ID_REALTEK, 916 .device = 0x5250, 917 .subvendor = PCI_ANY_ID, 918 .subdevice = PCI_ANY_ID, 919 .driver_data = (kernel_ulong_t)&sdhci_rtsx, 920 }, 921 922 { 923 .vendor = PCI_VENDOR_ID_INTEL, 924 .device = PCI_DEVICE_ID_INTEL_QRK_SD, 925 .subvendor = PCI_ANY_ID, 926 .subdevice = PCI_ANY_ID, 927 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk, 928 }, 929 930 { 931 .vendor = PCI_VENDOR_ID_INTEL, 932 .device = PCI_DEVICE_ID_INTEL_MRST_SD0, 933 .subvendor = PCI_ANY_ID, 934 .subdevice = PCI_ANY_ID, 935 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0, 936 }, 937 938 { 939 .vendor = PCI_VENDOR_ID_INTEL, 940 .device = PCI_DEVICE_ID_INTEL_MRST_SD1, 941 .subvendor = PCI_ANY_ID, 942 .subdevice = PCI_ANY_ID, 943 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 944 }, 945 946 { 947 .vendor = PCI_VENDOR_ID_INTEL, 948 .device = PCI_DEVICE_ID_INTEL_MRST_SD2, 949 .subvendor = PCI_ANY_ID, 950 .subdevice = PCI_ANY_ID, 951 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 952 }, 953 954 { 955 .vendor = PCI_VENDOR_ID_INTEL, 956 .device = PCI_DEVICE_ID_INTEL_MFD_SD, 957 .subvendor = PCI_ANY_ID, 958 .subdevice = PCI_ANY_ID, 959 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 960 }, 961 962 { 963 .vendor = PCI_VENDOR_ID_INTEL, 964 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1, 965 .subvendor = PCI_ANY_ID, 966 .subdevice = PCI_ANY_ID, 967 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 968 }, 969 970 { 971 .vendor = PCI_VENDOR_ID_INTEL, 972 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2, 973 .subvendor = PCI_ANY_ID, 974 .subdevice = PCI_ANY_ID, 975 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 976 }, 977 978 { 979 .vendor = PCI_VENDOR_ID_INTEL, 980 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0, 981 .subvendor = PCI_ANY_ID, 982 .subdevice = PCI_ANY_ID, 983 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 984 }, 985 986 { 987 .vendor = PCI_VENDOR_ID_INTEL, 988 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1, 989 .subvendor = PCI_ANY_ID, 990 .subdevice = PCI_ANY_ID, 991 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 992 }, 993 994 { 995 .vendor = PCI_VENDOR_ID_INTEL, 996 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0, 997 .subvendor = PCI_ANY_ID, 998 .subdevice = PCI_ANY_ID, 999 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1000 }, 1001 1002 { 1003 .vendor = PCI_VENDOR_ID_INTEL, 1004 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1, 1005 .subvendor = PCI_ANY_ID, 1006 .subdevice = PCI_ANY_ID, 1007 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1008 }, 1009 1010 { 1011 .vendor = PCI_VENDOR_ID_INTEL, 1012 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC, 1013 .subvendor = PCI_ANY_ID, 1014 .subdevice = PCI_ANY_ID, 1015 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1016 }, 1017 1018 { 1019 .vendor = PCI_VENDOR_ID_INTEL, 1020 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, 1021 .subvendor = PCI_ANY_ID, 1022 .subdevice = PCI_ANY_ID, 1023 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1024 }, 1025 1026 { 1027 .vendor = PCI_VENDOR_ID_INTEL, 1028 .device = PCI_DEVICE_ID_INTEL_BYT_SD, 1029 .subvendor = PCI_ANY_ID, 1030 .subdevice = PCI_ANY_ID, 1031 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1032 }, 1033 1034 { 1035 .vendor = PCI_VENDOR_ID_INTEL, 1036 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2, 1037 .subvendor = PCI_ANY_ID, 1038 .subdevice = PCI_ANY_ID, 1039 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1040 }, 1041 1042 { 1043 .vendor = PCI_VENDOR_ID_INTEL, 1044 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC, 1045 .subvendor = PCI_ANY_ID, 1046 .subdevice = PCI_ANY_ID, 1047 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1048 }, 1049 1050 { 1051 .vendor = PCI_VENDOR_ID_INTEL, 1052 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO, 1053 .subvendor = PCI_ANY_ID, 1054 .subdevice = PCI_ANY_ID, 1055 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1056 }, 1057 1058 { 1059 .vendor = PCI_VENDOR_ID_INTEL, 1060 .device = PCI_DEVICE_ID_INTEL_BSW_SD, 1061 .subvendor = PCI_ANY_ID, 1062 .subdevice = PCI_ANY_ID, 1063 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1064 }, 1065 1066 { 1067 .vendor = PCI_VENDOR_ID_INTEL, 1068 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0, 1069 .subvendor = PCI_ANY_ID, 1070 .subdevice = PCI_ANY_ID, 1071 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1072 }, 1073 1074 { 1075 .vendor = PCI_VENDOR_ID_INTEL, 1076 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1, 1077 .subvendor = PCI_ANY_ID, 1078 .subdevice = PCI_ANY_ID, 1079 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1080 }, 1081 1082 { 1083 .vendor = PCI_VENDOR_ID_INTEL, 1084 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2, 1085 .subvendor = PCI_ANY_ID, 1086 .subdevice = PCI_ANY_ID, 1087 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1088 }, 1089 1090 { 1091 .vendor = PCI_VENDOR_ID_INTEL, 1092 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0, 1093 .subvendor = PCI_ANY_ID, 1094 .subdevice = PCI_ANY_ID, 1095 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1096 }, 1097 1098 { 1099 .vendor = PCI_VENDOR_ID_INTEL, 1100 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1, 1101 .subvendor = PCI_ANY_ID, 1102 .subdevice = PCI_ANY_ID, 1103 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1104 }, 1105 1106 { 1107 .vendor = PCI_VENDOR_ID_INTEL, 1108 .device = PCI_DEVICE_ID_INTEL_MRFL_MMC, 1109 .subvendor = PCI_ANY_ID, 1110 .subdevice = PCI_ANY_ID, 1111 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfl_mmc, 1112 }, 1113 1114 { 1115 .vendor = PCI_VENDOR_ID_INTEL, 1116 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC, 1117 .subvendor = PCI_ANY_ID, 1118 .subdevice = PCI_ANY_ID, 1119 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1120 }, 1121 1122 { 1123 .vendor = PCI_VENDOR_ID_INTEL, 1124 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO, 1125 .subvendor = PCI_ANY_ID, 1126 .subdevice = PCI_ANY_ID, 1127 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1128 }, 1129 1130 { 1131 .vendor = PCI_VENDOR_ID_INTEL, 1132 .device = PCI_DEVICE_ID_INTEL_SPT_SD, 1133 .subvendor = PCI_ANY_ID, 1134 .subdevice = PCI_ANY_ID, 1135 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1136 }, 1137 1138 { 1139 .vendor = PCI_VENDOR_ID_INTEL, 1140 .device = PCI_DEVICE_ID_INTEL_DNV_EMMC, 1141 .subvendor = PCI_ANY_ID, 1142 .subdevice = PCI_ANY_ID, 1143 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1144 }, 1145 1146 { 1147 .vendor = PCI_VENDOR_ID_INTEL, 1148 .device = PCI_DEVICE_ID_INTEL_BXT_EMMC, 1149 .subvendor = PCI_ANY_ID, 1150 .subdevice = PCI_ANY_ID, 1151 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1152 }, 1153 1154 { 1155 .vendor = PCI_VENDOR_ID_INTEL, 1156 .device = PCI_DEVICE_ID_INTEL_BXT_SDIO, 1157 .subvendor = PCI_ANY_ID, 1158 .subdevice = PCI_ANY_ID, 1159 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1160 }, 1161 1162 { 1163 .vendor = PCI_VENDOR_ID_INTEL, 1164 .device = PCI_DEVICE_ID_INTEL_BXT_SD, 1165 .subvendor = PCI_ANY_ID, 1166 .subdevice = PCI_ANY_ID, 1167 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1168 }, 1169 1170 { 1171 .vendor = PCI_VENDOR_ID_INTEL, 1172 .device = PCI_DEVICE_ID_INTEL_BXTM_EMMC, 1173 .subvendor = PCI_ANY_ID, 1174 .subdevice = PCI_ANY_ID, 1175 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1176 }, 1177 1178 { 1179 .vendor = PCI_VENDOR_ID_INTEL, 1180 .device = PCI_DEVICE_ID_INTEL_BXTM_SDIO, 1181 .subvendor = PCI_ANY_ID, 1182 .subdevice = PCI_ANY_ID, 1183 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1184 }, 1185 1186 { 1187 .vendor = PCI_VENDOR_ID_INTEL, 1188 .device = PCI_DEVICE_ID_INTEL_BXTM_SD, 1189 .subvendor = PCI_ANY_ID, 1190 .subdevice = PCI_ANY_ID, 1191 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1192 }, 1193 1194 { 1195 .vendor = PCI_VENDOR_ID_INTEL, 1196 .device = PCI_DEVICE_ID_INTEL_APL_EMMC, 1197 .subvendor = PCI_ANY_ID, 1198 .subdevice = PCI_ANY_ID, 1199 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1200 }, 1201 1202 { 1203 .vendor = PCI_VENDOR_ID_INTEL, 1204 .device = PCI_DEVICE_ID_INTEL_APL_SDIO, 1205 .subvendor = PCI_ANY_ID, 1206 .subdevice = PCI_ANY_ID, 1207 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1208 }, 1209 1210 { 1211 .vendor = PCI_VENDOR_ID_INTEL, 1212 .device = PCI_DEVICE_ID_INTEL_APL_SD, 1213 .subvendor = PCI_ANY_ID, 1214 .subdevice = PCI_ANY_ID, 1215 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1216 }, 1217 1218 { 1219 .vendor = PCI_VENDOR_ID_O2, 1220 .device = PCI_DEVICE_ID_O2_8120, 1221 .subvendor = PCI_ANY_ID, 1222 .subdevice = PCI_ANY_ID, 1223 .driver_data = (kernel_ulong_t)&sdhci_o2, 1224 }, 1225 1226 { 1227 .vendor = PCI_VENDOR_ID_O2, 1228 .device = PCI_DEVICE_ID_O2_8220, 1229 .subvendor = PCI_ANY_ID, 1230 .subdevice = PCI_ANY_ID, 1231 .driver_data = (kernel_ulong_t)&sdhci_o2, 1232 }, 1233 1234 { 1235 .vendor = PCI_VENDOR_ID_O2, 1236 .device = PCI_DEVICE_ID_O2_8221, 1237 .subvendor = PCI_ANY_ID, 1238 .subdevice = PCI_ANY_ID, 1239 .driver_data = (kernel_ulong_t)&sdhci_o2, 1240 }, 1241 1242 { 1243 .vendor = PCI_VENDOR_ID_O2, 1244 .device = PCI_DEVICE_ID_O2_8320, 1245 .subvendor = PCI_ANY_ID, 1246 .subdevice = PCI_ANY_ID, 1247 .driver_data = (kernel_ulong_t)&sdhci_o2, 1248 }, 1249 1250 { 1251 .vendor = PCI_VENDOR_ID_O2, 1252 .device = PCI_DEVICE_ID_O2_8321, 1253 .subvendor = PCI_ANY_ID, 1254 .subdevice = PCI_ANY_ID, 1255 .driver_data = (kernel_ulong_t)&sdhci_o2, 1256 }, 1257 1258 { 1259 .vendor = PCI_VENDOR_ID_O2, 1260 .device = PCI_DEVICE_ID_O2_FUJIN2, 1261 .subvendor = PCI_ANY_ID, 1262 .subdevice = PCI_ANY_ID, 1263 .driver_data = (kernel_ulong_t)&sdhci_o2, 1264 }, 1265 1266 { 1267 .vendor = PCI_VENDOR_ID_O2, 1268 .device = PCI_DEVICE_ID_O2_SDS0, 1269 .subvendor = PCI_ANY_ID, 1270 .subdevice = PCI_ANY_ID, 1271 .driver_data = (kernel_ulong_t)&sdhci_o2, 1272 }, 1273 1274 { 1275 .vendor = PCI_VENDOR_ID_O2, 1276 .device = PCI_DEVICE_ID_O2_SDS1, 1277 .subvendor = PCI_ANY_ID, 1278 .subdevice = PCI_ANY_ID, 1279 .driver_data = (kernel_ulong_t)&sdhci_o2, 1280 }, 1281 1282 { 1283 .vendor = PCI_VENDOR_ID_O2, 1284 .device = PCI_DEVICE_ID_O2_SEABIRD0, 1285 .subvendor = PCI_ANY_ID, 1286 .subdevice = PCI_ANY_ID, 1287 .driver_data = (kernel_ulong_t)&sdhci_o2, 1288 }, 1289 1290 { 1291 .vendor = PCI_VENDOR_ID_O2, 1292 .device = PCI_DEVICE_ID_O2_SEABIRD1, 1293 .subvendor = PCI_ANY_ID, 1294 .subdevice = PCI_ANY_ID, 1295 .driver_data = (kernel_ulong_t)&sdhci_o2, 1296 }, 1297 { 1298 .vendor = PCI_VENDOR_ID_AMD, 1299 .device = PCI_ANY_ID, 1300 .class = PCI_CLASS_SYSTEM_SDHCI << 8, 1301 .class_mask = 0xFFFF00, 1302 .subvendor = PCI_ANY_ID, 1303 .subdevice = PCI_ANY_ID, 1304 .driver_data = (kernel_ulong_t)&sdhci_amd, 1305 }, 1306 { /* Generic SD host controller */ 1307 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) 1308 }, 1309 1310 { /* end: all zeroes */ }, 1311 }; 1312 1313 MODULE_DEVICE_TABLE(pci, pci_ids); 1314 1315 /*****************************************************************************\ 1316 * * 1317 * SDHCI core callbacks * 1318 * * 1319 \*****************************************************************************/ 1320 1321 static int sdhci_pci_enable_dma(struct sdhci_host *host) 1322 { 1323 struct sdhci_pci_slot *slot; 1324 struct pci_dev *pdev; 1325 1326 slot = sdhci_priv(host); 1327 pdev = slot->chip->pdev; 1328 1329 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1330 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1331 (host->flags & SDHCI_USE_SDMA)) { 1332 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1333 "doesn't fully claim to support it.\n"); 1334 } 1335 1336 pci_set_master(pdev); 1337 1338 return 0; 1339 } 1340 1341 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width) 1342 { 1343 u8 ctrl; 1344 1345 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1346 1347 switch (width) { 1348 case MMC_BUS_WIDTH_8: 1349 ctrl |= SDHCI_CTRL_8BITBUS; 1350 ctrl &= ~SDHCI_CTRL_4BITBUS; 1351 break; 1352 case MMC_BUS_WIDTH_4: 1353 ctrl |= SDHCI_CTRL_4BITBUS; 1354 ctrl &= ~SDHCI_CTRL_8BITBUS; 1355 break; 1356 default: 1357 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS); 1358 break; 1359 } 1360 1361 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1362 } 1363 1364 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1365 { 1366 struct sdhci_pci_slot *slot = sdhci_priv(host); 1367 int rst_n_gpio = slot->rst_n_gpio; 1368 1369 if (!gpio_is_valid(rst_n_gpio)) 1370 return; 1371 gpio_set_value_cansleep(rst_n_gpio, 0); 1372 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1373 udelay(10); 1374 gpio_set_value_cansleep(rst_n_gpio, 1); 1375 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1376 usleep_range(300, 1000); 1377 } 1378 1379 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1380 { 1381 struct sdhci_pci_slot *slot = sdhci_priv(host); 1382 1383 if (slot->hw_reset) 1384 slot->hw_reset(host); 1385 } 1386 1387 static int sdhci_pci_select_drive_strength(struct sdhci_host *host, 1388 struct mmc_card *card, 1389 unsigned int max_dtr, int host_drv, 1390 int card_drv, int *drv_type) 1391 { 1392 struct sdhci_pci_slot *slot = sdhci_priv(host); 1393 1394 if (!slot->select_drive_strength) 1395 return 0; 1396 1397 return slot->select_drive_strength(host, card, max_dtr, host_drv, 1398 card_drv, drv_type); 1399 } 1400 1401 static const struct sdhci_ops sdhci_pci_ops = { 1402 .set_clock = sdhci_set_clock, 1403 .enable_dma = sdhci_pci_enable_dma, 1404 .set_bus_width = sdhci_pci_set_bus_width, 1405 .reset = sdhci_reset, 1406 .set_uhs_signaling = sdhci_set_uhs_signaling, 1407 .hw_reset = sdhci_pci_hw_reset, 1408 .select_drive_strength = sdhci_pci_select_drive_strength, 1409 }; 1410 1411 /*****************************************************************************\ 1412 * * 1413 * Suspend/resume * 1414 * * 1415 \*****************************************************************************/ 1416 1417 #ifdef CONFIG_PM 1418 1419 static int sdhci_pci_suspend(struct device *dev) 1420 { 1421 struct pci_dev *pdev = to_pci_dev(dev); 1422 struct sdhci_pci_chip *chip; 1423 struct sdhci_pci_slot *slot; 1424 mmc_pm_flag_t slot_pm_flags; 1425 mmc_pm_flag_t pm_flags = 0; 1426 int i, ret; 1427 1428 chip = pci_get_drvdata(pdev); 1429 if (!chip) 1430 return 0; 1431 1432 for (i = 0; i < chip->num_slots; i++) { 1433 slot = chip->slots[i]; 1434 if (!slot) 1435 continue; 1436 1437 ret = sdhci_suspend_host(slot->host); 1438 1439 if (ret) 1440 goto err_pci_suspend; 1441 1442 slot_pm_flags = slot->host->mmc->pm_flags; 1443 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1444 sdhci_enable_irq_wakeups(slot->host); 1445 1446 pm_flags |= slot_pm_flags; 1447 } 1448 1449 if (chip->fixes && chip->fixes->suspend) { 1450 ret = chip->fixes->suspend(chip); 1451 if (ret) 1452 goto err_pci_suspend; 1453 } 1454 1455 if (pm_flags & MMC_PM_KEEP_POWER) { 1456 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1457 device_init_wakeup(dev, true); 1458 else 1459 device_init_wakeup(dev, false); 1460 } else 1461 device_init_wakeup(dev, false); 1462 1463 return 0; 1464 1465 err_pci_suspend: 1466 while (--i >= 0) 1467 sdhci_resume_host(chip->slots[i]->host); 1468 return ret; 1469 } 1470 1471 static int sdhci_pci_resume(struct device *dev) 1472 { 1473 struct pci_dev *pdev = to_pci_dev(dev); 1474 struct sdhci_pci_chip *chip; 1475 struct sdhci_pci_slot *slot; 1476 int i, ret; 1477 1478 chip = pci_get_drvdata(pdev); 1479 if (!chip) 1480 return 0; 1481 1482 if (chip->fixes && chip->fixes->resume) { 1483 ret = chip->fixes->resume(chip); 1484 if (ret) 1485 return ret; 1486 } 1487 1488 for (i = 0; i < chip->num_slots; i++) { 1489 slot = chip->slots[i]; 1490 if (!slot) 1491 continue; 1492 1493 ret = sdhci_resume_host(slot->host); 1494 if (ret) 1495 return ret; 1496 } 1497 1498 return 0; 1499 } 1500 1501 static int sdhci_pci_runtime_suspend(struct device *dev) 1502 { 1503 struct pci_dev *pdev = to_pci_dev(dev); 1504 struct sdhci_pci_chip *chip; 1505 struct sdhci_pci_slot *slot; 1506 int i, ret; 1507 1508 chip = pci_get_drvdata(pdev); 1509 if (!chip) 1510 return 0; 1511 1512 for (i = 0; i < chip->num_slots; i++) { 1513 slot = chip->slots[i]; 1514 if (!slot) 1515 continue; 1516 1517 ret = sdhci_runtime_suspend_host(slot->host); 1518 1519 if (ret) 1520 goto err_pci_runtime_suspend; 1521 } 1522 1523 if (chip->fixes && chip->fixes->suspend) { 1524 ret = chip->fixes->suspend(chip); 1525 if (ret) 1526 goto err_pci_runtime_suspend; 1527 } 1528 1529 return 0; 1530 1531 err_pci_runtime_suspend: 1532 while (--i >= 0) 1533 sdhci_runtime_resume_host(chip->slots[i]->host); 1534 return ret; 1535 } 1536 1537 static int sdhci_pci_runtime_resume(struct device *dev) 1538 { 1539 struct pci_dev *pdev = to_pci_dev(dev); 1540 struct sdhci_pci_chip *chip; 1541 struct sdhci_pci_slot *slot; 1542 int i, ret; 1543 1544 chip = pci_get_drvdata(pdev); 1545 if (!chip) 1546 return 0; 1547 1548 if (chip->fixes && chip->fixes->resume) { 1549 ret = chip->fixes->resume(chip); 1550 if (ret) 1551 return ret; 1552 } 1553 1554 for (i = 0; i < chip->num_slots; i++) { 1555 slot = chip->slots[i]; 1556 if (!slot) 1557 continue; 1558 1559 ret = sdhci_runtime_resume_host(slot->host); 1560 if (ret) 1561 return ret; 1562 } 1563 1564 return 0; 1565 } 1566 1567 #else /* CONFIG_PM */ 1568 1569 #define sdhci_pci_suspend NULL 1570 #define sdhci_pci_resume NULL 1571 1572 #endif /* CONFIG_PM */ 1573 1574 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1575 .suspend = sdhci_pci_suspend, 1576 .resume = sdhci_pci_resume, 1577 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1578 sdhci_pci_runtime_resume, NULL) 1579 }; 1580 1581 /*****************************************************************************\ 1582 * * 1583 * Device probing/removal * 1584 * * 1585 \*****************************************************************************/ 1586 1587 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1588 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1589 int slotno) 1590 { 1591 struct sdhci_pci_slot *slot; 1592 struct sdhci_host *host; 1593 int ret, bar = first_bar + slotno; 1594 1595 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1596 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1597 return ERR_PTR(-ENODEV); 1598 } 1599 1600 if (pci_resource_len(pdev, bar) < 0x100) { 1601 dev_err(&pdev->dev, "Invalid iomem size. You may " 1602 "experience problems.\n"); 1603 } 1604 1605 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1606 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1607 return ERR_PTR(-ENODEV); 1608 } 1609 1610 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1611 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1612 return ERR_PTR(-ENODEV); 1613 } 1614 1615 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot)); 1616 if (IS_ERR(host)) { 1617 dev_err(&pdev->dev, "cannot allocate host\n"); 1618 return ERR_CAST(host); 1619 } 1620 1621 slot = sdhci_priv(host); 1622 1623 slot->chip = chip; 1624 slot->host = host; 1625 slot->pci_bar = bar; 1626 slot->rst_n_gpio = -EINVAL; 1627 slot->cd_gpio = -EINVAL; 1628 slot->cd_idx = -1; 1629 1630 /* Retrieve platform data if there is any */ 1631 if (*sdhci_pci_get_data) 1632 slot->data = sdhci_pci_get_data(pdev, slotno); 1633 1634 if (slot->data) { 1635 if (slot->data->setup) { 1636 ret = slot->data->setup(slot->data); 1637 if (ret) { 1638 dev_err(&pdev->dev, "platform setup failed\n"); 1639 goto free; 1640 } 1641 } 1642 slot->rst_n_gpio = slot->data->rst_n_gpio; 1643 slot->cd_gpio = slot->data->cd_gpio; 1644 } 1645 1646 host->hw_name = "PCI"; 1647 host->ops = &sdhci_pci_ops; 1648 host->quirks = chip->quirks; 1649 host->quirks2 = chip->quirks2; 1650 1651 host->irq = pdev->irq; 1652 1653 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc)); 1654 if (ret) { 1655 dev_err(&pdev->dev, "cannot request region\n"); 1656 goto cleanup; 1657 } 1658 1659 host->ioaddr = pci_ioremap_bar(pdev, bar); 1660 if (!host->ioaddr) { 1661 dev_err(&pdev->dev, "failed to remap registers\n"); 1662 ret = -ENOMEM; 1663 goto release; 1664 } 1665 1666 if (chip->fixes && chip->fixes->probe_slot) { 1667 ret = chip->fixes->probe_slot(slot); 1668 if (ret) 1669 goto unmap; 1670 } 1671 1672 if (gpio_is_valid(slot->rst_n_gpio)) { 1673 if (!gpio_request(slot->rst_n_gpio, "eMMC_reset")) { 1674 gpio_direction_output(slot->rst_n_gpio, 1); 1675 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1676 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1677 } else { 1678 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1679 slot->rst_n_gpio = -EINVAL; 1680 } 1681 } 1682 1683 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; 1684 host->mmc->slotno = slotno; 1685 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1686 1687 if (slot->cd_idx >= 0 && 1688 mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx, 1689 slot->cd_override_level, 0, NULL)) { 1690 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 1691 slot->cd_idx = -1; 1692 } 1693 1694 ret = sdhci_add_host(host); 1695 if (ret) 1696 goto remove; 1697 1698 sdhci_pci_add_own_cd(slot); 1699 1700 /* 1701 * Check if the chip needs a separate GPIO for card detect to wake up 1702 * from runtime suspend. If it is not there, don't allow runtime PM. 1703 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 1704 */ 1705 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 1706 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 1707 chip->allow_runtime_pm = false; 1708 1709 return slot; 1710 1711 remove: 1712 if (gpio_is_valid(slot->rst_n_gpio)) 1713 gpio_free(slot->rst_n_gpio); 1714 1715 if (chip->fixes && chip->fixes->remove_slot) 1716 chip->fixes->remove_slot(slot, 0); 1717 1718 unmap: 1719 iounmap(host->ioaddr); 1720 1721 release: 1722 pci_release_region(pdev, bar); 1723 1724 cleanup: 1725 if (slot->data && slot->data->cleanup) 1726 slot->data->cleanup(slot->data); 1727 1728 free: 1729 sdhci_free_host(host); 1730 1731 return ERR_PTR(ret); 1732 } 1733 1734 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 1735 { 1736 int dead; 1737 u32 scratch; 1738 1739 sdhci_pci_remove_own_cd(slot); 1740 1741 dead = 0; 1742 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 1743 if (scratch == (u32)-1) 1744 dead = 1; 1745 1746 sdhci_remove_host(slot->host, dead); 1747 1748 if (gpio_is_valid(slot->rst_n_gpio)) 1749 gpio_free(slot->rst_n_gpio); 1750 1751 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 1752 slot->chip->fixes->remove_slot(slot, dead); 1753 1754 if (slot->data && slot->data->cleanup) 1755 slot->data->cleanup(slot->data); 1756 1757 pci_release_region(slot->chip->pdev, slot->pci_bar); 1758 1759 sdhci_free_host(slot->host); 1760 } 1761 1762 static void sdhci_pci_runtime_pm_allow(struct device *dev) 1763 { 1764 pm_runtime_put_noidle(dev); 1765 pm_runtime_allow(dev); 1766 pm_runtime_set_autosuspend_delay(dev, 50); 1767 pm_runtime_use_autosuspend(dev); 1768 pm_suspend_ignore_children(dev, 1); 1769 } 1770 1771 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 1772 { 1773 pm_runtime_forbid(dev); 1774 pm_runtime_get_noresume(dev); 1775 } 1776 1777 static int sdhci_pci_probe(struct pci_dev *pdev, 1778 const struct pci_device_id *ent) 1779 { 1780 struct sdhci_pci_chip *chip; 1781 struct sdhci_pci_slot *slot; 1782 1783 u8 slots, first_bar; 1784 int ret, i; 1785 1786 BUG_ON(pdev == NULL); 1787 BUG_ON(ent == NULL); 1788 1789 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 1790 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 1791 1792 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 1793 if (ret) 1794 return ret; 1795 1796 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 1797 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 1798 if (slots == 0) 1799 return -ENODEV; 1800 1801 BUG_ON(slots > MAX_SLOTS); 1802 1803 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 1804 if (ret) 1805 return ret; 1806 1807 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 1808 1809 if (first_bar > 5) { 1810 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 1811 return -ENODEV; 1812 } 1813 1814 ret = pci_enable_device(pdev); 1815 if (ret) 1816 return ret; 1817 1818 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL); 1819 if (!chip) { 1820 ret = -ENOMEM; 1821 goto err; 1822 } 1823 1824 chip->pdev = pdev; 1825 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 1826 if (chip->fixes) { 1827 chip->quirks = chip->fixes->quirks; 1828 chip->quirks2 = chip->fixes->quirks2; 1829 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 1830 } 1831 chip->num_slots = slots; 1832 1833 pci_set_drvdata(pdev, chip); 1834 1835 if (chip->fixes && chip->fixes->probe) { 1836 ret = chip->fixes->probe(chip); 1837 if (ret) 1838 goto free; 1839 } 1840 1841 slots = chip->num_slots; /* Quirk may have changed this */ 1842 1843 for (i = 0; i < slots; i++) { 1844 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 1845 if (IS_ERR(slot)) { 1846 for (i--; i >= 0; i--) 1847 sdhci_pci_remove_slot(chip->slots[i]); 1848 ret = PTR_ERR(slot); 1849 goto free; 1850 } 1851 1852 chip->slots[i] = slot; 1853 } 1854 1855 if (chip->allow_runtime_pm) 1856 sdhci_pci_runtime_pm_allow(&pdev->dev); 1857 1858 return 0; 1859 1860 free: 1861 pci_set_drvdata(pdev, NULL); 1862 kfree(chip); 1863 1864 err: 1865 pci_disable_device(pdev); 1866 return ret; 1867 } 1868 1869 static void sdhci_pci_remove(struct pci_dev *pdev) 1870 { 1871 int i; 1872 struct sdhci_pci_chip *chip; 1873 1874 chip = pci_get_drvdata(pdev); 1875 1876 if (chip) { 1877 if (chip->allow_runtime_pm) 1878 sdhci_pci_runtime_pm_forbid(&pdev->dev); 1879 1880 for (i = 0; i < chip->num_slots; i++) 1881 sdhci_pci_remove_slot(chip->slots[i]); 1882 1883 pci_set_drvdata(pdev, NULL); 1884 kfree(chip); 1885 } 1886 1887 pci_disable_device(pdev); 1888 } 1889 1890 static struct pci_driver sdhci_driver = { 1891 .name = "sdhci-pci", 1892 .id_table = pci_ids, 1893 .probe = sdhci_pci_probe, 1894 .remove = sdhci_pci_remove, 1895 .driver = { 1896 .pm = &sdhci_pci_pm_ops 1897 }, 1898 }; 1899 1900 module_pci_driver(sdhci_driver); 1901 1902 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 1903 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 1904 MODULE_LICENSE("GPL"); 1905