1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 2 * 3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 * 10 * Thanks to the following companies for their support: 11 * 12 * - JMicron (hardware and technical support) 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/highmem.h> 17 #include <linux/module.h> 18 #include <linux/pci.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/slab.h> 21 #include <linux/device.h> 22 #include <linux/mmc/host.h> 23 #include <linux/mmc/mmc.h> 24 #include <linux/scatterlist.h> 25 #include <linux/io.h> 26 #include <linux/gpio.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/mmc/slot-gpio.h> 29 #include <linux/mmc/sdhci-pci-data.h> 30 #include <linux/acpi.h> 31 32 #include "sdhci.h" 33 #include "sdhci-pci.h" 34 #include "sdhci-pci-o2micro.h" 35 36 static int sdhci_pci_enable_dma(struct sdhci_host *host); 37 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width); 38 static void sdhci_pci_hw_reset(struct sdhci_host *host); 39 static int sdhci_pci_select_drive_strength(struct sdhci_host *host, 40 struct mmc_card *card, 41 unsigned int max_dtr, int host_drv, 42 int card_drv, int *drv_type); 43 44 /*****************************************************************************\ 45 * * 46 * Hardware specific quirk handling * 47 * * 48 \*****************************************************************************/ 49 50 static int ricoh_probe(struct sdhci_pci_chip *chip) 51 { 52 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 53 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 54 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 55 return 0; 56 } 57 58 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 59 { 60 slot->host->caps = 61 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 62 & SDHCI_TIMEOUT_CLK_MASK) | 63 64 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 65 & SDHCI_CLOCK_BASE_MASK) | 66 67 SDHCI_TIMEOUT_CLK_UNIT | 68 SDHCI_CAN_VDD_330 | 69 SDHCI_CAN_DO_HISPD | 70 SDHCI_CAN_DO_SDMA; 71 return 0; 72 } 73 74 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 75 { 76 /* Apply a delay to allow controller to settle */ 77 /* Otherwise it becomes confused if card state changed 78 during suspend */ 79 msleep(500); 80 return 0; 81 } 82 83 static const struct sdhci_pci_fixes sdhci_ricoh = { 84 .probe = ricoh_probe, 85 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 86 SDHCI_QUIRK_FORCE_DMA | 87 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 88 }; 89 90 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 91 .probe_slot = ricoh_mmc_probe_slot, 92 .resume = ricoh_mmc_resume, 93 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 94 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 95 SDHCI_QUIRK_NO_CARD_NO_RESET | 96 SDHCI_QUIRK_MISSING_CAPS 97 }; 98 99 static const struct sdhci_pci_fixes sdhci_ene_712 = { 100 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 101 SDHCI_QUIRK_BROKEN_DMA, 102 }; 103 104 static const struct sdhci_pci_fixes sdhci_ene_714 = { 105 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 106 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 107 SDHCI_QUIRK_BROKEN_DMA, 108 }; 109 110 static const struct sdhci_pci_fixes sdhci_cafe = { 111 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 112 SDHCI_QUIRK_NO_BUSY_IRQ | 113 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 114 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 115 }; 116 117 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 118 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 119 }; 120 121 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 122 { 123 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 124 return 0; 125 } 126 127 /* 128 * ADMA operation is disabled for Moorestown platform due to 129 * hardware bugs. 130 */ 131 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 132 { 133 /* 134 * slots number is fixed here for MRST as SDIO3/5 are never used and 135 * have hardware bugs. 136 */ 137 chip->num_slots = 1; 138 return 0; 139 } 140 141 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 142 { 143 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 144 return 0; 145 } 146 147 #ifdef CONFIG_PM 148 149 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 150 { 151 struct sdhci_pci_slot *slot = dev_id; 152 struct sdhci_host *host = slot->host; 153 154 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 155 return IRQ_HANDLED; 156 } 157 158 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 159 { 160 int err, irq, gpio = slot->cd_gpio; 161 162 slot->cd_gpio = -EINVAL; 163 slot->cd_irq = -EINVAL; 164 165 if (!gpio_is_valid(gpio)) 166 return; 167 168 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 169 if (err < 0) 170 goto out; 171 172 err = gpio_direction_input(gpio); 173 if (err < 0) 174 goto out_free; 175 176 irq = gpio_to_irq(gpio); 177 if (irq < 0) 178 goto out_free; 179 180 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 181 IRQF_TRIGGER_FALLING, "sd_cd", slot); 182 if (err) 183 goto out_free; 184 185 slot->cd_gpio = gpio; 186 slot->cd_irq = irq; 187 188 return; 189 190 out_free: 191 devm_gpio_free(&slot->chip->pdev->dev, gpio); 192 out: 193 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 194 } 195 196 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 197 { 198 if (slot->cd_irq >= 0) 199 free_irq(slot->cd_irq, slot); 200 } 201 202 #else 203 204 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 205 { 206 } 207 208 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 209 { 210 } 211 212 #endif 213 214 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 215 { 216 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 217 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC | 218 MMC_CAP2_HC_ERASE_SZ; 219 return 0; 220 } 221 222 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 223 { 224 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 225 return 0; 226 } 227 228 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 229 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 230 .probe_slot = mrst_hc_probe_slot, 231 }; 232 233 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 234 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 235 .probe = mrst_hc_probe, 236 }; 237 238 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 239 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 240 .allow_runtime_pm = true, 241 .own_cd_for_runtime_pm = true, 242 }; 243 244 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 245 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 246 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 247 .allow_runtime_pm = true, 248 .probe_slot = mfd_sdio_probe_slot, 249 }; 250 251 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 252 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 253 .allow_runtime_pm = true, 254 .probe_slot = mfd_emmc_probe_slot, 255 }; 256 257 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 258 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 259 .probe_slot = pch_hc_probe_slot, 260 }; 261 262 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 263 { 264 u8 reg; 265 266 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 267 reg |= 0x10; 268 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 269 /* For eMMC, minimum is 1us but give it 9us for good measure */ 270 udelay(9); 271 reg &= ~0x10; 272 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 273 /* For eMMC, minimum is 200us but give it 300us for good measure */ 274 usleep_range(300, 1000); 275 } 276 277 static int spt_select_drive_strength(struct sdhci_host *host, 278 struct mmc_card *card, 279 unsigned int max_dtr, 280 int host_drv, int card_drv, int *drv_type) 281 { 282 int drive_strength; 283 284 if (sdhci_pci_spt_drive_strength > 0) 285 drive_strength = sdhci_pci_spt_drive_strength & 0xf; 286 else 287 drive_strength = 0; /* Default 50-ohm */ 288 289 if ((mmc_driver_type_mask(drive_strength) & card_drv) == 0) 290 drive_strength = 0; /* Default 50-ohm */ 291 292 return drive_strength; 293 } 294 295 /* Try to read the drive strength from the card */ 296 static void spt_read_drive_strength(struct sdhci_host *host) 297 { 298 u32 val, i, t; 299 u16 m; 300 301 if (sdhci_pci_spt_drive_strength) 302 return; 303 304 sdhci_pci_spt_drive_strength = -1; 305 306 m = sdhci_readw(host, SDHCI_HOST_CONTROL2) & 0x7; 307 if (m != 3 && m != 5) 308 return; 309 val = sdhci_readl(host, SDHCI_PRESENT_STATE); 310 if (val & 0x3) 311 return; 312 sdhci_writel(host, 0x007f0023, SDHCI_INT_ENABLE); 313 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 314 sdhci_writew(host, 0x10, SDHCI_TRANSFER_MODE); 315 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 316 sdhci_writew(host, 512, SDHCI_BLOCK_SIZE); 317 sdhci_writew(host, 1, SDHCI_BLOCK_COUNT); 318 sdhci_writel(host, 0, SDHCI_ARGUMENT); 319 sdhci_writew(host, 0x83b, SDHCI_COMMAND); 320 for (i = 0; i < 1000; i++) { 321 val = sdhci_readl(host, SDHCI_INT_STATUS); 322 if (val & 0xffff8000) 323 return; 324 if (val & 0x20) 325 break; 326 udelay(1); 327 } 328 val = sdhci_readl(host, SDHCI_PRESENT_STATE); 329 if (!(val & 0x800)) 330 return; 331 for (i = 0; i < 47; i++) 332 val = sdhci_readl(host, SDHCI_BUFFER); 333 t = val & 0xf00; 334 if (t != 0x200 && t != 0x300) 335 return; 336 337 sdhci_pci_spt_drive_strength = 0x10 | ((val >> 12) & 0xf); 338 } 339 340 static int bxt_get_cd(struct mmc_host *mmc) 341 { 342 int gpio_cd = mmc_gpio_get_cd(mmc); 343 struct sdhci_host *host = mmc_priv(mmc); 344 unsigned long flags; 345 int ret = 0; 346 347 if (!gpio_cd) 348 return 0; 349 350 spin_lock_irqsave(&host->lock, flags); 351 352 if (host->flags & SDHCI_DEVICE_DEAD) 353 goto out; 354 355 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 356 out: 357 spin_unlock_irqrestore(&host->lock, flags); 358 359 return ret; 360 } 361 362 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 363 { 364 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 365 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 366 MMC_CAP_CMD_DURING_TFR | 367 MMC_CAP_WAIT_WHILE_BUSY; 368 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ; 369 slot->hw_reset = sdhci_pci_int_hw_reset; 370 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 371 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 372 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_SPT_EMMC) { 373 spt_read_drive_strength(slot->host); 374 slot->select_drive_strength = spt_select_drive_strength; 375 } 376 return 0; 377 } 378 379 #ifdef CONFIG_ACPI 380 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 381 { 382 acpi_status status; 383 unsigned long long max_freq; 384 385 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 386 "MXFQ", NULL, &max_freq); 387 if (ACPI_FAILURE(status)) { 388 dev_err(&slot->chip->pdev->dev, 389 "MXFQ not found in acpi table\n"); 390 return -EINVAL; 391 } 392 393 slot->host->mmc->f_max = max_freq * 1000000; 394 395 return 0; 396 } 397 #else 398 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 399 { 400 return 0; 401 } 402 #endif 403 404 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 405 { 406 int err; 407 408 err = ni_set_max_freq(slot); 409 if (err) 410 return err; 411 412 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 413 MMC_CAP_WAIT_WHILE_BUSY; 414 return 0; 415 } 416 417 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 418 { 419 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 420 MMC_CAP_WAIT_WHILE_BUSY; 421 return 0; 422 } 423 424 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 425 { 426 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 427 slot->cd_idx = 0; 428 slot->cd_override_level = true; 429 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 430 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 431 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 432 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) { 433 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 434 slot->host->mmc->caps |= MMC_CAP_AGGRESSIVE_PM; 435 } 436 437 return 0; 438 } 439 440 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 441 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 442 443 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 444 unsigned short vdd) 445 { 446 int cntr; 447 u8 reg; 448 449 sdhci_set_power(host, mode, vdd); 450 451 if (mode == MMC_POWER_OFF) 452 return; 453 454 /* 455 * Bus power might not enable after D3 -> D0 transition due to the 456 * present state not yet having propagated. Retry for up to 2ms. 457 */ 458 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 459 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 460 if (reg & SDHCI_POWER_ON) 461 break; 462 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 463 reg |= SDHCI_POWER_ON; 464 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 465 } 466 } 467 468 static const struct sdhci_ops sdhci_intel_byt_ops = { 469 .set_clock = sdhci_set_clock, 470 .set_power = sdhci_intel_set_power, 471 .enable_dma = sdhci_pci_enable_dma, 472 .set_bus_width = sdhci_pci_set_bus_width, 473 .reset = sdhci_reset, 474 .set_uhs_signaling = sdhci_set_uhs_signaling, 475 .hw_reset = sdhci_pci_hw_reset, 476 .select_drive_strength = sdhci_pci_select_drive_strength, 477 }; 478 479 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 480 .allow_runtime_pm = true, 481 .probe_slot = byt_emmc_probe_slot, 482 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 483 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 484 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 485 SDHCI_QUIRK2_STOP_WITH_TC, 486 .ops = &sdhci_intel_byt_ops, 487 }; 488 489 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 490 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 491 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 492 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 493 .allow_runtime_pm = true, 494 .probe_slot = ni_byt_sdio_probe_slot, 495 .ops = &sdhci_intel_byt_ops, 496 }; 497 498 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 499 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 500 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 501 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 502 .allow_runtime_pm = true, 503 .probe_slot = byt_sdio_probe_slot, 504 .ops = &sdhci_intel_byt_ops, 505 }; 506 507 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 508 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 509 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 510 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 511 SDHCI_QUIRK2_STOP_WITH_TC, 512 .allow_runtime_pm = true, 513 .own_cd_for_runtime_pm = true, 514 .probe_slot = byt_sd_probe_slot, 515 .ops = &sdhci_intel_byt_ops, 516 }; 517 518 /* Define Host controllers for Intel Merrifield platform */ 519 #define INTEL_MRFLD_EMMC_0 0 520 #define INTEL_MRFLD_EMMC_1 1 521 #define INTEL_MRFLD_SD 2 522 #define INTEL_MRFLD_SDIO 3 523 524 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 525 { 526 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 527 528 switch (func) { 529 case INTEL_MRFLD_EMMC_0: 530 case INTEL_MRFLD_EMMC_1: 531 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 532 MMC_CAP_8_BIT_DATA | 533 MMC_CAP_1_8V_DDR; 534 break; 535 case INTEL_MRFLD_SD: 536 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 537 break; 538 case INTEL_MRFLD_SDIO: 539 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 540 MMC_CAP_POWER_OFF_CARD; 541 break; 542 default: 543 return -ENODEV; 544 } 545 return 0; 546 } 547 548 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 549 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 550 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 551 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 552 .allow_runtime_pm = true, 553 .probe_slot = intel_mrfld_mmc_probe_slot, 554 }; 555 556 /* O2Micro extra registers */ 557 #define O2_SD_LOCK_WP 0xD3 558 #define O2_SD_MULTI_VCC3V 0xEE 559 #define O2_SD_CLKREQ 0xEC 560 #define O2_SD_CAPS 0xE0 561 #define O2_SD_ADMA1 0xE2 562 #define O2_SD_ADMA2 0xE7 563 #define O2_SD_INF_MOD 0xF1 564 565 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 566 { 567 u8 scratch; 568 int ret; 569 570 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 571 if (ret) 572 return ret; 573 574 /* 575 * Turn PMOS on [bit 0], set over current detection to 2.4 V 576 * [bit 1:2] and enable over current debouncing [bit 6]. 577 */ 578 if (on) 579 scratch |= 0x47; 580 else 581 scratch &= ~0x47; 582 583 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 584 } 585 586 static int jmicron_probe(struct sdhci_pci_chip *chip) 587 { 588 int ret; 589 u16 mmcdev = 0; 590 591 if (chip->pdev->revision == 0) { 592 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 593 SDHCI_QUIRK_32BIT_DMA_SIZE | 594 SDHCI_QUIRK_32BIT_ADMA_SIZE | 595 SDHCI_QUIRK_RESET_AFTER_REQUEST | 596 SDHCI_QUIRK_BROKEN_SMALL_PIO; 597 } 598 599 /* 600 * JMicron chips can have two interfaces to the same hardware 601 * in order to work around limitations in Microsoft's driver. 602 * We need to make sure we only bind to one of them. 603 * 604 * This code assumes two things: 605 * 606 * 1. The PCI code adds subfunctions in order. 607 * 608 * 2. The MMC interface has a lower subfunction number 609 * than the SD interface. 610 */ 611 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 612 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 613 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 614 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 615 616 if (mmcdev) { 617 struct pci_dev *sd_dev; 618 619 sd_dev = NULL; 620 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 621 mmcdev, sd_dev)) != NULL) { 622 if ((PCI_SLOT(chip->pdev->devfn) == 623 PCI_SLOT(sd_dev->devfn)) && 624 (chip->pdev->bus == sd_dev->bus)) 625 break; 626 } 627 628 if (sd_dev) { 629 pci_dev_put(sd_dev); 630 dev_info(&chip->pdev->dev, "Refusing to bind to " 631 "secondary interface.\n"); 632 return -ENODEV; 633 } 634 } 635 636 /* 637 * JMicron chips need a bit of a nudge to enable the power 638 * output pins. 639 */ 640 ret = jmicron_pmos(chip, 1); 641 if (ret) { 642 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 643 return ret; 644 } 645 646 /* quirk for unsable RO-detection on JM388 chips */ 647 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 648 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 649 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 650 651 return 0; 652 } 653 654 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 655 { 656 u8 scratch; 657 658 scratch = readb(host->ioaddr + 0xC0); 659 660 if (on) 661 scratch |= 0x01; 662 else 663 scratch &= ~0x01; 664 665 writeb(scratch, host->ioaddr + 0xC0); 666 } 667 668 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 669 { 670 if (slot->chip->pdev->revision == 0) { 671 u16 version; 672 673 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 674 version = (version & SDHCI_VENDOR_VER_MASK) >> 675 SDHCI_VENDOR_VER_SHIFT; 676 677 /* 678 * Older versions of the chip have lots of nasty glitches 679 * in the ADMA engine. It's best just to avoid it 680 * completely. 681 */ 682 if (version < 0xAC) 683 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 684 } 685 686 /* JM388 MMC doesn't support 1.8V while SD supports it */ 687 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 688 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 689 MMC_VDD_29_30 | MMC_VDD_30_31 | 690 MMC_VDD_165_195; /* allow 1.8V */ 691 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 692 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 693 } 694 695 /* 696 * The secondary interface requires a bit set to get the 697 * interrupts. 698 */ 699 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 700 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 701 jmicron_enable_mmc(slot->host, 1); 702 703 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 704 705 return 0; 706 } 707 708 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 709 { 710 if (dead) 711 return; 712 713 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 714 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 715 jmicron_enable_mmc(slot->host, 0); 716 } 717 718 static int jmicron_suspend(struct sdhci_pci_chip *chip) 719 { 720 int i; 721 722 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 723 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 724 for (i = 0; i < chip->num_slots; i++) 725 jmicron_enable_mmc(chip->slots[i]->host, 0); 726 } 727 728 return 0; 729 } 730 731 static int jmicron_resume(struct sdhci_pci_chip *chip) 732 { 733 int ret, i; 734 735 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 736 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 737 for (i = 0; i < chip->num_slots; i++) 738 jmicron_enable_mmc(chip->slots[i]->host, 1); 739 } 740 741 ret = jmicron_pmos(chip, 1); 742 if (ret) { 743 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 744 return ret; 745 } 746 747 return 0; 748 } 749 750 static const struct sdhci_pci_fixes sdhci_o2 = { 751 .probe = sdhci_pci_o2_probe, 752 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 753 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 754 .probe_slot = sdhci_pci_o2_probe_slot, 755 .resume = sdhci_pci_o2_resume, 756 }; 757 758 static const struct sdhci_pci_fixes sdhci_jmicron = { 759 .probe = jmicron_probe, 760 761 .probe_slot = jmicron_probe_slot, 762 .remove_slot = jmicron_remove_slot, 763 764 .suspend = jmicron_suspend, 765 .resume = jmicron_resume, 766 }; 767 768 /* SysKonnect CardBus2SDIO extra registers */ 769 #define SYSKT_CTRL 0x200 770 #define SYSKT_RDFIFO_STAT 0x204 771 #define SYSKT_WRFIFO_STAT 0x208 772 #define SYSKT_POWER_DATA 0x20c 773 #define SYSKT_POWER_330 0xef 774 #define SYSKT_POWER_300 0xf8 775 #define SYSKT_POWER_184 0xcc 776 #define SYSKT_POWER_CMD 0x20d 777 #define SYSKT_POWER_START (1 << 7) 778 #define SYSKT_POWER_STATUS 0x20e 779 #define SYSKT_POWER_STATUS_OK (1 << 0) 780 #define SYSKT_BOARD_REV 0x210 781 #define SYSKT_CHIP_REV 0x211 782 #define SYSKT_CONF_DATA 0x212 783 #define SYSKT_CONF_DATA_1V8 (1 << 2) 784 #define SYSKT_CONF_DATA_2V5 (1 << 1) 785 #define SYSKT_CONF_DATA_3V3 (1 << 0) 786 787 static int syskt_probe(struct sdhci_pci_chip *chip) 788 { 789 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 790 chip->pdev->class &= ~0x0000FF; 791 chip->pdev->class |= PCI_SDHCI_IFDMA; 792 } 793 return 0; 794 } 795 796 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 797 { 798 int tm, ps; 799 800 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 801 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 802 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 803 "board rev %d.%d, chip rev %d.%d\n", 804 board_rev >> 4, board_rev & 0xf, 805 chip_rev >> 4, chip_rev & 0xf); 806 if (chip_rev >= 0x20) 807 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 808 809 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 810 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 811 udelay(50); 812 tm = 10; /* Wait max 1 ms */ 813 do { 814 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 815 if (ps & SYSKT_POWER_STATUS_OK) 816 break; 817 udelay(100); 818 } while (--tm); 819 if (!tm) { 820 dev_err(&slot->chip->pdev->dev, 821 "power regulator never stabilized"); 822 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 823 return -ENODEV; 824 } 825 826 return 0; 827 } 828 829 static const struct sdhci_pci_fixes sdhci_syskt = { 830 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 831 .probe = syskt_probe, 832 .probe_slot = syskt_probe_slot, 833 }; 834 835 static int via_probe(struct sdhci_pci_chip *chip) 836 { 837 if (chip->pdev->revision == 0x10) 838 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 839 840 return 0; 841 } 842 843 static const struct sdhci_pci_fixes sdhci_via = { 844 .probe = via_probe, 845 }; 846 847 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 848 { 849 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 850 return 0; 851 } 852 853 static const struct sdhci_pci_fixes sdhci_rtsx = { 854 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 855 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 856 SDHCI_QUIRK2_BROKEN_DDR50, 857 .probe_slot = rtsx_probe_slot, 858 }; 859 860 /*AMD chipset generation*/ 861 enum amd_chipset_gen { 862 AMD_CHIPSET_BEFORE_ML, 863 AMD_CHIPSET_CZ, 864 AMD_CHIPSET_NL, 865 AMD_CHIPSET_UNKNOWN, 866 }; 867 868 /* AMD registers */ 869 #define AMD_SD_AUTO_PATTERN 0xB8 870 #define AMD_MSLEEP_DURATION 4 871 #define AMD_SD_MISC_CONTROL 0xD0 872 #define AMD_MAX_TUNE_VALUE 0x0B 873 #define AMD_AUTO_TUNE_SEL 0x10800 874 #define AMD_FIFO_PTR 0x30 875 #define AMD_BIT_MASK 0x1F 876 877 static void amd_tuning_reset(struct sdhci_host *host) 878 { 879 unsigned int val; 880 881 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 882 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 883 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 884 885 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 886 val &= ~SDHCI_CTRL_EXEC_TUNING; 887 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 888 } 889 890 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 891 { 892 unsigned int val; 893 894 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 895 val &= ~AMD_BIT_MASK; 896 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 897 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 898 } 899 900 static void amd_enable_manual_tuning(struct pci_dev *pdev) 901 { 902 unsigned int val; 903 904 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 905 val |= AMD_FIFO_PTR; 906 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 907 } 908 909 static int amd_execute_tuning(struct sdhci_host *host, u32 opcode) 910 { 911 struct sdhci_pci_slot *slot = sdhci_priv(host); 912 struct pci_dev *pdev = slot->chip->pdev; 913 u8 valid_win = 0; 914 u8 valid_win_max = 0; 915 u8 valid_win_end = 0; 916 u8 ctrl, tune_around; 917 918 amd_tuning_reset(host); 919 920 for (tune_around = 0; tune_around < 12; tune_around++) { 921 amd_config_tuning_phase(pdev, tune_around); 922 923 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 924 valid_win = 0; 925 msleep(AMD_MSLEEP_DURATION); 926 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 927 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 928 } else if (++valid_win > valid_win_max) { 929 valid_win_max = valid_win; 930 valid_win_end = tune_around; 931 } 932 } 933 934 if (!valid_win_max) { 935 dev_err(&pdev->dev, "no tuning point found\n"); 936 return -EIO; 937 } 938 939 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 940 941 amd_enable_manual_tuning(pdev); 942 943 host->mmc->retune_period = 0; 944 945 return 0; 946 } 947 948 static int amd_probe(struct sdhci_pci_chip *chip) 949 { 950 struct pci_dev *smbus_dev; 951 enum amd_chipset_gen gen; 952 953 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 954 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 955 if (smbus_dev) { 956 gen = AMD_CHIPSET_BEFORE_ML; 957 } else { 958 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 959 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 960 if (smbus_dev) { 961 if (smbus_dev->revision < 0x51) 962 gen = AMD_CHIPSET_CZ; 963 else 964 gen = AMD_CHIPSET_NL; 965 } else { 966 gen = AMD_CHIPSET_UNKNOWN; 967 } 968 } 969 970 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 971 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 972 973 return 0; 974 } 975 976 static const struct sdhci_ops amd_sdhci_pci_ops = { 977 .set_clock = sdhci_set_clock, 978 .enable_dma = sdhci_pci_enable_dma, 979 .set_bus_width = sdhci_pci_set_bus_width, 980 .reset = sdhci_reset, 981 .set_uhs_signaling = sdhci_set_uhs_signaling, 982 .platform_execute_tuning = amd_execute_tuning, 983 }; 984 985 static const struct sdhci_pci_fixes sdhci_amd = { 986 .probe = amd_probe, 987 .ops = &amd_sdhci_pci_ops, 988 }; 989 990 static const struct pci_device_id pci_ids[] = { 991 { 992 .vendor = PCI_VENDOR_ID_RICOH, 993 .device = PCI_DEVICE_ID_RICOH_R5C822, 994 .subvendor = PCI_ANY_ID, 995 .subdevice = PCI_ANY_ID, 996 .driver_data = (kernel_ulong_t)&sdhci_ricoh, 997 }, 998 999 { 1000 .vendor = PCI_VENDOR_ID_RICOH, 1001 .device = 0x843, 1002 .subvendor = PCI_ANY_ID, 1003 .subdevice = PCI_ANY_ID, 1004 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 1005 }, 1006 1007 { 1008 .vendor = PCI_VENDOR_ID_RICOH, 1009 .device = 0xe822, 1010 .subvendor = PCI_ANY_ID, 1011 .subdevice = PCI_ANY_ID, 1012 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 1013 }, 1014 1015 { 1016 .vendor = PCI_VENDOR_ID_RICOH, 1017 .device = 0xe823, 1018 .subvendor = PCI_ANY_ID, 1019 .subdevice = PCI_ANY_ID, 1020 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 1021 }, 1022 1023 { 1024 .vendor = PCI_VENDOR_ID_ENE, 1025 .device = PCI_DEVICE_ID_ENE_CB712_SD, 1026 .subvendor = PCI_ANY_ID, 1027 .subdevice = PCI_ANY_ID, 1028 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 1029 }, 1030 1031 { 1032 .vendor = PCI_VENDOR_ID_ENE, 1033 .device = PCI_DEVICE_ID_ENE_CB712_SD_2, 1034 .subvendor = PCI_ANY_ID, 1035 .subdevice = PCI_ANY_ID, 1036 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 1037 }, 1038 1039 { 1040 .vendor = PCI_VENDOR_ID_ENE, 1041 .device = PCI_DEVICE_ID_ENE_CB714_SD, 1042 .subvendor = PCI_ANY_ID, 1043 .subdevice = PCI_ANY_ID, 1044 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 1045 }, 1046 1047 { 1048 .vendor = PCI_VENDOR_ID_ENE, 1049 .device = PCI_DEVICE_ID_ENE_CB714_SD_2, 1050 .subvendor = PCI_ANY_ID, 1051 .subdevice = PCI_ANY_ID, 1052 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 1053 }, 1054 1055 { 1056 .vendor = PCI_VENDOR_ID_MARVELL, 1057 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD, 1058 .subvendor = PCI_ANY_ID, 1059 .subdevice = PCI_ANY_ID, 1060 .driver_data = (kernel_ulong_t)&sdhci_cafe, 1061 }, 1062 1063 { 1064 .vendor = PCI_VENDOR_ID_JMICRON, 1065 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD, 1066 .subvendor = PCI_ANY_ID, 1067 .subdevice = PCI_ANY_ID, 1068 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1069 }, 1070 1071 { 1072 .vendor = PCI_VENDOR_ID_JMICRON, 1073 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC, 1074 .subvendor = PCI_ANY_ID, 1075 .subdevice = PCI_ANY_ID, 1076 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1077 }, 1078 1079 { 1080 .vendor = PCI_VENDOR_ID_JMICRON, 1081 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD, 1082 .subvendor = PCI_ANY_ID, 1083 .subdevice = PCI_ANY_ID, 1084 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1085 }, 1086 1087 { 1088 .vendor = PCI_VENDOR_ID_JMICRON, 1089 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD, 1090 .subvendor = PCI_ANY_ID, 1091 .subdevice = PCI_ANY_ID, 1092 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1093 }, 1094 1095 { 1096 .vendor = PCI_VENDOR_ID_SYSKONNECT, 1097 .device = 0x8000, 1098 .subvendor = PCI_ANY_ID, 1099 .subdevice = PCI_ANY_ID, 1100 .driver_data = (kernel_ulong_t)&sdhci_syskt, 1101 }, 1102 1103 { 1104 .vendor = PCI_VENDOR_ID_VIA, 1105 .device = 0x95d0, 1106 .subvendor = PCI_ANY_ID, 1107 .subdevice = PCI_ANY_ID, 1108 .driver_data = (kernel_ulong_t)&sdhci_via, 1109 }, 1110 1111 { 1112 .vendor = PCI_VENDOR_ID_REALTEK, 1113 .device = 0x5250, 1114 .subvendor = PCI_ANY_ID, 1115 .subdevice = PCI_ANY_ID, 1116 .driver_data = (kernel_ulong_t)&sdhci_rtsx, 1117 }, 1118 1119 { 1120 .vendor = PCI_VENDOR_ID_INTEL, 1121 .device = PCI_DEVICE_ID_INTEL_QRK_SD, 1122 .subvendor = PCI_ANY_ID, 1123 .subdevice = PCI_ANY_ID, 1124 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk, 1125 }, 1126 1127 { 1128 .vendor = PCI_VENDOR_ID_INTEL, 1129 .device = PCI_DEVICE_ID_INTEL_MRST_SD0, 1130 .subvendor = PCI_ANY_ID, 1131 .subdevice = PCI_ANY_ID, 1132 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0, 1133 }, 1134 1135 { 1136 .vendor = PCI_VENDOR_ID_INTEL, 1137 .device = PCI_DEVICE_ID_INTEL_MRST_SD1, 1138 .subvendor = PCI_ANY_ID, 1139 .subdevice = PCI_ANY_ID, 1140 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 1141 }, 1142 1143 { 1144 .vendor = PCI_VENDOR_ID_INTEL, 1145 .device = PCI_DEVICE_ID_INTEL_MRST_SD2, 1146 .subvendor = PCI_ANY_ID, 1147 .subdevice = PCI_ANY_ID, 1148 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 1149 }, 1150 1151 { 1152 .vendor = PCI_VENDOR_ID_INTEL, 1153 .device = PCI_DEVICE_ID_INTEL_MFD_SD, 1154 .subvendor = PCI_ANY_ID, 1155 .subdevice = PCI_ANY_ID, 1156 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1157 }, 1158 1159 { 1160 .vendor = PCI_VENDOR_ID_INTEL, 1161 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1, 1162 .subvendor = PCI_ANY_ID, 1163 .subdevice = PCI_ANY_ID, 1164 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1165 }, 1166 1167 { 1168 .vendor = PCI_VENDOR_ID_INTEL, 1169 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2, 1170 .subvendor = PCI_ANY_ID, 1171 .subdevice = PCI_ANY_ID, 1172 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1173 }, 1174 1175 { 1176 .vendor = PCI_VENDOR_ID_INTEL, 1177 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0, 1178 .subvendor = PCI_ANY_ID, 1179 .subdevice = PCI_ANY_ID, 1180 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1181 }, 1182 1183 { 1184 .vendor = PCI_VENDOR_ID_INTEL, 1185 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1, 1186 .subvendor = PCI_ANY_ID, 1187 .subdevice = PCI_ANY_ID, 1188 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1189 }, 1190 1191 { 1192 .vendor = PCI_VENDOR_ID_INTEL, 1193 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0, 1194 .subvendor = PCI_ANY_ID, 1195 .subdevice = PCI_ANY_ID, 1196 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1197 }, 1198 1199 { 1200 .vendor = PCI_VENDOR_ID_INTEL, 1201 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1, 1202 .subvendor = PCI_ANY_ID, 1203 .subdevice = PCI_ANY_ID, 1204 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1205 }, 1206 1207 { 1208 .vendor = PCI_VENDOR_ID_INTEL, 1209 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC, 1210 .subvendor = PCI_ANY_ID, 1211 .subdevice = PCI_ANY_ID, 1212 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1213 }, 1214 1215 { 1216 .vendor = PCI_VENDOR_ID_INTEL, 1217 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, 1218 .subvendor = PCI_VENDOR_ID_NI, 1219 .subdevice = 0x7884, 1220 .driver_data = (kernel_ulong_t)&sdhci_ni_byt_sdio, 1221 }, 1222 1223 { 1224 .vendor = PCI_VENDOR_ID_INTEL, 1225 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, 1226 .subvendor = PCI_ANY_ID, 1227 .subdevice = PCI_ANY_ID, 1228 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1229 }, 1230 1231 { 1232 .vendor = PCI_VENDOR_ID_INTEL, 1233 .device = PCI_DEVICE_ID_INTEL_BYT_SD, 1234 .subvendor = PCI_ANY_ID, 1235 .subdevice = PCI_ANY_ID, 1236 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1237 }, 1238 1239 { 1240 .vendor = PCI_VENDOR_ID_INTEL, 1241 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2, 1242 .subvendor = PCI_ANY_ID, 1243 .subdevice = PCI_ANY_ID, 1244 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1245 }, 1246 1247 { 1248 .vendor = PCI_VENDOR_ID_INTEL, 1249 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC, 1250 .subvendor = PCI_ANY_ID, 1251 .subdevice = PCI_ANY_ID, 1252 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1253 }, 1254 1255 { 1256 .vendor = PCI_VENDOR_ID_INTEL, 1257 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO, 1258 .subvendor = PCI_ANY_ID, 1259 .subdevice = PCI_ANY_ID, 1260 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1261 }, 1262 1263 { 1264 .vendor = PCI_VENDOR_ID_INTEL, 1265 .device = PCI_DEVICE_ID_INTEL_BSW_SD, 1266 .subvendor = PCI_ANY_ID, 1267 .subdevice = PCI_ANY_ID, 1268 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1269 }, 1270 1271 { 1272 .vendor = PCI_VENDOR_ID_INTEL, 1273 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0, 1274 .subvendor = PCI_ANY_ID, 1275 .subdevice = PCI_ANY_ID, 1276 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1277 }, 1278 1279 { 1280 .vendor = PCI_VENDOR_ID_INTEL, 1281 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1, 1282 .subvendor = PCI_ANY_ID, 1283 .subdevice = PCI_ANY_ID, 1284 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1285 }, 1286 1287 { 1288 .vendor = PCI_VENDOR_ID_INTEL, 1289 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2, 1290 .subvendor = PCI_ANY_ID, 1291 .subdevice = PCI_ANY_ID, 1292 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1293 }, 1294 1295 { 1296 .vendor = PCI_VENDOR_ID_INTEL, 1297 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0, 1298 .subvendor = PCI_ANY_ID, 1299 .subdevice = PCI_ANY_ID, 1300 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1301 }, 1302 1303 { 1304 .vendor = PCI_VENDOR_ID_INTEL, 1305 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1, 1306 .subvendor = PCI_ANY_ID, 1307 .subdevice = PCI_ANY_ID, 1308 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1309 }, 1310 1311 { 1312 .vendor = PCI_VENDOR_ID_INTEL, 1313 .device = PCI_DEVICE_ID_INTEL_MRFLD_MMC, 1314 .subvendor = PCI_ANY_ID, 1315 .subdevice = PCI_ANY_ID, 1316 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfld_mmc, 1317 }, 1318 1319 { 1320 .vendor = PCI_VENDOR_ID_INTEL, 1321 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC, 1322 .subvendor = PCI_ANY_ID, 1323 .subdevice = PCI_ANY_ID, 1324 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1325 }, 1326 1327 { 1328 .vendor = PCI_VENDOR_ID_INTEL, 1329 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO, 1330 .subvendor = PCI_ANY_ID, 1331 .subdevice = PCI_ANY_ID, 1332 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1333 }, 1334 1335 { 1336 .vendor = PCI_VENDOR_ID_INTEL, 1337 .device = PCI_DEVICE_ID_INTEL_SPT_SD, 1338 .subvendor = PCI_ANY_ID, 1339 .subdevice = PCI_ANY_ID, 1340 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1341 }, 1342 1343 { 1344 .vendor = PCI_VENDOR_ID_INTEL, 1345 .device = PCI_DEVICE_ID_INTEL_DNV_EMMC, 1346 .subvendor = PCI_ANY_ID, 1347 .subdevice = PCI_ANY_ID, 1348 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1349 }, 1350 1351 { 1352 .vendor = PCI_VENDOR_ID_INTEL, 1353 .device = PCI_DEVICE_ID_INTEL_BXT_EMMC, 1354 .subvendor = PCI_ANY_ID, 1355 .subdevice = PCI_ANY_ID, 1356 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1357 }, 1358 1359 { 1360 .vendor = PCI_VENDOR_ID_INTEL, 1361 .device = PCI_DEVICE_ID_INTEL_BXT_SDIO, 1362 .subvendor = PCI_ANY_ID, 1363 .subdevice = PCI_ANY_ID, 1364 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1365 }, 1366 1367 { 1368 .vendor = PCI_VENDOR_ID_INTEL, 1369 .device = PCI_DEVICE_ID_INTEL_BXT_SD, 1370 .subvendor = PCI_ANY_ID, 1371 .subdevice = PCI_ANY_ID, 1372 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1373 }, 1374 1375 { 1376 .vendor = PCI_VENDOR_ID_INTEL, 1377 .device = PCI_DEVICE_ID_INTEL_BXTM_EMMC, 1378 .subvendor = PCI_ANY_ID, 1379 .subdevice = PCI_ANY_ID, 1380 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1381 }, 1382 1383 { 1384 .vendor = PCI_VENDOR_ID_INTEL, 1385 .device = PCI_DEVICE_ID_INTEL_BXTM_SDIO, 1386 .subvendor = PCI_ANY_ID, 1387 .subdevice = PCI_ANY_ID, 1388 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1389 }, 1390 1391 { 1392 .vendor = PCI_VENDOR_ID_INTEL, 1393 .device = PCI_DEVICE_ID_INTEL_BXTM_SD, 1394 .subvendor = PCI_ANY_ID, 1395 .subdevice = PCI_ANY_ID, 1396 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1397 }, 1398 1399 { 1400 .vendor = PCI_VENDOR_ID_INTEL, 1401 .device = PCI_DEVICE_ID_INTEL_APL_EMMC, 1402 .subvendor = PCI_ANY_ID, 1403 .subdevice = PCI_ANY_ID, 1404 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1405 }, 1406 1407 { 1408 .vendor = PCI_VENDOR_ID_INTEL, 1409 .device = PCI_DEVICE_ID_INTEL_APL_SDIO, 1410 .subvendor = PCI_ANY_ID, 1411 .subdevice = PCI_ANY_ID, 1412 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1413 }, 1414 1415 { 1416 .vendor = PCI_VENDOR_ID_INTEL, 1417 .device = PCI_DEVICE_ID_INTEL_APL_SD, 1418 .subvendor = PCI_ANY_ID, 1419 .subdevice = PCI_ANY_ID, 1420 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1421 }, 1422 1423 { 1424 .vendor = PCI_VENDOR_ID_INTEL, 1425 .device = PCI_DEVICE_ID_INTEL_GLK_EMMC, 1426 .subvendor = PCI_ANY_ID, 1427 .subdevice = PCI_ANY_ID, 1428 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1429 }, 1430 1431 { 1432 .vendor = PCI_VENDOR_ID_INTEL, 1433 .device = PCI_DEVICE_ID_INTEL_GLK_SDIO, 1434 .subvendor = PCI_ANY_ID, 1435 .subdevice = PCI_ANY_ID, 1436 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1437 }, 1438 1439 { 1440 .vendor = PCI_VENDOR_ID_INTEL, 1441 .device = PCI_DEVICE_ID_INTEL_GLK_SD, 1442 .subvendor = PCI_ANY_ID, 1443 .subdevice = PCI_ANY_ID, 1444 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1445 }, 1446 1447 { 1448 .vendor = PCI_VENDOR_ID_O2, 1449 .device = PCI_DEVICE_ID_O2_8120, 1450 .subvendor = PCI_ANY_ID, 1451 .subdevice = PCI_ANY_ID, 1452 .driver_data = (kernel_ulong_t)&sdhci_o2, 1453 }, 1454 1455 { 1456 .vendor = PCI_VENDOR_ID_O2, 1457 .device = PCI_DEVICE_ID_O2_8220, 1458 .subvendor = PCI_ANY_ID, 1459 .subdevice = PCI_ANY_ID, 1460 .driver_data = (kernel_ulong_t)&sdhci_o2, 1461 }, 1462 1463 { 1464 .vendor = PCI_VENDOR_ID_O2, 1465 .device = PCI_DEVICE_ID_O2_8221, 1466 .subvendor = PCI_ANY_ID, 1467 .subdevice = PCI_ANY_ID, 1468 .driver_data = (kernel_ulong_t)&sdhci_o2, 1469 }, 1470 1471 { 1472 .vendor = PCI_VENDOR_ID_O2, 1473 .device = PCI_DEVICE_ID_O2_8320, 1474 .subvendor = PCI_ANY_ID, 1475 .subdevice = PCI_ANY_ID, 1476 .driver_data = (kernel_ulong_t)&sdhci_o2, 1477 }, 1478 1479 { 1480 .vendor = PCI_VENDOR_ID_O2, 1481 .device = PCI_DEVICE_ID_O2_8321, 1482 .subvendor = PCI_ANY_ID, 1483 .subdevice = PCI_ANY_ID, 1484 .driver_data = (kernel_ulong_t)&sdhci_o2, 1485 }, 1486 1487 { 1488 .vendor = PCI_VENDOR_ID_O2, 1489 .device = PCI_DEVICE_ID_O2_FUJIN2, 1490 .subvendor = PCI_ANY_ID, 1491 .subdevice = PCI_ANY_ID, 1492 .driver_data = (kernel_ulong_t)&sdhci_o2, 1493 }, 1494 1495 { 1496 .vendor = PCI_VENDOR_ID_O2, 1497 .device = PCI_DEVICE_ID_O2_SDS0, 1498 .subvendor = PCI_ANY_ID, 1499 .subdevice = PCI_ANY_ID, 1500 .driver_data = (kernel_ulong_t)&sdhci_o2, 1501 }, 1502 1503 { 1504 .vendor = PCI_VENDOR_ID_O2, 1505 .device = PCI_DEVICE_ID_O2_SDS1, 1506 .subvendor = PCI_ANY_ID, 1507 .subdevice = PCI_ANY_ID, 1508 .driver_data = (kernel_ulong_t)&sdhci_o2, 1509 }, 1510 1511 { 1512 .vendor = PCI_VENDOR_ID_O2, 1513 .device = PCI_DEVICE_ID_O2_SEABIRD0, 1514 .subvendor = PCI_ANY_ID, 1515 .subdevice = PCI_ANY_ID, 1516 .driver_data = (kernel_ulong_t)&sdhci_o2, 1517 }, 1518 1519 { 1520 .vendor = PCI_VENDOR_ID_O2, 1521 .device = PCI_DEVICE_ID_O2_SEABIRD1, 1522 .subvendor = PCI_ANY_ID, 1523 .subdevice = PCI_ANY_ID, 1524 .driver_data = (kernel_ulong_t)&sdhci_o2, 1525 }, 1526 { 1527 .vendor = PCI_VENDOR_ID_AMD, 1528 .device = PCI_ANY_ID, 1529 .class = PCI_CLASS_SYSTEM_SDHCI << 8, 1530 .class_mask = 0xFFFF00, 1531 .subvendor = PCI_ANY_ID, 1532 .subdevice = PCI_ANY_ID, 1533 .driver_data = (kernel_ulong_t)&sdhci_amd, 1534 }, 1535 { /* Generic SD host controller */ 1536 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) 1537 }, 1538 1539 { /* end: all zeroes */ }, 1540 }; 1541 1542 MODULE_DEVICE_TABLE(pci, pci_ids); 1543 1544 /*****************************************************************************\ 1545 * * 1546 * SDHCI core callbacks * 1547 * * 1548 \*****************************************************************************/ 1549 1550 static int sdhci_pci_enable_dma(struct sdhci_host *host) 1551 { 1552 struct sdhci_pci_slot *slot; 1553 struct pci_dev *pdev; 1554 1555 slot = sdhci_priv(host); 1556 pdev = slot->chip->pdev; 1557 1558 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1559 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1560 (host->flags & SDHCI_USE_SDMA)) { 1561 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1562 "doesn't fully claim to support it.\n"); 1563 } 1564 1565 pci_set_master(pdev); 1566 1567 return 0; 1568 } 1569 1570 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width) 1571 { 1572 u8 ctrl; 1573 1574 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1575 1576 switch (width) { 1577 case MMC_BUS_WIDTH_8: 1578 ctrl |= SDHCI_CTRL_8BITBUS; 1579 ctrl &= ~SDHCI_CTRL_4BITBUS; 1580 break; 1581 case MMC_BUS_WIDTH_4: 1582 ctrl |= SDHCI_CTRL_4BITBUS; 1583 ctrl &= ~SDHCI_CTRL_8BITBUS; 1584 break; 1585 default: 1586 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS); 1587 break; 1588 } 1589 1590 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1591 } 1592 1593 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1594 { 1595 struct sdhci_pci_slot *slot = sdhci_priv(host); 1596 int rst_n_gpio = slot->rst_n_gpio; 1597 1598 if (!gpio_is_valid(rst_n_gpio)) 1599 return; 1600 gpio_set_value_cansleep(rst_n_gpio, 0); 1601 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1602 udelay(10); 1603 gpio_set_value_cansleep(rst_n_gpio, 1); 1604 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1605 usleep_range(300, 1000); 1606 } 1607 1608 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1609 { 1610 struct sdhci_pci_slot *slot = sdhci_priv(host); 1611 1612 if (slot->hw_reset) 1613 slot->hw_reset(host); 1614 } 1615 1616 static int sdhci_pci_select_drive_strength(struct sdhci_host *host, 1617 struct mmc_card *card, 1618 unsigned int max_dtr, int host_drv, 1619 int card_drv, int *drv_type) 1620 { 1621 struct sdhci_pci_slot *slot = sdhci_priv(host); 1622 1623 if (!slot->select_drive_strength) 1624 return 0; 1625 1626 return slot->select_drive_strength(host, card, max_dtr, host_drv, 1627 card_drv, drv_type); 1628 } 1629 1630 static const struct sdhci_ops sdhci_pci_ops = { 1631 .set_clock = sdhci_set_clock, 1632 .enable_dma = sdhci_pci_enable_dma, 1633 .set_bus_width = sdhci_pci_set_bus_width, 1634 .reset = sdhci_reset, 1635 .set_uhs_signaling = sdhci_set_uhs_signaling, 1636 .hw_reset = sdhci_pci_hw_reset, 1637 .select_drive_strength = sdhci_pci_select_drive_strength, 1638 }; 1639 1640 /*****************************************************************************\ 1641 * * 1642 * Suspend/resume * 1643 * * 1644 \*****************************************************************************/ 1645 1646 #ifdef CONFIG_PM_SLEEP 1647 static int sdhci_pci_suspend(struct device *dev) 1648 { 1649 struct pci_dev *pdev = to_pci_dev(dev); 1650 struct sdhci_pci_chip *chip; 1651 struct sdhci_pci_slot *slot; 1652 mmc_pm_flag_t slot_pm_flags; 1653 mmc_pm_flag_t pm_flags = 0; 1654 int i, ret; 1655 1656 chip = pci_get_drvdata(pdev); 1657 if (!chip) 1658 return 0; 1659 1660 for (i = 0; i < chip->num_slots; i++) { 1661 slot = chip->slots[i]; 1662 if (!slot) 1663 continue; 1664 1665 ret = sdhci_suspend_host(slot->host); 1666 1667 if (ret) 1668 goto err_pci_suspend; 1669 1670 slot_pm_flags = slot->host->mmc->pm_flags; 1671 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1672 sdhci_enable_irq_wakeups(slot->host); 1673 1674 pm_flags |= slot_pm_flags; 1675 } 1676 1677 if (chip->fixes && chip->fixes->suspend) { 1678 ret = chip->fixes->suspend(chip); 1679 if (ret) 1680 goto err_pci_suspend; 1681 } 1682 1683 if (pm_flags & MMC_PM_KEEP_POWER) { 1684 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1685 device_init_wakeup(dev, true); 1686 else 1687 device_init_wakeup(dev, false); 1688 } else 1689 device_init_wakeup(dev, false); 1690 1691 return 0; 1692 1693 err_pci_suspend: 1694 while (--i >= 0) 1695 sdhci_resume_host(chip->slots[i]->host); 1696 return ret; 1697 } 1698 1699 static int sdhci_pci_resume(struct device *dev) 1700 { 1701 struct pci_dev *pdev = to_pci_dev(dev); 1702 struct sdhci_pci_chip *chip; 1703 struct sdhci_pci_slot *slot; 1704 int i, ret; 1705 1706 chip = pci_get_drvdata(pdev); 1707 if (!chip) 1708 return 0; 1709 1710 if (chip->fixes && chip->fixes->resume) { 1711 ret = chip->fixes->resume(chip); 1712 if (ret) 1713 return ret; 1714 } 1715 1716 for (i = 0; i < chip->num_slots; i++) { 1717 slot = chip->slots[i]; 1718 if (!slot) 1719 continue; 1720 1721 ret = sdhci_resume_host(slot->host); 1722 if (ret) 1723 return ret; 1724 } 1725 1726 return 0; 1727 } 1728 #endif 1729 1730 #ifdef CONFIG_PM 1731 static int sdhci_pci_runtime_suspend(struct device *dev) 1732 { 1733 struct pci_dev *pdev = to_pci_dev(dev); 1734 struct sdhci_pci_chip *chip; 1735 struct sdhci_pci_slot *slot; 1736 int i, ret; 1737 1738 chip = pci_get_drvdata(pdev); 1739 if (!chip) 1740 return 0; 1741 1742 for (i = 0; i < chip->num_slots; i++) { 1743 slot = chip->slots[i]; 1744 if (!slot) 1745 continue; 1746 1747 ret = sdhci_runtime_suspend_host(slot->host); 1748 1749 if (ret) 1750 goto err_pci_runtime_suspend; 1751 } 1752 1753 if (chip->fixes && chip->fixes->suspend) { 1754 ret = chip->fixes->suspend(chip); 1755 if (ret) 1756 goto err_pci_runtime_suspend; 1757 } 1758 1759 return 0; 1760 1761 err_pci_runtime_suspend: 1762 while (--i >= 0) 1763 sdhci_runtime_resume_host(chip->slots[i]->host); 1764 return ret; 1765 } 1766 1767 static int sdhci_pci_runtime_resume(struct device *dev) 1768 { 1769 struct pci_dev *pdev = to_pci_dev(dev); 1770 struct sdhci_pci_chip *chip; 1771 struct sdhci_pci_slot *slot; 1772 int i, ret; 1773 1774 chip = pci_get_drvdata(pdev); 1775 if (!chip) 1776 return 0; 1777 1778 if (chip->fixes && chip->fixes->resume) { 1779 ret = chip->fixes->resume(chip); 1780 if (ret) 1781 return ret; 1782 } 1783 1784 for (i = 0; i < chip->num_slots; i++) { 1785 slot = chip->slots[i]; 1786 if (!slot) 1787 continue; 1788 1789 ret = sdhci_runtime_resume_host(slot->host); 1790 if (ret) 1791 return ret; 1792 } 1793 1794 return 0; 1795 } 1796 #endif 1797 1798 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1799 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1800 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1801 sdhci_pci_runtime_resume, NULL) 1802 }; 1803 1804 /*****************************************************************************\ 1805 * * 1806 * Device probing/removal * 1807 * * 1808 \*****************************************************************************/ 1809 1810 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1811 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1812 int slotno) 1813 { 1814 struct sdhci_pci_slot *slot; 1815 struct sdhci_host *host; 1816 int ret, bar = first_bar + slotno; 1817 1818 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1819 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1820 return ERR_PTR(-ENODEV); 1821 } 1822 1823 if (pci_resource_len(pdev, bar) < 0x100) { 1824 dev_err(&pdev->dev, "Invalid iomem size. You may " 1825 "experience problems.\n"); 1826 } 1827 1828 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1829 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1830 return ERR_PTR(-ENODEV); 1831 } 1832 1833 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1834 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1835 return ERR_PTR(-ENODEV); 1836 } 1837 1838 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot)); 1839 if (IS_ERR(host)) { 1840 dev_err(&pdev->dev, "cannot allocate host\n"); 1841 return ERR_CAST(host); 1842 } 1843 1844 slot = sdhci_priv(host); 1845 1846 slot->chip = chip; 1847 slot->host = host; 1848 slot->rst_n_gpio = -EINVAL; 1849 slot->cd_gpio = -EINVAL; 1850 slot->cd_idx = -1; 1851 1852 /* Retrieve platform data if there is any */ 1853 if (*sdhci_pci_get_data) 1854 slot->data = sdhci_pci_get_data(pdev, slotno); 1855 1856 if (slot->data) { 1857 if (slot->data->setup) { 1858 ret = slot->data->setup(slot->data); 1859 if (ret) { 1860 dev_err(&pdev->dev, "platform setup failed\n"); 1861 goto free; 1862 } 1863 } 1864 slot->rst_n_gpio = slot->data->rst_n_gpio; 1865 slot->cd_gpio = slot->data->cd_gpio; 1866 } 1867 1868 host->hw_name = "PCI"; 1869 host->ops = chip->fixes && chip->fixes->ops ? 1870 chip->fixes->ops : 1871 &sdhci_pci_ops; 1872 host->quirks = chip->quirks; 1873 host->quirks2 = chip->quirks2; 1874 1875 host->irq = pdev->irq; 1876 1877 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1878 if (ret) { 1879 dev_err(&pdev->dev, "cannot request region\n"); 1880 goto cleanup; 1881 } 1882 1883 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1884 1885 if (chip->fixes && chip->fixes->probe_slot) { 1886 ret = chip->fixes->probe_slot(slot); 1887 if (ret) 1888 goto cleanup; 1889 } 1890 1891 if (gpio_is_valid(slot->rst_n_gpio)) { 1892 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1893 gpio_direction_output(slot->rst_n_gpio, 1); 1894 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1895 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1896 } else { 1897 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1898 slot->rst_n_gpio = -EINVAL; 1899 } 1900 } 1901 1902 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; 1903 host->mmc->slotno = slotno; 1904 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1905 1906 if (slot->cd_idx >= 0) { 1907 ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx, 1908 slot->cd_override_level, 0, NULL); 1909 if (ret == -EPROBE_DEFER) 1910 goto remove; 1911 1912 if (ret) { 1913 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 1914 slot->cd_idx = -1; 1915 } 1916 } 1917 1918 ret = sdhci_add_host(host); 1919 if (ret) 1920 goto remove; 1921 1922 sdhci_pci_add_own_cd(slot); 1923 1924 /* 1925 * Check if the chip needs a separate GPIO for card detect to wake up 1926 * from runtime suspend. If it is not there, don't allow runtime PM. 1927 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 1928 */ 1929 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 1930 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 1931 chip->allow_runtime_pm = false; 1932 1933 return slot; 1934 1935 remove: 1936 if (chip->fixes && chip->fixes->remove_slot) 1937 chip->fixes->remove_slot(slot, 0); 1938 1939 cleanup: 1940 if (slot->data && slot->data->cleanup) 1941 slot->data->cleanup(slot->data); 1942 1943 free: 1944 sdhci_free_host(host); 1945 1946 return ERR_PTR(ret); 1947 } 1948 1949 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 1950 { 1951 int dead; 1952 u32 scratch; 1953 1954 sdhci_pci_remove_own_cd(slot); 1955 1956 dead = 0; 1957 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 1958 if (scratch == (u32)-1) 1959 dead = 1; 1960 1961 sdhci_remove_host(slot->host, dead); 1962 1963 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 1964 slot->chip->fixes->remove_slot(slot, dead); 1965 1966 if (slot->data && slot->data->cleanup) 1967 slot->data->cleanup(slot->data); 1968 1969 sdhci_free_host(slot->host); 1970 } 1971 1972 static void sdhci_pci_runtime_pm_allow(struct device *dev) 1973 { 1974 pm_suspend_ignore_children(dev, 1); 1975 pm_runtime_set_autosuspend_delay(dev, 50); 1976 pm_runtime_use_autosuspend(dev); 1977 pm_runtime_allow(dev); 1978 /* Stay active until mmc core scans for a card */ 1979 pm_runtime_put_noidle(dev); 1980 } 1981 1982 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 1983 { 1984 pm_runtime_forbid(dev); 1985 pm_runtime_get_noresume(dev); 1986 } 1987 1988 static int sdhci_pci_probe(struct pci_dev *pdev, 1989 const struct pci_device_id *ent) 1990 { 1991 struct sdhci_pci_chip *chip; 1992 struct sdhci_pci_slot *slot; 1993 1994 u8 slots, first_bar; 1995 int ret, i; 1996 1997 BUG_ON(pdev == NULL); 1998 BUG_ON(ent == NULL); 1999 2000 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 2001 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 2002 2003 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 2004 if (ret) 2005 return ret; 2006 2007 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 2008 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 2009 if (slots == 0) 2010 return -ENODEV; 2011 2012 BUG_ON(slots > MAX_SLOTS); 2013 2014 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 2015 if (ret) 2016 return ret; 2017 2018 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 2019 2020 if (first_bar > 5) { 2021 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 2022 return -ENODEV; 2023 } 2024 2025 ret = pcim_enable_device(pdev); 2026 if (ret) 2027 return ret; 2028 2029 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 2030 if (!chip) 2031 return -ENOMEM; 2032 2033 chip->pdev = pdev; 2034 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 2035 if (chip->fixes) { 2036 chip->quirks = chip->fixes->quirks; 2037 chip->quirks2 = chip->fixes->quirks2; 2038 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 2039 } 2040 chip->num_slots = slots; 2041 2042 pci_set_drvdata(pdev, chip); 2043 2044 if (chip->fixes && chip->fixes->probe) { 2045 ret = chip->fixes->probe(chip); 2046 if (ret) 2047 return ret; 2048 } 2049 2050 slots = chip->num_slots; /* Quirk may have changed this */ 2051 2052 for (i = 0; i < slots; i++) { 2053 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 2054 if (IS_ERR(slot)) { 2055 for (i--; i >= 0; i--) 2056 sdhci_pci_remove_slot(chip->slots[i]); 2057 return PTR_ERR(slot); 2058 } 2059 2060 chip->slots[i] = slot; 2061 } 2062 2063 if (chip->allow_runtime_pm) 2064 sdhci_pci_runtime_pm_allow(&pdev->dev); 2065 2066 return 0; 2067 } 2068 2069 static void sdhci_pci_remove(struct pci_dev *pdev) 2070 { 2071 int i; 2072 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 2073 2074 if (chip->allow_runtime_pm) 2075 sdhci_pci_runtime_pm_forbid(&pdev->dev); 2076 2077 for (i = 0; i < chip->num_slots; i++) 2078 sdhci_pci_remove_slot(chip->slots[i]); 2079 } 2080 2081 static struct pci_driver sdhci_driver = { 2082 .name = "sdhci-pci", 2083 .id_table = pci_ids, 2084 .probe = sdhci_pci_probe, 2085 .remove = sdhci_pci_remove, 2086 .driver = { 2087 .pm = &sdhci_pci_pm_ops 2088 }, 2089 }; 2090 2091 module_pci_driver(sdhci_driver); 2092 2093 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 2094 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 2095 MODULE_LICENSE("GPL"); 2096