1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 2 * 3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 * 10 * Thanks to the following companies for their support: 11 * 12 * - JMicron (hardware and technical support) 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/highmem.h> 17 #include <linux/module.h> 18 #include <linux/pci.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/slab.h> 21 #include <linux/device.h> 22 #include <linux/mmc/host.h> 23 #include <linux/mmc/mmc.h> 24 #include <linux/scatterlist.h> 25 #include <linux/io.h> 26 #include <linux/gpio.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/mmc/slot-gpio.h> 29 #include <linux/mmc/sdhci-pci-data.h> 30 31 #include "sdhci.h" 32 #include "sdhci-pci.h" 33 #include "sdhci-pci-o2micro.h" 34 35 /*****************************************************************************\ 36 * * 37 * Hardware specific quirk handling * 38 * * 39 \*****************************************************************************/ 40 41 static int ricoh_probe(struct sdhci_pci_chip *chip) 42 { 43 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 44 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 45 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 46 return 0; 47 } 48 49 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 50 { 51 slot->host->caps = 52 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 53 & SDHCI_TIMEOUT_CLK_MASK) | 54 55 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 56 & SDHCI_CLOCK_BASE_MASK) | 57 58 SDHCI_TIMEOUT_CLK_UNIT | 59 SDHCI_CAN_VDD_330 | 60 SDHCI_CAN_DO_HISPD | 61 SDHCI_CAN_DO_SDMA; 62 return 0; 63 } 64 65 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 66 { 67 /* Apply a delay to allow controller to settle */ 68 /* Otherwise it becomes confused if card state changed 69 during suspend */ 70 msleep(500); 71 return 0; 72 } 73 74 static const struct sdhci_pci_fixes sdhci_ricoh = { 75 .probe = ricoh_probe, 76 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 77 SDHCI_QUIRK_FORCE_DMA | 78 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 79 }; 80 81 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 82 .probe_slot = ricoh_mmc_probe_slot, 83 .resume = ricoh_mmc_resume, 84 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 85 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 86 SDHCI_QUIRK_NO_CARD_NO_RESET | 87 SDHCI_QUIRK_MISSING_CAPS 88 }; 89 90 static const struct sdhci_pci_fixes sdhci_ene_712 = { 91 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 92 SDHCI_QUIRK_BROKEN_DMA, 93 }; 94 95 static const struct sdhci_pci_fixes sdhci_ene_714 = { 96 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 97 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 98 SDHCI_QUIRK_BROKEN_DMA, 99 }; 100 101 static const struct sdhci_pci_fixes sdhci_cafe = { 102 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 103 SDHCI_QUIRK_NO_BUSY_IRQ | 104 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 105 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 106 }; 107 108 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 109 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 110 }; 111 112 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 113 { 114 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 115 return 0; 116 } 117 118 /* 119 * ADMA operation is disabled for Moorestown platform due to 120 * hardware bugs. 121 */ 122 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 123 { 124 /* 125 * slots number is fixed here for MRST as SDIO3/5 are never used and 126 * have hardware bugs. 127 */ 128 chip->num_slots = 1; 129 return 0; 130 } 131 132 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 133 { 134 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 135 return 0; 136 } 137 138 #ifdef CONFIG_PM 139 140 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 141 { 142 struct sdhci_pci_slot *slot = dev_id; 143 struct sdhci_host *host = slot->host; 144 145 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 146 return IRQ_HANDLED; 147 } 148 149 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 150 { 151 int err, irq, gpio = slot->cd_gpio; 152 153 slot->cd_gpio = -EINVAL; 154 slot->cd_irq = -EINVAL; 155 156 if (!gpio_is_valid(gpio)) 157 return; 158 159 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 160 if (err < 0) 161 goto out; 162 163 err = gpio_direction_input(gpio); 164 if (err < 0) 165 goto out_free; 166 167 irq = gpio_to_irq(gpio); 168 if (irq < 0) 169 goto out_free; 170 171 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 172 IRQF_TRIGGER_FALLING, "sd_cd", slot); 173 if (err) 174 goto out_free; 175 176 slot->cd_gpio = gpio; 177 slot->cd_irq = irq; 178 179 return; 180 181 out_free: 182 devm_gpio_free(&slot->chip->pdev->dev, gpio); 183 out: 184 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 185 } 186 187 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 188 { 189 if (slot->cd_irq >= 0) 190 free_irq(slot->cd_irq, slot); 191 } 192 193 #else 194 195 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 196 { 197 } 198 199 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 200 { 201 } 202 203 #endif 204 205 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 206 { 207 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 208 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC | 209 MMC_CAP2_HC_ERASE_SZ; 210 return 0; 211 } 212 213 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 214 { 215 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 216 return 0; 217 } 218 219 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 220 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 221 .probe_slot = mrst_hc_probe_slot, 222 }; 223 224 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 225 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 226 .probe = mrst_hc_probe, 227 }; 228 229 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 230 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 231 .allow_runtime_pm = true, 232 .own_cd_for_runtime_pm = true, 233 }; 234 235 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 236 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 237 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 238 .allow_runtime_pm = true, 239 .probe_slot = mfd_sdio_probe_slot, 240 }; 241 242 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 243 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 244 .allow_runtime_pm = true, 245 .probe_slot = mfd_emmc_probe_slot, 246 }; 247 248 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 249 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 250 .probe_slot = pch_hc_probe_slot, 251 }; 252 253 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 254 { 255 u8 reg; 256 257 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 258 reg |= 0x10; 259 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 260 /* For eMMC, minimum is 1us but give it 9us for good measure */ 261 udelay(9); 262 reg &= ~0x10; 263 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 264 /* For eMMC, minimum is 200us but give it 300us for good measure */ 265 usleep_range(300, 1000); 266 } 267 268 static int spt_select_drive_strength(struct sdhci_host *host, 269 struct mmc_card *card, 270 unsigned int max_dtr, 271 int host_drv, int card_drv, int *drv_type) 272 { 273 int drive_strength; 274 275 if (sdhci_pci_spt_drive_strength > 0) 276 drive_strength = sdhci_pci_spt_drive_strength & 0xf; 277 else 278 drive_strength = 0; /* Default 50-ohm */ 279 280 if ((mmc_driver_type_mask(drive_strength) & card_drv) == 0) 281 drive_strength = 0; /* Default 50-ohm */ 282 283 return drive_strength; 284 } 285 286 /* Try to read the drive strength from the card */ 287 static void spt_read_drive_strength(struct sdhci_host *host) 288 { 289 u32 val, i, t; 290 u16 m; 291 292 if (sdhci_pci_spt_drive_strength) 293 return; 294 295 sdhci_pci_spt_drive_strength = -1; 296 297 m = sdhci_readw(host, SDHCI_HOST_CONTROL2) & 0x7; 298 if (m != 3 && m != 5) 299 return; 300 val = sdhci_readl(host, SDHCI_PRESENT_STATE); 301 if (val & 0x3) 302 return; 303 sdhci_writel(host, 0x007f0023, SDHCI_INT_ENABLE); 304 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 305 sdhci_writew(host, 0x10, SDHCI_TRANSFER_MODE); 306 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 307 sdhci_writew(host, 512, SDHCI_BLOCK_SIZE); 308 sdhci_writew(host, 1, SDHCI_BLOCK_COUNT); 309 sdhci_writel(host, 0, SDHCI_ARGUMENT); 310 sdhci_writew(host, 0x83b, SDHCI_COMMAND); 311 for (i = 0; i < 1000; i++) { 312 val = sdhci_readl(host, SDHCI_INT_STATUS); 313 if (val & 0xffff8000) 314 return; 315 if (val & 0x20) 316 break; 317 udelay(1); 318 } 319 val = sdhci_readl(host, SDHCI_PRESENT_STATE); 320 if (!(val & 0x800)) 321 return; 322 for (i = 0; i < 47; i++) 323 val = sdhci_readl(host, SDHCI_BUFFER); 324 t = val & 0xf00; 325 if (t != 0x200 && t != 0x300) 326 return; 327 328 sdhci_pci_spt_drive_strength = 0x10 | ((val >> 12) & 0xf); 329 } 330 331 static int bxt_get_cd(struct mmc_host *mmc) 332 { 333 int gpio_cd = mmc_gpio_get_cd(mmc); 334 struct sdhci_host *host = mmc_priv(mmc); 335 unsigned long flags; 336 int ret = 0; 337 338 if (!gpio_cd) 339 return 0; 340 341 spin_lock_irqsave(&host->lock, flags); 342 343 if (host->flags & SDHCI_DEVICE_DEAD) 344 goto out; 345 346 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 347 out: 348 spin_unlock_irqrestore(&host->lock, flags); 349 350 return ret; 351 } 352 353 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 354 { 355 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 356 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 357 MMC_CAP_WAIT_WHILE_BUSY; 358 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ; 359 slot->hw_reset = sdhci_pci_int_hw_reset; 360 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 361 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 362 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_SPT_EMMC) { 363 spt_read_drive_strength(slot->host); 364 slot->select_drive_strength = spt_select_drive_strength; 365 } 366 return 0; 367 } 368 369 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 370 { 371 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 372 MMC_CAP_WAIT_WHILE_BUSY; 373 return 0; 374 } 375 376 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 377 { 378 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 379 slot->cd_con_id = NULL; 380 slot->cd_idx = 0; 381 slot->cd_override_level = true; 382 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 383 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 384 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD) { 385 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 386 slot->host->mmc->caps |= MMC_CAP_AGGRESSIVE_PM; 387 } 388 389 return 0; 390 } 391 392 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 393 .allow_runtime_pm = true, 394 .probe_slot = byt_emmc_probe_slot, 395 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 396 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 397 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 398 SDHCI_QUIRK2_STOP_WITH_TC, 399 }; 400 401 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 402 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 403 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 404 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 405 .allow_runtime_pm = true, 406 .probe_slot = byt_sdio_probe_slot, 407 }; 408 409 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 410 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 411 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 412 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 413 SDHCI_QUIRK2_STOP_WITH_TC, 414 .allow_runtime_pm = true, 415 .own_cd_for_runtime_pm = true, 416 .probe_slot = byt_sd_probe_slot, 417 }; 418 419 /* Define Host controllers for Intel Merrifield platform */ 420 #define INTEL_MRFLD_EMMC_0 0 421 #define INTEL_MRFLD_EMMC_1 1 422 423 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 424 { 425 if ((PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFLD_EMMC_0) && 426 (PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFLD_EMMC_1)) 427 /* SD support is not ready yet */ 428 return -ENODEV; 429 430 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 431 MMC_CAP_1_8V_DDR; 432 433 return 0; 434 } 435 436 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 437 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 438 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 439 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 440 .allow_runtime_pm = true, 441 .probe_slot = intel_mrfld_mmc_probe_slot, 442 }; 443 444 /* O2Micro extra registers */ 445 #define O2_SD_LOCK_WP 0xD3 446 #define O2_SD_MULTI_VCC3V 0xEE 447 #define O2_SD_CLKREQ 0xEC 448 #define O2_SD_CAPS 0xE0 449 #define O2_SD_ADMA1 0xE2 450 #define O2_SD_ADMA2 0xE7 451 #define O2_SD_INF_MOD 0xF1 452 453 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 454 { 455 u8 scratch; 456 int ret; 457 458 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 459 if (ret) 460 return ret; 461 462 /* 463 * Turn PMOS on [bit 0], set over current detection to 2.4 V 464 * [bit 1:2] and enable over current debouncing [bit 6]. 465 */ 466 if (on) 467 scratch |= 0x47; 468 else 469 scratch &= ~0x47; 470 471 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 472 } 473 474 static int jmicron_probe(struct sdhci_pci_chip *chip) 475 { 476 int ret; 477 u16 mmcdev = 0; 478 479 if (chip->pdev->revision == 0) { 480 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 481 SDHCI_QUIRK_32BIT_DMA_SIZE | 482 SDHCI_QUIRK_32BIT_ADMA_SIZE | 483 SDHCI_QUIRK_RESET_AFTER_REQUEST | 484 SDHCI_QUIRK_BROKEN_SMALL_PIO; 485 } 486 487 /* 488 * JMicron chips can have two interfaces to the same hardware 489 * in order to work around limitations in Microsoft's driver. 490 * We need to make sure we only bind to one of them. 491 * 492 * This code assumes two things: 493 * 494 * 1. The PCI code adds subfunctions in order. 495 * 496 * 2. The MMC interface has a lower subfunction number 497 * than the SD interface. 498 */ 499 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 500 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 501 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 502 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 503 504 if (mmcdev) { 505 struct pci_dev *sd_dev; 506 507 sd_dev = NULL; 508 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 509 mmcdev, sd_dev)) != NULL) { 510 if ((PCI_SLOT(chip->pdev->devfn) == 511 PCI_SLOT(sd_dev->devfn)) && 512 (chip->pdev->bus == sd_dev->bus)) 513 break; 514 } 515 516 if (sd_dev) { 517 pci_dev_put(sd_dev); 518 dev_info(&chip->pdev->dev, "Refusing to bind to " 519 "secondary interface.\n"); 520 return -ENODEV; 521 } 522 } 523 524 /* 525 * JMicron chips need a bit of a nudge to enable the power 526 * output pins. 527 */ 528 ret = jmicron_pmos(chip, 1); 529 if (ret) { 530 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 531 return ret; 532 } 533 534 /* quirk for unsable RO-detection on JM388 chips */ 535 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 536 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 537 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 538 539 return 0; 540 } 541 542 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 543 { 544 u8 scratch; 545 546 scratch = readb(host->ioaddr + 0xC0); 547 548 if (on) 549 scratch |= 0x01; 550 else 551 scratch &= ~0x01; 552 553 writeb(scratch, host->ioaddr + 0xC0); 554 } 555 556 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 557 { 558 if (slot->chip->pdev->revision == 0) { 559 u16 version; 560 561 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 562 version = (version & SDHCI_VENDOR_VER_MASK) >> 563 SDHCI_VENDOR_VER_SHIFT; 564 565 /* 566 * Older versions of the chip have lots of nasty glitches 567 * in the ADMA engine. It's best just to avoid it 568 * completely. 569 */ 570 if (version < 0xAC) 571 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 572 } 573 574 /* JM388 MMC doesn't support 1.8V while SD supports it */ 575 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 576 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 577 MMC_VDD_29_30 | MMC_VDD_30_31 | 578 MMC_VDD_165_195; /* allow 1.8V */ 579 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 580 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 581 } 582 583 /* 584 * The secondary interface requires a bit set to get the 585 * interrupts. 586 */ 587 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 588 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 589 jmicron_enable_mmc(slot->host, 1); 590 591 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 592 593 return 0; 594 } 595 596 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 597 { 598 if (dead) 599 return; 600 601 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 602 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 603 jmicron_enable_mmc(slot->host, 0); 604 } 605 606 static int jmicron_suspend(struct sdhci_pci_chip *chip) 607 { 608 int i; 609 610 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 611 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 612 for (i = 0; i < chip->num_slots; i++) 613 jmicron_enable_mmc(chip->slots[i]->host, 0); 614 } 615 616 return 0; 617 } 618 619 static int jmicron_resume(struct sdhci_pci_chip *chip) 620 { 621 int ret, i; 622 623 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 624 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 625 for (i = 0; i < chip->num_slots; i++) 626 jmicron_enable_mmc(chip->slots[i]->host, 1); 627 } 628 629 ret = jmicron_pmos(chip, 1); 630 if (ret) { 631 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 632 return ret; 633 } 634 635 return 0; 636 } 637 638 static const struct sdhci_pci_fixes sdhci_o2 = { 639 .probe = sdhci_pci_o2_probe, 640 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 641 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 642 .probe_slot = sdhci_pci_o2_probe_slot, 643 .resume = sdhci_pci_o2_resume, 644 }; 645 646 static const struct sdhci_pci_fixes sdhci_jmicron = { 647 .probe = jmicron_probe, 648 649 .probe_slot = jmicron_probe_slot, 650 .remove_slot = jmicron_remove_slot, 651 652 .suspend = jmicron_suspend, 653 .resume = jmicron_resume, 654 }; 655 656 /* SysKonnect CardBus2SDIO extra registers */ 657 #define SYSKT_CTRL 0x200 658 #define SYSKT_RDFIFO_STAT 0x204 659 #define SYSKT_WRFIFO_STAT 0x208 660 #define SYSKT_POWER_DATA 0x20c 661 #define SYSKT_POWER_330 0xef 662 #define SYSKT_POWER_300 0xf8 663 #define SYSKT_POWER_184 0xcc 664 #define SYSKT_POWER_CMD 0x20d 665 #define SYSKT_POWER_START (1 << 7) 666 #define SYSKT_POWER_STATUS 0x20e 667 #define SYSKT_POWER_STATUS_OK (1 << 0) 668 #define SYSKT_BOARD_REV 0x210 669 #define SYSKT_CHIP_REV 0x211 670 #define SYSKT_CONF_DATA 0x212 671 #define SYSKT_CONF_DATA_1V8 (1 << 2) 672 #define SYSKT_CONF_DATA_2V5 (1 << 1) 673 #define SYSKT_CONF_DATA_3V3 (1 << 0) 674 675 static int syskt_probe(struct sdhci_pci_chip *chip) 676 { 677 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 678 chip->pdev->class &= ~0x0000FF; 679 chip->pdev->class |= PCI_SDHCI_IFDMA; 680 } 681 return 0; 682 } 683 684 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 685 { 686 int tm, ps; 687 688 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 689 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 690 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 691 "board rev %d.%d, chip rev %d.%d\n", 692 board_rev >> 4, board_rev & 0xf, 693 chip_rev >> 4, chip_rev & 0xf); 694 if (chip_rev >= 0x20) 695 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 696 697 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 698 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 699 udelay(50); 700 tm = 10; /* Wait max 1 ms */ 701 do { 702 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 703 if (ps & SYSKT_POWER_STATUS_OK) 704 break; 705 udelay(100); 706 } while (--tm); 707 if (!tm) { 708 dev_err(&slot->chip->pdev->dev, 709 "power regulator never stabilized"); 710 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 711 return -ENODEV; 712 } 713 714 return 0; 715 } 716 717 static const struct sdhci_pci_fixes sdhci_syskt = { 718 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 719 .probe = syskt_probe, 720 .probe_slot = syskt_probe_slot, 721 }; 722 723 static int via_probe(struct sdhci_pci_chip *chip) 724 { 725 if (chip->pdev->revision == 0x10) 726 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 727 728 return 0; 729 } 730 731 static const struct sdhci_pci_fixes sdhci_via = { 732 .probe = via_probe, 733 }; 734 735 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 736 { 737 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 738 return 0; 739 } 740 741 static const struct sdhci_pci_fixes sdhci_rtsx = { 742 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 743 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 744 SDHCI_QUIRK2_BROKEN_DDR50, 745 .probe_slot = rtsx_probe_slot, 746 }; 747 748 /*AMD chipset generation*/ 749 enum amd_chipset_gen { 750 AMD_CHIPSET_BEFORE_ML, 751 AMD_CHIPSET_CZ, 752 AMD_CHIPSET_NL, 753 AMD_CHIPSET_UNKNOWN, 754 }; 755 756 static int amd_probe(struct sdhci_pci_chip *chip) 757 { 758 struct pci_dev *smbus_dev; 759 enum amd_chipset_gen gen; 760 761 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 762 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 763 if (smbus_dev) { 764 gen = AMD_CHIPSET_BEFORE_ML; 765 } else { 766 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 767 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 768 if (smbus_dev) { 769 if (smbus_dev->revision < 0x51) 770 gen = AMD_CHIPSET_CZ; 771 else 772 gen = AMD_CHIPSET_NL; 773 } else { 774 gen = AMD_CHIPSET_UNKNOWN; 775 } 776 } 777 778 if ((gen == AMD_CHIPSET_BEFORE_ML) || (gen == AMD_CHIPSET_CZ)) { 779 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 780 chip->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 781 } 782 783 return 0; 784 } 785 786 static const struct sdhci_pci_fixes sdhci_amd = { 787 .probe = amd_probe, 788 }; 789 790 static const struct pci_device_id pci_ids[] = { 791 { 792 .vendor = PCI_VENDOR_ID_RICOH, 793 .device = PCI_DEVICE_ID_RICOH_R5C822, 794 .subvendor = PCI_ANY_ID, 795 .subdevice = PCI_ANY_ID, 796 .driver_data = (kernel_ulong_t)&sdhci_ricoh, 797 }, 798 799 { 800 .vendor = PCI_VENDOR_ID_RICOH, 801 .device = 0x843, 802 .subvendor = PCI_ANY_ID, 803 .subdevice = PCI_ANY_ID, 804 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 805 }, 806 807 { 808 .vendor = PCI_VENDOR_ID_RICOH, 809 .device = 0xe822, 810 .subvendor = PCI_ANY_ID, 811 .subdevice = PCI_ANY_ID, 812 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 813 }, 814 815 { 816 .vendor = PCI_VENDOR_ID_RICOH, 817 .device = 0xe823, 818 .subvendor = PCI_ANY_ID, 819 .subdevice = PCI_ANY_ID, 820 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 821 }, 822 823 { 824 .vendor = PCI_VENDOR_ID_ENE, 825 .device = PCI_DEVICE_ID_ENE_CB712_SD, 826 .subvendor = PCI_ANY_ID, 827 .subdevice = PCI_ANY_ID, 828 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 829 }, 830 831 { 832 .vendor = PCI_VENDOR_ID_ENE, 833 .device = PCI_DEVICE_ID_ENE_CB712_SD_2, 834 .subvendor = PCI_ANY_ID, 835 .subdevice = PCI_ANY_ID, 836 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 837 }, 838 839 { 840 .vendor = PCI_VENDOR_ID_ENE, 841 .device = PCI_DEVICE_ID_ENE_CB714_SD, 842 .subvendor = PCI_ANY_ID, 843 .subdevice = PCI_ANY_ID, 844 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 845 }, 846 847 { 848 .vendor = PCI_VENDOR_ID_ENE, 849 .device = PCI_DEVICE_ID_ENE_CB714_SD_2, 850 .subvendor = PCI_ANY_ID, 851 .subdevice = PCI_ANY_ID, 852 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 853 }, 854 855 { 856 .vendor = PCI_VENDOR_ID_MARVELL, 857 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD, 858 .subvendor = PCI_ANY_ID, 859 .subdevice = PCI_ANY_ID, 860 .driver_data = (kernel_ulong_t)&sdhci_cafe, 861 }, 862 863 { 864 .vendor = PCI_VENDOR_ID_JMICRON, 865 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD, 866 .subvendor = PCI_ANY_ID, 867 .subdevice = PCI_ANY_ID, 868 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 869 }, 870 871 { 872 .vendor = PCI_VENDOR_ID_JMICRON, 873 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC, 874 .subvendor = PCI_ANY_ID, 875 .subdevice = PCI_ANY_ID, 876 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 877 }, 878 879 { 880 .vendor = PCI_VENDOR_ID_JMICRON, 881 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD, 882 .subvendor = PCI_ANY_ID, 883 .subdevice = PCI_ANY_ID, 884 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 885 }, 886 887 { 888 .vendor = PCI_VENDOR_ID_JMICRON, 889 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD, 890 .subvendor = PCI_ANY_ID, 891 .subdevice = PCI_ANY_ID, 892 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 893 }, 894 895 { 896 .vendor = PCI_VENDOR_ID_SYSKONNECT, 897 .device = 0x8000, 898 .subvendor = PCI_ANY_ID, 899 .subdevice = PCI_ANY_ID, 900 .driver_data = (kernel_ulong_t)&sdhci_syskt, 901 }, 902 903 { 904 .vendor = PCI_VENDOR_ID_VIA, 905 .device = 0x95d0, 906 .subvendor = PCI_ANY_ID, 907 .subdevice = PCI_ANY_ID, 908 .driver_data = (kernel_ulong_t)&sdhci_via, 909 }, 910 911 { 912 .vendor = PCI_VENDOR_ID_REALTEK, 913 .device = 0x5250, 914 .subvendor = PCI_ANY_ID, 915 .subdevice = PCI_ANY_ID, 916 .driver_data = (kernel_ulong_t)&sdhci_rtsx, 917 }, 918 919 { 920 .vendor = PCI_VENDOR_ID_INTEL, 921 .device = PCI_DEVICE_ID_INTEL_QRK_SD, 922 .subvendor = PCI_ANY_ID, 923 .subdevice = PCI_ANY_ID, 924 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk, 925 }, 926 927 { 928 .vendor = PCI_VENDOR_ID_INTEL, 929 .device = PCI_DEVICE_ID_INTEL_MRST_SD0, 930 .subvendor = PCI_ANY_ID, 931 .subdevice = PCI_ANY_ID, 932 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0, 933 }, 934 935 { 936 .vendor = PCI_VENDOR_ID_INTEL, 937 .device = PCI_DEVICE_ID_INTEL_MRST_SD1, 938 .subvendor = PCI_ANY_ID, 939 .subdevice = PCI_ANY_ID, 940 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 941 }, 942 943 { 944 .vendor = PCI_VENDOR_ID_INTEL, 945 .device = PCI_DEVICE_ID_INTEL_MRST_SD2, 946 .subvendor = PCI_ANY_ID, 947 .subdevice = PCI_ANY_ID, 948 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 949 }, 950 951 { 952 .vendor = PCI_VENDOR_ID_INTEL, 953 .device = PCI_DEVICE_ID_INTEL_MFD_SD, 954 .subvendor = PCI_ANY_ID, 955 .subdevice = PCI_ANY_ID, 956 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 957 }, 958 959 { 960 .vendor = PCI_VENDOR_ID_INTEL, 961 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1, 962 .subvendor = PCI_ANY_ID, 963 .subdevice = PCI_ANY_ID, 964 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 965 }, 966 967 { 968 .vendor = PCI_VENDOR_ID_INTEL, 969 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2, 970 .subvendor = PCI_ANY_ID, 971 .subdevice = PCI_ANY_ID, 972 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 973 }, 974 975 { 976 .vendor = PCI_VENDOR_ID_INTEL, 977 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0, 978 .subvendor = PCI_ANY_ID, 979 .subdevice = PCI_ANY_ID, 980 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 981 }, 982 983 { 984 .vendor = PCI_VENDOR_ID_INTEL, 985 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1, 986 .subvendor = PCI_ANY_ID, 987 .subdevice = PCI_ANY_ID, 988 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 989 }, 990 991 { 992 .vendor = PCI_VENDOR_ID_INTEL, 993 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0, 994 .subvendor = PCI_ANY_ID, 995 .subdevice = PCI_ANY_ID, 996 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 997 }, 998 999 { 1000 .vendor = PCI_VENDOR_ID_INTEL, 1001 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1, 1002 .subvendor = PCI_ANY_ID, 1003 .subdevice = PCI_ANY_ID, 1004 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1005 }, 1006 1007 { 1008 .vendor = PCI_VENDOR_ID_INTEL, 1009 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC, 1010 .subvendor = PCI_ANY_ID, 1011 .subdevice = PCI_ANY_ID, 1012 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1013 }, 1014 1015 { 1016 .vendor = PCI_VENDOR_ID_INTEL, 1017 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, 1018 .subvendor = PCI_ANY_ID, 1019 .subdevice = PCI_ANY_ID, 1020 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1021 }, 1022 1023 { 1024 .vendor = PCI_VENDOR_ID_INTEL, 1025 .device = PCI_DEVICE_ID_INTEL_BYT_SD, 1026 .subvendor = PCI_ANY_ID, 1027 .subdevice = PCI_ANY_ID, 1028 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1029 }, 1030 1031 { 1032 .vendor = PCI_VENDOR_ID_INTEL, 1033 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2, 1034 .subvendor = PCI_ANY_ID, 1035 .subdevice = PCI_ANY_ID, 1036 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1037 }, 1038 1039 { 1040 .vendor = PCI_VENDOR_ID_INTEL, 1041 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC, 1042 .subvendor = PCI_ANY_ID, 1043 .subdevice = PCI_ANY_ID, 1044 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1045 }, 1046 1047 { 1048 .vendor = PCI_VENDOR_ID_INTEL, 1049 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO, 1050 .subvendor = PCI_ANY_ID, 1051 .subdevice = PCI_ANY_ID, 1052 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1053 }, 1054 1055 { 1056 .vendor = PCI_VENDOR_ID_INTEL, 1057 .device = PCI_DEVICE_ID_INTEL_BSW_SD, 1058 .subvendor = PCI_ANY_ID, 1059 .subdevice = PCI_ANY_ID, 1060 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1061 }, 1062 1063 { 1064 .vendor = PCI_VENDOR_ID_INTEL, 1065 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0, 1066 .subvendor = PCI_ANY_ID, 1067 .subdevice = PCI_ANY_ID, 1068 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1069 }, 1070 1071 { 1072 .vendor = PCI_VENDOR_ID_INTEL, 1073 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1, 1074 .subvendor = PCI_ANY_ID, 1075 .subdevice = PCI_ANY_ID, 1076 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1077 }, 1078 1079 { 1080 .vendor = PCI_VENDOR_ID_INTEL, 1081 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2, 1082 .subvendor = PCI_ANY_ID, 1083 .subdevice = PCI_ANY_ID, 1084 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1085 }, 1086 1087 { 1088 .vendor = PCI_VENDOR_ID_INTEL, 1089 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0, 1090 .subvendor = PCI_ANY_ID, 1091 .subdevice = PCI_ANY_ID, 1092 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1093 }, 1094 1095 { 1096 .vendor = PCI_VENDOR_ID_INTEL, 1097 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1, 1098 .subvendor = PCI_ANY_ID, 1099 .subdevice = PCI_ANY_ID, 1100 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1101 }, 1102 1103 { 1104 .vendor = PCI_VENDOR_ID_INTEL, 1105 .device = PCI_DEVICE_ID_INTEL_MRFLD_MMC, 1106 .subvendor = PCI_ANY_ID, 1107 .subdevice = PCI_ANY_ID, 1108 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfld_mmc, 1109 }, 1110 1111 { 1112 .vendor = PCI_VENDOR_ID_INTEL, 1113 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC, 1114 .subvendor = PCI_ANY_ID, 1115 .subdevice = PCI_ANY_ID, 1116 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1117 }, 1118 1119 { 1120 .vendor = PCI_VENDOR_ID_INTEL, 1121 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO, 1122 .subvendor = PCI_ANY_ID, 1123 .subdevice = PCI_ANY_ID, 1124 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1125 }, 1126 1127 { 1128 .vendor = PCI_VENDOR_ID_INTEL, 1129 .device = PCI_DEVICE_ID_INTEL_SPT_SD, 1130 .subvendor = PCI_ANY_ID, 1131 .subdevice = PCI_ANY_ID, 1132 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1133 }, 1134 1135 { 1136 .vendor = PCI_VENDOR_ID_INTEL, 1137 .device = PCI_DEVICE_ID_INTEL_DNV_EMMC, 1138 .subvendor = PCI_ANY_ID, 1139 .subdevice = PCI_ANY_ID, 1140 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1141 }, 1142 1143 { 1144 .vendor = PCI_VENDOR_ID_INTEL, 1145 .device = PCI_DEVICE_ID_INTEL_BXT_EMMC, 1146 .subvendor = PCI_ANY_ID, 1147 .subdevice = PCI_ANY_ID, 1148 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1149 }, 1150 1151 { 1152 .vendor = PCI_VENDOR_ID_INTEL, 1153 .device = PCI_DEVICE_ID_INTEL_BXT_SDIO, 1154 .subvendor = PCI_ANY_ID, 1155 .subdevice = PCI_ANY_ID, 1156 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1157 }, 1158 1159 { 1160 .vendor = PCI_VENDOR_ID_INTEL, 1161 .device = PCI_DEVICE_ID_INTEL_BXT_SD, 1162 .subvendor = PCI_ANY_ID, 1163 .subdevice = PCI_ANY_ID, 1164 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1165 }, 1166 1167 { 1168 .vendor = PCI_VENDOR_ID_INTEL, 1169 .device = PCI_DEVICE_ID_INTEL_BXTM_EMMC, 1170 .subvendor = PCI_ANY_ID, 1171 .subdevice = PCI_ANY_ID, 1172 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1173 }, 1174 1175 { 1176 .vendor = PCI_VENDOR_ID_INTEL, 1177 .device = PCI_DEVICE_ID_INTEL_BXTM_SDIO, 1178 .subvendor = PCI_ANY_ID, 1179 .subdevice = PCI_ANY_ID, 1180 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1181 }, 1182 1183 { 1184 .vendor = PCI_VENDOR_ID_INTEL, 1185 .device = PCI_DEVICE_ID_INTEL_BXTM_SD, 1186 .subvendor = PCI_ANY_ID, 1187 .subdevice = PCI_ANY_ID, 1188 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1189 }, 1190 1191 { 1192 .vendor = PCI_VENDOR_ID_INTEL, 1193 .device = PCI_DEVICE_ID_INTEL_APL_EMMC, 1194 .subvendor = PCI_ANY_ID, 1195 .subdevice = PCI_ANY_ID, 1196 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1197 }, 1198 1199 { 1200 .vendor = PCI_VENDOR_ID_INTEL, 1201 .device = PCI_DEVICE_ID_INTEL_APL_SDIO, 1202 .subvendor = PCI_ANY_ID, 1203 .subdevice = PCI_ANY_ID, 1204 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1205 }, 1206 1207 { 1208 .vendor = PCI_VENDOR_ID_INTEL, 1209 .device = PCI_DEVICE_ID_INTEL_APL_SD, 1210 .subvendor = PCI_ANY_ID, 1211 .subdevice = PCI_ANY_ID, 1212 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1213 }, 1214 1215 { 1216 .vendor = PCI_VENDOR_ID_O2, 1217 .device = PCI_DEVICE_ID_O2_8120, 1218 .subvendor = PCI_ANY_ID, 1219 .subdevice = PCI_ANY_ID, 1220 .driver_data = (kernel_ulong_t)&sdhci_o2, 1221 }, 1222 1223 { 1224 .vendor = PCI_VENDOR_ID_O2, 1225 .device = PCI_DEVICE_ID_O2_8220, 1226 .subvendor = PCI_ANY_ID, 1227 .subdevice = PCI_ANY_ID, 1228 .driver_data = (kernel_ulong_t)&sdhci_o2, 1229 }, 1230 1231 { 1232 .vendor = PCI_VENDOR_ID_O2, 1233 .device = PCI_DEVICE_ID_O2_8221, 1234 .subvendor = PCI_ANY_ID, 1235 .subdevice = PCI_ANY_ID, 1236 .driver_data = (kernel_ulong_t)&sdhci_o2, 1237 }, 1238 1239 { 1240 .vendor = PCI_VENDOR_ID_O2, 1241 .device = PCI_DEVICE_ID_O2_8320, 1242 .subvendor = PCI_ANY_ID, 1243 .subdevice = PCI_ANY_ID, 1244 .driver_data = (kernel_ulong_t)&sdhci_o2, 1245 }, 1246 1247 { 1248 .vendor = PCI_VENDOR_ID_O2, 1249 .device = PCI_DEVICE_ID_O2_8321, 1250 .subvendor = PCI_ANY_ID, 1251 .subdevice = PCI_ANY_ID, 1252 .driver_data = (kernel_ulong_t)&sdhci_o2, 1253 }, 1254 1255 { 1256 .vendor = PCI_VENDOR_ID_O2, 1257 .device = PCI_DEVICE_ID_O2_FUJIN2, 1258 .subvendor = PCI_ANY_ID, 1259 .subdevice = PCI_ANY_ID, 1260 .driver_data = (kernel_ulong_t)&sdhci_o2, 1261 }, 1262 1263 { 1264 .vendor = PCI_VENDOR_ID_O2, 1265 .device = PCI_DEVICE_ID_O2_SDS0, 1266 .subvendor = PCI_ANY_ID, 1267 .subdevice = PCI_ANY_ID, 1268 .driver_data = (kernel_ulong_t)&sdhci_o2, 1269 }, 1270 1271 { 1272 .vendor = PCI_VENDOR_ID_O2, 1273 .device = PCI_DEVICE_ID_O2_SDS1, 1274 .subvendor = PCI_ANY_ID, 1275 .subdevice = PCI_ANY_ID, 1276 .driver_data = (kernel_ulong_t)&sdhci_o2, 1277 }, 1278 1279 { 1280 .vendor = PCI_VENDOR_ID_O2, 1281 .device = PCI_DEVICE_ID_O2_SEABIRD0, 1282 .subvendor = PCI_ANY_ID, 1283 .subdevice = PCI_ANY_ID, 1284 .driver_data = (kernel_ulong_t)&sdhci_o2, 1285 }, 1286 1287 { 1288 .vendor = PCI_VENDOR_ID_O2, 1289 .device = PCI_DEVICE_ID_O2_SEABIRD1, 1290 .subvendor = PCI_ANY_ID, 1291 .subdevice = PCI_ANY_ID, 1292 .driver_data = (kernel_ulong_t)&sdhci_o2, 1293 }, 1294 { 1295 .vendor = PCI_VENDOR_ID_AMD, 1296 .device = PCI_ANY_ID, 1297 .class = PCI_CLASS_SYSTEM_SDHCI << 8, 1298 .class_mask = 0xFFFF00, 1299 .subvendor = PCI_ANY_ID, 1300 .subdevice = PCI_ANY_ID, 1301 .driver_data = (kernel_ulong_t)&sdhci_amd, 1302 }, 1303 { /* Generic SD host controller */ 1304 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) 1305 }, 1306 1307 { /* end: all zeroes */ }, 1308 }; 1309 1310 MODULE_DEVICE_TABLE(pci, pci_ids); 1311 1312 /*****************************************************************************\ 1313 * * 1314 * SDHCI core callbacks * 1315 * * 1316 \*****************************************************************************/ 1317 1318 static int sdhci_pci_enable_dma(struct sdhci_host *host) 1319 { 1320 struct sdhci_pci_slot *slot; 1321 struct pci_dev *pdev; 1322 1323 slot = sdhci_priv(host); 1324 pdev = slot->chip->pdev; 1325 1326 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1327 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1328 (host->flags & SDHCI_USE_SDMA)) { 1329 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1330 "doesn't fully claim to support it.\n"); 1331 } 1332 1333 pci_set_master(pdev); 1334 1335 return 0; 1336 } 1337 1338 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width) 1339 { 1340 u8 ctrl; 1341 1342 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1343 1344 switch (width) { 1345 case MMC_BUS_WIDTH_8: 1346 ctrl |= SDHCI_CTRL_8BITBUS; 1347 ctrl &= ~SDHCI_CTRL_4BITBUS; 1348 break; 1349 case MMC_BUS_WIDTH_4: 1350 ctrl |= SDHCI_CTRL_4BITBUS; 1351 ctrl &= ~SDHCI_CTRL_8BITBUS; 1352 break; 1353 default: 1354 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS); 1355 break; 1356 } 1357 1358 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1359 } 1360 1361 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1362 { 1363 struct sdhci_pci_slot *slot = sdhci_priv(host); 1364 int rst_n_gpio = slot->rst_n_gpio; 1365 1366 if (!gpio_is_valid(rst_n_gpio)) 1367 return; 1368 gpio_set_value_cansleep(rst_n_gpio, 0); 1369 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1370 udelay(10); 1371 gpio_set_value_cansleep(rst_n_gpio, 1); 1372 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1373 usleep_range(300, 1000); 1374 } 1375 1376 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1377 { 1378 struct sdhci_pci_slot *slot = sdhci_priv(host); 1379 1380 if (slot->hw_reset) 1381 slot->hw_reset(host); 1382 } 1383 1384 static int sdhci_pci_select_drive_strength(struct sdhci_host *host, 1385 struct mmc_card *card, 1386 unsigned int max_dtr, int host_drv, 1387 int card_drv, int *drv_type) 1388 { 1389 struct sdhci_pci_slot *slot = sdhci_priv(host); 1390 1391 if (!slot->select_drive_strength) 1392 return 0; 1393 1394 return slot->select_drive_strength(host, card, max_dtr, host_drv, 1395 card_drv, drv_type); 1396 } 1397 1398 static const struct sdhci_ops sdhci_pci_ops = { 1399 .set_clock = sdhci_set_clock, 1400 .enable_dma = sdhci_pci_enable_dma, 1401 .set_bus_width = sdhci_pci_set_bus_width, 1402 .reset = sdhci_reset, 1403 .set_uhs_signaling = sdhci_set_uhs_signaling, 1404 .hw_reset = sdhci_pci_hw_reset, 1405 .select_drive_strength = sdhci_pci_select_drive_strength, 1406 }; 1407 1408 /*****************************************************************************\ 1409 * * 1410 * Suspend/resume * 1411 * * 1412 \*****************************************************************************/ 1413 1414 #ifdef CONFIG_PM_SLEEP 1415 static int sdhci_pci_suspend(struct device *dev) 1416 { 1417 struct pci_dev *pdev = to_pci_dev(dev); 1418 struct sdhci_pci_chip *chip; 1419 struct sdhci_pci_slot *slot; 1420 mmc_pm_flag_t slot_pm_flags; 1421 mmc_pm_flag_t pm_flags = 0; 1422 int i, ret; 1423 1424 chip = pci_get_drvdata(pdev); 1425 if (!chip) 1426 return 0; 1427 1428 for (i = 0; i < chip->num_slots; i++) { 1429 slot = chip->slots[i]; 1430 if (!slot) 1431 continue; 1432 1433 ret = sdhci_suspend_host(slot->host); 1434 1435 if (ret) 1436 goto err_pci_suspend; 1437 1438 slot_pm_flags = slot->host->mmc->pm_flags; 1439 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1440 sdhci_enable_irq_wakeups(slot->host); 1441 1442 pm_flags |= slot_pm_flags; 1443 } 1444 1445 if (chip->fixes && chip->fixes->suspend) { 1446 ret = chip->fixes->suspend(chip); 1447 if (ret) 1448 goto err_pci_suspend; 1449 } 1450 1451 if (pm_flags & MMC_PM_KEEP_POWER) { 1452 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1453 device_init_wakeup(dev, true); 1454 else 1455 device_init_wakeup(dev, false); 1456 } else 1457 device_init_wakeup(dev, false); 1458 1459 return 0; 1460 1461 err_pci_suspend: 1462 while (--i >= 0) 1463 sdhci_resume_host(chip->slots[i]->host); 1464 return ret; 1465 } 1466 1467 static int sdhci_pci_resume(struct device *dev) 1468 { 1469 struct pci_dev *pdev = to_pci_dev(dev); 1470 struct sdhci_pci_chip *chip; 1471 struct sdhci_pci_slot *slot; 1472 int i, ret; 1473 1474 chip = pci_get_drvdata(pdev); 1475 if (!chip) 1476 return 0; 1477 1478 if (chip->fixes && chip->fixes->resume) { 1479 ret = chip->fixes->resume(chip); 1480 if (ret) 1481 return ret; 1482 } 1483 1484 for (i = 0; i < chip->num_slots; i++) { 1485 slot = chip->slots[i]; 1486 if (!slot) 1487 continue; 1488 1489 ret = sdhci_resume_host(slot->host); 1490 if (ret) 1491 return ret; 1492 } 1493 1494 return 0; 1495 } 1496 #endif 1497 1498 #ifdef CONFIG_PM 1499 static int sdhci_pci_runtime_suspend(struct device *dev) 1500 { 1501 struct pci_dev *pdev = to_pci_dev(dev); 1502 struct sdhci_pci_chip *chip; 1503 struct sdhci_pci_slot *slot; 1504 int i, ret; 1505 1506 chip = pci_get_drvdata(pdev); 1507 if (!chip) 1508 return 0; 1509 1510 for (i = 0; i < chip->num_slots; i++) { 1511 slot = chip->slots[i]; 1512 if (!slot) 1513 continue; 1514 1515 ret = sdhci_runtime_suspend_host(slot->host); 1516 1517 if (ret) 1518 goto err_pci_runtime_suspend; 1519 } 1520 1521 if (chip->fixes && chip->fixes->suspend) { 1522 ret = chip->fixes->suspend(chip); 1523 if (ret) 1524 goto err_pci_runtime_suspend; 1525 } 1526 1527 return 0; 1528 1529 err_pci_runtime_suspend: 1530 while (--i >= 0) 1531 sdhci_runtime_resume_host(chip->slots[i]->host); 1532 return ret; 1533 } 1534 1535 static int sdhci_pci_runtime_resume(struct device *dev) 1536 { 1537 struct pci_dev *pdev = to_pci_dev(dev); 1538 struct sdhci_pci_chip *chip; 1539 struct sdhci_pci_slot *slot; 1540 int i, ret; 1541 1542 chip = pci_get_drvdata(pdev); 1543 if (!chip) 1544 return 0; 1545 1546 if (chip->fixes && chip->fixes->resume) { 1547 ret = chip->fixes->resume(chip); 1548 if (ret) 1549 return ret; 1550 } 1551 1552 for (i = 0; i < chip->num_slots; i++) { 1553 slot = chip->slots[i]; 1554 if (!slot) 1555 continue; 1556 1557 ret = sdhci_runtime_resume_host(slot->host); 1558 if (ret) 1559 return ret; 1560 } 1561 1562 return 0; 1563 } 1564 #endif 1565 1566 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1567 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1568 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1569 sdhci_pci_runtime_resume, NULL) 1570 }; 1571 1572 /*****************************************************************************\ 1573 * * 1574 * Device probing/removal * 1575 * * 1576 \*****************************************************************************/ 1577 1578 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1579 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1580 int slotno) 1581 { 1582 struct sdhci_pci_slot *slot; 1583 struct sdhci_host *host; 1584 int ret, bar = first_bar + slotno; 1585 1586 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1587 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1588 return ERR_PTR(-ENODEV); 1589 } 1590 1591 if (pci_resource_len(pdev, bar) < 0x100) { 1592 dev_err(&pdev->dev, "Invalid iomem size. You may " 1593 "experience problems.\n"); 1594 } 1595 1596 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1597 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1598 return ERR_PTR(-ENODEV); 1599 } 1600 1601 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1602 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1603 return ERR_PTR(-ENODEV); 1604 } 1605 1606 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot)); 1607 if (IS_ERR(host)) { 1608 dev_err(&pdev->dev, "cannot allocate host\n"); 1609 return ERR_CAST(host); 1610 } 1611 1612 slot = sdhci_priv(host); 1613 1614 slot->chip = chip; 1615 slot->host = host; 1616 slot->rst_n_gpio = -EINVAL; 1617 slot->cd_gpio = -EINVAL; 1618 slot->cd_idx = -1; 1619 1620 /* Retrieve platform data if there is any */ 1621 if (*sdhci_pci_get_data) 1622 slot->data = sdhci_pci_get_data(pdev, slotno); 1623 1624 if (slot->data) { 1625 if (slot->data->setup) { 1626 ret = slot->data->setup(slot->data); 1627 if (ret) { 1628 dev_err(&pdev->dev, "platform setup failed\n"); 1629 goto free; 1630 } 1631 } 1632 slot->rst_n_gpio = slot->data->rst_n_gpio; 1633 slot->cd_gpio = slot->data->cd_gpio; 1634 } 1635 1636 host->hw_name = "PCI"; 1637 host->ops = &sdhci_pci_ops; 1638 host->quirks = chip->quirks; 1639 host->quirks2 = chip->quirks2; 1640 1641 host->irq = pdev->irq; 1642 1643 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1644 if (ret) { 1645 dev_err(&pdev->dev, "cannot request region\n"); 1646 goto cleanup; 1647 } 1648 1649 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1650 1651 if (chip->fixes && chip->fixes->probe_slot) { 1652 ret = chip->fixes->probe_slot(slot); 1653 if (ret) 1654 goto cleanup; 1655 } 1656 1657 if (gpio_is_valid(slot->rst_n_gpio)) { 1658 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1659 gpio_direction_output(slot->rst_n_gpio, 1); 1660 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1661 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1662 } else { 1663 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1664 slot->rst_n_gpio = -EINVAL; 1665 } 1666 } 1667 1668 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; 1669 host->mmc->slotno = slotno; 1670 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1671 1672 if (slot->cd_idx >= 0 && 1673 mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx, 1674 slot->cd_override_level, 0, NULL)) { 1675 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 1676 slot->cd_idx = -1; 1677 } 1678 1679 ret = sdhci_add_host(host); 1680 if (ret) 1681 goto remove; 1682 1683 sdhci_pci_add_own_cd(slot); 1684 1685 /* 1686 * Check if the chip needs a separate GPIO for card detect to wake up 1687 * from runtime suspend. If it is not there, don't allow runtime PM. 1688 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 1689 */ 1690 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 1691 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 1692 chip->allow_runtime_pm = false; 1693 1694 return slot; 1695 1696 remove: 1697 if (chip->fixes && chip->fixes->remove_slot) 1698 chip->fixes->remove_slot(slot, 0); 1699 1700 cleanup: 1701 if (slot->data && slot->data->cleanup) 1702 slot->data->cleanup(slot->data); 1703 1704 free: 1705 sdhci_free_host(host); 1706 1707 return ERR_PTR(ret); 1708 } 1709 1710 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 1711 { 1712 int dead; 1713 u32 scratch; 1714 1715 sdhci_pci_remove_own_cd(slot); 1716 1717 dead = 0; 1718 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 1719 if (scratch == (u32)-1) 1720 dead = 1; 1721 1722 sdhci_remove_host(slot->host, dead); 1723 1724 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 1725 slot->chip->fixes->remove_slot(slot, dead); 1726 1727 if (slot->data && slot->data->cleanup) 1728 slot->data->cleanup(slot->data); 1729 1730 sdhci_free_host(slot->host); 1731 } 1732 1733 static void sdhci_pci_runtime_pm_allow(struct device *dev) 1734 { 1735 pm_suspend_ignore_children(dev, 1); 1736 pm_runtime_set_autosuspend_delay(dev, 50); 1737 pm_runtime_use_autosuspend(dev); 1738 pm_runtime_allow(dev); 1739 /* Stay active until mmc core scans for a card */ 1740 pm_runtime_put_noidle(dev); 1741 } 1742 1743 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 1744 { 1745 pm_runtime_forbid(dev); 1746 pm_runtime_get_noresume(dev); 1747 } 1748 1749 static int sdhci_pci_probe(struct pci_dev *pdev, 1750 const struct pci_device_id *ent) 1751 { 1752 struct sdhci_pci_chip *chip; 1753 struct sdhci_pci_slot *slot; 1754 1755 u8 slots, first_bar; 1756 int ret, i; 1757 1758 BUG_ON(pdev == NULL); 1759 BUG_ON(ent == NULL); 1760 1761 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 1762 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 1763 1764 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 1765 if (ret) 1766 return ret; 1767 1768 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 1769 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 1770 if (slots == 0) 1771 return -ENODEV; 1772 1773 BUG_ON(slots > MAX_SLOTS); 1774 1775 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 1776 if (ret) 1777 return ret; 1778 1779 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 1780 1781 if (first_bar > 5) { 1782 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 1783 return -ENODEV; 1784 } 1785 1786 ret = pcim_enable_device(pdev); 1787 if (ret) 1788 return ret; 1789 1790 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 1791 if (!chip) 1792 return -ENOMEM; 1793 1794 chip->pdev = pdev; 1795 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 1796 if (chip->fixes) { 1797 chip->quirks = chip->fixes->quirks; 1798 chip->quirks2 = chip->fixes->quirks2; 1799 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 1800 } 1801 chip->num_slots = slots; 1802 1803 pci_set_drvdata(pdev, chip); 1804 1805 if (chip->fixes && chip->fixes->probe) { 1806 ret = chip->fixes->probe(chip); 1807 if (ret) 1808 return ret; 1809 } 1810 1811 slots = chip->num_slots; /* Quirk may have changed this */ 1812 1813 for (i = 0; i < slots; i++) { 1814 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 1815 if (IS_ERR(slot)) { 1816 for (i--; i >= 0; i--) 1817 sdhci_pci_remove_slot(chip->slots[i]); 1818 return PTR_ERR(slot); 1819 } 1820 1821 chip->slots[i] = slot; 1822 } 1823 1824 if (chip->allow_runtime_pm) 1825 sdhci_pci_runtime_pm_allow(&pdev->dev); 1826 1827 return 0; 1828 } 1829 1830 static void sdhci_pci_remove(struct pci_dev *pdev) 1831 { 1832 int i; 1833 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1834 1835 if (chip->allow_runtime_pm) 1836 sdhci_pci_runtime_pm_forbid(&pdev->dev); 1837 1838 for (i = 0; i < chip->num_slots; i++) 1839 sdhci_pci_remove_slot(chip->slots[i]); 1840 } 1841 1842 static struct pci_driver sdhci_driver = { 1843 .name = "sdhci-pci", 1844 .id_table = pci_ids, 1845 .probe = sdhci_pci_probe, 1846 .remove = sdhci_pci_remove, 1847 .driver = { 1848 .pm = &sdhci_pci_pm_ops 1849 }, 1850 }; 1851 1852 module_pci_driver(sdhci_driver); 1853 1854 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 1855 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 1856 MODULE_LICENSE("GPL"); 1857