1 /*  linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2  *
3  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation; either version 2 of the License, or (at
8  * your option) any later version.
9  *
10  * Thanks to the following companies for their support:
11  *
12  *     - JMicron (hardware and technical support)
13  */
14 
15 #include <linux/bitfield.h>
16 #include <linux/string.h>
17 #include <linux/delay.h>
18 #include <linux/highmem.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/slab.h>
23 #include <linux/device.h>
24 #include <linux/mmc/host.h>
25 #include <linux/mmc/mmc.h>
26 #include <linux/scatterlist.h>
27 #include <linux/io.h>
28 #include <linux/gpio.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/mmc/slot-gpio.h>
31 #include <linux/mmc/sdhci-pci-data.h>
32 #include <linux/acpi.h>
33 
34 #include "cqhci.h"
35 
36 #include "sdhci.h"
37 #include "sdhci-pci.h"
38 
39 static void sdhci_pci_hw_reset(struct sdhci_host *host);
40 
41 #ifdef CONFIG_PM_SLEEP
42 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip)
43 {
44 	mmc_pm_flag_t pm_flags = 0;
45 	bool cap_cd_wake = false;
46 	int i;
47 
48 	for (i = 0; i < chip->num_slots; i++) {
49 		struct sdhci_pci_slot *slot = chip->slots[i];
50 
51 		if (slot) {
52 			pm_flags |= slot->host->mmc->pm_flags;
53 			if (slot->host->mmc->caps & MMC_CAP_CD_WAKE)
54 				cap_cd_wake = true;
55 		}
56 	}
57 
58 	if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ))
59 		return device_wakeup_enable(&chip->pdev->dev);
60 	else if (!cap_cd_wake)
61 		return device_wakeup_disable(&chip->pdev->dev);
62 
63 	return 0;
64 }
65 
66 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
67 {
68 	int i, ret;
69 
70 	sdhci_pci_init_wakeup(chip);
71 
72 	for (i = 0; i < chip->num_slots; i++) {
73 		struct sdhci_pci_slot *slot = chip->slots[i];
74 		struct sdhci_host *host;
75 
76 		if (!slot)
77 			continue;
78 
79 		host = slot->host;
80 
81 		if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3)
82 			mmc_retune_needed(host->mmc);
83 
84 		ret = sdhci_suspend_host(host);
85 		if (ret)
86 			goto err_pci_suspend;
87 
88 		if (device_may_wakeup(&chip->pdev->dev))
89 			mmc_gpio_set_cd_wake(host->mmc, true);
90 	}
91 
92 	return 0;
93 
94 err_pci_suspend:
95 	while (--i >= 0)
96 		sdhci_resume_host(chip->slots[i]->host);
97 	return ret;
98 }
99 
100 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip)
101 {
102 	struct sdhci_pci_slot *slot;
103 	int i, ret;
104 
105 	for (i = 0; i < chip->num_slots; i++) {
106 		slot = chip->slots[i];
107 		if (!slot)
108 			continue;
109 
110 		ret = sdhci_resume_host(slot->host);
111 		if (ret)
112 			return ret;
113 
114 		mmc_gpio_set_cd_wake(slot->host->mmc, false);
115 	}
116 
117 	return 0;
118 }
119 
120 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip)
121 {
122 	int ret;
123 
124 	ret = cqhci_suspend(chip->slots[0]->host->mmc);
125 	if (ret)
126 		return ret;
127 
128 	return sdhci_pci_suspend_host(chip);
129 }
130 
131 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip)
132 {
133 	int ret;
134 
135 	ret = sdhci_pci_resume_host(chip);
136 	if (ret)
137 		return ret;
138 
139 	return cqhci_resume(chip->slots[0]->host->mmc);
140 }
141 #endif
142 
143 #ifdef CONFIG_PM
144 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip)
145 {
146 	struct sdhci_pci_slot *slot;
147 	struct sdhci_host *host;
148 	int i, ret;
149 
150 	for (i = 0; i < chip->num_slots; i++) {
151 		slot = chip->slots[i];
152 		if (!slot)
153 			continue;
154 
155 		host = slot->host;
156 
157 		ret = sdhci_runtime_suspend_host(host);
158 		if (ret)
159 			goto err_pci_runtime_suspend;
160 
161 		if (chip->rpm_retune &&
162 		    host->tuning_mode != SDHCI_TUNING_MODE_3)
163 			mmc_retune_needed(host->mmc);
164 	}
165 
166 	return 0;
167 
168 err_pci_runtime_suspend:
169 	while (--i >= 0)
170 		sdhci_runtime_resume_host(chip->slots[i]->host);
171 	return ret;
172 }
173 
174 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip)
175 {
176 	struct sdhci_pci_slot *slot;
177 	int i, ret;
178 
179 	for (i = 0; i < chip->num_slots; i++) {
180 		slot = chip->slots[i];
181 		if (!slot)
182 			continue;
183 
184 		ret = sdhci_runtime_resume_host(slot->host);
185 		if (ret)
186 			return ret;
187 	}
188 
189 	return 0;
190 }
191 
192 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip)
193 {
194 	int ret;
195 
196 	ret = cqhci_suspend(chip->slots[0]->host->mmc);
197 	if (ret)
198 		return ret;
199 
200 	return sdhci_pci_runtime_suspend_host(chip);
201 }
202 
203 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip)
204 {
205 	int ret;
206 
207 	ret = sdhci_pci_runtime_resume_host(chip);
208 	if (ret)
209 		return ret;
210 
211 	return cqhci_resume(chip->slots[0]->host->mmc);
212 }
213 #endif
214 
215 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask)
216 {
217 	int cmd_error = 0;
218 	int data_error = 0;
219 
220 	if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
221 		return intmask;
222 
223 	cqhci_irq(host->mmc, intmask, cmd_error, data_error);
224 
225 	return 0;
226 }
227 
228 static void sdhci_pci_dumpregs(struct mmc_host *mmc)
229 {
230 	sdhci_dumpregs(mmc_priv(mmc));
231 }
232 
233 /*****************************************************************************\
234  *                                                                           *
235  * Hardware specific quirk handling                                          *
236  *                                                                           *
237 \*****************************************************************************/
238 
239 static int ricoh_probe(struct sdhci_pci_chip *chip)
240 {
241 	if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
242 	    chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
243 		chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
244 	return 0;
245 }
246 
247 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
248 {
249 	slot->host->caps =
250 		((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
251 			& SDHCI_TIMEOUT_CLK_MASK) |
252 
253 		((0x21 << SDHCI_CLOCK_BASE_SHIFT)
254 			& SDHCI_CLOCK_BASE_MASK) |
255 
256 		SDHCI_TIMEOUT_CLK_UNIT |
257 		SDHCI_CAN_VDD_330 |
258 		SDHCI_CAN_DO_HISPD |
259 		SDHCI_CAN_DO_SDMA;
260 	return 0;
261 }
262 
263 #ifdef CONFIG_PM_SLEEP
264 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
265 {
266 	/* Apply a delay to allow controller to settle */
267 	/* Otherwise it becomes confused if card state changed
268 		during suspend */
269 	msleep(500);
270 	return sdhci_pci_resume_host(chip);
271 }
272 #endif
273 
274 static const struct sdhci_pci_fixes sdhci_ricoh = {
275 	.probe		= ricoh_probe,
276 	.quirks		= SDHCI_QUIRK_32BIT_DMA_ADDR |
277 			  SDHCI_QUIRK_FORCE_DMA |
278 			  SDHCI_QUIRK_CLOCK_BEFORE_RESET,
279 };
280 
281 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
282 	.probe_slot	= ricoh_mmc_probe_slot,
283 #ifdef CONFIG_PM_SLEEP
284 	.resume		= ricoh_mmc_resume,
285 #endif
286 	.quirks		= SDHCI_QUIRK_32BIT_DMA_ADDR |
287 			  SDHCI_QUIRK_CLOCK_BEFORE_RESET |
288 			  SDHCI_QUIRK_NO_CARD_NO_RESET |
289 			  SDHCI_QUIRK_MISSING_CAPS
290 };
291 
292 static const struct sdhci_pci_fixes sdhci_ene_712 = {
293 	.quirks		= SDHCI_QUIRK_SINGLE_POWER_WRITE |
294 			  SDHCI_QUIRK_BROKEN_DMA,
295 };
296 
297 static const struct sdhci_pci_fixes sdhci_ene_714 = {
298 	.quirks		= SDHCI_QUIRK_SINGLE_POWER_WRITE |
299 			  SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
300 			  SDHCI_QUIRK_BROKEN_DMA,
301 };
302 
303 static const struct sdhci_pci_fixes sdhci_cafe = {
304 	.quirks		= SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
305 			  SDHCI_QUIRK_NO_BUSY_IRQ |
306 			  SDHCI_QUIRK_BROKEN_CARD_DETECTION |
307 			  SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
308 };
309 
310 static const struct sdhci_pci_fixes sdhci_intel_qrk = {
311 	.quirks		= SDHCI_QUIRK_NO_HISPD_BIT,
312 };
313 
314 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
315 {
316 	slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
317 	return 0;
318 }
319 
320 /*
321  * ADMA operation is disabled for Moorestown platform due to
322  * hardware bugs.
323  */
324 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
325 {
326 	/*
327 	 * slots number is fixed here for MRST as SDIO3/5 are never used and
328 	 * have hardware bugs.
329 	 */
330 	chip->num_slots = 1;
331 	return 0;
332 }
333 
334 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
335 {
336 	slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
337 	return 0;
338 }
339 
340 #ifdef CONFIG_PM
341 
342 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
343 {
344 	struct sdhci_pci_slot *slot = dev_id;
345 	struct sdhci_host *host = slot->host;
346 
347 	mmc_detect_change(host->mmc, msecs_to_jiffies(200));
348 	return IRQ_HANDLED;
349 }
350 
351 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
352 {
353 	int err, irq, gpio = slot->cd_gpio;
354 
355 	slot->cd_gpio = -EINVAL;
356 	slot->cd_irq = -EINVAL;
357 
358 	if (!gpio_is_valid(gpio))
359 		return;
360 
361 	err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd");
362 	if (err < 0)
363 		goto out;
364 
365 	err = gpio_direction_input(gpio);
366 	if (err < 0)
367 		goto out_free;
368 
369 	irq = gpio_to_irq(gpio);
370 	if (irq < 0)
371 		goto out_free;
372 
373 	err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
374 			  IRQF_TRIGGER_FALLING, "sd_cd", slot);
375 	if (err)
376 		goto out_free;
377 
378 	slot->cd_gpio = gpio;
379 	slot->cd_irq = irq;
380 
381 	return;
382 
383 out_free:
384 	devm_gpio_free(&slot->chip->pdev->dev, gpio);
385 out:
386 	dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
387 }
388 
389 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
390 {
391 	if (slot->cd_irq >= 0)
392 		free_irq(slot->cd_irq, slot);
393 }
394 
395 #else
396 
397 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
398 {
399 }
400 
401 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
402 {
403 }
404 
405 #endif
406 
407 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
408 {
409 	slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
410 	slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC;
411 	return 0;
412 }
413 
414 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
415 {
416 	slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
417 	return 0;
418 }
419 
420 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
421 	.quirks		= SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
422 	.probe_slot	= mrst_hc_probe_slot,
423 };
424 
425 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
426 	.quirks		= SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
427 	.probe		= mrst_hc_probe,
428 };
429 
430 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
431 	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
432 	.allow_runtime_pm = true,
433 	.own_cd_for_runtime_pm = true,
434 };
435 
436 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
437 	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
438 	.quirks2	= SDHCI_QUIRK2_HOST_OFF_CARD_ON,
439 	.allow_runtime_pm = true,
440 	.probe_slot	= mfd_sdio_probe_slot,
441 };
442 
443 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
444 	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
445 	.allow_runtime_pm = true,
446 	.probe_slot	= mfd_emmc_probe_slot,
447 };
448 
449 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
450 	.quirks		= SDHCI_QUIRK_BROKEN_ADMA,
451 	.probe_slot	= pch_hc_probe_slot,
452 };
453 
454 enum {
455 	INTEL_DSM_FNS		=  0,
456 	INTEL_DSM_V18_SWITCH	=  3,
457 	INTEL_DSM_V33_SWITCH	=  4,
458 	INTEL_DSM_DRV_STRENGTH	=  9,
459 	INTEL_DSM_D3_RETUNE	= 10,
460 };
461 
462 struct intel_host {
463 	u32	dsm_fns;
464 	int	drv_strength;
465 	bool	d3_retune;
466 	bool	rpm_retune_ok;
467 	u32	glk_rx_ctrl1;
468 	u32	glk_tun_val;
469 };
470 
471 static const guid_t intel_dsm_guid =
472 	GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
473 		  0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
474 
475 static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
476 		       unsigned int fn, u32 *result)
477 {
478 	union acpi_object *obj;
479 	int err = 0;
480 	size_t len;
481 
482 	obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
483 	if (!obj)
484 		return -EOPNOTSUPP;
485 
486 	if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) {
487 		err = -EINVAL;
488 		goto out;
489 	}
490 
491 	len = min_t(size_t, obj->buffer.length, 4);
492 
493 	*result = 0;
494 	memcpy(result, obj->buffer.pointer, len);
495 out:
496 	ACPI_FREE(obj);
497 
498 	return err;
499 }
500 
501 static int intel_dsm(struct intel_host *intel_host, struct device *dev,
502 		     unsigned int fn, u32 *result)
503 {
504 	if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
505 		return -EOPNOTSUPP;
506 
507 	return __intel_dsm(intel_host, dev, fn, result);
508 }
509 
510 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
511 			   struct mmc_host *mmc)
512 {
513 	int err;
514 	u32 val;
515 
516 	intel_host->d3_retune = true;
517 
518 	err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
519 	if (err) {
520 		pr_debug("%s: DSM not supported, error %d\n",
521 			 mmc_hostname(mmc), err);
522 		return;
523 	}
524 
525 	pr_debug("%s: DSM function mask %#x\n",
526 		 mmc_hostname(mmc), intel_host->dsm_fns);
527 
528 	err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val);
529 	intel_host->drv_strength = err ? 0 : val;
530 
531 	err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val);
532 	intel_host->d3_retune = err ? true : !!val;
533 }
534 
535 static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
536 {
537 	u8 reg;
538 
539 	reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
540 	reg |= 0x10;
541 	sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
542 	/* For eMMC, minimum is 1us but give it 9us for good measure */
543 	udelay(9);
544 	reg &= ~0x10;
545 	sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
546 	/* For eMMC, minimum is 200us but give it 300us for good measure */
547 	usleep_range(300, 1000);
548 }
549 
550 static int intel_select_drive_strength(struct mmc_card *card,
551 				       unsigned int max_dtr, int host_drv,
552 				       int card_drv, int *drv_type)
553 {
554 	struct sdhci_host *host = mmc_priv(card->host);
555 	struct sdhci_pci_slot *slot = sdhci_priv(host);
556 	struct intel_host *intel_host = sdhci_pci_priv(slot);
557 
558 	return intel_host->drv_strength;
559 }
560 
561 static int bxt_get_cd(struct mmc_host *mmc)
562 {
563 	int gpio_cd = mmc_gpio_get_cd(mmc);
564 	struct sdhci_host *host = mmc_priv(mmc);
565 	unsigned long flags;
566 	int ret = 0;
567 
568 	if (!gpio_cd)
569 		return 0;
570 
571 	spin_lock_irqsave(&host->lock, flags);
572 
573 	if (host->flags & SDHCI_DEVICE_DEAD)
574 		goto out;
575 
576 	ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
577 out:
578 	spin_unlock_irqrestore(&host->lock, flags);
579 
580 	return ret;
581 }
582 
583 #define SDHCI_INTEL_PWR_TIMEOUT_CNT	20
584 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY	100
585 
586 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
587 				  unsigned short vdd)
588 {
589 	int cntr;
590 	u8 reg;
591 
592 	sdhci_set_power(host, mode, vdd);
593 
594 	if (mode == MMC_POWER_OFF)
595 		return;
596 
597 	/*
598 	 * Bus power might not enable after D3 -> D0 transition due to the
599 	 * present state not yet having propagated. Retry for up to 2ms.
600 	 */
601 	for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) {
602 		reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
603 		if (reg & SDHCI_POWER_ON)
604 			break;
605 		udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY);
606 		reg |= SDHCI_POWER_ON;
607 		sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
608 	}
609 }
610 
611 #define INTEL_HS400_ES_REG 0x78
612 #define INTEL_HS400_ES_BIT BIT(0)
613 
614 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc,
615 					struct mmc_ios *ios)
616 {
617 	struct sdhci_host *host = mmc_priv(mmc);
618 	u32 val;
619 
620 	val = sdhci_readl(host, INTEL_HS400_ES_REG);
621 	if (ios->enhanced_strobe)
622 		val |= INTEL_HS400_ES_BIT;
623 	else
624 		val &= ~INTEL_HS400_ES_BIT;
625 	sdhci_writel(host, val, INTEL_HS400_ES_REG);
626 }
627 
628 static int intel_start_signal_voltage_switch(struct mmc_host *mmc,
629 					     struct mmc_ios *ios)
630 {
631 	struct device *dev = mmc_dev(mmc);
632 	struct sdhci_host *host = mmc_priv(mmc);
633 	struct sdhci_pci_slot *slot = sdhci_priv(host);
634 	struct intel_host *intel_host = sdhci_pci_priv(slot);
635 	unsigned int fn;
636 	u32 result = 0;
637 	int err;
638 
639 	err = sdhci_start_signal_voltage_switch(mmc, ios);
640 	if (err)
641 		return err;
642 
643 	switch (ios->signal_voltage) {
644 	case MMC_SIGNAL_VOLTAGE_330:
645 		fn = INTEL_DSM_V33_SWITCH;
646 		break;
647 	case MMC_SIGNAL_VOLTAGE_180:
648 		fn = INTEL_DSM_V18_SWITCH;
649 		break;
650 	default:
651 		return 0;
652 	}
653 
654 	err = intel_dsm(intel_host, dev, fn, &result);
655 	pr_debug("%s: %s DSM fn %u error %d result %u\n",
656 		 mmc_hostname(mmc), __func__, fn, err, result);
657 
658 	return 0;
659 }
660 
661 static const struct sdhci_ops sdhci_intel_byt_ops = {
662 	.set_clock		= sdhci_set_clock,
663 	.set_power		= sdhci_intel_set_power,
664 	.enable_dma		= sdhci_pci_enable_dma,
665 	.set_bus_width		= sdhci_set_bus_width,
666 	.reset			= sdhci_reset,
667 	.set_uhs_signaling	= sdhci_set_uhs_signaling,
668 	.hw_reset		= sdhci_pci_hw_reset,
669 };
670 
671 static const struct sdhci_ops sdhci_intel_glk_ops = {
672 	.set_clock		= sdhci_set_clock,
673 	.set_power		= sdhci_intel_set_power,
674 	.enable_dma		= sdhci_pci_enable_dma,
675 	.set_bus_width		= sdhci_set_bus_width,
676 	.reset			= sdhci_reset,
677 	.set_uhs_signaling	= sdhci_set_uhs_signaling,
678 	.hw_reset		= sdhci_pci_hw_reset,
679 	.irq			= sdhci_cqhci_irq,
680 };
681 
682 static void byt_read_dsm(struct sdhci_pci_slot *slot)
683 {
684 	struct intel_host *intel_host = sdhci_pci_priv(slot);
685 	struct device *dev = &slot->chip->pdev->dev;
686 	struct mmc_host *mmc = slot->host->mmc;
687 
688 	intel_dsm_init(intel_host, dev, mmc);
689 	slot->chip->rpm_retune = intel_host->d3_retune;
690 }
691 
692 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode)
693 {
694 	int err = sdhci_execute_tuning(mmc, opcode);
695 	struct sdhci_host *host = mmc_priv(mmc);
696 
697 	if (err)
698 		return err;
699 
700 	/*
701 	 * Tuning can leave the IP in an active state (Buffer Read Enable bit
702 	 * set) which prevents the entry to low power states (i.e. S0i3). Data
703 	 * reset will clear it.
704 	 */
705 	sdhci_reset(host, SDHCI_RESET_DATA);
706 
707 	return 0;
708 }
709 
710 static void byt_probe_slot(struct sdhci_pci_slot *slot)
711 {
712 	struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
713 	struct device *dev = &slot->chip->pdev->dev;
714 	struct mmc_host *mmc = slot->host->mmc;
715 
716 	byt_read_dsm(slot);
717 
718 	ops->execute_tuning = intel_execute_tuning;
719 	ops->start_signal_voltage_switch = intel_start_signal_voltage_switch;
720 
721 	device_property_read_u32(dev, "max-frequency", &mmc->f_max);
722 }
723 
724 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
725 {
726 	byt_probe_slot(slot);
727 	slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
728 				 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
729 				 MMC_CAP_CMD_DURING_TFR |
730 				 MMC_CAP_WAIT_WHILE_BUSY;
731 	slot->hw_reset = sdhci_pci_int_hw_reset;
732 	if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
733 		slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
734 	slot->host->mmc_host_ops.select_drive_strength =
735 						intel_select_drive_strength;
736 	return 0;
737 }
738 
739 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot)
740 {
741 	int ret = byt_emmc_probe_slot(slot);
742 
743 	slot->host->mmc->caps2 |= MMC_CAP2_CQE;
744 
745 	if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) {
746 		slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES,
747 		slot->host->mmc_host_ops.hs400_enhanced_strobe =
748 						intel_hs400_enhanced_strobe;
749 		slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
750 	}
751 
752 	return ret;
753 }
754 
755 static const struct cqhci_host_ops glk_cqhci_ops = {
756 	.enable		= sdhci_cqe_enable,
757 	.disable	= sdhci_cqe_disable,
758 	.dumpregs	= sdhci_pci_dumpregs,
759 };
760 
761 static int glk_emmc_add_host(struct sdhci_pci_slot *slot)
762 {
763 	struct device *dev = &slot->chip->pdev->dev;
764 	struct sdhci_host *host = slot->host;
765 	struct cqhci_host *cq_host;
766 	bool dma64;
767 	int ret;
768 
769 	ret = sdhci_setup_host(host);
770 	if (ret)
771 		return ret;
772 
773 	cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
774 	if (!cq_host) {
775 		ret = -ENOMEM;
776 		goto cleanup;
777 	}
778 
779 	cq_host->mmio = host->ioaddr + 0x200;
780 	cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
781 	cq_host->ops = &glk_cqhci_ops;
782 
783 	dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
784 	if (dma64)
785 		cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
786 
787 	ret = cqhci_init(cq_host, host->mmc, dma64);
788 	if (ret)
789 		goto cleanup;
790 
791 	ret = __sdhci_add_host(host);
792 	if (ret)
793 		goto cleanup;
794 
795 	return 0;
796 
797 cleanup:
798 	sdhci_cleanup_host(host);
799 	return ret;
800 }
801 
802 #ifdef CONFIG_PM
803 #define GLK_RX_CTRL1	0x834
804 #define GLK_TUN_VAL	0x840
805 #define GLK_PATH_PLL	GENMASK(13, 8)
806 #define GLK_DLY		GENMASK(6, 0)
807 /* Workaround firmware failing to restore the tuning value */
808 static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp)
809 {
810 	struct sdhci_pci_slot *slot = chip->slots[0];
811 	struct intel_host *intel_host = sdhci_pci_priv(slot);
812 	struct sdhci_host *host = slot->host;
813 	u32 glk_rx_ctrl1;
814 	u32 glk_tun_val;
815 	u32 dly;
816 
817 	if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc))
818 		return;
819 
820 	glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1);
821 	glk_tun_val = sdhci_readl(host, GLK_TUN_VAL);
822 
823 	if (susp) {
824 		intel_host->glk_rx_ctrl1 = glk_rx_ctrl1;
825 		intel_host->glk_tun_val = glk_tun_val;
826 		return;
827 	}
828 
829 	if (!intel_host->glk_tun_val)
830 		return;
831 
832 	if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) {
833 		intel_host->rpm_retune_ok = true;
834 		return;
835 	}
836 
837 	dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) +
838 				  (intel_host->glk_tun_val << 1));
839 	if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1))
840 		return;
841 
842 	glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly;
843 	sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1);
844 
845 	intel_host->rpm_retune_ok = true;
846 	chip->rpm_retune = true;
847 	mmc_retune_needed(host->mmc);
848 	pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc));
849 }
850 
851 static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp)
852 {
853 	if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC &&
854 	    !chip->rpm_retune)
855 		glk_rpm_retune_wa(chip, susp);
856 }
857 
858 static int glk_runtime_suspend(struct sdhci_pci_chip *chip)
859 {
860 	glk_rpm_retune_chk(chip, true);
861 
862 	return sdhci_cqhci_runtime_suspend(chip);
863 }
864 
865 static int glk_runtime_resume(struct sdhci_pci_chip *chip)
866 {
867 	glk_rpm_retune_chk(chip, false);
868 
869 	return sdhci_cqhci_runtime_resume(chip);
870 }
871 #endif
872 
873 #ifdef CONFIG_ACPI
874 static int ni_set_max_freq(struct sdhci_pci_slot *slot)
875 {
876 	acpi_status status;
877 	unsigned long long max_freq;
878 
879 	status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev),
880 				       "MXFQ", NULL, &max_freq);
881 	if (ACPI_FAILURE(status)) {
882 		dev_err(&slot->chip->pdev->dev,
883 			"MXFQ not found in acpi table\n");
884 		return -EINVAL;
885 	}
886 
887 	slot->host->mmc->f_max = max_freq * 1000000;
888 
889 	return 0;
890 }
891 #else
892 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot)
893 {
894 	return 0;
895 }
896 #endif
897 
898 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
899 {
900 	int err;
901 
902 	byt_probe_slot(slot);
903 
904 	err = ni_set_max_freq(slot);
905 	if (err)
906 		return err;
907 
908 	slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
909 				 MMC_CAP_WAIT_WHILE_BUSY;
910 	return 0;
911 }
912 
913 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
914 {
915 	byt_probe_slot(slot);
916 	slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
917 				 MMC_CAP_WAIT_WHILE_BUSY;
918 	return 0;
919 }
920 
921 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
922 {
923 	byt_probe_slot(slot);
924 	slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY |
925 				 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE;
926 	slot->cd_idx = 0;
927 	slot->cd_override_level = true;
928 	if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
929 	    slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
930 	    slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD ||
931 	    slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD)
932 		slot->host->mmc_host_ops.get_cd = bxt_get_cd;
933 
934 	if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI &&
935 	    slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3)
936 		slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V;
937 
938 	return 0;
939 }
940 
941 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
942 	.allow_runtime_pm = true,
943 	.probe_slot	= byt_emmc_probe_slot,
944 	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
945 			  SDHCI_QUIRK_NO_LED,
946 	.quirks2	= SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
947 			  SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
948 			  SDHCI_QUIRK2_STOP_WITH_TC,
949 	.ops		= &sdhci_intel_byt_ops,
950 	.priv_size	= sizeof(struct intel_host),
951 };
952 
953 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = {
954 	.allow_runtime_pm	= true,
955 	.probe_slot		= glk_emmc_probe_slot,
956 	.add_host		= glk_emmc_add_host,
957 #ifdef CONFIG_PM_SLEEP
958 	.suspend		= sdhci_cqhci_suspend,
959 	.resume			= sdhci_cqhci_resume,
960 #endif
961 #ifdef CONFIG_PM
962 	.runtime_suspend	= glk_runtime_suspend,
963 	.runtime_resume		= glk_runtime_resume,
964 #endif
965 	.quirks			= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
966 				  SDHCI_QUIRK_NO_LED,
967 	.quirks2		= SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
968 				  SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
969 				  SDHCI_QUIRK2_STOP_WITH_TC,
970 	.ops			= &sdhci_intel_glk_ops,
971 	.priv_size		= sizeof(struct intel_host),
972 };
973 
974 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = {
975 	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
976 			  SDHCI_QUIRK_NO_LED,
977 	.quirks2	= SDHCI_QUIRK2_HOST_OFF_CARD_ON |
978 			  SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
979 	.allow_runtime_pm = true,
980 	.probe_slot	= ni_byt_sdio_probe_slot,
981 	.ops		= &sdhci_intel_byt_ops,
982 	.priv_size	= sizeof(struct intel_host),
983 };
984 
985 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
986 	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
987 			  SDHCI_QUIRK_NO_LED,
988 	.quirks2	= SDHCI_QUIRK2_HOST_OFF_CARD_ON |
989 			SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
990 	.allow_runtime_pm = true,
991 	.probe_slot	= byt_sdio_probe_slot,
992 	.ops		= &sdhci_intel_byt_ops,
993 	.priv_size	= sizeof(struct intel_host),
994 };
995 
996 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
997 	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
998 			  SDHCI_QUIRK_NO_LED,
999 	.quirks2	= SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
1000 			  SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1001 			  SDHCI_QUIRK2_STOP_WITH_TC,
1002 	.allow_runtime_pm = true,
1003 	.own_cd_for_runtime_pm = true,
1004 	.probe_slot	= byt_sd_probe_slot,
1005 	.ops		= &sdhci_intel_byt_ops,
1006 	.priv_size	= sizeof(struct intel_host),
1007 };
1008 
1009 /* Define Host controllers for Intel Merrifield platform */
1010 #define INTEL_MRFLD_EMMC_0	0
1011 #define INTEL_MRFLD_EMMC_1	1
1012 #define INTEL_MRFLD_SD		2
1013 #define INTEL_MRFLD_SDIO	3
1014 
1015 #ifdef CONFIG_ACPI
1016 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot)
1017 {
1018 	struct acpi_device *device, *child;
1019 
1020 	device = ACPI_COMPANION(&slot->chip->pdev->dev);
1021 	if (!device)
1022 		return;
1023 
1024 	acpi_device_fix_up_power(device);
1025 	list_for_each_entry(child, &device->children, node)
1026 		if (child->status.present && child->status.enabled)
1027 			acpi_device_fix_up_power(child);
1028 }
1029 #else
1030 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {}
1031 #endif
1032 
1033 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot)
1034 {
1035 	unsigned int func = PCI_FUNC(slot->chip->pdev->devfn);
1036 
1037 	switch (func) {
1038 	case INTEL_MRFLD_EMMC_0:
1039 	case INTEL_MRFLD_EMMC_1:
1040 		slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
1041 					 MMC_CAP_8_BIT_DATA |
1042 					 MMC_CAP_1_8V_DDR;
1043 		break;
1044 	case INTEL_MRFLD_SD:
1045 		slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1046 		break;
1047 	case INTEL_MRFLD_SDIO:
1048 		/* Advertise 2.0v for compatibility with the SDIO card's OCR */
1049 		slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195;
1050 		slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
1051 					 MMC_CAP_POWER_OFF_CARD;
1052 		break;
1053 	default:
1054 		return -ENODEV;
1055 	}
1056 
1057 	intel_mrfld_mmc_fix_up_power_slot(slot);
1058 	return 0;
1059 }
1060 
1061 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = {
1062 	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1063 	.quirks2	= SDHCI_QUIRK2_BROKEN_HS200 |
1064 			SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1065 	.allow_runtime_pm = true,
1066 	.probe_slot	= intel_mrfld_mmc_probe_slot,
1067 };
1068 
1069 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
1070 {
1071 	u8 scratch;
1072 	int ret;
1073 
1074 	ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
1075 	if (ret)
1076 		return ret;
1077 
1078 	/*
1079 	 * Turn PMOS on [bit 0], set over current detection to 2.4 V
1080 	 * [bit 1:2] and enable over current debouncing [bit 6].
1081 	 */
1082 	if (on)
1083 		scratch |= 0x47;
1084 	else
1085 		scratch &= ~0x47;
1086 
1087 	return pci_write_config_byte(chip->pdev, 0xAE, scratch);
1088 }
1089 
1090 static int jmicron_probe(struct sdhci_pci_chip *chip)
1091 {
1092 	int ret;
1093 	u16 mmcdev = 0;
1094 
1095 	if (chip->pdev->revision == 0) {
1096 		chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
1097 			  SDHCI_QUIRK_32BIT_DMA_SIZE |
1098 			  SDHCI_QUIRK_32BIT_ADMA_SIZE |
1099 			  SDHCI_QUIRK_RESET_AFTER_REQUEST |
1100 			  SDHCI_QUIRK_BROKEN_SMALL_PIO;
1101 	}
1102 
1103 	/*
1104 	 * JMicron chips can have two interfaces to the same hardware
1105 	 * in order to work around limitations in Microsoft's driver.
1106 	 * We need to make sure we only bind to one of them.
1107 	 *
1108 	 * This code assumes two things:
1109 	 *
1110 	 * 1. The PCI code adds subfunctions in order.
1111 	 *
1112 	 * 2. The MMC interface has a lower subfunction number
1113 	 *    than the SD interface.
1114 	 */
1115 	if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
1116 		mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
1117 	else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
1118 		mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
1119 
1120 	if (mmcdev) {
1121 		struct pci_dev *sd_dev;
1122 
1123 		sd_dev = NULL;
1124 		while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
1125 						mmcdev, sd_dev)) != NULL) {
1126 			if ((PCI_SLOT(chip->pdev->devfn) ==
1127 				PCI_SLOT(sd_dev->devfn)) &&
1128 				(chip->pdev->bus == sd_dev->bus))
1129 				break;
1130 		}
1131 
1132 		if (sd_dev) {
1133 			pci_dev_put(sd_dev);
1134 			dev_info(&chip->pdev->dev, "Refusing to bind to "
1135 				"secondary interface.\n");
1136 			return -ENODEV;
1137 		}
1138 	}
1139 
1140 	/*
1141 	 * JMicron chips need a bit of a nudge to enable the power
1142 	 * output pins.
1143 	 */
1144 	ret = jmicron_pmos(chip, 1);
1145 	if (ret) {
1146 		dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1147 		return ret;
1148 	}
1149 
1150 	/* quirk for unsable RO-detection on JM388 chips */
1151 	if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
1152 	    chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1153 		chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
1154 
1155 	return 0;
1156 }
1157 
1158 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
1159 {
1160 	u8 scratch;
1161 
1162 	scratch = readb(host->ioaddr + 0xC0);
1163 
1164 	if (on)
1165 		scratch |= 0x01;
1166 	else
1167 		scratch &= ~0x01;
1168 
1169 	writeb(scratch, host->ioaddr + 0xC0);
1170 }
1171 
1172 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
1173 {
1174 	if (slot->chip->pdev->revision == 0) {
1175 		u16 version;
1176 
1177 		version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
1178 		version = (version & SDHCI_VENDOR_VER_MASK) >>
1179 			SDHCI_VENDOR_VER_SHIFT;
1180 
1181 		/*
1182 		 * Older versions of the chip have lots of nasty glitches
1183 		 * in the ADMA engine. It's best just to avoid it
1184 		 * completely.
1185 		 */
1186 		if (version < 0xAC)
1187 			slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1188 	}
1189 
1190 	/* JM388 MMC doesn't support 1.8V while SD supports it */
1191 	if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1192 		slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
1193 			MMC_VDD_29_30 | MMC_VDD_30_31 |
1194 			MMC_VDD_165_195; /* allow 1.8V */
1195 		slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
1196 			MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
1197 	}
1198 
1199 	/*
1200 	 * The secondary interface requires a bit set to get the
1201 	 * interrupts.
1202 	 */
1203 	if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1204 	    slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1205 		jmicron_enable_mmc(slot->host, 1);
1206 
1207 	slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
1208 
1209 	return 0;
1210 }
1211 
1212 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
1213 {
1214 	if (dead)
1215 		return;
1216 
1217 	if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1218 	    slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1219 		jmicron_enable_mmc(slot->host, 0);
1220 }
1221 
1222 #ifdef CONFIG_PM_SLEEP
1223 static int jmicron_suspend(struct sdhci_pci_chip *chip)
1224 {
1225 	int i, ret;
1226 
1227 	ret = sdhci_pci_suspend_host(chip);
1228 	if (ret)
1229 		return ret;
1230 
1231 	if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1232 	    chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1233 		for (i = 0; i < chip->num_slots; i++)
1234 			jmicron_enable_mmc(chip->slots[i]->host, 0);
1235 	}
1236 
1237 	return 0;
1238 }
1239 
1240 static int jmicron_resume(struct sdhci_pci_chip *chip)
1241 {
1242 	int ret, i;
1243 
1244 	if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1245 	    chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1246 		for (i = 0; i < chip->num_slots; i++)
1247 			jmicron_enable_mmc(chip->slots[i]->host, 1);
1248 	}
1249 
1250 	ret = jmicron_pmos(chip, 1);
1251 	if (ret) {
1252 		dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1253 		return ret;
1254 	}
1255 
1256 	return sdhci_pci_resume_host(chip);
1257 }
1258 #endif
1259 
1260 static const struct sdhci_pci_fixes sdhci_jmicron = {
1261 	.probe		= jmicron_probe,
1262 
1263 	.probe_slot	= jmicron_probe_slot,
1264 	.remove_slot	= jmicron_remove_slot,
1265 
1266 #ifdef CONFIG_PM_SLEEP
1267 	.suspend	= jmicron_suspend,
1268 	.resume		= jmicron_resume,
1269 #endif
1270 };
1271 
1272 /* SysKonnect CardBus2SDIO extra registers */
1273 #define SYSKT_CTRL		0x200
1274 #define SYSKT_RDFIFO_STAT	0x204
1275 #define SYSKT_WRFIFO_STAT	0x208
1276 #define SYSKT_POWER_DATA	0x20c
1277 #define   SYSKT_POWER_330	0xef
1278 #define   SYSKT_POWER_300	0xf8
1279 #define   SYSKT_POWER_184	0xcc
1280 #define SYSKT_POWER_CMD		0x20d
1281 #define   SYSKT_POWER_START	(1 << 7)
1282 #define SYSKT_POWER_STATUS	0x20e
1283 #define   SYSKT_POWER_STATUS_OK	(1 << 0)
1284 #define SYSKT_BOARD_REV		0x210
1285 #define SYSKT_CHIP_REV		0x211
1286 #define SYSKT_CONF_DATA		0x212
1287 #define   SYSKT_CONF_DATA_1V8	(1 << 2)
1288 #define   SYSKT_CONF_DATA_2V5	(1 << 1)
1289 #define   SYSKT_CONF_DATA_3V3	(1 << 0)
1290 
1291 static int syskt_probe(struct sdhci_pci_chip *chip)
1292 {
1293 	if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1294 		chip->pdev->class &= ~0x0000FF;
1295 		chip->pdev->class |= PCI_SDHCI_IFDMA;
1296 	}
1297 	return 0;
1298 }
1299 
1300 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
1301 {
1302 	int tm, ps;
1303 
1304 	u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
1305 	u8  chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
1306 	dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
1307 					 "board rev %d.%d, chip rev %d.%d\n",
1308 					 board_rev >> 4, board_rev & 0xf,
1309 					 chip_rev >> 4,  chip_rev & 0xf);
1310 	if (chip_rev >= 0x20)
1311 		slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
1312 
1313 	writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
1314 	writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
1315 	udelay(50);
1316 	tm = 10;  /* Wait max 1 ms */
1317 	do {
1318 		ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
1319 		if (ps & SYSKT_POWER_STATUS_OK)
1320 			break;
1321 		udelay(100);
1322 	} while (--tm);
1323 	if (!tm) {
1324 		dev_err(&slot->chip->pdev->dev,
1325 			"power regulator never stabilized");
1326 		writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
1327 		return -ENODEV;
1328 	}
1329 
1330 	return 0;
1331 }
1332 
1333 static const struct sdhci_pci_fixes sdhci_syskt = {
1334 	.quirks		= SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
1335 	.probe		= syskt_probe,
1336 	.probe_slot	= syskt_probe_slot,
1337 };
1338 
1339 static int via_probe(struct sdhci_pci_chip *chip)
1340 {
1341 	if (chip->pdev->revision == 0x10)
1342 		chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
1343 
1344 	return 0;
1345 }
1346 
1347 static const struct sdhci_pci_fixes sdhci_via = {
1348 	.probe		= via_probe,
1349 };
1350 
1351 static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
1352 {
1353 	slot->host->mmc->caps2 |= MMC_CAP2_HS200;
1354 	return 0;
1355 }
1356 
1357 static const struct sdhci_pci_fixes sdhci_rtsx = {
1358 	.quirks2	= SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1359 			SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
1360 			SDHCI_QUIRK2_BROKEN_DDR50,
1361 	.probe_slot	= rtsx_probe_slot,
1362 };
1363 
1364 /*AMD chipset generation*/
1365 enum amd_chipset_gen {
1366 	AMD_CHIPSET_BEFORE_ML,
1367 	AMD_CHIPSET_CZ,
1368 	AMD_CHIPSET_NL,
1369 	AMD_CHIPSET_UNKNOWN,
1370 };
1371 
1372 /* AMD registers */
1373 #define AMD_SD_AUTO_PATTERN		0xB8
1374 #define AMD_MSLEEP_DURATION		4
1375 #define AMD_SD_MISC_CONTROL		0xD0
1376 #define AMD_MAX_TUNE_VALUE		0x0B
1377 #define AMD_AUTO_TUNE_SEL		0x10800
1378 #define AMD_FIFO_PTR			0x30
1379 #define AMD_BIT_MASK			0x1F
1380 
1381 static void amd_tuning_reset(struct sdhci_host *host)
1382 {
1383 	unsigned int val;
1384 
1385 	val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1386 	val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING;
1387 	sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1388 
1389 	val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1390 	val &= ~SDHCI_CTRL_EXEC_TUNING;
1391 	sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1392 }
1393 
1394 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase)
1395 {
1396 	unsigned int val;
1397 
1398 	pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val);
1399 	val &= ~AMD_BIT_MASK;
1400 	val |= (AMD_AUTO_TUNE_SEL | (phase << 1));
1401 	pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val);
1402 }
1403 
1404 static void amd_enable_manual_tuning(struct pci_dev *pdev)
1405 {
1406 	unsigned int val;
1407 
1408 	pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val);
1409 	val |= AMD_FIFO_PTR;
1410 	pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val);
1411 }
1412 
1413 static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode)
1414 {
1415 	struct sdhci_pci_slot *slot = sdhci_priv(host);
1416 	struct pci_dev *pdev = slot->chip->pdev;
1417 	u8 valid_win = 0;
1418 	u8 valid_win_max = 0;
1419 	u8 valid_win_end = 0;
1420 	u8 ctrl, tune_around;
1421 
1422 	amd_tuning_reset(host);
1423 
1424 	for (tune_around = 0; tune_around < 12; tune_around++) {
1425 		amd_config_tuning_phase(pdev, tune_around);
1426 
1427 		if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1428 			valid_win = 0;
1429 			msleep(AMD_MSLEEP_DURATION);
1430 			ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA;
1431 			sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET);
1432 		} else if (++valid_win > valid_win_max) {
1433 			valid_win_max = valid_win;
1434 			valid_win_end = tune_around;
1435 		}
1436 	}
1437 
1438 	if (!valid_win_max) {
1439 		dev_err(&pdev->dev, "no tuning point found\n");
1440 		return -EIO;
1441 	}
1442 
1443 	amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2);
1444 
1445 	amd_enable_manual_tuning(pdev);
1446 
1447 	host->mmc->retune_period = 0;
1448 
1449 	return 0;
1450 }
1451 
1452 static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode)
1453 {
1454 	struct sdhci_host *host = mmc_priv(mmc);
1455 
1456 	/* AMD requires custom HS200 tuning */
1457 	if (host->timing == MMC_TIMING_MMC_HS200)
1458 		return amd_execute_tuning_hs200(host, opcode);
1459 
1460 	/* Otherwise perform standard SDHCI tuning */
1461 	return sdhci_execute_tuning(mmc, opcode);
1462 }
1463 
1464 static int amd_probe_slot(struct sdhci_pci_slot *slot)
1465 {
1466 	struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
1467 
1468 	ops->execute_tuning = amd_execute_tuning;
1469 
1470 	return 0;
1471 }
1472 
1473 static int amd_probe(struct sdhci_pci_chip *chip)
1474 {
1475 	struct pci_dev	*smbus_dev;
1476 	enum amd_chipset_gen gen;
1477 
1478 	smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1479 			PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
1480 	if (smbus_dev) {
1481 		gen = AMD_CHIPSET_BEFORE_ML;
1482 	} else {
1483 		smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1484 				PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
1485 		if (smbus_dev) {
1486 			if (smbus_dev->revision < 0x51)
1487 				gen = AMD_CHIPSET_CZ;
1488 			else
1489 				gen = AMD_CHIPSET_NL;
1490 		} else {
1491 			gen = AMD_CHIPSET_UNKNOWN;
1492 		}
1493 	}
1494 
1495 	if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ)
1496 		chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
1497 
1498 	return 0;
1499 }
1500 
1501 static const struct sdhci_ops amd_sdhci_pci_ops = {
1502 	.set_clock			= sdhci_set_clock,
1503 	.enable_dma			= sdhci_pci_enable_dma,
1504 	.set_bus_width			= sdhci_set_bus_width,
1505 	.reset				= sdhci_reset,
1506 	.set_uhs_signaling		= sdhci_set_uhs_signaling,
1507 };
1508 
1509 static const struct sdhci_pci_fixes sdhci_amd = {
1510 	.probe		= amd_probe,
1511 	.ops		= &amd_sdhci_pci_ops,
1512 	.probe_slot	= amd_probe_slot,
1513 };
1514 
1515 static const struct pci_device_id pci_ids[] = {
1516 	SDHCI_PCI_DEVICE(RICOH, R5C822,  ricoh),
1517 	SDHCI_PCI_DEVICE(RICOH, R5C843,  ricoh_mmc),
1518 	SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc),
1519 	SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc),
1520 	SDHCI_PCI_DEVICE(ENE, CB712_SD,   ene_712),
1521 	SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712),
1522 	SDHCI_PCI_DEVICE(ENE, CB714_SD,   ene_714),
1523 	SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714),
1524 	SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe),
1525 	SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD,  jmicron),
1526 	SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron),
1527 	SDHCI_PCI_DEVICE(JMICRON, JMB388_SD,  jmicron),
1528 	SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron),
1529 	SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt),
1530 	SDHCI_PCI_DEVICE(VIA, 95D0, via),
1531 	SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx),
1532 	SDHCI_PCI_DEVICE(INTEL, QRK_SD,    intel_qrk),
1533 	SDHCI_PCI_DEVICE(INTEL, MRST_SD0,  intel_mrst_hc0),
1534 	SDHCI_PCI_DEVICE(INTEL, MRST_SD1,  intel_mrst_hc1_hc2),
1535 	SDHCI_PCI_DEVICE(INTEL, MRST_SD2,  intel_mrst_hc1_hc2),
1536 	SDHCI_PCI_DEVICE(INTEL, MFD_SD,    intel_mfd_sd),
1537 	SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio),
1538 	SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio),
1539 	SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc),
1540 	SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc),
1541 	SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio),
1542 	SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio),
1543 	SDHCI_PCI_DEVICE(INTEL, BYT_EMMC,  intel_byt_emmc),
1544 	SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio),
1545 	SDHCI_PCI_DEVICE(INTEL, BYT_SDIO,  intel_byt_sdio),
1546 	SDHCI_PCI_DEVICE(INTEL, BYT_SD,    intel_byt_sd),
1547 	SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc),
1548 	SDHCI_PCI_DEVICE(INTEL, BSW_EMMC,  intel_byt_emmc),
1549 	SDHCI_PCI_DEVICE(INTEL, BSW_SDIO,  intel_byt_sdio),
1550 	SDHCI_PCI_DEVICE(INTEL, BSW_SD,    intel_byt_sd),
1551 	SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd),
1552 	SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio),
1553 	SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio),
1554 	SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc),
1555 	SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc),
1556 	SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc),
1557 	SDHCI_PCI_DEVICE(INTEL, SPT_EMMC,  intel_byt_emmc),
1558 	SDHCI_PCI_DEVICE(INTEL, SPT_SDIO,  intel_byt_sdio),
1559 	SDHCI_PCI_DEVICE(INTEL, SPT_SD,    intel_byt_sd),
1560 	SDHCI_PCI_DEVICE(INTEL, DNV_EMMC,  intel_byt_emmc),
1561 	SDHCI_PCI_DEVICE(INTEL, CDF_EMMC,  intel_glk_emmc),
1562 	SDHCI_PCI_DEVICE(INTEL, BXT_EMMC,  intel_byt_emmc),
1563 	SDHCI_PCI_DEVICE(INTEL, BXT_SDIO,  intel_byt_sdio),
1564 	SDHCI_PCI_DEVICE(INTEL, BXT_SD,    intel_byt_sd),
1565 	SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc),
1566 	SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio),
1567 	SDHCI_PCI_DEVICE(INTEL, BXTM_SD,   intel_byt_sd),
1568 	SDHCI_PCI_DEVICE(INTEL, APL_EMMC,  intel_byt_emmc),
1569 	SDHCI_PCI_DEVICE(INTEL, APL_SDIO,  intel_byt_sdio),
1570 	SDHCI_PCI_DEVICE(INTEL, APL_SD,    intel_byt_sd),
1571 	SDHCI_PCI_DEVICE(INTEL, GLK_EMMC,  intel_glk_emmc),
1572 	SDHCI_PCI_DEVICE(INTEL, GLK_SDIO,  intel_byt_sdio),
1573 	SDHCI_PCI_DEVICE(INTEL, GLK_SD,    intel_byt_sd),
1574 	SDHCI_PCI_DEVICE(INTEL, CNP_EMMC,  intel_glk_emmc),
1575 	SDHCI_PCI_DEVICE(INTEL, CNP_SD,    intel_byt_sd),
1576 	SDHCI_PCI_DEVICE(INTEL, CNPH_SD,   intel_byt_sd),
1577 	SDHCI_PCI_DEVICE(INTEL, ICP_EMMC,  intel_glk_emmc),
1578 	SDHCI_PCI_DEVICE(INTEL, ICP_SD,    intel_byt_sd),
1579 	SDHCI_PCI_DEVICE(O2, 8120,     o2),
1580 	SDHCI_PCI_DEVICE(O2, 8220,     o2),
1581 	SDHCI_PCI_DEVICE(O2, 8221,     o2),
1582 	SDHCI_PCI_DEVICE(O2, 8320,     o2),
1583 	SDHCI_PCI_DEVICE(O2, 8321,     o2),
1584 	SDHCI_PCI_DEVICE(O2, FUJIN2,   o2),
1585 	SDHCI_PCI_DEVICE(O2, SDS0,     o2),
1586 	SDHCI_PCI_DEVICE(O2, SDS1,     o2),
1587 	SDHCI_PCI_DEVICE(O2, SEABIRD0, o2),
1588 	SDHCI_PCI_DEVICE(O2, SEABIRD1, o2),
1589 	SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan),
1590 	SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps),
1591 	SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
1592 	/* Generic SD host controller */
1593 	{PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)},
1594 	{ /* end: all zeroes */ },
1595 };
1596 
1597 MODULE_DEVICE_TABLE(pci, pci_ids);
1598 
1599 /*****************************************************************************\
1600  *                                                                           *
1601  * SDHCI core callbacks                                                      *
1602  *                                                                           *
1603 \*****************************************************************************/
1604 
1605 int sdhci_pci_enable_dma(struct sdhci_host *host)
1606 {
1607 	struct sdhci_pci_slot *slot;
1608 	struct pci_dev *pdev;
1609 
1610 	slot = sdhci_priv(host);
1611 	pdev = slot->chip->pdev;
1612 
1613 	if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1614 		((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1615 		(host->flags & SDHCI_USE_SDMA)) {
1616 		dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1617 			"doesn't fully claim to support it.\n");
1618 	}
1619 
1620 	pci_set_master(pdev);
1621 
1622 	return 0;
1623 }
1624 
1625 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
1626 {
1627 	struct sdhci_pci_slot *slot = sdhci_priv(host);
1628 	int rst_n_gpio = slot->rst_n_gpio;
1629 
1630 	if (!gpio_is_valid(rst_n_gpio))
1631 		return;
1632 	gpio_set_value_cansleep(rst_n_gpio, 0);
1633 	/* For eMMC, minimum is 1us but give it 10us for good measure */
1634 	udelay(10);
1635 	gpio_set_value_cansleep(rst_n_gpio, 1);
1636 	/* For eMMC, minimum is 200us but give it 300us for good measure */
1637 	usleep_range(300, 1000);
1638 }
1639 
1640 static void sdhci_pci_hw_reset(struct sdhci_host *host)
1641 {
1642 	struct sdhci_pci_slot *slot = sdhci_priv(host);
1643 
1644 	if (slot->hw_reset)
1645 		slot->hw_reset(host);
1646 }
1647 
1648 static const struct sdhci_ops sdhci_pci_ops = {
1649 	.set_clock	= sdhci_set_clock,
1650 	.enable_dma	= sdhci_pci_enable_dma,
1651 	.set_bus_width	= sdhci_set_bus_width,
1652 	.reset		= sdhci_reset,
1653 	.set_uhs_signaling = sdhci_set_uhs_signaling,
1654 	.hw_reset		= sdhci_pci_hw_reset,
1655 };
1656 
1657 /*****************************************************************************\
1658  *                                                                           *
1659  * Suspend/resume                                                            *
1660  *                                                                           *
1661 \*****************************************************************************/
1662 
1663 #ifdef CONFIG_PM_SLEEP
1664 static int sdhci_pci_suspend(struct device *dev)
1665 {
1666 	struct pci_dev *pdev = to_pci_dev(dev);
1667 	struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1668 
1669 	if (!chip)
1670 		return 0;
1671 
1672 	if (chip->fixes && chip->fixes->suspend)
1673 		return chip->fixes->suspend(chip);
1674 
1675 	return sdhci_pci_suspend_host(chip);
1676 }
1677 
1678 static int sdhci_pci_resume(struct device *dev)
1679 {
1680 	struct pci_dev *pdev = to_pci_dev(dev);
1681 	struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1682 
1683 	if (!chip)
1684 		return 0;
1685 
1686 	if (chip->fixes && chip->fixes->resume)
1687 		return chip->fixes->resume(chip);
1688 
1689 	return sdhci_pci_resume_host(chip);
1690 }
1691 #endif
1692 
1693 #ifdef CONFIG_PM
1694 static int sdhci_pci_runtime_suspend(struct device *dev)
1695 {
1696 	struct pci_dev *pdev = to_pci_dev(dev);
1697 	struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1698 
1699 	if (!chip)
1700 		return 0;
1701 
1702 	if (chip->fixes && chip->fixes->runtime_suspend)
1703 		return chip->fixes->runtime_suspend(chip);
1704 
1705 	return sdhci_pci_runtime_suspend_host(chip);
1706 }
1707 
1708 static int sdhci_pci_runtime_resume(struct device *dev)
1709 {
1710 	struct pci_dev *pdev = to_pci_dev(dev);
1711 	struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1712 
1713 	if (!chip)
1714 		return 0;
1715 
1716 	if (chip->fixes && chip->fixes->runtime_resume)
1717 		return chip->fixes->runtime_resume(chip);
1718 
1719 	return sdhci_pci_runtime_resume_host(chip);
1720 }
1721 #endif
1722 
1723 static const struct dev_pm_ops sdhci_pci_pm_ops = {
1724 	SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume)
1725 	SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1726 			sdhci_pci_runtime_resume, NULL)
1727 };
1728 
1729 /*****************************************************************************\
1730  *                                                                           *
1731  * Device probing/removal                                                    *
1732  *                                                                           *
1733 \*****************************************************************************/
1734 
1735 static struct sdhci_pci_slot *sdhci_pci_probe_slot(
1736 	struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1737 	int slotno)
1738 {
1739 	struct sdhci_pci_slot *slot;
1740 	struct sdhci_host *host;
1741 	int ret, bar = first_bar + slotno;
1742 	size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0;
1743 
1744 	if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1745 		dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1746 		return ERR_PTR(-ENODEV);
1747 	}
1748 
1749 	if (pci_resource_len(pdev, bar) < 0x100) {
1750 		dev_err(&pdev->dev, "Invalid iomem size. You may "
1751 			"experience problems.\n");
1752 	}
1753 
1754 	if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1755 		dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1756 		return ERR_PTR(-ENODEV);
1757 	}
1758 
1759 	if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1760 		dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1761 		return ERR_PTR(-ENODEV);
1762 	}
1763 
1764 	host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size);
1765 	if (IS_ERR(host)) {
1766 		dev_err(&pdev->dev, "cannot allocate host\n");
1767 		return ERR_CAST(host);
1768 	}
1769 
1770 	slot = sdhci_priv(host);
1771 
1772 	slot->chip = chip;
1773 	slot->host = host;
1774 	slot->rst_n_gpio = -EINVAL;
1775 	slot->cd_gpio = -EINVAL;
1776 	slot->cd_idx = -1;
1777 
1778 	/* Retrieve platform data if there is any */
1779 	if (*sdhci_pci_get_data)
1780 		slot->data = sdhci_pci_get_data(pdev, slotno);
1781 
1782 	if (slot->data) {
1783 		if (slot->data->setup) {
1784 			ret = slot->data->setup(slot->data);
1785 			if (ret) {
1786 				dev_err(&pdev->dev, "platform setup failed\n");
1787 				goto free;
1788 			}
1789 		}
1790 		slot->rst_n_gpio = slot->data->rst_n_gpio;
1791 		slot->cd_gpio = slot->data->cd_gpio;
1792 	}
1793 
1794 	host->hw_name = "PCI";
1795 	host->ops = chip->fixes && chip->fixes->ops ?
1796 		    chip->fixes->ops :
1797 		    &sdhci_pci_ops;
1798 	host->quirks = chip->quirks;
1799 	host->quirks2 = chip->quirks2;
1800 
1801 	host->irq = pdev->irq;
1802 
1803 	ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc));
1804 	if (ret) {
1805 		dev_err(&pdev->dev, "cannot request region\n");
1806 		goto cleanup;
1807 	}
1808 
1809 	host->ioaddr = pcim_iomap_table(pdev)[bar];
1810 
1811 	if (chip->fixes && chip->fixes->probe_slot) {
1812 		ret = chip->fixes->probe_slot(slot);
1813 		if (ret)
1814 			goto cleanup;
1815 	}
1816 
1817 	if (gpio_is_valid(slot->rst_n_gpio)) {
1818 		if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) {
1819 			gpio_direction_output(slot->rst_n_gpio, 1);
1820 			slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1821 			slot->hw_reset = sdhci_pci_gpio_hw_reset;
1822 		} else {
1823 			dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1824 			slot->rst_n_gpio = -EINVAL;
1825 		}
1826 	}
1827 
1828 	host->mmc->pm_caps = MMC_PM_KEEP_POWER;
1829 	host->mmc->slotno = slotno;
1830 	host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
1831 
1832 	if (device_can_wakeup(&pdev->dev))
1833 		host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
1834 
1835 	if (host->mmc->caps & MMC_CAP_CD_WAKE)
1836 		device_init_wakeup(&pdev->dev, true);
1837 
1838 	if (slot->cd_idx >= 0) {
1839 		ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx,
1840 					   slot->cd_override_level, 0, NULL);
1841 		if (ret && ret != -EPROBE_DEFER)
1842 			ret = mmc_gpiod_request_cd(host->mmc, NULL,
1843 						   slot->cd_idx,
1844 						   slot->cd_override_level,
1845 						   0, NULL);
1846 		if (ret == -EPROBE_DEFER)
1847 			goto remove;
1848 
1849 		if (ret) {
1850 			dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1851 			slot->cd_idx = -1;
1852 		}
1853 	}
1854 
1855 	if (chip->fixes && chip->fixes->add_host)
1856 		ret = chip->fixes->add_host(slot);
1857 	else
1858 		ret = sdhci_add_host(host);
1859 	if (ret)
1860 		goto remove;
1861 
1862 	sdhci_pci_add_own_cd(slot);
1863 
1864 	/*
1865 	 * Check if the chip needs a separate GPIO for card detect to wake up
1866 	 * from runtime suspend.  If it is not there, don't allow runtime PM.
1867 	 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1868 	 */
1869 	if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
1870 	    !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
1871 		chip->allow_runtime_pm = false;
1872 
1873 	return slot;
1874 
1875 remove:
1876 	if (chip->fixes && chip->fixes->remove_slot)
1877 		chip->fixes->remove_slot(slot, 0);
1878 
1879 cleanup:
1880 	if (slot->data && slot->data->cleanup)
1881 		slot->data->cleanup(slot->data);
1882 
1883 free:
1884 	sdhci_free_host(host);
1885 
1886 	return ERR_PTR(ret);
1887 }
1888 
1889 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1890 {
1891 	int dead;
1892 	u32 scratch;
1893 
1894 	sdhci_pci_remove_own_cd(slot);
1895 
1896 	dead = 0;
1897 	scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1898 	if (scratch == (u32)-1)
1899 		dead = 1;
1900 
1901 	sdhci_remove_host(slot->host, dead);
1902 
1903 	if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1904 		slot->chip->fixes->remove_slot(slot, dead);
1905 
1906 	if (slot->data && slot->data->cleanup)
1907 		slot->data->cleanup(slot->data);
1908 
1909 	sdhci_free_host(slot->host);
1910 }
1911 
1912 static void sdhci_pci_runtime_pm_allow(struct device *dev)
1913 {
1914 	pm_suspend_ignore_children(dev, 1);
1915 	pm_runtime_set_autosuspend_delay(dev, 50);
1916 	pm_runtime_use_autosuspend(dev);
1917 	pm_runtime_allow(dev);
1918 	/* Stay active until mmc core scans for a card */
1919 	pm_runtime_put_noidle(dev);
1920 }
1921 
1922 static void sdhci_pci_runtime_pm_forbid(struct device *dev)
1923 {
1924 	pm_runtime_forbid(dev);
1925 	pm_runtime_get_noresume(dev);
1926 }
1927 
1928 static int sdhci_pci_probe(struct pci_dev *pdev,
1929 				     const struct pci_device_id *ent)
1930 {
1931 	struct sdhci_pci_chip *chip;
1932 	struct sdhci_pci_slot *slot;
1933 
1934 	u8 slots, first_bar;
1935 	int ret, i;
1936 
1937 	BUG_ON(pdev == NULL);
1938 	BUG_ON(ent == NULL);
1939 
1940 	dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1941 		 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1942 
1943 	ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1944 	if (ret)
1945 		return ret;
1946 
1947 	slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1948 	dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1949 	if (slots == 0)
1950 		return -ENODEV;
1951 
1952 	BUG_ON(slots > MAX_SLOTS);
1953 
1954 	ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1955 	if (ret)
1956 		return ret;
1957 
1958 	first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1959 
1960 	if (first_bar > 5) {
1961 		dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1962 		return -ENODEV;
1963 	}
1964 
1965 	ret = pcim_enable_device(pdev);
1966 	if (ret)
1967 		return ret;
1968 
1969 	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
1970 	if (!chip)
1971 		return -ENOMEM;
1972 
1973 	chip->pdev = pdev;
1974 	chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1975 	if (chip->fixes) {
1976 		chip->quirks = chip->fixes->quirks;
1977 		chip->quirks2 = chip->fixes->quirks2;
1978 		chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1979 	}
1980 	chip->num_slots = slots;
1981 	chip->pm_retune = true;
1982 	chip->rpm_retune = true;
1983 
1984 	pci_set_drvdata(pdev, chip);
1985 
1986 	if (chip->fixes && chip->fixes->probe) {
1987 		ret = chip->fixes->probe(chip);
1988 		if (ret)
1989 			return ret;
1990 	}
1991 
1992 	slots = chip->num_slots;	/* Quirk may have changed this */
1993 
1994 	for (i = 0; i < slots; i++) {
1995 		slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
1996 		if (IS_ERR(slot)) {
1997 			for (i--; i >= 0; i--)
1998 				sdhci_pci_remove_slot(chip->slots[i]);
1999 			return PTR_ERR(slot);
2000 		}
2001 
2002 		chip->slots[i] = slot;
2003 	}
2004 
2005 	if (chip->allow_runtime_pm)
2006 		sdhci_pci_runtime_pm_allow(&pdev->dev);
2007 
2008 	return 0;
2009 }
2010 
2011 static void sdhci_pci_remove(struct pci_dev *pdev)
2012 {
2013 	int i;
2014 	struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
2015 
2016 	if (chip->allow_runtime_pm)
2017 		sdhci_pci_runtime_pm_forbid(&pdev->dev);
2018 
2019 	for (i = 0; i < chip->num_slots; i++)
2020 		sdhci_pci_remove_slot(chip->slots[i]);
2021 }
2022 
2023 static struct pci_driver sdhci_driver = {
2024 	.name =		"sdhci-pci",
2025 	.id_table =	pci_ids,
2026 	.probe =	sdhci_pci_probe,
2027 	.remove =	sdhci_pci_remove,
2028 	.driver =	{
2029 		.pm =   &sdhci_pci_pm_ops
2030 	},
2031 };
2032 
2033 module_pci_driver(sdhci_driver);
2034 
2035 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2036 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
2037 MODULE_LICENSE("GPL");
2038