1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 2 * 3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 * 10 * Thanks to the following companies for their support: 11 * 12 * - JMicron (hardware and technical support) 13 */ 14 15 #include <linux/string.h> 16 #include <linux/delay.h> 17 #include <linux/highmem.h> 18 #include <linux/module.h> 19 #include <linux/pci.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/slab.h> 22 #include <linux/device.h> 23 #include <linux/mmc/host.h> 24 #include <linux/mmc/mmc.h> 25 #include <linux/scatterlist.h> 26 #include <linux/io.h> 27 #include <linux/gpio.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/mmc/slot-gpio.h> 30 #include <linux/mmc/sdhci-pci-data.h> 31 #include <linux/acpi.h> 32 33 #include "sdhci.h" 34 #include "sdhci-pci.h" 35 #include "sdhci-pci-o2micro.h" 36 37 static int sdhci_pci_enable_dma(struct sdhci_host *host); 38 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width); 39 static void sdhci_pci_hw_reset(struct sdhci_host *host); 40 41 #ifdef CONFIG_PM_SLEEP 42 static int __sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 43 { 44 int i, ret; 45 46 for (i = 0; i < chip->num_slots; i++) { 47 struct sdhci_pci_slot *slot = chip->slots[i]; 48 struct sdhci_host *host; 49 50 if (!slot) 51 continue; 52 53 host = slot->host; 54 55 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 56 mmc_retune_needed(host->mmc); 57 58 ret = sdhci_suspend_host(host); 59 if (ret) 60 goto err_pci_suspend; 61 62 if (host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ) 63 sdhci_enable_irq_wakeups(host); 64 } 65 66 return 0; 67 68 err_pci_suspend: 69 while (--i >= 0) 70 sdhci_resume_host(chip->slots[i]->host); 71 return ret; 72 } 73 74 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip) 75 { 76 mmc_pm_flag_t pm_flags = 0; 77 int i; 78 79 for (i = 0; i < chip->num_slots; i++) { 80 struct sdhci_pci_slot *slot = chip->slots[i]; 81 82 if (slot) 83 pm_flags |= slot->host->mmc->pm_flags; 84 } 85 86 return device_init_wakeup(&chip->pdev->dev, 87 (pm_flags & MMC_PM_KEEP_POWER) && 88 (pm_flags & MMC_PM_WAKE_SDIO_IRQ)); 89 } 90 91 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 92 { 93 int ret; 94 95 ret = __sdhci_pci_suspend_host(chip); 96 if (ret) 97 return ret; 98 99 sdhci_pci_init_wakeup(chip); 100 101 return 0; 102 } 103 104 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip) 105 { 106 struct sdhci_pci_slot *slot; 107 int i, ret; 108 109 for (i = 0; i < chip->num_slots; i++) { 110 slot = chip->slots[i]; 111 if (!slot) 112 continue; 113 114 ret = sdhci_resume_host(slot->host); 115 if (ret) 116 return ret; 117 } 118 119 return 0; 120 } 121 #endif 122 123 #ifdef CONFIG_PM 124 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip) 125 { 126 struct sdhci_pci_slot *slot; 127 struct sdhci_host *host; 128 int i, ret; 129 130 for (i = 0; i < chip->num_slots; i++) { 131 slot = chip->slots[i]; 132 if (!slot) 133 continue; 134 135 host = slot->host; 136 137 ret = sdhci_runtime_suspend_host(host); 138 if (ret) 139 goto err_pci_runtime_suspend; 140 141 if (chip->rpm_retune && 142 host->tuning_mode != SDHCI_TUNING_MODE_3) 143 mmc_retune_needed(host->mmc); 144 } 145 146 return 0; 147 148 err_pci_runtime_suspend: 149 while (--i >= 0) 150 sdhci_runtime_resume_host(chip->slots[i]->host); 151 return ret; 152 } 153 154 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip) 155 { 156 struct sdhci_pci_slot *slot; 157 int i, ret; 158 159 for (i = 0; i < chip->num_slots; i++) { 160 slot = chip->slots[i]; 161 if (!slot) 162 continue; 163 164 ret = sdhci_runtime_resume_host(slot->host); 165 if (ret) 166 return ret; 167 } 168 169 return 0; 170 } 171 #endif 172 173 /*****************************************************************************\ 174 * * 175 * Hardware specific quirk handling * 176 * * 177 \*****************************************************************************/ 178 179 static int ricoh_probe(struct sdhci_pci_chip *chip) 180 { 181 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 182 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 183 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 184 return 0; 185 } 186 187 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 188 { 189 slot->host->caps = 190 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 191 & SDHCI_TIMEOUT_CLK_MASK) | 192 193 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 194 & SDHCI_CLOCK_BASE_MASK) | 195 196 SDHCI_TIMEOUT_CLK_UNIT | 197 SDHCI_CAN_VDD_330 | 198 SDHCI_CAN_DO_HISPD | 199 SDHCI_CAN_DO_SDMA; 200 return 0; 201 } 202 203 #ifdef CONFIG_PM_SLEEP 204 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 205 { 206 /* Apply a delay to allow controller to settle */ 207 /* Otherwise it becomes confused if card state changed 208 during suspend */ 209 msleep(500); 210 return sdhci_pci_resume_host(chip); 211 } 212 #endif 213 214 static const struct sdhci_pci_fixes sdhci_ricoh = { 215 .probe = ricoh_probe, 216 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 217 SDHCI_QUIRK_FORCE_DMA | 218 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 219 }; 220 221 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 222 .probe_slot = ricoh_mmc_probe_slot, 223 #ifdef CONFIG_PM_SLEEP 224 .resume = ricoh_mmc_resume, 225 #endif 226 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 227 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 228 SDHCI_QUIRK_NO_CARD_NO_RESET | 229 SDHCI_QUIRK_MISSING_CAPS 230 }; 231 232 static const struct sdhci_pci_fixes sdhci_ene_712 = { 233 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 234 SDHCI_QUIRK_BROKEN_DMA, 235 }; 236 237 static const struct sdhci_pci_fixes sdhci_ene_714 = { 238 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 239 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 240 SDHCI_QUIRK_BROKEN_DMA, 241 }; 242 243 static const struct sdhci_pci_fixes sdhci_cafe = { 244 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 245 SDHCI_QUIRK_NO_BUSY_IRQ | 246 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 247 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 248 }; 249 250 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 251 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 252 }; 253 254 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 255 { 256 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 257 return 0; 258 } 259 260 /* 261 * ADMA operation is disabled for Moorestown platform due to 262 * hardware bugs. 263 */ 264 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 265 { 266 /* 267 * slots number is fixed here for MRST as SDIO3/5 are never used and 268 * have hardware bugs. 269 */ 270 chip->num_slots = 1; 271 return 0; 272 } 273 274 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 275 { 276 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 277 return 0; 278 } 279 280 #ifdef CONFIG_PM 281 282 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 283 { 284 struct sdhci_pci_slot *slot = dev_id; 285 struct sdhci_host *host = slot->host; 286 287 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 288 return IRQ_HANDLED; 289 } 290 291 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 292 { 293 int err, irq, gpio = slot->cd_gpio; 294 295 slot->cd_gpio = -EINVAL; 296 slot->cd_irq = -EINVAL; 297 298 if (!gpio_is_valid(gpio)) 299 return; 300 301 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 302 if (err < 0) 303 goto out; 304 305 err = gpio_direction_input(gpio); 306 if (err < 0) 307 goto out_free; 308 309 irq = gpio_to_irq(gpio); 310 if (irq < 0) 311 goto out_free; 312 313 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 314 IRQF_TRIGGER_FALLING, "sd_cd", slot); 315 if (err) 316 goto out_free; 317 318 slot->cd_gpio = gpio; 319 slot->cd_irq = irq; 320 321 return; 322 323 out_free: 324 devm_gpio_free(&slot->chip->pdev->dev, gpio); 325 out: 326 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 327 } 328 329 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 330 { 331 if (slot->cd_irq >= 0) 332 free_irq(slot->cd_irq, slot); 333 } 334 335 #else 336 337 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 338 { 339 } 340 341 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 342 { 343 } 344 345 #endif 346 347 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 348 { 349 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 350 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC | 351 MMC_CAP2_HC_ERASE_SZ; 352 return 0; 353 } 354 355 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 356 { 357 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 358 return 0; 359 } 360 361 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 362 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 363 .probe_slot = mrst_hc_probe_slot, 364 }; 365 366 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 367 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 368 .probe = mrst_hc_probe, 369 }; 370 371 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 372 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 373 .allow_runtime_pm = true, 374 .own_cd_for_runtime_pm = true, 375 }; 376 377 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 378 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 379 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 380 .allow_runtime_pm = true, 381 .probe_slot = mfd_sdio_probe_slot, 382 }; 383 384 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 385 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 386 .allow_runtime_pm = true, 387 .probe_slot = mfd_emmc_probe_slot, 388 }; 389 390 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 391 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 392 .probe_slot = pch_hc_probe_slot, 393 }; 394 395 enum { 396 INTEL_DSM_FNS = 0, 397 INTEL_DSM_DRV_STRENGTH = 9, 398 INTEL_DSM_D3_RETUNE = 10, 399 }; 400 401 struct intel_host { 402 u32 dsm_fns; 403 int drv_strength; 404 bool d3_retune; 405 }; 406 407 const u8 intel_dsm_uuid[] = { 408 0xA5, 0x3E, 0xC1, 0xF6, 0xCD, 0x65, 0x1F, 0x46, 409 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61, 410 }; 411 412 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 413 unsigned int fn, u32 *result) 414 { 415 union acpi_object *obj; 416 int err = 0; 417 size_t len; 418 419 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), intel_dsm_uuid, 0, fn, NULL); 420 if (!obj) 421 return -EOPNOTSUPP; 422 423 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { 424 err = -EINVAL; 425 goto out; 426 } 427 428 len = min_t(size_t, obj->buffer.length, 4); 429 430 *result = 0; 431 memcpy(result, obj->buffer.pointer, len); 432 out: 433 ACPI_FREE(obj); 434 435 return err; 436 } 437 438 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 439 unsigned int fn, u32 *result) 440 { 441 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 442 return -EOPNOTSUPP; 443 444 return __intel_dsm(intel_host, dev, fn, result); 445 } 446 447 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 448 struct mmc_host *mmc) 449 { 450 int err; 451 u32 val; 452 453 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 454 if (err) { 455 pr_debug("%s: DSM not supported, error %d\n", 456 mmc_hostname(mmc), err); 457 return; 458 } 459 460 pr_debug("%s: DSM function mask %#x\n", 461 mmc_hostname(mmc), intel_host->dsm_fns); 462 463 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 464 intel_host->drv_strength = err ? 0 : val; 465 466 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 467 intel_host->d3_retune = err ? true : !!val; 468 } 469 470 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 471 { 472 u8 reg; 473 474 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 475 reg |= 0x10; 476 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 477 /* For eMMC, minimum is 1us but give it 9us for good measure */ 478 udelay(9); 479 reg &= ~0x10; 480 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 481 /* For eMMC, minimum is 200us but give it 300us for good measure */ 482 usleep_range(300, 1000); 483 } 484 485 static int intel_select_drive_strength(struct mmc_card *card, 486 unsigned int max_dtr, int host_drv, 487 int card_drv, int *drv_type) 488 { 489 struct sdhci_host *host = mmc_priv(card->host); 490 struct sdhci_pci_slot *slot = sdhci_priv(host); 491 struct intel_host *intel_host = sdhci_pci_priv(slot); 492 493 return intel_host->drv_strength; 494 } 495 496 static int bxt_get_cd(struct mmc_host *mmc) 497 { 498 int gpio_cd = mmc_gpio_get_cd(mmc); 499 struct sdhci_host *host = mmc_priv(mmc); 500 unsigned long flags; 501 int ret = 0; 502 503 if (!gpio_cd) 504 return 0; 505 506 spin_lock_irqsave(&host->lock, flags); 507 508 if (host->flags & SDHCI_DEVICE_DEAD) 509 goto out; 510 511 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 512 out: 513 spin_unlock_irqrestore(&host->lock, flags); 514 515 return ret; 516 } 517 518 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 519 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 520 521 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 522 unsigned short vdd) 523 { 524 int cntr; 525 u8 reg; 526 527 sdhci_set_power(host, mode, vdd); 528 529 if (mode == MMC_POWER_OFF) 530 return; 531 532 /* 533 * Bus power might not enable after D3 -> D0 transition due to the 534 * present state not yet having propagated. Retry for up to 2ms. 535 */ 536 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 537 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 538 if (reg & SDHCI_POWER_ON) 539 break; 540 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 541 reg |= SDHCI_POWER_ON; 542 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 543 } 544 } 545 546 #define INTEL_HS400_ES_REG 0x78 547 #define INTEL_HS400_ES_BIT BIT(0) 548 549 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc, 550 struct mmc_ios *ios) 551 { 552 struct sdhci_host *host = mmc_priv(mmc); 553 u32 val; 554 555 val = sdhci_readl(host, INTEL_HS400_ES_REG); 556 if (ios->enhanced_strobe) 557 val |= INTEL_HS400_ES_BIT; 558 else 559 val &= ~INTEL_HS400_ES_BIT; 560 sdhci_writel(host, val, INTEL_HS400_ES_REG); 561 } 562 563 static const struct sdhci_ops sdhci_intel_byt_ops = { 564 .set_clock = sdhci_set_clock, 565 .set_power = sdhci_intel_set_power, 566 .enable_dma = sdhci_pci_enable_dma, 567 .set_bus_width = sdhci_pci_set_bus_width, 568 .reset = sdhci_reset, 569 .set_uhs_signaling = sdhci_set_uhs_signaling, 570 .hw_reset = sdhci_pci_hw_reset, 571 }; 572 573 static void byt_read_dsm(struct sdhci_pci_slot *slot) 574 { 575 struct intel_host *intel_host = sdhci_pci_priv(slot); 576 struct device *dev = &slot->chip->pdev->dev; 577 struct mmc_host *mmc = slot->host->mmc; 578 579 intel_dsm_init(intel_host, dev, mmc); 580 slot->chip->rpm_retune = intel_host->d3_retune; 581 } 582 583 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 584 { 585 byt_read_dsm(slot); 586 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 587 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 588 MMC_CAP_CMD_DURING_TFR | 589 MMC_CAP_WAIT_WHILE_BUSY; 590 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ; 591 slot->hw_reset = sdhci_pci_int_hw_reset; 592 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 593 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 594 slot->host->mmc_host_ops.select_drive_strength = 595 intel_select_drive_strength; 596 return 0; 597 } 598 599 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot) 600 { 601 int ret = byt_emmc_probe_slot(slot); 602 603 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) { 604 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES, 605 slot->host->mmc_host_ops.hs400_enhanced_strobe = 606 intel_hs400_enhanced_strobe; 607 } 608 609 return ret; 610 } 611 612 #ifdef CONFIG_ACPI 613 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 614 { 615 acpi_status status; 616 unsigned long long max_freq; 617 618 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 619 "MXFQ", NULL, &max_freq); 620 if (ACPI_FAILURE(status)) { 621 dev_err(&slot->chip->pdev->dev, 622 "MXFQ not found in acpi table\n"); 623 return -EINVAL; 624 } 625 626 slot->host->mmc->f_max = max_freq * 1000000; 627 628 return 0; 629 } 630 #else 631 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 632 { 633 return 0; 634 } 635 #endif 636 637 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 638 { 639 int err; 640 641 byt_read_dsm(slot); 642 643 err = ni_set_max_freq(slot); 644 if (err) 645 return err; 646 647 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 648 MMC_CAP_WAIT_WHILE_BUSY; 649 return 0; 650 } 651 652 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 653 { 654 byt_read_dsm(slot); 655 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 656 MMC_CAP_WAIT_WHILE_BUSY; 657 return 0; 658 } 659 660 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 661 { 662 byt_read_dsm(slot); 663 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | 664 MMC_CAP_AGGRESSIVE_PM; 665 slot->cd_idx = 0; 666 slot->cd_override_level = true; 667 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 668 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 669 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 670 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) 671 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 672 673 return 0; 674 } 675 676 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 677 .allow_runtime_pm = true, 678 .probe_slot = byt_emmc_probe_slot, 679 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 680 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 681 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 682 SDHCI_QUIRK2_STOP_WITH_TC, 683 .ops = &sdhci_intel_byt_ops, 684 .priv_size = sizeof(struct intel_host), 685 }; 686 687 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = { 688 .allow_runtime_pm = true, 689 .probe_slot = glk_emmc_probe_slot, 690 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 691 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 692 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 693 SDHCI_QUIRK2_STOP_WITH_TC, 694 .ops = &sdhci_intel_byt_ops, 695 .priv_size = sizeof(struct intel_host), 696 }; 697 698 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 699 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 700 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 701 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 702 .allow_runtime_pm = true, 703 .probe_slot = ni_byt_sdio_probe_slot, 704 .ops = &sdhci_intel_byt_ops, 705 .priv_size = sizeof(struct intel_host), 706 }; 707 708 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 709 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 710 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 711 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 712 .allow_runtime_pm = true, 713 .probe_slot = byt_sdio_probe_slot, 714 .ops = &sdhci_intel_byt_ops, 715 .priv_size = sizeof(struct intel_host), 716 }; 717 718 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 719 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 720 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 721 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 722 SDHCI_QUIRK2_STOP_WITH_TC, 723 .allow_runtime_pm = true, 724 .own_cd_for_runtime_pm = true, 725 .probe_slot = byt_sd_probe_slot, 726 .ops = &sdhci_intel_byt_ops, 727 .priv_size = sizeof(struct intel_host), 728 }; 729 730 /* Define Host controllers for Intel Merrifield platform */ 731 #define INTEL_MRFLD_EMMC_0 0 732 #define INTEL_MRFLD_EMMC_1 1 733 #define INTEL_MRFLD_SD 2 734 #define INTEL_MRFLD_SDIO 3 735 736 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 737 { 738 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 739 740 switch (func) { 741 case INTEL_MRFLD_EMMC_0: 742 case INTEL_MRFLD_EMMC_1: 743 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 744 MMC_CAP_8_BIT_DATA | 745 MMC_CAP_1_8V_DDR; 746 break; 747 case INTEL_MRFLD_SD: 748 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 749 break; 750 case INTEL_MRFLD_SDIO: 751 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 752 MMC_CAP_POWER_OFF_CARD; 753 break; 754 default: 755 return -ENODEV; 756 } 757 return 0; 758 } 759 760 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 761 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 762 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 763 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 764 .allow_runtime_pm = true, 765 .probe_slot = intel_mrfld_mmc_probe_slot, 766 }; 767 768 /* O2Micro extra registers */ 769 #define O2_SD_LOCK_WP 0xD3 770 #define O2_SD_MULTI_VCC3V 0xEE 771 #define O2_SD_CLKREQ 0xEC 772 #define O2_SD_CAPS 0xE0 773 #define O2_SD_ADMA1 0xE2 774 #define O2_SD_ADMA2 0xE7 775 #define O2_SD_INF_MOD 0xF1 776 777 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 778 { 779 u8 scratch; 780 int ret; 781 782 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 783 if (ret) 784 return ret; 785 786 /* 787 * Turn PMOS on [bit 0], set over current detection to 2.4 V 788 * [bit 1:2] and enable over current debouncing [bit 6]. 789 */ 790 if (on) 791 scratch |= 0x47; 792 else 793 scratch &= ~0x47; 794 795 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 796 } 797 798 static int jmicron_probe(struct sdhci_pci_chip *chip) 799 { 800 int ret; 801 u16 mmcdev = 0; 802 803 if (chip->pdev->revision == 0) { 804 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 805 SDHCI_QUIRK_32BIT_DMA_SIZE | 806 SDHCI_QUIRK_32BIT_ADMA_SIZE | 807 SDHCI_QUIRK_RESET_AFTER_REQUEST | 808 SDHCI_QUIRK_BROKEN_SMALL_PIO; 809 } 810 811 /* 812 * JMicron chips can have two interfaces to the same hardware 813 * in order to work around limitations in Microsoft's driver. 814 * We need to make sure we only bind to one of them. 815 * 816 * This code assumes two things: 817 * 818 * 1. The PCI code adds subfunctions in order. 819 * 820 * 2. The MMC interface has a lower subfunction number 821 * than the SD interface. 822 */ 823 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 824 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 825 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 826 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 827 828 if (mmcdev) { 829 struct pci_dev *sd_dev; 830 831 sd_dev = NULL; 832 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 833 mmcdev, sd_dev)) != NULL) { 834 if ((PCI_SLOT(chip->pdev->devfn) == 835 PCI_SLOT(sd_dev->devfn)) && 836 (chip->pdev->bus == sd_dev->bus)) 837 break; 838 } 839 840 if (sd_dev) { 841 pci_dev_put(sd_dev); 842 dev_info(&chip->pdev->dev, "Refusing to bind to " 843 "secondary interface.\n"); 844 return -ENODEV; 845 } 846 } 847 848 /* 849 * JMicron chips need a bit of a nudge to enable the power 850 * output pins. 851 */ 852 ret = jmicron_pmos(chip, 1); 853 if (ret) { 854 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 855 return ret; 856 } 857 858 /* quirk for unsable RO-detection on JM388 chips */ 859 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 860 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 861 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 862 863 return 0; 864 } 865 866 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 867 { 868 u8 scratch; 869 870 scratch = readb(host->ioaddr + 0xC0); 871 872 if (on) 873 scratch |= 0x01; 874 else 875 scratch &= ~0x01; 876 877 writeb(scratch, host->ioaddr + 0xC0); 878 } 879 880 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 881 { 882 if (slot->chip->pdev->revision == 0) { 883 u16 version; 884 885 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 886 version = (version & SDHCI_VENDOR_VER_MASK) >> 887 SDHCI_VENDOR_VER_SHIFT; 888 889 /* 890 * Older versions of the chip have lots of nasty glitches 891 * in the ADMA engine. It's best just to avoid it 892 * completely. 893 */ 894 if (version < 0xAC) 895 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 896 } 897 898 /* JM388 MMC doesn't support 1.8V while SD supports it */ 899 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 900 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 901 MMC_VDD_29_30 | MMC_VDD_30_31 | 902 MMC_VDD_165_195; /* allow 1.8V */ 903 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 904 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 905 } 906 907 /* 908 * The secondary interface requires a bit set to get the 909 * interrupts. 910 */ 911 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 912 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 913 jmicron_enable_mmc(slot->host, 1); 914 915 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 916 917 return 0; 918 } 919 920 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 921 { 922 if (dead) 923 return; 924 925 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 926 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 927 jmicron_enable_mmc(slot->host, 0); 928 } 929 930 #ifdef CONFIG_PM_SLEEP 931 static int jmicron_suspend(struct sdhci_pci_chip *chip) 932 { 933 int i, ret; 934 935 ret = __sdhci_pci_suspend_host(chip); 936 if (ret) 937 return ret; 938 939 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 940 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 941 for (i = 0; i < chip->num_slots; i++) 942 jmicron_enable_mmc(chip->slots[i]->host, 0); 943 } 944 945 sdhci_pci_init_wakeup(chip); 946 947 return 0; 948 } 949 950 static int jmicron_resume(struct sdhci_pci_chip *chip) 951 { 952 int ret, i; 953 954 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 955 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 956 for (i = 0; i < chip->num_slots; i++) 957 jmicron_enable_mmc(chip->slots[i]->host, 1); 958 } 959 960 ret = jmicron_pmos(chip, 1); 961 if (ret) { 962 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 963 return ret; 964 } 965 966 return sdhci_pci_resume_host(chip); 967 } 968 #endif 969 970 static const struct sdhci_pci_fixes sdhci_o2 = { 971 .probe = sdhci_pci_o2_probe, 972 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 973 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 974 .probe_slot = sdhci_pci_o2_probe_slot, 975 #ifdef CONFIG_PM_SLEEP 976 .resume = sdhci_pci_o2_resume, 977 #endif 978 }; 979 980 static const struct sdhci_pci_fixes sdhci_jmicron = { 981 .probe = jmicron_probe, 982 983 .probe_slot = jmicron_probe_slot, 984 .remove_slot = jmicron_remove_slot, 985 986 #ifdef CONFIG_PM_SLEEP 987 .suspend = jmicron_suspend, 988 .resume = jmicron_resume, 989 #endif 990 }; 991 992 /* SysKonnect CardBus2SDIO extra registers */ 993 #define SYSKT_CTRL 0x200 994 #define SYSKT_RDFIFO_STAT 0x204 995 #define SYSKT_WRFIFO_STAT 0x208 996 #define SYSKT_POWER_DATA 0x20c 997 #define SYSKT_POWER_330 0xef 998 #define SYSKT_POWER_300 0xf8 999 #define SYSKT_POWER_184 0xcc 1000 #define SYSKT_POWER_CMD 0x20d 1001 #define SYSKT_POWER_START (1 << 7) 1002 #define SYSKT_POWER_STATUS 0x20e 1003 #define SYSKT_POWER_STATUS_OK (1 << 0) 1004 #define SYSKT_BOARD_REV 0x210 1005 #define SYSKT_CHIP_REV 0x211 1006 #define SYSKT_CONF_DATA 0x212 1007 #define SYSKT_CONF_DATA_1V8 (1 << 2) 1008 #define SYSKT_CONF_DATA_2V5 (1 << 1) 1009 #define SYSKT_CONF_DATA_3V3 (1 << 0) 1010 1011 static int syskt_probe(struct sdhci_pci_chip *chip) 1012 { 1013 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1014 chip->pdev->class &= ~0x0000FF; 1015 chip->pdev->class |= PCI_SDHCI_IFDMA; 1016 } 1017 return 0; 1018 } 1019 1020 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 1021 { 1022 int tm, ps; 1023 1024 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 1025 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 1026 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 1027 "board rev %d.%d, chip rev %d.%d\n", 1028 board_rev >> 4, board_rev & 0xf, 1029 chip_rev >> 4, chip_rev & 0xf); 1030 if (chip_rev >= 0x20) 1031 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 1032 1033 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 1034 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 1035 udelay(50); 1036 tm = 10; /* Wait max 1 ms */ 1037 do { 1038 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 1039 if (ps & SYSKT_POWER_STATUS_OK) 1040 break; 1041 udelay(100); 1042 } while (--tm); 1043 if (!tm) { 1044 dev_err(&slot->chip->pdev->dev, 1045 "power regulator never stabilized"); 1046 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 1047 return -ENODEV; 1048 } 1049 1050 return 0; 1051 } 1052 1053 static const struct sdhci_pci_fixes sdhci_syskt = { 1054 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 1055 .probe = syskt_probe, 1056 .probe_slot = syskt_probe_slot, 1057 }; 1058 1059 static int via_probe(struct sdhci_pci_chip *chip) 1060 { 1061 if (chip->pdev->revision == 0x10) 1062 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 1063 1064 return 0; 1065 } 1066 1067 static const struct sdhci_pci_fixes sdhci_via = { 1068 .probe = via_probe, 1069 }; 1070 1071 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 1072 { 1073 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 1074 return 0; 1075 } 1076 1077 static const struct sdhci_pci_fixes sdhci_rtsx = { 1078 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1079 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 1080 SDHCI_QUIRK2_BROKEN_DDR50, 1081 .probe_slot = rtsx_probe_slot, 1082 }; 1083 1084 /*AMD chipset generation*/ 1085 enum amd_chipset_gen { 1086 AMD_CHIPSET_BEFORE_ML, 1087 AMD_CHIPSET_CZ, 1088 AMD_CHIPSET_NL, 1089 AMD_CHIPSET_UNKNOWN, 1090 }; 1091 1092 /* AMD registers */ 1093 #define AMD_SD_AUTO_PATTERN 0xB8 1094 #define AMD_MSLEEP_DURATION 4 1095 #define AMD_SD_MISC_CONTROL 0xD0 1096 #define AMD_MAX_TUNE_VALUE 0x0B 1097 #define AMD_AUTO_TUNE_SEL 0x10800 1098 #define AMD_FIFO_PTR 0x30 1099 #define AMD_BIT_MASK 0x1F 1100 1101 static void amd_tuning_reset(struct sdhci_host *host) 1102 { 1103 unsigned int val; 1104 1105 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1106 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 1107 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1108 1109 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1110 val &= ~SDHCI_CTRL_EXEC_TUNING; 1111 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1112 } 1113 1114 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 1115 { 1116 unsigned int val; 1117 1118 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 1119 val &= ~AMD_BIT_MASK; 1120 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 1121 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 1122 } 1123 1124 static void amd_enable_manual_tuning(struct pci_dev *pdev) 1125 { 1126 unsigned int val; 1127 1128 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 1129 val |= AMD_FIFO_PTR; 1130 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 1131 } 1132 1133 static int amd_execute_tuning(struct sdhci_host *host, u32 opcode) 1134 { 1135 struct sdhci_pci_slot *slot = sdhci_priv(host); 1136 struct pci_dev *pdev = slot->chip->pdev; 1137 u8 valid_win = 0; 1138 u8 valid_win_max = 0; 1139 u8 valid_win_end = 0; 1140 u8 ctrl, tune_around; 1141 1142 amd_tuning_reset(host); 1143 1144 for (tune_around = 0; tune_around < 12; tune_around++) { 1145 amd_config_tuning_phase(pdev, tune_around); 1146 1147 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1148 valid_win = 0; 1149 msleep(AMD_MSLEEP_DURATION); 1150 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 1151 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 1152 } else if (++valid_win > valid_win_max) { 1153 valid_win_max = valid_win; 1154 valid_win_end = tune_around; 1155 } 1156 } 1157 1158 if (!valid_win_max) { 1159 dev_err(&pdev->dev, "no tuning point found\n"); 1160 return -EIO; 1161 } 1162 1163 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 1164 1165 amd_enable_manual_tuning(pdev); 1166 1167 host->mmc->retune_period = 0; 1168 1169 return 0; 1170 } 1171 1172 static int amd_probe(struct sdhci_pci_chip *chip) 1173 { 1174 struct pci_dev *smbus_dev; 1175 enum amd_chipset_gen gen; 1176 1177 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1178 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 1179 if (smbus_dev) { 1180 gen = AMD_CHIPSET_BEFORE_ML; 1181 } else { 1182 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1183 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1184 if (smbus_dev) { 1185 if (smbus_dev->revision < 0x51) 1186 gen = AMD_CHIPSET_CZ; 1187 else 1188 gen = AMD_CHIPSET_NL; 1189 } else { 1190 gen = AMD_CHIPSET_UNKNOWN; 1191 } 1192 } 1193 1194 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1195 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1196 1197 return 0; 1198 } 1199 1200 static const struct sdhci_ops amd_sdhci_pci_ops = { 1201 .set_clock = sdhci_set_clock, 1202 .enable_dma = sdhci_pci_enable_dma, 1203 .set_bus_width = sdhci_pci_set_bus_width, 1204 .reset = sdhci_reset, 1205 .set_uhs_signaling = sdhci_set_uhs_signaling, 1206 .platform_execute_tuning = amd_execute_tuning, 1207 }; 1208 1209 static const struct sdhci_pci_fixes sdhci_amd = { 1210 .probe = amd_probe, 1211 .ops = &amd_sdhci_pci_ops, 1212 }; 1213 1214 static const struct pci_device_id pci_ids[] = { 1215 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh), 1216 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc), 1217 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc), 1218 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc), 1219 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712), 1220 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712), 1221 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714), 1222 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714), 1223 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe), 1224 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron), 1225 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron), 1226 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron), 1227 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron), 1228 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt), 1229 SDHCI_PCI_DEVICE(VIA, 95D0, via), 1230 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx), 1231 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk), 1232 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0), 1233 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2), 1234 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2), 1235 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd), 1236 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio), 1237 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio), 1238 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc), 1239 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc), 1240 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio), 1241 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio), 1242 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc), 1243 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio), 1244 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio), 1245 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd), 1246 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc), 1247 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc), 1248 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio), 1249 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd), 1250 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd), 1251 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio), 1252 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio), 1253 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc), 1254 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc), 1255 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc), 1256 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc), 1257 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio), 1258 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd), 1259 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc), 1260 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc), 1261 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio), 1262 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd), 1263 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc), 1264 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio), 1265 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd), 1266 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc), 1267 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio), 1268 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd), 1269 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc), 1270 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio), 1271 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd), 1272 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc), 1273 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd), 1274 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd), 1275 SDHCI_PCI_DEVICE(O2, 8120, o2), 1276 SDHCI_PCI_DEVICE(O2, 8220, o2), 1277 SDHCI_PCI_DEVICE(O2, 8221, o2), 1278 SDHCI_PCI_DEVICE(O2, 8320, o2), 1279 SDHCI_PCI_DEVICE(O2, 8321, o2), 1280 SDHCI_PCI_DEVICE(O2, FUJIN2, o2), 1281 SDHCI_PCI_DEVICE(O2, SDS0, o2), 1282 SDHCI_PCI_DEVICE(O2, SDS1, o2), 1283 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2), 1284 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), 1285 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), 1286 /* Generic SD host controller */ 1287 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, 1288 { /* end: all zeroes */ }, 1289 }; 1290 1291 MODULE_DEVICE_TABLE(pci, pci_ids); 1292 1293 /*****************************************************************************\ 1294 * * 1295 * SDHCI core callbacks * 1296 * * 1297 \*****************************************************************************/ 1298 1299 static int sdhci_pci_enable_dma(struct sdhci_host *host) 1300 { 1301 struct sdhci_pci_slot *slot; 1302 struct pci_dev *pdev; 1303 1304 slot = sdhci_priv(host); 1305 pdev = slot->chip->pdev; 1306 1307 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1308 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1309 (host->flags & SDHCI_USE_SDMA)) { 1310 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1311 "doesn't fully claim to support it.\n"); 1312 } 1313 1314 pci_set_master(pdev); 1315 1316 return 0; 1317 } 1318 1319 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width) 1320 { 1321 u8 ctrl; 1322 1323 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1324 1325 switch (width) { 1326 case MMC_BUS_WIDTH_8: 1327 ctrl |= SDHCI_CTRL_8BITBUS; 1328 ctrl &= ~SDHCI_CTRL_4BITBUS; 1329 break; 1330 case MMC_BUS_WIDTH_4: 1331 ctrl |= SDHCI_CTRL_4BITBUS; 1332 ctrl &= ~SDHCI_CTRL_8BITBUS; 1333 break; 1334 default: 1335 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS); 1336 break; 1337 } 1338 1339 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1340 } 1341 1342 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1343 { 1344 struct sdhci_pci_slot *slot = sdhci_priv(host); 1345 int rst_n_gpio = slot->rst_n_gpio; 1346 1347 if (!gpio_is_valid(rst_n_gpio)) 1348 return; 1349 gpio_set_value_cansleep(rst_n_gpio, 0); 1350 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1351 udelay(10); 1352 gpio_set_value_cansleep(rst_n_gpio, 1); 1353 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1354 usleep_range(300, 1000); 1355 } 1356 1357 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1358 { 1359 struct sdhci_pci_slot *slot = sdhci_priv(host); 1360 1361 if (slot->hw_reset) 1362 slot->hw_reset(host); 1363 } 1364 1365 static const struct sdhci_ops sdhci_pci_ops = { 1366 .set_clock = sdhci_set_clock, 1367 .enable_dma = sdhci_pci_enable_dma, 1368 .set_bus_width = sdhci_pci_set_bus_width, 1369 .reset = sdhci_reset, 1370 .set_uhs_signaling = sdhci_set_uhs_signaling, 1371 .hw_reset = sdhci_pci_hw_reset, 1372 }; 1373 1374 /*****************************************************************************\ 1375 * * 1376 * Suspend/resume * 1377 * * 1378 \*****************************************************************************/ 1379 1380 #ifdef CONFIG_PM_SLEEP 1381 static int sdhci_pci_suspend(struct device *dev) 1382 { 1383 struct pci_dev *pdev = to_pci_dev(dev); 1384 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1385 1386 if (!chip) 1387 return 0; 1388 1389 if (chip->fixes && chip->fixes->suspend) 1390 return chip->fixes->suspend(chip); 1391 1392 return sdhci_pci_suspend_host(chip); 1393 } 1394 1395 static int sdhci_pci_resume(struct device *dev) 1396 { 1397 struct pci_dev *pdev = to_pci_dev(dev); 1398 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1399 1400 if (!chip) 1401 return 0; 1402 1403 if (chip->fixes && chip->fixes->resume) 1404 return chip->fixes->resume(chip); 1405 1406 return sdhci_pci_resume_host(chip); 1407 } 1408 #endif 1409 1410 #ifdef CONFIG_PM 1411 static int sdhci_pci_runtime_suspend(struct device *dev) 1412 { 1413 struct pci_dev *pdev = to_pci_dev(dev); 1414 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1415 1416 if (!chip) 1417 return 0; 1418 1419 if (chip->fixes && chip->fixes->runtime_suspend) 1420 return chip->fixes->runtime_suspend(chip); 1421 1422 return sdhci_pci_runtime_suspend_host(chip); 1423 } 1424 1425 static int sdhci_pci_runtime_resume(struct device *dev) 1426 { 1427 struct pci_dev *pdev = to_pci_dev(dev); 1428 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1429 1430 if (!chip) 1431 return 0; 1432 1433 if (chip->fixes && chip->fixes->runtime_resume) 1434 return chip->fixes->runtime_resume(chip); 1435 1436 return sdhci_pci_runtime_resume_host(chip); 1437 } 1438 #endif 1439 1440 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1441 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1442 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1443 sdhci_pci_runtime_resume, NULL) 1444 }; 1445 1446 /*****************************************************************************\ 1447 * * 1448 * Device probing/removal * 1449 * * 1450 \*****************************************************************************/ 1451 1452 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1453 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1454 int slotno) 1455 { 1456 struct sdhci_pci_slot *slot; 1457 struct sdhci_host *host; 1458 int ret, bar = first_bar + slotno; 1459 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 1460 1461 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1462 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1463 return ERR_PTR(-ENODEV); 1464 } 1465 1466 if (pci_resource_len(pdev, bar) < 0x100) { 1467 dev_err(&pdev->dev, "Invalid iomem size. You may " 1468 "experience problems.\n"); 1469 } 1470 1471 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1472 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1473 return ERR_PTR(-ENODEV); 1474 } 1475 1476 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1477 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1478 return ERR_PTR(-ENODEV); 1479 } 1480 1481 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 1482 if (IS_ERR(host)) { 1483 dev_err(&pdev->dev, "cannot allocate host\n"); 1484 return ERR_CAST(host); 1485 } 1486 1487 slot = sdhci_priv(host); 1488 1489 slot->chip = chip; 1490 slot->host = host; 1491 slot->rst_n_gpio = -EINVAL; 1492 slot->cd_gpio = -EINVAL; 1493 slot->cd_idx = -1; 1494 1495 /* Retrieve platform data if there is any */ 1496 if (*sdhci_pci_get_data) 1497 slot->data = sdhci_pci_get_data(pdev, slotno); 1498 1499 if (slot->data) { 1500 if (slot->data->setup) { 1501 ret = slot->data->setup(slot->data); 1502 if (ret) { 1503 dev_err(&pdev->dev, "platform setup failed\n"); 1504 goto free; 1505 } 1506 } 1507 slot->rst_n_gpio = slot->data->rst_n_gpio; 1508 slot->cd_gpio = slot->data->cd_gpio; 1509 } 1510 1511 host->hw_name = "PCI"; 1512 host->ops = chip->fixes && chip->fixes->ops ? 1513 chip->fixes->ops : 1514 &sdhci_pci_ops; 1515 host->quirks = chip->quirks; 1516 host->quirks2 = chip->quirks2; 1517 1518 host->irq = pdev->irq; 1519 1520 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1521 if (ret) { 1522 dev_err(&pdev->dev, "cannot request region\n"); 1523 goto cleanup; 1524 } 1525 1526 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1527 1528 if (chip->fixes && chip->fixes->probe_slot) { 1529 ret = chip->fixes->probe_slot(slot); 1530 if (ret) 1531 goto cleanup; 1532 } 1533 1534 if (gpio_is_valid(slot->rst_n_gpio)) { 1535 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1536 gpio_direction_output(slot->rst_n_gpio, 1); 1537 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1538 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1539 } else { 1540 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1541 slot->rst_n_gpio = -EINVAL; 1542 } 1543 } 1544 1545 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; 1546 host->mmc->slotno = slotno; 1547 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1548 1549 if (slot->cd_idx >= 0) { 1550 ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx, 1551 slot->cd_override_level, 0, NULL); 1552 if (ret == -EPROBE_DEFER) 1553 goto remove; 1554 1555 if (ret) { 1556 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 1557 slot->cd_idx = -1; 1558 } 1559 } 1560 1561 if (chip->fixes && chip->fixes->add_host) 1562 ret = chip->fixes->add_host(slot); 1563 else 1564 ret = sdhci_add_host(host); 1565 if (ret) 1566 goto remove; 1567 1568 sdhci_pci_add_own_cd(slot); 1569 1570 /* 1571 * Check if the chip needs a separate GPIO for card detect to wake up 1572 * from runtime suspend. If it is not there, don't allow runtime PM. 1573 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 1574 */ 1575 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 1576 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 1577 chip->allow_runtime_pm = false; 1578 1579 return slot; 1580 1581 remove: 1582 if (chip->fixes && chip->fixes->remove_slot) 1583 chip->fixes->remove_slot(slot, 0); 1584 1585 cleanup: 1586 if (slot->data && slot->data->cleanup) 1587 slot->data->cleanup(slot->data); 1588 1589 free: 1590 sdhci_free_host(host); 1591 1592 return ERR_PTR(ret); 1593 } 1594 1595 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 1596 { 1597 int dead; 1598 u32 scratch; 1599 1600 sdhci_pci_remove_own_cd(slot); 1601 1602 dead = 0; 1603 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 1604 if (scratch == (u32)-1) 1605 dead = 1; 1606 1607 sdhci_remove_host(slot->host, dead); 1608 1609 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 1610 slot->chip->fixes->remove_slot(slot, dead); 1611 1612 if (slot->data && slot->data->cleanup) 1613 slot->data->cleanup(slot->data); 1614 1615 sdhci_free_host(slot->host); 1616 } 1617 1618 static void sdhci_pci_runtime_pm_allow(struct device *dev) 1619 { 1620 pm_suspend_ignore_children(dev, 1); 1621 pm_runtime_set_autosuspend_delay(dev, 50); 1622 pm_runtime_use_autosuspend(dev); 1623 pm_runtime_allow(dev); 1624 /* Stay active until mmc core scans for a card */ 1625 pm_runtime_put_noidle(dev); 1626 } 1627 1628 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 1629 { 1630 pm_runtime_forbid(dev); 1631 pm_runtime_get_noresume(dev); 1632 } 1633 1634 static int sdhci_pci_probe(struct pci_dev *pdev, 1635 const struct pci_device_id *ent) 1636 { 1637 struct sdhci_pci_chip *chip; 1638 struct sdhci_pci_slot *slot; 1639 1640 u8 slots, first_bar; 1641 int ret, i; 1642 1643 BUG_ON(pdev == NULL); 1644 BUG_ON(ent == NULL); 1645 1646 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 1647 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 1648 1649 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 1650 if (ret) 1651 return ret; 1652 1653 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 1654 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 1655 if (slots == 0) 1656 return -ENODEV; 1657 1658 BUG_ON(slots > MAX_SLOTS); 1659 1660 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 1661 if (ret) 1662 return ret; 1663 1664 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 1665 1666 if (first_bar > 5) { 1667 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 1668 return -ENODEV; 1669 } 1670 1671 ret = pcim_enable_device(pdev); 1672 if (ret) 1673 return ret; 1674 1675 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 1676 if (!chip) 1677 return -ENOMEM; 1678 1679 chip->pdev = pdev; 1680 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 1681 if (chip->fixes) { 1682 chip->quirks = chip->fixes->quirks; 1683 chip->quirks2 = chip->fixes->quirks2; 1684 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 1685 } 1686 chip->num_slots = slots; 1687 chip->pm_retune = true; 1688 chip->rpm_retune = true; 1689 1690 pci_set_drvdata(pdev, chip); 1691 1692 if (chip->fixes && chip->fixes->probe) { 1693 ret = chip->fixes->probe(chip); 1694 if (ret) 1695 return ret; 1696 } 1697 1698 slots = chip->num_slots; /* Quirk may have changed this */ 1699 1700 for (i = 0; i < slots; i++) { 1701 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 1702 if (IS_ERR(slot)) { 1703 for (i--; i >= 0; i--) 1704 sdhci_pci_remove_slot(chip->slots[i]); 1705 return PTR_ERR(slot); 1706 } 1707 1708 chip->slots[i] = slot; 1709 } 1710 1711 if (chip->allow_runtime_pm) 1712 sdhci_pci_runtime_pm_allow(&pdev->dev); 1713 1714 return 0; 1715 } 1716 1717 static void sdhci_pci_remove(struct pci_dev *pdev) 1718 { 1719 int i; 1720 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1721 1722 if (chip->allow_runtime_pm) 1723 sdhci_pci_runtime_pm_forbid(&pdev->dev); 1724 1725 for (i = 0; i < chip->num_slots; i++) 1726 sdhci_pci_remove_slot(chip->slots[i]); 1727 } 1728 1729 static struct pci_driver sdhci_driver = { 1730 .name = "sdhci-pci", 1731 .id_table = pci_ids, 1732 .probe = sdhci_pci_probe, 1733 .remove = sdhci_pci_remove, 1734 .driver = { 1735 .pm = &sdhci_pci_pm_ops 1736 }, 1737 }; 1738 1739 module_pci_driver(sdhci_driver); 1740 1741 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 1742 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 1743 MODULE_LICENSE("GPL"); 1744