1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 2 * 3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 * 10 * Thanks to the following companies for their support: 11 * 12 * - JMicron (hardware and technical support) 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/highmem.h> 17 #include <linux/module.h> 18 #include <linux/pci.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/slab.h> 21 #include <linux/device.h> 22 #include <linux/mmc/host.h> 23 #include <linux/mmc/mmc.h> 24 #include <linux/scatterlist.h> 25 #include <linux/io.h> 26 #include <linux/gpio.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/mmc/slot-gpio.h> 29 #include <linux/mmc/sdhci-pci-data.h> 30 #include <linux/acpi.h> 31 32 #include "sdhci.h" 33 #include "sdhci-pci.h" 34 #include "sdhci-pci-o2micro.h" 35 36 static int sdhci_pci_enable_dma(struct sdhci_host *host); 37 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width); 38 static void sdhci_pci_hw_reset(struct sdhci_host *host); 39 40 /*****************************************************************************\ 41 * * 42 * Hardware specific quirk handling * 43 * * 44 \*****************************************************************************/ 45 46 static int ricoh_probe(struct sdhci_pci_chip *chip) 47 { 48 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 49 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 50 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 51 return 0; 52 } 53 54 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 55 { 56 slot->host->caps = 57 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 58 & SDHCI_TIMEOUT_CLK_MASK) | 59 60 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 61 & SDHCI_CLOCK_BASE_MASK) | 62 63 SDHCI_TIMEOUT_CLK_UNIT | 64 SDHCI_CAN_VDD_330 | 65 SDHCI_CAN_DO_HISPD | 66 SDHCI_CAN_DO_SDMA; 67 return 0; 68 } 69 70 #ifdef CONFIG_PM_SLEEP 71 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 72 { 73 /* Apply a delay to allow controller to settle */ 74 /* Otherwise it becomes confused if card state changed 75 during suspend */ 76 msleep(500); 77 return 0; 78 } 79 #endif 80 81 static const struct sdhci_pci_fixes sdhci_ricoh = { 82 .probe = ricoh_probe, 83 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 84 SDHCI_QUIRK_FORCE_DMA | 85 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 86 }; 87 88 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 89 .probe_slot = ricoh_mmc_probe_slot, 90 #ifdef CONFIG_PM_SLEEP 91 .resume = ricoh_mmc_resume, 92 #endif 93 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 94 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 95 SDHCI_QUIRK_NO_CARD_NO_RESET | 96 SDHCI_QUIRK_MISSING_CAPS 97 }; 98 99 static const struct sdhci_pci_fixes sdhci_ene_712 = { 100 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 101 SDHCI_QUIRK_BROKEN_DMA, 102 }; 103 104 static const struct sdhci_pci_fixes sdhci_ene_714 = { 105 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 106 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 107 SDHCI_QUIRK_BROKEN_DMA, 108 }; 109 110 static const struct sdhci_pci_fixes sdhci_cafe = { 111 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 112 SDHCI_QUIRK_NO_BUSY_IRQ | 113 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 114 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 115 }; 116 117 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 118 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 119 }; 120 121 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 122 { 123 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 124 return 0; 125 } 126 127 /* 128 * ADMA operation is disabled for Moorestown platform due to 129 * hardware bugs. 130 */ 131 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 132 { 133 /* 134 * slots number is fixed here for MRST as SDIO3/5 are never used and 135 * have hardware bugs. 136 */ 137 chip->num_slots = 1; 138 return 0; 139 } 140 141 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 142 { 143 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 144 return 0; 145 } 146 147 #ifdef CONFIG_PM 148 149 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 150 { 151 struct sdhci_pci_slot *slot = dev_id; 152 struct sdhci_host *host = slot->host; 153 154 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 155 return IRQ_HANDLED; 156 } 157 158 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 159 { 160 int err, irq, gpio = slot->cd_gpio; 161 162 slot->cd_gpio = -EINVAL; 163 slot->cd_irq = -EINVAL; 164 165 if (!gpio_is_valid(gpio)) 166 return; 167 168 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 169 if (err < 0) 170 goto out; 171 172 err = gpio_direction_input(gpio); 173 if (err < 0) 174 goto out_free; 175 176 irq = gpio_to_irq(gpio); 177 if (irq < 0) 178 goto out_free; 179 180 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 181 IRQF_TRIGGER_FALLING, "sd_cd", slot); 182 if (err) 183 goto out_free; 184 185 slot->cd_gpio = gpio; 186 slot->cd_irq = irq; 187 188 return; 189 190 out_free: 191 devm_gpio_free(&slot->chip->pdev->dev, gpio); 192 out: 193 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 194 } 195 196 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 197 { 198 if (slot->cd_irq >= 0) 199 free_irq(slot->cd_irq, slot); 200 } 201 202 #else 203 204 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 205 { 206 } 207 208 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 209 { 210 } 211 212 #endif 213 214 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 215 { 216 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 217 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC | 218 MMC_CAP2_HC_ERASE_SZ; 219 return 0; 220 } 221 222 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 223 { 224 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 225 return 0; 226 } 227 228 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 229 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 230 .probe_slot = mrst_hc_probe_slot, 231 }; 232 233 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 234 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 235 .probe = mrst_hc_probe, 236 }; 237 238 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 239 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 240 .allow_runtime_pm = true, 241 .own_cd_for_runtime_pm = true, 242 }; 243 244 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 245 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 246 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 247 .allow_runtime_pm = true, 248 .probe_slot = mfd_sdio_probe_slot, 249 }; 250 251 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 252 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 253 .allow_runtime_pm = true, 254 .probe_slot = mfd_emmc_probe_slot, 255 }; 256 257 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 258 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 259 .probe_slot = pch_hc_probe_slot, 260 }; 261 262 enum { 263 INTEL_DSM_FNS = 0, 264 INTEL_DSM_DRV_STRENGTH = 9, 265 INTEL_DSM_D3_RETUNE = 10, 266 }; 267 268 struct intel_host { 269 u32 dsm_fns; 270 int drv_strength; 271 bool d3_retune; 272 }; 273 274 const u8 intel_dsm_uuid[] = { 275 0xA5, 0x3E, 0xC1, 0xF6, 0xCD, 0x65, 0x1F, 0x46, 276 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61, 277 }; 278 279 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 280 unsigned int fn, u32 *result) 281 { 282 union acpi_object *obj; 283 int err = 0; 284 285 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), intel_dsm_uuid, 0, fn, NULL); 286 if (!obj) 287 return -EOPNOTSUPP; 288 289 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { 290 err = -EINVAL; 291 goto out; 292 } 293 294 if (obj->buffer.length >= 4) 295 *result = *(u32 *)obj->buffer.pointer; 296 else if (obj->buffer.length >= 2) 297 *result = *(u16 *)obj->buffer.pointer; 298 else 299 *result = *(u8 *)obj->buffer.pointer; 300 out: 301 ACPI_FREE(obj); 302 303 return err; 304 } 305 306 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 307 unsigned int fn, u32 *result) 308 { 309 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 310 return -EOPNOTSUPP; 311 312 return __intel_dsm(intel_host, dev, fn, result); 313 } 314 315 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 316 struct mmc_host *mmc) 317 { 318 int err; 319 u32 val; 320 321 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 322 if (err) { 323 pr_debug("%s: DSM not supported, error %d\n", 324 mmc_hostname(mmc), err); 325 return; 326 } 327 328 pr_debug("%s: DSM function mask %#x\n", 329 mmc_hostname(mmc), intel_host->dsm_fns); 330 331 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 332 intel_host->drv_strength = err ? 0 : val; 333 334 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 335 intel_host->d3_retune = err ? true : !!val; 336 } 337 338 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 339 { 340 u8 reg; 341 342 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 343 reg |= 0x10; 344 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 345 /* For eMMC, minimum is 1us but give it 9us for good measure */ 346 udelay(9); 347 reg &= ~0x10; 348 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 349 /* For eMMC, minimum is 200us but give it 300us for good measure */ 350 usleep_range(300, 1000); 351 } 352 353 static int intel_select_drive_strength(struct mmc_card *card, 354 unsigned int max_dtr, int host_drv, 355 int card_drv, int *drv_type) 356 { 357 struct sdhci_host *host = mmc_priv(card->host); 358 struct sdhci_pci_slot *slot = sdhci_priv(host); 359 struct intel_host *intel_host = sdhci_pci_priv(slot); 360 361 return intel_host->drv_strength; 362 } 363 364 static int bxt_get_cd(struct mmc_host *mmc) 365 { 366 int gpio_cd = mmc_gpio_get_cd(mmc); 367 struct sdhci_host *host = mmc_priv(mmc); 368 unsigned long flags; 369 int ret = 0; 370 371 if (!gpio_cd) 372 return 0; 373 374 spin_lock_irqsave(&host->lock, flags); 375 376 if (host->flags & SDHCI_DEVICE_DEAD) 377 goto out; 378 379 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 380 out: 381 spin_unlock_irqrestore(&host->lock, flags); 382 383 return ret; 384 } 385 386 static void byt_read_dsm(struct sdhci_pci_slot *slot) 387 { 388 struct intel_host *intel_host = sdhci_pci_priv(slot); 389 struct device *dev = &slot->chip->pdev->dev; 390 struct mmc_host *mmc = slot->host->mmc; 391 392 intel_dsm_init(intel_host, dev, mmc); 393 slot->chip->rpm_retune = intel_host->d3_retune; 394 } 395 396 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 397 { 398 byt_read_dsm(slot); 399 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 400 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 401 MMC_CAP_CMD_DURING_TFR | 402 MMC_CAP_WAIT_WHILE_BUSY; 403 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ; 404 slot->hw_reset = sdhci_pci_int_hw_reset; 405 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 406 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 407 slot->host->mmc_host_ops.select_drive_strength = 408 intel_select_drive_strength; 409 return 0; 410 } 411 412 #ifdef CONFIG_ACPI 413 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 414 { 415 acpi_status status; 416 unsigned long long max_freq; 417 418 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 419 "MXFQ", NULL, &max_freq); 420 if (ACPI_FAILURE(status)) { 421 dev_err(&slot->chip->pdev->dev, 422 "MXFQ not found in acpi table\n"); 423 return -EINVAL; 424 } 425 426 slot->host->mmc->f_max = max_freq * 1000000; 427 428 return 0; 429 } 430 #else 431 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 432 { 433 return 0; 434 } 435 #endif 436 437 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 438 { 439 int err; 440 441 byt_read_dsm(slot); 442 443 err = ni_set_max_freq(slot); 444 if (err) 445 return err; 446 447 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 448 MMC_CAP_WAIT_WHILE_BUSY; 449 return 0; 450 } 451 452 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 453 { 454 byt_read_dsm(slot); 455 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 456 MMC_CAP_WAIT_WHILE_BUSY; 457 return 0; 458 } 459 460 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 461 { 462 byt_read_dsm(slot); 463 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 464 slot->cd_idx = 0; 465 slot->cd_override_level = true; 466 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 467 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 468 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 469 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) { 470 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 471 slot->host->mmc->caps |= MMC_CAP_AGGRESSIVE_PM; 472 } 473 474 return 0; 475 } 476 477 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 478 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 479 480 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 481 unsigned short vdd) 482 { 483 int cntr; 484 u8 reg; 485 486 sdhci_set_power(host, mode, vdd); 487 488 if (mode == MMC_POWER_OFF) 489 return; 490 491 /* 492 * Bus power might not enable after D3 -> D0 transition due to the 493 * present state not yet having propagated. Retry for up to 2ms. 494 */ 495 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 496 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 497 if (reg & SDHCI_POWER_ON) 498 break; 499 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 500 reg |= SDHCI_POWER_ON; 501 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 502 } 503 } 504 505 static const struct sdhci_ops sdhci_intel_byt_ops = { 506 .set_clock = sdhci_set_clock, 507 .set_power = sdhci_intel_set_power, 508 .enable_dma = sdhci_pci_enable_dma, 509 .set_bus_width = sdhci_pci_set_bus_width, 510 .reset = sdhci_reset, 511 .set_uhs_signaling = sdhci_set_uhs_signaling, 512 .hw_reset = sdhci_pci_hw_reset, 513 }; 514 515 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 516 .allow_runtime_pm = true, 517 .probe_slot = byt_emmc_probe_slot, 518 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 519 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 520 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 521 SDHCI_QUIRK2_STOP_WITH_TC, 522 .ops = &sdhci_intel_byt_ops, 523 .priv_size = sizeof(struct intel_host), 524 }; 525 526 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 527 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 528 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 529 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 530 .allow_runtime_pm = true, 531 .probe_slot = ni_byt_sdio_probe_slot, 532 .ops = &sdhci_intel_byt_ops, 533 .priv_size = sizeof(struct intel_host), 534 }; 535 536 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 537 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 538 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 539 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 540 .allow_runtime_pm = true, 541 .probe_slot = byt_sdio_probe_slot, 542 .ops = &sdhci_intel_byt_ops, 543 .priv_size = sizeof(struct intel_host), 544 }; 545 546 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 547 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 548 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 549 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 550 SDHCI_QUIRK2_STOP_WITH_TC, 551 .allow_runtime_pm = true, 552 .own_cd_for_runtime_pm = true, 553 .probe_slot = byt_sd_probe_slot, 554 .ops = &sdhci_intel_byt_ops, 555 .priv_size = sizeof(struct intel_host), 556 }; 557 558 /* Define Host controllers for Intel Merrifield platform */ 559 #define INTEL_MRFLD_EMMC_0 0 560 #define INTEL_MRFLD_EMMC_1 1 561 #define INTEL_MRFLD_SD 2 562 #define INTEL_MRFLD_SDIO 3 563 564 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 565 { 566 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 567 568 switch (func) { 569 case INTEL_MRFLD_EMMC_0: 570 case INTEL_MRFLD_EMMC_1: 571 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 572 MMC_CAP_8_BIT_DATA | 573 MMC_CAP_1_8V_DDR; 574 break; 575 case INTEL_MRFLD_SD: 576 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 577 break; 578 case INTEL_MRFLD_SDIO: 579 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 580 MMC_CAP_POWER_OFF_CARD; 581 break; 582 default: 583 return -ENODEV; 584 } 585 return 0; 586 } 587 588 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 589 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 590 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 591 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 592 .allow_runtime_pm = true, 593 .probe_slot = intel_mrfld_mmc_probe_slot, 594 }; 595 596 /* O2Micro extra registers */ 597 #define O2_SD_LOCK_WP 0xD3 598 #define O2_SD_MULTI_VCC3V 0xEE 599 #define O2_SD_CLKREQ 0xEC 600 #define O2_SD_CAPS 0xE0 601 #define O2_SD_ADMA1 0xE2 602 #define O2_SD_ADMA2 0xE7 603 #define O2_SD_INF_MOD 0xF1 604 605 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 606 { 607 u8 scratch; 608 int ret; 609 610 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 611 if (ret) 612 return ret; 613 614 /* 615 * Turn PMOS on [bit 0], set over current detection to 2.4 V 616 * [bit 1:2] and enable over current debouncing [bit 6]. 617 */ 618 if (on) 619 scratch |= 0x47; 620 else 621 scratch &= ~0x47; 622 623 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 624 } 625 626 static int jmicron_probe(struct sdhci_pci_chip *chip) 627 { 628 int ret; 629 u16 mmcdev = 0; 630 631 if (chip->pdev->revision == 0) { 632 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 633 SDHCI_QUIRK_32BIT_DMA_SIZE | 634 SDHCI_QUIRK_32BIT_ADMA_SIZE | 635 SDHCI_QUIRK_RESET_AFTER_REQUEST | 636 SDHCI_QUIRK_BROKEN_SMALL_PIO; 637 } 638 639 /* 640 * JMicron chips can have two interfaces to the same hardware 641 * in order to work around limitations in Microsoft's driver. 642 * We need to make sure we only bind to one of them. 643 * 644 * This code assumes two things: 645 * 646 * 1. The PCI code adds subfunctions in order. 647 * 648 * 2. The MMC interface has a lower subfunction number 649 * than the SD interface. 650 */ 651 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 652 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 653 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 654 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 655 656 if (mmcdev) { 657 struct pci_dev *sd_dev; 658 659 sd_dev = NULL; 660 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 661 mmcdev, sd_dev)) != NULL) { 662 if ((PCI_SLOT(chip->pdev->devfn) == 663 PCI_SLOT(sd_dev->devfn)) && 664 (chip->pdev->bus == sd_dev->bus)) 665 break; 666 } 667 668 if (sd_dev) { 669 pci_dev_put(sd_dev); 670 dev_info(&chip->pdev->dev, "Refusing to bind to " 671 "secondary interface.\n"); 672 return -ENODEV; 673 } 674 } 675 676 /* 677 * JMicron chips need a bit of a nudge to enable the power 678 * output pins. 679 */ 680 ret = jmicron_pmos(chip, 1); 681 if (ret) { 682 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 683 return ret; 684 } 685 686 /* quirk for unsable RO-detection on JM388 chips */ 687 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 688 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 689 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 690 691 return 0; 692 } 693 694 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 695 { 696 u8 scratch; 697 698 scratch = readb(host->ioaddr + 0xC0); 699 700 if (on) 701 scratch |= 0x01; 702 else 703 scratch &= ~0x01; 704 705 writeb(scratch, host->ioaddr + 0xC0); 706 } 707 708 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 709 { 710 if (slot->chip->pdev->revision == 0) { 711 u16 version; 712 713 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 714 version = (version & SDHCI_VENDOR_VER_MASK) >> 715 SDHCI_VENDOR_VER_SHIFT; 716 717 /* 718 * Older versions of the chip have lots of nasty glitches 719 * in the ADMA engine. It's best just to avoid it 720 * completely. 721 */ 722 if (version < 0xAC) 723 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 724 } 725 726 /* JM388 MMC doesn't support 1.8V while SD supports it */ 727 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 728 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 729 MMC_VDD_29_30 | MMC_VDD_30_31 | 730 MMC_VDD_165_195; /* allow 1.8V */ 731 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 732 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 733 } 734 735 /* 736 * The secondary interface requires a bit set to get the 737 * interrupts. 738 */ 739 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 740 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 741 jmicron_enable_mmc(slot->host, 1); 742 743 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 744 745 return 0; 746 } 747 748 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 749 { 750 if (dead) 751 return; 752 753 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 754 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 755 jmicron_enable_mmc(slot->host, 0); 756 } 757 758 #ifdef CONFIG_PM_SLEEP 759 static int jmicron_suspend(struct sdhci_pci_chip *chip) 760 { 761 int i; 762 763 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 764 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 765 for (i = 0; i < chip->num_slots; i++) 766 jmicron_enable_mmc(chip->slots[i]->host, 0); 767 } 768 769 return 0; 770 } 771 772 static int jmicron_resume(struct sdhci_pci_chip *chip) 773 { 774 int ret, i; 775 776 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 777 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 778 for (i = 0; i < chip->num_slots; i++) 779 jmicron_enable_mmc(chip->slots[i]->host, 1); 780 } 781 782 ret = jmicron_pmos(chip, 1); 783 if (ret) { 784 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 785 return ret; 786 } 787 788 return 0; 789 } 790 #endif 791 792 static const struct sdhci_pci_fixes sdhci_o2 = { 793 .probe = sdhci_pci_o2_probe, 794 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 795 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 796 .probe_slot = sdhci_pci_o2_probe_slot, 797 #ifdef CONFIG_PM_SLEEP 798 .resume = sdhci_pci_o2_resume, 799 #endif 800 }; 801 802 static const struct sdhci_pci_fixes sdhci_jmicron = { 803 .probe = jmicron_probe, 804 805 .probe_slot = jmicron_probe_slot, 806 .remove_slot = jmicron_remove_slot, 807 808 #ifdef CONFIG_PM_SLEEP 809 .suspend = jmicron_suspend, 810 .resume = jmicron_resume, 811 #endif 812 }; 813 814 /* SysKonnect CardBus2SDIO extra registers */ 815 #define SYSKT_CTRL 0x200 816 #define SYSKT_RDFIFO_STAT 0x204 817 #define SYSKT_WRFIFO_STAT 0x208 818 #define SYSKT_POWER_DATA 0x20c 819 #define SYSKT_POWER_330 0xef 820 #define SYSKT_POWER_300 0xf8 821 #define SYSKT_POWER_184 0xcc 822 #define SYSKT_POWER_CMD 0x20d 823 #define SYSKT_POWER_START (1 << 7) 824 #define SYSKT_POWER_STATUS 0x20e 825 #define SYSKT_POWER_STATUS_OK (1 << 0) 826 #define SYSKT_BOARD_REV 0x210 827 #define SYSKT_CHIP_REV 0x211 828 #define SYSKT_CONF_DATA 0x212 829 #define SYSKT_CONF_DATA_1V8 (1 << 2) 830 #define SYSKT_CONF_DATA_2V5 (1 << 1) 831 #define SYSKT_CONF_DATA_3V3 (1 << 0) 832 833 static int syskt_probe(struct sdhci_pci_chip *chip) 834 { 835 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 836 chip->pdev->class &= ~0x0000FF; 837 chip->pdev->class |= PCI_SDHCI_IFDMA; 838 } 839 return 0; 840 } 841 842 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 843 { 844 int tm, ps; 845 846 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 847 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 848 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 849 "board rev %d.%d, chip rev %d.%d\n", 850 board_rev >> 4, board_rev & 0xf, 851 chip_rev >> 4, chip_rev & 0xf); 852 if (chip_rev >= 0x20) 853 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 854 855 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 856 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 857 udelay(50); 858 tm = 10; /* Wait max 1 ms */ 859 do { 860 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 861 if (ps & SYSKT_POWER_STATUS_OK) 862 break; 863 udelay(100); 864 } while (--tm); 865 if (!tm) { 866 dev_err(&slot->chip->pdev->dev, 867 "power regulator never stabilized"); 868 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 869 return -ENODEV; 870 } 871 872 return 0; 873 } 874 875 static const struct sdhci_pci_fixes sdhci_syskt = { 876 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 877 .probe = syskt_probe, 878 .probe_slot = syskt_probe_slot, 879 }; 880 881 static int via_probe(struct sdhci_pci_chip *chip) 882 { 883 if (chip->pdev->revision == 0x10) 884 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 885 886 return 0; 887 } 888 889 static const struct sdhci_pci_fixes sdhci_via = { 890 .probe = via_probe, 891 }; 892 893 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 894 { 895 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 896 return 0; 897 } 898 899 static const struct sdhci_pci_fixes sdhci_rtsx = { 900 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 901 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 902 SDHCI_QUIRK2_BROKEN_DDR50, 903 .probe_slot = rtsx_probe_slot, 904 }; 905 906 /*AMD chipset generation*/ 907 enum amd_chipset_gen { 908 AMD_CHIPSET_BEFORE_ML, 909 AMD_CHIPSET_CZ, 910 AMD_CHIPSET_NL, 911 AMD_CHIPSET_UNKNOWN, 912 }; 913 914 /* AMD registers */ 915 #define AMD_SD_AUTO_PATTERN 0xB8 916 #define AMD_MSLEEP_DURATION 4 917 #define AMD_SD_MISC_CONTROL 0xD0 918 #define AMD_MAX_TUNE_VALUE 0x0B 919 #define AMD_AUTO_TUNE_SEL 0x10800 920 #define AMD_FIFO_PTR 0x30 921 #define AMD_BIT_MASK 0x1F 922 923 static void amd_tuning_reset(struct sdhci_host *host) 924 { 925 unsigned int val; 926 927 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 928 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 929 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 930 931 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 932 val &= ~SDHCI_CTRL_EXEC_TUNING; 933 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 934 } 935 936 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 937 { 938 unsigned int val; 939 940 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 941 val &= ~AMD_BIT_MASK; 942 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 943 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 944 } 945 946 static void amd_enable_manual_tuning(struct pci_dev *pdev) 947 { 948 unsigned int val; 949 950 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 951 val |= AMD_FIFO_PTR; 952 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 953 } 954 955 static int amd_execute_tuning(struct sdhci_host *host, u32 opcode) 956 { 957 struct sdhci_pci_slot *slot = sdhci_priv(host); 958 struct pci_dev *pdev = slot->chip->pdev; 959 u8 valid_win = 0; 960 u8 valid_win_max = 0; 961 u8 valid_win_end = 0; 962 u8 ctrl, tune_around; 963 964 amd_tuning_reset(host); 965 966 for (tune_around = 0; tune_around < 12; tune_around++) { 967 amd_config_tuning_phase(pdev, tune_around); 968 969 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 970 valid_win = 0; 971 msleep(AMD_MSLEEP_DURATION); 972 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 973 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 974 } else if (++valid_win > valid_win_max) { 975 valid_win_max = valid_win; 976 valid_win_end = tune_around; 977 } 978 } 979 980 if (!valid_win_max) { 981 dev_err(&pdev->dev, "no tuning point found\n"); 982 return -EIO; 983 } 984 985 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 986 987 amd_enable_manual_tuning(pdev); 988 989 host->mmc->retune_period = 0; 990 991 return 0; 992 } 993 994 static int amd_probe(struct sdhci_pci_chip *chip) 995 { 996 struct pci_dev *smbus_dev; 997 enum amd_chipset_gen gen; 998 999 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1000 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 1001 if (smbus_dev) { 1002 gen = AMD_CHIPSET_BEFORE_ML; 1003 } else { 1004 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1005 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1006 if (smbus_dev) { 1007 if (smbus_dev->revision < 0x51) 1008 gen = AMD_CHIPSET_CZ; 1009 else 1010 gen = AMD_CHIPSET_NL; 1011 } else { 1012 gen = AMD_CHIPSET_UNKNOWN; 1013 } 1014 } 1015 1016 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1017 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1018 1019 return 0; 1020 } 1021 1022 static const struct sdhci_ops amd_sdhci_pci_ops = { 1023 .set_clock = sdhci_set_clock, 1024 .enable_dma = sdhci_pci_enable_dma, 1025 .set_bus_width = sdhci_pci_set_bus_width, 1026 .reset = sdhci_reset, 1027 .set_uhs_signaling = sdhci_set_uhs_signaling, 1028 .platform_execute_tuning = amd_execute_tuning, 1029 }; 1030 1031 static const struct sdhci_pci_fixes sdhci_amd = { 1032 .probe = amd_probe, 1033 .ops = &amd_sdhci_pci_ops, 1034 }; 1035 1036 static const struct pci_device_id pci_ids[] = { 1037 { 1038 .vendor = PCI_VENDOR_ID_RICOH, 1039 .device = PCI_DEVICE_ID_RICOH_R5C822, 1040 .subvendor = PCI_ANY_ID, 1041 .subdevice = PCI_ANY_ID, 1042 .driver_data = (kernel_ulong_t)&sdhci_ricoh, 1043 }, 1044 1045 { 1046 .vendor = PCI_VENDOR_ID_RICOH, 1047 .device = 0x843, 1048 .subvendor = PCI_ANY_ID, 1049 .subdevice = PCI_ANY_ID, 1050 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 1051 }, 1052 1053 { 1054 .vendor = PCI_VENDOR_ID_RICOH, 1055 .device = 0xe822, 1056 .subvendor = PCI_ANY_ID, 1057 .subdevice = PCI_ANY_ID, 1058 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 1059 }, 1060 1061 { 1062 .vendor = PCI_VENDOR_ID_RICOH, 1063 .device = 0xe823, 1064 .subvendor = PCI_ANY_ID, 1065 .subdevice = PCI_ANY_ID, 1066 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 1067 }, 1068 1069 { 1070 .vendor = PCI_VENDOR_ID_ENE, 1071 .device = PCI_DEVICE_ID_ENE_CB712_SD, 1072 .subvendor = PCI_ANY_ID, 1073 .subdevice = PCI_ANY_ID, 1074 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 1075 }, 1076 1077 { 1078 .vendor = PCI_VENDOR_ID_ENE, 1079 .device = PCI_DEVICE_ID_ENE_CB712_SD_2, 1080 .subvendor = PCI_ANY_ID, 1081 .subdevice = PCI_ANY_ID, 1082 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 1083 }, 1084 1085 { 1086 .vendor = PCI_VENDOR_ID_ENE, 1087 .device = PCI_DEVICE_ID_ENE_CB714_SD, 1088 .subvendor = PCI_ANY_ID, 1089 .subdevice = PCI_ANY_ID, 1090 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 1091 }, 1092 1093 { 1094 .vendor = PCI_VENDOR_ID_ENE, 1095 .device = PCI_DEVICE_ID_ENE_CB714_SD_2, 1096 .subvendor = PCI_ANY_ID, 1097 .subdevice = PCI_ANY_ID, 1098 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 1099 }, 1100 1101 { 1102 .vendor = PCI_VENDOR_ID_MARVELL, 1103 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD, 1104 .subvendor = PCI_ANY_ID, 1105 .subdevice = PCI_ANY_ID, 1106 .driver_data = (kernel_ulong_t)&sdhci_cafe, 1107 }, 1108 1109 { 1110 .vendor = PCI_VENDOR_ID_JMICRON, 1111 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD, 1112 .subvendor = PCI_ANY_ID, 1113 .subdevice = PCI_ANY_ID, 1114 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1115 }, 1116 1117 { 1118 .vendor = PCI_VENDOR_ID_JMICRON, 1119 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC, 1120 .subvendor = PCI_ANY_ID, 1121 .subdevice = PCI_ANY_ID, 1122 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1123 }, 1124 1125 { 1126 .vendor = PCI_VENDOR_ID_JMICRON, 1127 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD, 1128 .subvendor = PCI_ANY_ID, 1129 .subdevice = PCI_ANY_ID, 1130 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1131 }, 1132 1133 { 1134 .vendor = PCI_VENDOR_ID_JMICRON, 1135 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD, 1136 .subvendor = PCI_ANY_ID, 1137 .subdevice = PCI_ANY_ID, 1138 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1139 }, 1140 1141 { 1142 .vendor = PCI_VENDOR_ID_SYSKONNECT, 1143 .device = 0x8000, 1144 .subvendor = PCI_ANY_ID, 1145 .subdevice = PCI_ANY_ID, 1146 .driver_data = (kernel_ulong_t)&sdhci_syskt, 1147 }, 1148 1149 { 1150 .vendor = PCI_VENDOR_ID_VIA, 1151 .device = 0x95d0, 1152 .subvendor = PCI_ANY_ID, 1153 .subdevice = PCI_ANY_ID, 1154 .driver_data = (kernel_ulong_t)&sdhci_via, 1155 }, 1156 1157 { 1158 .vendor = PCI_VENDOR_ID_REALTEK, 1159 .device = 0x5250, 1160 .subvendor = PCI_ANY_ID, 1161 .subdevice = PCI_ANY_ID, 1162 .driver_data = (kernel_ulong_t)&sdhci_rtsx, 1163 }, 1164 1165 { 1166 .vendor = PCI_VENDOR_ID_INTEL, 1167 .device = PCI_DEVICE_ID_INTEL_QRK_SD, 1168 .subvendor = PCI_ANY_ID, 1169 .subdevice = PCI_ANY_ID, 1170 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk, 1171 }, 1172 1173 { 1174 .vendor = PCI_VENDOR_ID_INTEL, 1175 .device = PCI_DEVICE_ID_INTEL_MRST_SD0, 1176 .subvendor = PCI_ANY_ID, 1177 .subdevice = PCI_ANY_ID, 1178 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0, 1179 }, 1180 1181 { 1182 .vendor = PCI_VENDOR_ID_INTEL, 1183 .device = PCI_DEVICE_ID_INTEL_MRST_SD1, 1184 .subvendor = PCI_ANY_ID, 1185 .subdevice = PCI_ANY_ID, 1186 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 1187 }, 1188 1189 { 1190 .vendor = PCI_VENDOR_ID_INTEL, 1191 .device = PCI_DEVICE_ID_INTEL_MRST_SD2, 1192 .subvendor = PCI_ANY_ID, 1193 .subdevice = PCI_ANY_ID, 1194 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 1195 }, 1196 1197 { 1198 .vendor = PCI_VENDOR_ID_INTEL, 1199 .device = PCI_DEVICE_ID_INTEL_MFD_SD, 1200 .subvendor = PCI_ANY_ID, 1201 .subdevice = PCI_ANY_ID, 1202 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1203 }, 1204 1205 { 1206 .vendor = PCI_VENDOR_ID_INTEL, 1207 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1, 1208 .subvendor = PCI_ANY_ID, 1209 .subdevice = PCI_ANY_ID, 1210 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1211 }, 1212 1213 { 1214 .vendor = PCI_VENDOR_ID_INTEL, 1215 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2, 1216 .subvendor = PCI_ANY_ID, 1217 .subdevice = PCI_ANY_ID, 1218 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1219 }, 1220 1221 { 1222 .vendor = PCI_VENDOR_ID_INTEL, 1223 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0, 1224 .subvendor = PCI_ANY_ID, 1225 .subdevice = PCI_ANY_ID, 1226 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1227 }, 1228 1229 { 1230 .vendor = PCI_VENDOR_ID_INTEL, 1231 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1, 1232 .subvendor = PCI_ANY_ID, 1233 .subdevice = PCI_ANY_ID, 1234 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1235 }, 1236 1237 { 1238 .vendor = PCI_VENDOR_ID_INTEL, 1239 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0, 1240 .subvendor = PCI_ANY_ID, 1241 .subdevice = PCI_ANY_ID, 1242 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1243 }, 1244 1245 { 1246 .vendor = PCI_VENDOR_ID_INTEL, 1247 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1, 1248 .subvendor = PCI_ANY_ID, 1249 .subdevice = PCI_ANY_ID, 1250 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1251 }, 1252 1253 { 1254 .vendor = PCI_VENDOR_ID_INTEL, 1255 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC, 1256 .subvendor = PCI_ANY_ID, 1257 .subdevice = PCI_ANY_ID, 1258 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1259 }, 1260 1261 { 1262 .vendor = PCI_VENDOR_ID_INTEL, 1263 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, 1264 .subvendor = PCI_VENDOR_ID_NI, 1265 .subdevice = 0x7884, 1266 .driver_data = (kernel_ulong_t)&sdhci_ni_byt_sdio, 1267 }, 1268 1269 { 1270 .vendor = PCI_VENDOR_ID_INTEL, 1271 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, 1272 .subvendor = PCI_ANY_ID, 1273 .subdevice = PCI_ANY_ID, 1274 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1275 }, 1276 1277 { 1278 .vendor = PCI_VENDOR_ID_INTEL, 1279 .device = PCI_DEVICE_ID_INTEL_BYT_SD, 1280 .subvendor = PCI_ANY_ID, 1281 .subdevice = PCI_ANY_ID, 1282 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1283 }, 1284 1285 { 1286 .vendor = PCI_VENDOR_ID_INTEL, 1287 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2, 1288 .subvendor = PCI_ANY_ID, 1289 .subdevice = PCI_ANY_ID, 1290 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1291 }, 1292 1293 { 1294 .vendor = PCI_VENDOR_ID_INTEL, 1295 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC, 1296 .subvendor = PCI_ANY_ID, 1297 .subdevice = PCI_ANY_ID, 1298 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1299 }, 1300 1301 { 1302 .vendor = PCI_VENDOR_ID_INTEL, 1303 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO, 1304 .subvendor = PCI_ANY_ID, 1305 .subdevice = PCI_ANY_ID, 1306 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1307 }, 1308 1309 { 1310 .vendor = PCI_VENDOR_ID_INTEL, 1311 .device = PCI_DEVICE_ID_INTEL_BSW_SD, 1312 .subvendor = PCI_ANY_ID, 1313 .subdevice = PCI_ANY_ID, 1314 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1315 }, 1316 1317 { 1318 .vendor = PCI_VENDOR_ID_INTEL, 1319 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0, 1320 .subvendor = PCI_ANY_ID, 1321 .subdevice = PCI_ANY_ID, 1322 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1323 }, 1324 1325 { 1326 .vendor = PCI_VENDOR_ID_INTEL, 1327 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1, 1328 .subvendor = PCI_ANY_ID, 1329 .subdevice = PCI_ANY_ID, 1330 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1331 }, 1332 1333 { 1334 .vendor = PCI_VENDOR_ID_INTEL, 1335 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2, 1336 .subvendor = PCI_ANY_ID, 1337 .subdevice = PCI_ANY_ID, 1338 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1339 }, 1340 1341 { 1342 .vendor = PCI_VENDOR_ID_INTEL, 1343 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0, 1344 .subvendor = PCI_ANY_ID, 1345 .subdevice = PCI_ANY_ID, 1346 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1347 }, 1348 1349 { 1350 .vendor = PCI_VENDOR_ID_INTEL, 1351 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1, 1352 .subvendor = PCI_ANY_ID, 1353 .subdevice = PCI_ANY_ID, 1354 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1355 }, 1356 1357 { 1358 .vendor = PCI_VENDOR_ID_INTEL, 1359 .device = PCI_DEVICE_ID_INTEL_MRFLD_MMC, 1360 .subvendor = PCI_ANY_ID, 1361 .subdevice = PCI_ANY_ID, 1362 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfld_mmc, 1363 }, 1364 1365 { 1366 .vendor = PCI_VENDOR_ID_INTEL, 1367 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC, 1368 .subvendor = PCI_ANY_ID, 1369 .subdevice = PCI_ANY_ID, 1370 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1371 }, 1372 1373 { 1374 .vendor = PCI_VENDOR_ID_INTEL, 1375 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO, 1376 .subvendor = PCI_ANY_ID, 1377 .subdevice = PCI_ANY_ID, 1378 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1379 }, 1380 1381 { 1382 .vendor = PCI_VENDOR_ID_INTEL, 1383 .device = PCI_DEVICE_ID_INTEL_SPT_SD, 1384 .subvendor = PCI_ANY_ID, 1385 .subdevice = PCI_ANY_ID, 1386 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1387 }, 1388 1389 { 1390 .vendor = PCI_VENDOR_ID_INTEL, 1391 .device = PCI_DEVICE_ID_INTEL_DNV_EMMC, 1392 .subvendor = PCI_ANY_ID, 1393 .subdevice = PCI_ANY_ID, 1394 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1395 }, 1396 1397 { 1398 .vendor = PCI_VENDOR_ID_INTEL, 1399 .device = PCI_DEVICE_ID_INTEL_BXT_EMMC, 1400 .subvendor = PCI_ANY_ID, 1401 .subdevice = PCI_ANY_ID, 1402 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1403 }, 1404 1405 { 1406 .vendor = PCI_VENDOR_ID_INTEL, 1407 .device = PCI_DEVICE_ID_INTEL_BXT_SDIO, 1408 .subvendor = PCI_ANY_ID, 1409 .subdevice = PCI_ANY_ID, 1410 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1411 }, 1412 1413 { 1414 .vendor = PCI_VENDOR_ID_INTEL, 1415 .device = PCI_DEVICE_ID_INTEL_BXT_SD, 1416 .subvendor = PCI_ANY_ID, 1417 .subdevice = PCI_ANY_ID, 1418 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1419 }, 1420 1421 { 1422 .vendor = PCI_VENDOR_ID_INTEL, 1423 .device = PCI_DEVICE_ID_INTEL_BXTM_EMMC, 1424 .subvendor = PCI_ANY_ID, 1425 .subdevice = PCI_ANY_ID, 1426 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1427 }, 1428 1429 { 1430 .vendor = PCI_VENDOR_ID_INTEL, 1431 .device = PCI_DEVICE_ID_INTEL_BXTM_SDIO, 1432 .subvendor = PCI_ANY_ID, 1433 .subdevice = PCI_ANY_ID, 1434 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1435 }, 1436 1437 { 1438 .vendor = PCI_VENDOR_ID_INTEL, 1439 .device = PCI_DEVICE_ID_INTEL_BXTM_SD, 1440 .subvendor = PCI_ANY_ID, 1441 .subdevice = PCI_ANY_ID, 1442 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1443 }, 1444 1445 { 1446 .vendor = PCI_VENDOR_ID_INTEL, 1447 .device = PCI_DEVICE_ID_INTEL_APL_EMMC, 1448 .subvendor = PCI_ANY_ID, 1449 .subdevice = PCI_ANY_ID, 1450 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1451 }, 1452 1453 { 1454 .vendor = PCI_VENDOR_ID_INTEL, 1455 .device = PCI_DEVICE_ID_INTEL_APL_SDIO, 1456 .subvendor = PCI_ANY_ID, 1457 .subdevice = PCI_ANY_ID, 1458 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1459 }, 1460 1461 { 1462 .vendor = PCI_VENDOR_ID_INTEL, 1463 .device = PCI_DEVICE_ID_INTEL_APL_SD, 1464 .subvendor = PCI_ANY_ID, 1465 .subdevice = PCI_ANY_ID, 1466 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1467 }, 1468 1469 { 1470 .vendor = PCI_VENDOR_ID_INTEL, 1471 .device = PCI_DEVICE_ID_INTEL_GLK_EMMC, 1472 .subvendor = PCI_ANY_ID, 1473 .subdevice = PCI_ANY_ID, 1474 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1475 }, 1476 1477 { 1478 .vendor = PCI_VENDOR_ID_INTEL, 1479 .device = PCI_DEVICE_ID_INTEL_GLK_SDIO, 1480 .subvendor = PCI_ANY_ID, 1481 .subdevice = PCI_ANY_ID, 1482 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1483 }, 1484 1485 { 1486 .vendor = PCI_VENDOR_ID_INTEL, 1487 .device = PCI_DEVICE_ID_INTEL_GLK_SD, 1488 .subvendor = PCI_ANY_ID, 1489 .subdevice = PCI_ANY_ID, 1490 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1491 }, 1492 1493 { 1494 .vendor = PCI_VENDOR_ID_O2, 1495 .device = PCI_DEVICE_ID_O2_8120, 1496 .subvendor = PCI_ANY_ID, 1497 .subdevice = PCI_ANY_ID, 1498 .driver_data = (kernel_ulong_t)&sdhci_o2, 1499 }, 1500 1501 { 1502 .vendor = PCI_VENDOR_ID_O2, 1503 .device = PCI_DEVICE_ID_O2_8220, 1504 .subvendor = PCI_ANY_ID, 1505 .subdevice = PCI_ANY_ID, 1506 .driver_data = (kernel_ulong_t)&sdhci_o2, 1507 }, 1508 1509 { 1510 .vendor = PCI_VENDOR_ID_O2, 1511 .device = PCI_DEVICE_ID_O2_8221, 1512 .subvendor = PCI_ANY_ID, 1513 .subdevice = PCI_ANY_ID, 1514 .driver_data = (kernel_ulong_t)&sdhci_o2, 1515 }, 1516 1517 { 1518 .vendor = PCI_VENDOR_ID_O2, 1519 .device = PCI_DEVICE_ID_O2_8320, 1520 .subvendor = PCI_ANY_ID, 1521 .subdevice = PCI_ANY_ID, 1522 .driver_data = (kernel_ulong_t)&sdhci_o2, 1523 }, 1524 1525 { 1526 .vendor = PCI_VENDOR_ID_O2, 1527 .device = PCI_DEVICE_ID_O2_8321, 1528 .subvendor = PCI_ANY_ID, 1529 .subdevice = PCI_ANY_ID, 1530 .driver_data = (kernel_ulong_t)&sdhci_o2, 1531 }, 1532 1533 { 1534 .vendor = PCI_VENDOR_ID_O2, 1535 .device = PCI_DEVICE_ID_O2_FUJIN2, 1536 .subvendor = PCI_ANY_ID, 1537 .subdevice = PCI_ANY_ID, 1538 .driver_data = (kernel_ulong_t)&sdhci_o2, 1539 }, 1540 1541 { 1542 .vendor = PCI_VENDOR_ID_O2, 1543 .device = PCI_DEVICE_ID_O2_SDS0, 1544 .subvendor = PCI_ANY_ID, 1545 .subdevice = PCI_ANY_ID, 1546 .driver_data = (kernel_ulong_t)&sdhci_o2, 1547 }, 1548 1549 { 1550 .vendor = PCI_VENDOR_ID_O2, 1551 .device = PCI_DEVICE_ID_O2_SDS1, 1552 .subvendor = PCI_ANY_ID, 1553 .subdevice = PCI_ANY_ID, 1554 .driver_data = (kernel_ulong_t)&sdhci_o2, 1555 }, 1556 1557 { 1558 .vendor = PCI_VENDOR_ID_O2, 1559 .device = PCI_DEVICE_ID_O2_SEABIRD0, 1560 .subvendor = PCI_ANY_ID, 1561 .subdevice = PCI_ANY_ID, 1562 .driver_data = (kernel_ulong_t)&sdhci_o2, 1563 }, 1564 1565 { 1566 .vendor = PCI_VENDOR_ID_O2, 1567 .device = PCI_DEVICE_ID_O2_SEABIRD1, 1568 .subvendor = PCI_ANY_ID, 1569 .subdevice = PCI_ANY_ID, 1570 .driver_data = (kernel_ulong_t)&sdhci_o2, 1571 }, 1572 { 1573 .vendor = PCI_VENDOR_ID_AMD, 1574 .device = PCI_ANY_ID, 1575 .class = PCI_CLASS_SYSTEM_SDHCI << 8, 1576 .class_mask = 0xFFFF00, 1577 .subvendor = PCI_ANY_ID, 1578 .subdevice = PCI_ANY_ID, 1579 .driver_data = (kernel_ulong_t)&sdhci_amd, 1580 }, 1581 { /* Generic SD host controller */ 1582 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) 1583 }, 1584 1585 { /* end: all zeroes */ }, 1586 }; 1587 1588 MODULE_DEVICE_TABLE(pci, pci_ids); 1589 1590 /*****************************************************************************\ 1591 * * 1592 * SDHCI core callbacks * 1593 * * 1594 \*****************************************************************************/ 1595 1596 static int sdhci_pci_enable_dma(struct sdhci_host *host) 1597 { 1598 struct sdhci_pci_slot *slot; 1599 struct pci_dev *pdev; 1600 1601 slot = sdhci_priv(host); 1602 pdev = slot->chip->pdev; 1603 1604 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1605 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1606 (host->flags & SDHCI_USE_SDMA)) { 1607 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1608 "doesn't fully claim to support it.\n"); 1609 } 1610 1611 pci_set_master(pdev); 1612 1613 return 0; 1614 } 1615 1616 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width) 1617 { 1618 u8 ctrl; 1619 1620 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1621 1622 switch (width) { 1623 case MMC_BUS_WIDTH_8: 1624 ctrl |= SDHCI_CTRL_8BITBUS; 1625 ctrl &= ~SDHCI_CTRL_4BITBUS; 1626 break; 1627 case MMC_BUS_WIDTH_4: 1628 ctrl |= SDHCI_CTRL_4BITBUS; 1629 ctrl &= ~SDHCI_CTRL_8BITBUS; 1630 break; 1631 default: 1632 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS); 1633 break; 1634 } 1635 1636 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1637 } 1638 1639 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1640 { 1641 struct sdhci_pci_slot *slot = sdhci_priv(host); 1642 int rst_n_gpio = slot->rst_n_gpio; 1643 1644 if (!gpio_is_valid(rst_n_gpio)) 1645 return; 1646 gpio_set_value_cansleep(rst_n_gpio, 0); 1647 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1648 udelay(10); 1649 gpio_set_value_cansleep(rst_n_gpio, 1); 1650 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1651 usleep_range(300, 1000); 1652 } 1653 1654 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1655 { 1656 struct sdhci_pci_slot *slot = sdhci_priv(host); 1657 1658 if (slot->hw_reset) 1659 slot->hw_reset(host); 1660 } 1661 1662 static const struct sdhci_ops sdhci_pci_ops = { 1663 .set_clock = sdhci_set_clock, 1664 .enable_dma = sdhci_pci_enable_dma, 1665 .set_bus_width = sdhci_pci_set_bus_width, 1666 .reset = sdhci_reset, 1667 .set_uhs_signaling = sdhci_set_uhs_signaling, 1668 .hw_reset = sdhci_pci_hw_reset, 1669 }; 1670 1671 /*****************************************************************************\ 1672 * * 1673 * Suspend/resume * 1674 * * 1675 \*****************************************************************************/ 1676 1677 #ifdef CONFIG_PM_SLEEP 1678 static int sdhci_pci_suspend(struct device *dev) 1679 { 1680 struct pci_dev *pdev = to_pci_dev(dev); 1681 struct sdhci_pci_chip *chip; 1682 struct sdhci_pci_slot *slot; 1683 struct sdhci_host *host; 1684 mmc_pm_flag_t slot_pm_flags; 1685 mmc_pm_flag_t pm_flags = 0; 1686 int i, ret; 1687 1688 chip = pci_get_drvdata(pdev); 1689 if (!chip) 1690 return 0; 1691 1692 for (i = 0; i < chip->num_slots; i++) { 1693 slot = chip->slots[i]; 1694 if (!slot) 1695 continue; 1696 1697 host = slot->host; 1698 1699 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 1700 mmc_retune_needed(host->mmc); 1701 1702 ret = sdhci_suspend_host(host); 1703 1704 if (ret) 1705 goto err_pci_suspend; 1706 1707 slot_pm_flags = host->mmc->pm_flags; 1708 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1709 sdhci_enable_irq_wakeups(host); 1710 1711 pm_flags |= slot_pm_flags; 1712 } 1713 1714 if (chip->fixes && chip->fixes->suspend) { 1715 ret = chip->fixes->suspend(chip); 1716 if (ret) 1717 goto err_pci_suspend; 1718 } 1719 1720 if (pm_flags & MMC_PM_KEEP_POWER) { 1721 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1722 device_init_wakeup(dev, true); 1723 else 1724 device_init_wakeup(dev, false); 1725 } else 1726 device_init_wakeup(dev, false); 1727 1728 return 0; 1729 1730 err_pci_suspend: 1731 while (--i >= 0) 1732 sdhci_resume_host(chip->slots[i]->host); 1733 return ret; 1734 } 1735 1736 static int sdhci_pci_resume(struct device *dev) 1737 { 1738 struct pci_dev *pdev = to_pci_dev(dev); 1739 struct sdhci_pci_chip *chip; 1740 struct sdhci_pci_slot *slot; 1741 int i, ret; 1742 1743 chip = pci_get_drvdata(pdev); 1744 if (!chip) 1745 return 0; 1746 1747 if (chip->fixes && chip->fixes->resume) { 1748 ret = chip->fixes->resume(chip); 1749 if (ret) 1750 return ret; 1751 } 1752 1753 for (i = 0; i < chip->num_slots; i++) { 1754 slot = chip->slots[i]; 1755 if (!slot) 1756 continue; 1757 1758 ret = sdhci_resume_host(slot->host); 1759 if (ret) 1760 return ret; 1761 } 1762 1763 return 0; 1764 } 1765 #endif 1766 1767 #ifdef CONFIG_PM 1768 static int sdhci_pci_runtime_suspend(struct device *dev) 1769 { 1770 struct pci_dev *pdev = to_pci_dev(dev); 1771 struct sdhci_pci_chip *chip; 1772 struct sdhci_pci_slot *slot; 1773 struct sdhci_host *host; 1774 int i, ret; 1775 1776 chip = pci_get_drvdata(pdev); 1777 if (!chip) 1778 return 0; 1779 1780 for (i = 0; i < chip->num_slots; i++) { 1781 slot = chip->slots[i]; 1782 if (!slot) 1783 continue; 1784 1785 host = slot->host; 1786 1787 ret = sdhci_runtime_suspend_host(host); 1788 if (ret) 1789 goto err_pci_runtime_suspend; 1790 1791 if (chip->rpm_retune && 1792 host->tuning_mode != SDHCI_TUNING_MODE_3) 1793 mmc_retune_needed(host->mmc); 1794 } 1795 1796 return 0; 1797 1798 err_pci_runtime_suspend: 1799 while (--i >= 0) 1800 sdhci_runtime_resume_host(chip->slots[i]->host); 1801 return ret; 1802 } 1803 1804 static int sdhci_pci_runtime_resume(struct device *dev) 1805 { 1806 struct pci_dev *pdev = to_pci_dev(dev); 1807 struct sdhci_pci_chip *chip; 1808 struct sdhci_pci_slot *slot; 1809 int i, ret; 1810 1811 chip = pci_get_drvdata(pdev); 1812 if (!chip) 1813 return 0; 1814 1815 for (i = 0; i < chip->num_slots; i++) { 1816 slot = chip->slots[i]; 1817 if (!slot) 1818 continue; 1819 1820 ret = sdhci_runtime_resume_host(slot->host); 1821 if (ret) 1822 return ret; 1823 } 1824 1825 return 0; 1826 } 1827 #endif 1828 1829 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1830 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1831 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1832 sdhci_pci_runtime_resume, NULL) 1833 }; 1834 1835 /*****************************************************************************\ 1836 * * 1837 * Device probing/removal * 1838 * * 1839 \*****************************************************************************/ 1840 1841 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1842 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1843 int slotno) 1844 { 1845 struct sdhci_pci_slot *slot; 1846 struct sdhci_host *host; 1847 int ret, bar = first_bar + slotno; 1848 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 1849 1850 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1851 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1852 return ERR_PTR(-ENODEV); 1853 } 1854 1855 if (pci_resource_len(pdev, bar) < 0x100) { 1856 dev_err(&pdev->dev, "Invalid iomem size. You may " 1857 "experience problems.\n"); 1858 } 1859 1860 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1861 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1862 return ERR_PTR(-ENODEV); 1863 } 1864 1865 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1866 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1867 return ERR_PTR(-ENODEV); 1868 } 1869 1870 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 1871 if (IS_ERR(host)) { 1872 dev_err(&pdev->dev, "cannot allocate host\n"); 1873 return ERR_CAST(host); 1874 } 1875 1876 slot = sdhci_priv(host); 1877 1878 slot->chip = chip; 1879 slot->host = host; 1880 slot->rst_n_gpio = -EINVAL; 1881 slot->cd_gpio = -EINVAL; 1882 slot->cd_idx = -1; 1883 1884 /* Retrieve platform data if there is any */ 1885 if (*sdhci_pci_get_data) 1886 slot->data = sdhci_pci_get_data(pdev, slotno); 1887 1888 if (slot->data) { 1889 if (slot->data->setup) { 1890 ret = slot->data->setup(slot->data); 1891 if (ret) { 1892 dev_err(&pdev->dev, "platform setup failed\n"); 1893 goto free; 1894 } 1895 } 1896 slot->rst_n_gpio = slot->data->rst_n_gpio; 1897 slot->cd_gpio = slot->data->cd_gpio; 1898 } 1899 1900 host->hw_name = "PCI"; 1901 host->ops = chip->fixes && chip->fixes->ops ? 1902 chip->fixes->ops : 1903 &sdhci_pci_ops; 1904 host->quirks = chip->quirks; 1905 host->quirks2 = chip->quirks2; 1906 1907 host->irq = pdev->irq; 1908 1909 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1910 if (ret) { 1911 dev_err(&pdev->dev, "cannot request region\n"); 1912 goto cleanup; 1913 } 1914 1915 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1916 1917 if (chip->fixes && chip->fixes->probe_slot) { 1918 ret = chip->fixes->probe_slot(slot); 1919 if (ret) 1920 goto cleanup; 1921 } 1922 1923 if (gpio_is_valid(slot->rst_n_gpio)) { 1924 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1925 gpio_direction_output(slot->rst_n_gpio, 1); 1926 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1927 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1928 } else { 1929 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1930 slot->rst_n_gpio = -EINVAL; 1931 } 1932 } 1933 1934 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; 1935 host->mmc->slotno = slotno; 1936 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1937 1938 if (slot->cd_idx >= 0) { 1939 ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx, 1940 slot->cd_override_level, 0, NULL); 1941 if (ret == -EPROBE_DEFER) 1942 goto remove; 1943 1944 if (ret) { 1945 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 1946 slot->cd_idx = -1; 1947 } 1948 } 1949 1950 if (chip->fixes && chip->fixes->add_host) 1951 ret = chip->fixes->add_host(slot); 1952 else 1953 ret = sdhci_add_host(host); 1954 if (ret) 1955 goto remove; 1956 1957 sdhci_pci_add_own_cd(slot); 1958 1959 /* 1960 * Check if the chip needs a separate GPIO for card detect to wake up 1961 * from runtime suspend. If it is not there, don't allow runtime PM. 1962 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 1963 */ 1964 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 1965 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 1966 chip->allow_runtime_pm = false; 1967 1968 return slot; 1969 1970 remove: 1971 if (chip->fixes && chip->fixes->remove_slot) 1972 chip->fixes->remove_slot(slot, 0); 1973 1974 cleanup: 1975 if (slot->data && slot->data->cleanup) 1976 slot->data->cleanup(slot->data); 1977 1978 free: 1979 sdhci_free_host(host); 1980 1981 return ERR_PTR(ret); 1982 } 1983 1984 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 1985 { 1986 int dead; 1987 u32 scratch; 1988 1989 sdhci_pci_remove_own_cd(slot); 1990 1991 dead = 0; 1992 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 1993 if (scratch == (u32)-1) 1994 dead = 1; 1995 1996 sdhci_remove_host(slot->host, dead); 1997 1998 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 1999 slot->chip->fixes->remove_slot(slot, dead); 2000 2001 if (slot->data && slot->data->cleanup) 2002 slot->data->cleanup(slot->data); 2003 2004 sdhci_free_host(slot->host); 2005 } 2006 2007 static void sdhci_pci_runtime_pm_allow(struct device *dev) 2008 { 2009 pm_suspend_ignore_children(dev, 1); 2010 pm_runtime_set_autosuspend_delay(dev, 50); 2011 pm_runtime_use_autosuspend(dev); 2012 pm_runtime_allow(dev); 2013 /* Stay active until mmc core scans for a card */ 2014 pm_runtime_put_noidle(dev); 2015 } 2016 2017 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 2018 { 2019 pm_runtime_forbid(dev); 2020 pm_runtime_get_noresume(dev); 2021 } 2022 2023 static int sdhci_pci_probe(struct pci_dev *pdev, 2024 const struct pci_device_id *ent) 2025 { 2026 struct sdhci_pci_chip *chip; 2027 struct sdhci_pci_slot *slot; 2028 2029 u8 slots, first_bar; 2030 int ret, i; 2031 2032 BUG_ON(pdev == NULL); 2033 BUG_ON(ent == NULL); 2034 2035 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 2036 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 2037 2038 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 2039 if (ret) 2040 return ret; 2041 2042 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 2043 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 2044 if (slots == 0) 2045 return -ENODEV; 2046 2047 BUG_ON(slots > MAX_SLOTS); 2048 2049 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 2050 if (ret) 2051 return ret; 2052 2053 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 2054 2055 if (first_bar > 5) { 2056 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 2057 return -ENODEV; 2058 } 2059 2060 ret = pcim_enable_device(pdev); 2061 if (ret) 2062 return ret; 2063 2064 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 2065 if (!chip) 2066 return -ENOMEM; 2067 2068 chip->pdev = pdev; 2069 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 2070 if (chip->fixes) { 2071 chip->quirks = chip->fixes->quirks; 2072 chip->quirks2 = chip->fixes->quirks2; 2073 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 2074 } 2075 chip->num_slots = slots; 2076 chip->pm_retune = true; 2077 chip->rpm_retune = true; 2078 2079 pci_set_drvdata(pdev, chip); 2080 2081 if (chip->fixes && chip->fixes->probe) { 2082 ret = chip->fixes->probe(chip); 2083 if (ret) 2084 return ret; 2085 } 2086 2087 slots = chip->num_slots; /* Quirk may have changed this */ 2088 2089 for (i = 0; i < slots; i++) { 2090 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 2091 if (IS_ERR(slot)) { 2092 for (i--; i >= 0; i--) 2093 sdhci_pci_remove_slot(chip->slots[i]); 2094 return PTR_ERR(slot); 2095 } 2096 2097 chip->slots[i] = slot; 2098 } 2099 2100 if (chip->allow_runtime_pm) 2101 sdhci_pci_runtime_pm_allow(&pdev->dev); 2102 2103 return 0; 2104 } 2105 2106 static void sdhci_pci_remove(struct pci_dev *pdev) 2107 { 2108 int i; 2109 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 2110 2111 if (chip->allow_runtime_pm) 2112 sdhci_pci_runtime_pm_forbid(&pdev->dev); 2113 2114 for (i = 0; i < chip->num_slots; i++) 2115 sdhci_pci_remove_slot(chip->slots[i]); 2116 } 2117 2118 static struct pci_driver sdhci_driver = { 2119 .name = "sdhci-pci", 2120 .id_table = pci_ids, 2121 .probe = sdhci_pci_probe, 2122 .remove = sdhci_pci_remove, 2123 .driver = { 2124 .pm = &sdhci_pci_pm_ops 2125 }, 2126 }; 2127 2128 module_pci_driver(sdhci_driver); 2129 2130 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 2131 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 2132 MODULE_LICENSE("GPL"); 2133