1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 3 * 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 5 * 6 * Thanks to the following companies for their support: 7 * 8 * - JMicron (hardware and technical support) 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/string.h> 13 #include <linux/delay.h> 14 #include <linux/highmem.h> 15 #include <linux/module.h> 16 #include <linux/pci.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/slab.h> 19 #include <linux/device.h> 20 #include <linux/mmc/host.h> 21 #include <linux/mmc/mmc.h> 22 #include <linux/scatterlist.h> 23 #include <linux/io.h> 24 #include <linux/iopoll.h> 25 #include <linux/gpio.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/mmc/slot-gpio.h> 28 #include <linux/mmc/sdhci-pci-data.h> 29 #include <linux/acpi.h> 30 #include <linux/dmi.h> 31 32 #ifdef CONFIG_X86 33 #include <asm/iosf_mbi.h> 34 #endif 35 36 #include "cqhci.h" 37 38 #include "sdhci.h" 39 #include "sdhci-pci.h" 40 41 static void sdhci_pci_hw_reset(struct sdhci_host *host); 42 43 #ifdef CONFIG_PM_SLEEP 44 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip) 45 { 46 mmc_pm_flag_t pm_flags = 0; 47 bool cap_cd_wake = false; 48 int i; 49 50 for (i = 0; i < chip->num_slots; i++) { 51 struct sdhci_pci_slot *slot = chip->slots[i]; 52 53 if (slot) { 54 pm_flags |= slot->host->mmc->pm_flags; 55 if (slot->host->mmc->caps & MMC_CAP_CD_WAKE) 56 cap_cd_wake = true; 57 } 58 } 59 60 if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ)) 61 return device_wakeup_enable(&chip->pdev->dev); 62 else if (!cap_cd_wake) 63 return device_wakeup_disable(&chip->pdev->dev); 64 65 return 0; 66 } 67 68 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 69 { 70 int i, ret; 71 72 sdhci_pci_init_wakeup(chip); 73 74 for (i = 0; i < chip->num_slots; i++) { 75 struct sdhci_pci_slot *slot = chip->slots[i]; 76 struct sdhci_host *host; 77 78 if (!slot) 79 continue; 80 81 host = slot->host; 82 83 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 84 mmc_retune_needed(host->mmc); 85 86 ret = sdhci_suspend_host(host); 87 if (ret) 88 goto err_pci_suspend; 89 90 if (device_may_wakeup(&chip->pdev->dev)) 91 mmc_gpio_set_cd_wake(host->mmc, true); 92 } 93 94 return 0; 95 96 err_pci_suspend: 97 while (--i >= 0) 98 sdhci_resume_host(chip->slots[i]->host); 99 return ret; 100 } 101 102 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip) 103 { 104 struct sdhci_pci_slot *slot; 105 int i, ret; 106 107 for (i = 0; i < chip->num_slots; i++) { 108 slot = chip->slots[i]; 109 if (!slot) 110 continue; 111 112 ret = sdhci_resume_host(slot->host); 113 if (ret) 114 return ret; 115 116 mmc_gpio_set_cd_wake(slot->host->mmc, false); 117 } 118 119 return 0; 120 } 121 122 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip) 123 { 124 int ret; 125 126 ret = cqhci_suspend(chip->slots[0]->host->mmc); 127 if (ret) 128 return ret; 129 130 return sdhci_pci_suspend_host(chip); 131 } 132 133 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip) 134 { 135 int ret; 136 137 ret = sdhci_pci_resume_host(chip); 138 if (ret) 139 return ret; 140 141 return cqhci_resume(chip->slots[0]->host->mmc); 142 } 143 #endif 144 145 #ifdef CONFIG_PM 146 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip) 147 { 148 struct sdhci_pci_slot *slot; 149 struct sdhci_host *host; 150 int i, ret; 151 152 for (i = 0; i < chip->num_slots; i++) { 153 slot = chip->slots[i]; 154 if (!slot) 155 continue; 156 157 host = slot->host; 158 159 ret = sdhci_runtime_suspend_host(host); 160 if (ret) 161 goto err_pci_runtime_suspend; 162 163 if (chip->rpm_retune && 164 host->tuning_mode != SDHCI_TUNING_MODE_3) 165 mmc_retune_needed(host->mmc); 166 } 167 168 return 0; 169 170 err_pci_runtime_suspend: 171 while (--i >= 0) 172 sdhci_runtime_resume_host(chip->slots[i]->host, 0); 173 return ret; 174 } 175 176 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip) 177 { 178 struct sdhci_pci_slot *slot; 179 int i, ret; 180 181 for (i = 0; i < chip->num_slots; i++) { 182 slot = chip->slots[i]; 183 if (!slot) 184 continue; 185 186 ret = sdhci_runtime_resume_host(slot->host, 0); 187 if (ret) 188 return ret; 189 } 190 191 return 0; 192 } 193 194 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip) 195 { 196 int ret; 197 198 ret = cqhci_suspend(chip->slots[0]->host->mmc); 199 if (ret) 200 return ret; 201 202 return sdhci_pci_runtime_suspend_host(chip); 203 } 204 205 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip) 206 { 207 int ret; 208 209 ret = sdhci_pci_runtime_resume_host(chip); 210 if (ret) 211 return ret; 212 213 return cqhci_resume(chip->slots[0]->host->mmc); 214 } 215 #endif 216 217 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask) 218 { 219 int cmd_error = 0; 220 int data_error = 0; 221 222 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 223 return intmask; 224 225 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 226 227 return 0; 228 } 229 230 static void sdhci_pci_dumpregs(struct mmc_host *mmc) 231 { 232 sdhci_dumpregs(mmc_priv(mmc)); 233 } 234 235 static void sdhci_cqhci_reset(struct sdhci_host *host, u8 mask) 236 { 237 if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) && 238 host->mmc->cqe_private) 239 cqhci_deactivate(host->mmc); 240 sdhci_reset(host, mask); 241 } 242 243 /*****************************************************************************\ 244 * * 245 * Hardware specific quirk handling * 246 * * 247 \*****************************************************************************/ 248 249 static int ricoh_probe(struct sdhci_pci_chip *chip) 250 { 251 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 252 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 253 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 254 return 0; 255 } 256 257 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 258 { 259 slot->host->caps = 260 FIELD_PREP(SDHCI_TIMEOUT_CLK_MASK, 0x21) | 261 FIELD_PREP(SDHCI_CLOCK_BASE_MASK, 0x21) | 262 SDHCI_TIMEOUT_CLK_UNIT | 263 SDHCI_CAN_VDD_330 | 264 SDHCI_CAN_DO_HISPD | 265 SDHCI_CAN_DO_SDMA; 266 return 0; 267 } 268 269 #ifdef CONFIG_PM_SLEEP 270 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 271 { 272 /* Apply a delay to allow controller to settle */ 273 /* Otherwise it becomes confused if card state changed 274 during suspend */ 275 msleep(500); 276 return sdhci_pci_resume_host(chip); 277 } 278 #endif 279 280 static const struct sdhci_pci_fixes sdhci_ricoh = { 281 .probe = ricoh_probe, 282 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 283 SDHCI_QUIRK_FORCE_DMA | 284 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 285 }; 286 287 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 288 .probe_slot = ricoh_mmc_probe_slot, 289 #ifdef CONFIG_PM_SLEEP 290 .resume = ricoh_mmc_resume, 291 #endif 292 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 293 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 294 SDHCI_QUIRK_NO_CARD_NO_RESET | 295 SDHCI_QUIRK_MISSING_CAPS 296 }; 297 298 static const struct sdhci_pci_fixes sdhci_ene_712 = { 299 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 300 SDHCI_QUIRK_BROKEN_DMA, 301 }; 302 303 static const struct sdhci_pci_fixes sdhci_ene_714 = { 304 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 305 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 306 SDHCI_QUIRK_BROKEN_DMA, 307 }; 308 309 static const struct sdhci_pci_fixes sdhci_cafe = { 310 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 311 SDHCI_QUIRK_NO_BUSY_IRQ | 312 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 313 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 314 }; 315 316 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 317 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 318 }; 319 320 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 321 { 322 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 323 return 0; 324 } 325 326 /* 327 * ADMA operation is disabled for Moorestown platform due to 328 * hardware bugs. 329 */ 330 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 331 { 332 /* 333 * slots number is fixed here for MRST as SDIO3/5 are never used and 334 * have hardware bugs. 335 */ 336 chip->num_slots = 1; 337 return 0; 338 } 339 340 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 341 { 342 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 343 return 0; 344 } 345 346 #ifdef CONFIG_PM 347 348 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 349 { 350 struct sdhci_pci_slot *slot = dev_id; 351 struct sdhci_host *host = slot->host; 352 353 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 354 return IRQ_HANDLED; 355 } 356 357 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 358 { 359 int err, irq, gpio = slot->cd_gpio; 360 361 slot->cd_gpio = -EINVAL; 362 slot->cd_irq = -EINVAL; 363 364 if (!gpio_is_valid(gpio)) 365 return; 366 367 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 368 if (err < 0) 369 goto out; 370 371 err = gpio_direction_input(gpio); 372 if (err < 0) 373 goto out_free; 374 375 irq = gpio_to_irq(gpio); 376 if (irq < 0) 377 goto out_free; 378 379 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 380 IRQF_TRIGGER_FALLING, "sd_cd", slot); 381 if (err) 382 goto out_free; 383 384 slot->cd_gpio = gpio; 385 slot->cd_irq = irq; 386 387 return; 388 389 out_free: 390 devm_gpio_free(&slot->chip->pdev->dev, gpio); 391 out: 392 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 393 } 394 395 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 396 { 397 if (slot->cd_irq >= 0) 398 free_irq(slot->cd_irq, slot); 399 } 400 401 #else 402 403 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 404 { 405 } 406 407 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 408 { 409 } 410 411 #endif 412 413 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 414 { 415 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 416 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC; 417 return 0; 418 } 419 420 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 421 { 422 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 423 return 0; 424 } 425 426 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 427 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 428 .probe_slot = mrst_hc_probe_slot, 429 }; 430 431 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 432 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 433 .probe = mrst_hc_probe, 434 }; 435 436 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 437 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 438 .allow_runtime_pm = true, 439 .own_cd_for_runtime_pm = true, 440 }; 441 442 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 443 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 444 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 445 .allow_runtime_pm = true, 446 .probe_slot = mfd_sdio_probe_slot, 447 }; 448 449 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 450 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 451 .allow_runtime_pm = true, 452 .probe_slot = mfd_emmc_probe_slot, 453 }; 454 455 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 456 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 457 .probe_slot = pch_hc_probe_slot, 458 }; 459 460 #ifdef CONFIG_X86 461 462 #define BYT_IOSF_SCCEP 0x63 463 #define BYT_IOSF_OCP_NETCTRL0 0x1078 464 #define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8) 465 466 static void byt_ocp_setting(struct pci_dev *pdev) 467 { 468 u32 val = 0; 469 470 if (pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC && 471 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SDIO && 472 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SD && 473 pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC2) 474 return; 475 476 if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0, 477 &val)) { 478 dev_err(&pdev->dev, "%s read error\n", __func__); 479 return; 480 } 481 482 if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE)) 483 return; 484 485 val &= ~BYT_IOSF_OCP_TIMEOUT_BASE; 486 487 if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0, 488 val)) { 489 dev_err(&pdev->dev, "%s write error\n", __func__); 490 return; 491 } 492 493 dev_dbg(&pdev->dev, "%s completed\n", __func__); 494 } 495 496 #else 497 498 static inline void byt_ocp_setting(struct pci_dev *pdev) 499 { 500 } 501 502 #endif 503 504 enum { 505 INTEL_DSM_FNS = 0, 506 INTEL_DSM_V18_SWITCH = 3, 507 INTEL_DSM_V33_SWITCH = 4, 508 INTEL_DSM_DRV_STRENGTH = 9, 509 INTEL_DSM_D3_RETUNE = 10, 510 }; 511 512 struct intel_host { 513 u32 dsm_fns; 514 int drv_strength; 515 bool d3_retune; 516 bool rpm_retune_ok; 517 u32 glk_rx_ctrl1; 518 u32 glk_tun_val; 519 }; 520 521 static const guid_t intel_dsm_guid = 522 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F, 523 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61); 524 525 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 526 unsigned int fn, u32 *result) 527 { 528 union acpi_object *obj; 529 int err = 0; 530 size_t len; 531 532 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL); 533 if (!obj) 534 return -EOPNOTSUPP; 535 536 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { 537 err = -EINVAL; 538 goto out; 539 } 540 541 len = min_t(size_t, obj->buffer.length, 4); 542 543 *result = 0; 544 memcpy(result, obj->buffer.pointer, len); 545 out: 546 ACPI_FREE(obj); 547 548 return err; 549 } 550 551 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 552 unsigned int fn, u32 *result) 553 { 554 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 555 return -EOPNOTSUPP; 556 557 return __intel_dsm(intel_host, dev, fn, result); 558 } 559 560 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 561 struct mmc_host *mmc) 562 { 563 int err; 564 u32 val; 565 566 intel_host->d3_retune = true; 567 568 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 569 if (err) { 570 pr_debug("%s: DSM not supported, error %d\n", 571 mmc_hostname(mmc), err); 572 return; 573 } 574 575 pr_debug("%s: DSM function mask %#x\n", 576 mmc_hostname(mmc), intel_host->dsm_fns); 577 578 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 579 intel_host->drv_strength = err ? 0 : val; 580 581 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 582 intel_host->d3_retune = err ? true : !!val; 583 } 584 585 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 586 { 587 u8 reg; 588 589 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 590 reg |= 0x10; 591 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 592 /* For eMMC, minimum is 1us but give it 9us for good measure */ 593 udelay(9); 594 reg &= ~0x10; 595 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 596 /* For eMMC, minimum is 200us but give it 300us for good measure */ 597 usleep_range(300, 1000); 598 } 599 600 static int intel_select_drive_strength(struct mmc_card *card, 601 unsigned int max_dtr, int host_drv, 602 int card_drv, int *drv_type) 603 { 604 struct sdhci_host *host = mmc_priv(card->host); 605 struct sdhci_pci_slot *slot = sdhci_priv(host); 606 struct intel_host *intel_host = sdhci_pci_priv(slot); 607 608 if (!(mmc_driver_type_mask(intel_host->drv_strength) & card_drv)) 609 return 0; 610 611 return intel_host->drv_strength; 612 } 613 614 static int bxt_get_cd(struct mmc_host *mmc) 615 { 616 int gpio_cd = mmc_gpio_get_cd(mmc); 617 struct sdhci_host *host = mmc_priv(mmc); 618 unsigned long flags; 619 int ret = 0; 620 621 if (!gpio_cd) 622 return 0; 623 624 spin_lock_irqsave(&host->lock, flags); 625 626 if (host->flags & SDHCI_DEVICE_DEAD) 627 goto out; 628 629 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 630 out: 631 spin_unlock_irqrestore(&host->lock, flags); 632 633 return ret; 634 } 635 636 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 637 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 638 639 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 640 unsigned short vdd) 641 { 642 int cntr; 643 u8 reg; 644 645 sdhci_set_power(host, mode, vdd); 646 647 if (mode == MMC_POWER_OFF) 648 return; 649 650 /* 651 * Bus power might not enable after D3 -> D0 transition due to the 652 * present state not yet having propagated. Retry for up to 2ms. 653 */ 654 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 655 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 656 if (reg & SDHCI_POWER_ON) 657 break; 658 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 659 reg |= SDHCI_POWER_ON; 660 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 661 } 662 } 663 664 #define INTEL_HS400_ES_REG 0x78 665 #define INTEL_HS400_ES_BIT BIT(0) 666 667 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc, 668 struct mmc_ios *ios) 669 { 670 struct sdhci_host *host = mmc_priv(mmc); 671 u32 val; 672 673 val = sdhci_readl(host, INTEL_HS400_ES_REG); 674 if (ios->enhanced_strobe) 675 val |= INTEL_HS400_ES_BIT; 676 else 677 val &= ~INTEL_HS400_ES_BIT; 678 sdhci_writel(host, val, INTEL_HS400_ES_REG); 679 } 680 681 static int intel_start_signal_voltage_switch(struct mmc_host *mmc, 682 struct mmc_ios *ios) 683 { 684 struct device *dev = mmc_dev(mmc); 685 struct sdhci_host *host = mmc_priv(mmc); 686 struct sdhci_pci_slot *slot = sdhci_priv(host); 687 struct intel_host *intel_host = sdhci_pci_priv(slot); 688 unsigned int fn; 689 u32 result = 0; 690 int err; 691 692 err = sdhci_start_signal_voltage_switch(mmc, ios); 693 if (err) 694 return err; 695 696 switch (ios->signal_voltage) { 697 case MMC_SIGNAL_VOLTAGE_330: 698 fn = INTEL_DSM_V33_SWITCH; 699 break; 700 case MMC_SIGNAL_VOLTAGE_180: 701 fn = INTEL_DSM_V18_SWITCH; 702 break; 703 default: 704 return 0; 705 } 706 707 err = intel_dsm(intel_host, dev, fn, &result); 708 pr_debug("%s: %s DSM fn %u error %d result %u\n", 709 mmc_hostname(mmc), __func__, fn, err, result); 710 711 return 0; 712 } 713 714 static const struct sdhci_ops sdhci_intel_byt_ops = { 715 .set_clock = sdhci_set_clock, 716 .set_power = sdhci_intel_set_power, 717 .enable_dma = sdhci_pci_enable_dma, 718 .set_bus_width = sdhci_set_bus_width, 719 .reset = sdhci_reset, 720 .set_uhs_signaling = sdhci_set_uhs_signaling, 721 .hw_reset = sdhci_pci_hw_reset, 722 }; 723 724 static const struct sdhci_ops sdhci_intel_glk_ops = { 725 .set_clock = sdhci_set_clock, 726 .set_power = sdhci_intel_set_power, 727 .enable_dma = sdhci_pci_enable_dma, 728 .set_bus_width = sdhci_set_bus_width, 729 .reset = sdhci_cqhci_reset, 730 .set_uhs_signaling = sdhci_set_uhs_signaling, 731 .hw_reset = sdhci_pci_hw_reset, 732 .irq = sdhci_cqhci_irq, 733 }; 734 735 static void byt_read_dsm(struct sdhci_pci_slot *slot) 736 { 737 struct intel_host *intel_host = sdhci_pci_priv(slot); 738 struct device *dev = &slot->chip->pdev->dev; 739 struct mmc_host *mmc = slot->host->mmc; 740 741 intel_dsm_init(intel_host, dev, mmc); 742 slot->chip->rpm_retune = intel_host->d3_retune; 743 } 744 745 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode) 746 { 747 int err = sdhci_execute_tuning(mmc, opcode); 748 struct sdhci_host *host = mmc_priv(mmc); 749 750 if (err) 751 return err; 752 753 /* 754 * Tuning can leave the IP in an active state (Buffer Read Enable bit 755 * set) which prevents the entry to low power states (i.e. S0i3). Data 756 * reset will clear it. 757 */ 758 sdhci_reset(host, SDHCI_RESET_DATA); 759 760 return 0; 761 } 762 763 static void byt_probe_slot(struct sdhci_pci_slot *slot) 764 { 765 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 766 struct device *dev = &slot->chip->pdev->dev; 767 struct mmc_host *mmc = slot->host->mmc; 768 769 byt_read_dsm(slot); 770 771 byt_ocp_setting(slot->chip->pdev); 772 773 ops->execute_tuning = intel_execute_tuning; 774 ops->start_signal_voltage_switch = intel_start_signal_voltage_switch; 775 776 device_property_read_u32(dev, "max-frequency", &mmc->f_max); 777 } 778 779 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 780 { 781 byt_probe_slot(slot); 782 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 783 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 784 MMC_CAP_CMD_DURING_TFR | 785 MMC_CAP_WAIT_WHILE_BUSY; 786 slot->hw_reset = sdhci_pci_int_hw_reset; 787 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 788 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 789 slot->host->mmc_host_ops.select_drive_strength = 790 intel_select_drive_strength; 791 return 0; 792 } 793 794 static bool glk_broken_cqhci(struct sdhci_pci_slot *slot) 795 { 796 return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 797 (dmi_match(DMI_BIOS_VENDOR, "LENOVO") || 798 dmi_match(DMI_SYS_VENDOR, "IRBIS")); 799 } 800 801 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot) 802 { 803 int ret = byt_emmc_probe_slot(slot); 804 805 if (!glk_broken_cqhci(slot)) 806 slot->host->mmc->caps2 |= MMC_CAP2_CQE; 807 808 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) { 809 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES, 810 slot->host->mmc_host_ops.hs400_enhanced_strobe = 811 intel_hs400_enhanced_strobe; 812 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; 813 } 814 815 return ret; 816 } 817 818 static const struct cqhci_host_ops glk_cqhci_ops = { 819 .enable = sdhci_cqe_enable, 820 .disable = sdhci_cqe_disable, 821 .dumpregs = sdhci_pci_dumpregs, 822 }; 823 824 static int glk_emmc_add_host(struct sdhci_pci_slot *slot) 825 { 826 struct device *dev = &slot->chip->pdev->dev; 827 struct sdhci_host *host = slot->host; 828 struct cqhci_host *cq_host; 829 bool dma64; 830 int ret; 831 832 ret = sdhci_setup_host(host); 833 if (ret) 834 return ret; 835 836 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); 837 if (!cq_host) { 838 ret = -ENOMEM; 839 goto cleanup; 840 } 841 842 cq_host->mmio = host->ioaddr + 0x200; 843 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 844 cq_host->ops = &glk_cqhci_ops; 845 846 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 847 if (dma64) 848 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 849 850 ret = cqhci_init(cq_host, host->mmc, dma64); 851 if (ret) 852 goto cleanup; 853 854 ret = __sdhci_add_host(host); 855 if (ret) 856 goto cleanup; 857 858 return 0; 859 860 cleanup: 861 sdhci_cleanup_host(host); 862 return ret; 863 } 864 865 #ifdef CONFIG_PM 866 #define GLK_RX_CTRL1 0x834 867 #define GLK_TUN_VAL 0x840 868 #define GLK_PATH_PLL GENMASK(13, 8) 869 #define GLK_DLY GENMASK(6, 0) 870 /* Workaround firmware failing to restore the tuning value */ 871 static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp) 872 { 873 struct sdhci_pci_slot *slot = chip->slots[0]; 874 struct intel_host *intel_host = sdhci_pci_priv(slot); 875 struct sdhci_host *host = slot->host; 876 u32 glk_rx_ctrl1; 877 u32 glk_tun_val; 878 u32 dly; 879 880 if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc)) 881 return; 882 883 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1); 884 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL); 885 886 if (susp) { 887 intel_host->glk_rx_ctrl1 = glk_rx_ctrl1; 888 intel_host->glk_tun_val = glk_tun_val; 889 return; 890 } 891 892 if (!intel_host->glk_tun_val) 893 return; 894 895 if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) { 896 intel_host->rpm_retune_ok = true; 897 return; 898 } 899 900 dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) + 901 (intel_host->glk_tun_val << 1)); 902 if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1)) 903 return; 904 905 glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly; 906 sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1); 907 908 intel_host->rpm_retune_ok = true; 909 chip->rpm_retune = true; 910 mmc_retune_needed(host->mmc); 911 pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc)); 912 } 913 914 static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp) 915 { 916 if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 917 !chip->rpm_retune) 918 glk_rpm_retune_wa(chip, susp); 919 } 920 921 static int glk_runtime_suspend(struct sdhci_pci_chip *chip) 922 { 923 glk_rpm_retune_chk(chip, true); 924 925 return sdhci_cqhci_runtime_suspend(chip); 926 } 927 928 static int glk_runtime_resume(struct sdhci_pci_chip *chip) 929 { 930 glk_rpm_retune_chk(chip, false); 931 932 return sdhci_cqhci_runtime_resume(chip); 933 } 934 #endif 935 936 #ifdef CONFIG_ACPI 937 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 938 { 939 acpi_status status; 940 unsigned long long max_freq; 941 942 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 943 "MXFQ", NULL, &max_freq); 944 if (ACPI_FAILURE(status)) { 945 dev_err(&slot->chip->pdev->dev, 946 "MXFQ not found in acpi table\n"); 947 return -EINVAL; 948 } 949 950 slot->host->mmc->f_max = max_freq * 1000000; 951 952 return 0; 953 } 954 #else 955 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 956 { 957 return 0; 958 } 959 #endif 960 961 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 962 { 963 int err; 964 965 byt_probe_slot(slot); 966 967 err = ni_set_max_freq(slot); 968 if (err) 969 return err; 970 971 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 972 MMC_CAP_WAIT_WHILE_BUSY; 973 return 0; 974 } 975 976 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 977 { 978 byt_probe_slot(slot); 979 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 980 MMC_CAP_WAIT_WHILE_BUSY; 981 return 0; 982 } 983 984 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 985 { 986 byt_probe_slot(slot); 987 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | 988 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE; 989 slot->cd_idx = 0; 990 slot->cd_override_level = true; 991 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 992 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 993 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 994 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) 995 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 996 997 if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI && 998 slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3) 999 slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V; 1000 1001 return 0; 1002 } 1003 1004 #ifdef CONFIG_PM_SLEEP 1005 1006 static int byt_resume(struct sdhci_pci_chip *chip) 1007 { 1008 byt_ocp_setting(chip->pdev); 1009 1010 return sdhci_pci_resume_host(chip); 1011 } 1012 1013 #endif 1014 1015 #ifdef CONFIG_PM 1016 1017 static int byt_runtime_resume(struct sdhci_pci_chip *chip) 1018 { 1019 byt_ocp_setting(chip->pdev); 1020 1021 return sdhci_pci_runtime_resume_host(chip); 1022 } 1023 1024 #endif 1025 1026 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 1027 #ifdef CONFIG_PM_SLEEP 1028 .resume = byt_resume, 1029 #endif 1030 #ifdef CONFIG_PM 1031 .runtime_resume = byt_runtime_resume, 1032 #endif 1033 .allow_runtime_pm = true, 1034 .probe_slot = byt_emmc_probe_slot, 1035 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1036 SDHCI_QUIRK_NO_LED, 1037 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1038 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1039 SDHCI_QUIRK2_STOP_WITH_TC, 1040 .ops = &sdhci_intel_byt_ops, 1041 .priv_size = sizeof(struct intel_host), 1042 }; 1043 1044 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = { 1045 .allow_runtime_pm = true, 1046 .probe_slot = glk_emmc_probe_slot, 1047 .add_host = glk_emmc_add_host, 1048 #ifdef CONFIG_PM_SLEEP 1049 .suspend = sdhci_cqhci_suspend, 1050 .resume = sdhci_cqhci_resume, 1051 #endif 1052 #ifdef CONFIG_PM 1053 .runtime_suspend = glk_runtime_suspend, 1054 .runtime_resume = glk_runtime_resume, 1055 #endif 1056 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1057 SDHCI_QUIRK_NO_LED, 1058 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1059 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1060 SDHCI_QUIRK2_STOP_WITH_TC, 1061 .ops = &sdhci_intel_glk_ops, 1062 .priv_size = sizeof(struct intel_host), 1063 }; 1064 1065 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 1066 #ifdef CONFIG_PM_SLEEP 1067 .resume = byt_resume, 1068 #endif 1069 #ifdef CONFIG_PM 1070 .runtime_resume = byt_runtime_resume, 1071 #endif 1072 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1073 SDHCI_QUIRK_NO_LED, 1074 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1075 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1076 .allow_runtime_pm = true, 1077 .probe_slot = ni_byt_sdio_probe_slot, 1078 .ops = &sdhci_intel_byt_ops, 1079 .priv_size = sizeof(struct intel_host), 1080 }; 1081 1082 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 1083 #ifdef CONFIG_PM_SLEEP 1084 .resume = byt_resume, 1085 #endif 1086 #ifdef CONFIG_PM 1087 .runtime_resume = byt_runtime_resume, 1088 #endif 1089 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1090 SDHCI_QUIRK_NO_LED, 1091 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1092 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1093 .allow_runtime_pm = true, 1094 .probe_slot = byt_sdio_probe_slot, 1095 .ops = &sdhci_intel_byt_ops, 1096 .priv_size = sizeof(struct intel_host), 1097 }; 1098 1099 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 1100 #ifdef CONFIG_PM_SLEEP 1101 .resume = byt_resume, 1102 #endif 1103 #ifdef CONFIG_PM 1104 .runtime_resume = byt_runtime_resume, 1105 #endif 1106 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1107 SDHCI_QUIRK_NO_LED, 1108 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 1109 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1110 SDHCI_QUIRK2_STOP_WITH_TC, 1111 .allow_runtime_pm = true, 1112 .own_cd_for_runtime_pm = true, 1113 .probe_slot = byt_sd_probe_slot, 1114 .ops = &sdhci_intel_byt_ops, 1115 .priv_size = sizeof(struct intel_host), 1116 }; 1117 1118 /* Define Host controllers for Intel Merrifield platform */ 1119 #define INTEL_MRFLD_EMMC_0 0 1120 #define INTEL_MRFLD_EMMC_1 1 1121 #define INTEL_MRFLD_SD 2 1122 #define INTEL_MRFLD_SDIO 3 1123 1124 #ifdef CONFIG_ACPI 1125 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) 1126 { 1127 struct acpi_device *device, *child; 1128 1129 device = ACPI_COMPANION(&slot->chip->pdev->dev); 1130 if (!device) 1131 return; 1132 1133 acpi_device_fix_up_power(device); 1134 list_for_each_entry(child, &device->children, node) 1135 if (child->status.present && child->status.enabled) 1136 acpi_device_fix_up_power(child); 1137 } 1138 #else 1139 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {} 1140 #endif 1141 1142 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 1143 { 1144 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 1145 1146 switch (func) { 1147 case INTEL_MRFLD_EMMC_0: 1148 case INTEL_MRFLD_EMMC_1: 1149 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1150 MMC_CAP_8_BIT_DATA | 1151 MMC_CAP_1_8V_DDR; 1152 break; 1153 case INTEL_MRFLD_SD: 1154 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1155 break; 1156 case INTEL_MRFLD_SDIO: 1157 /* Advertise 2.0v for compatibility with the SDIO card's OCR */ 1158 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195; 1159 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1160 MMC_CAP_POWER_OFF_CARD; 1161 break; 1162 default: 1163 return -ENODEV; 1164 } 1165 1166 intel_mrfld_mmc_fix_up_power_slot(slot); 1167 return 0; 1168 } 1169 1170 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 1171 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1172 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 1173 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1174 .allow_runtime_pm = true, 1175 .probe_slot = intel_mrfld_mmc_probe_slot, 1176 }; 1177 1178 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 1179 { 1180 u8 scratch; 1181 int ret; 1182 1183 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 1184 if (ret) 1185 return ret; 1186 1187 /* 1188 * Turn PMOS on [bit 0], set over current detection to 2.4 V 1189 * [bit 1:2] and enable over current debouncing [bit 6]. 1190 */ 1191 if (on) 1192 scratch |= 0x47; 1193 else 1194 scratch &= ~0x47; 1195 1196 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 1197 } 1198 1199 static int jmicron_probe(struct sdhci_pci_chip *chip) 1200 { 1201 int ret; 1202 u16 mmcdev = 0; 1203 1204 if (chip->pdev->revision == 0) { 1205 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 1206 SDHCI_QUIRK_32BIT_DMA_SIZE | 1207 SDHCI_QUIRK_32BIT_ADMA_SIZE | 1208 SDHCI_QUIRK_RESET_AFTER_REQUEST | 1209 SDHCI_QUIRK_BROKEN_SMALL_PIO; 1210 } 1211 1212 /* 1213 * JMicron chips can have two interfaces to the same hardware 1214 * in order to work around limitations in Microsoft's driver. 1215 * We need to make sure we only bind to one of them. 1216 * 1217 * This code assumes two things: 1218 * 1219 * 1. The PCI code adds subfunctions in order. 1220 * 1221 * 2. The MMC interface has a lower subfunction number 1222 * than the SD interface. 1223 */ 1224 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 1225 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 1226 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 1227 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 1228 1229 if (mmcdev) { 1230 struct pci_dev *sd_dev; 1231 1232 sd_dev = NULL; 1233 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 1234 mmcdev, sd_dev)) != NULL) { 1235 if ((PCI_SLOT(chip->pdev->devfn) == 1236 PCI_SLOT(sd_dev->devfn)) && 1237 (chip->pdev->bus == sd_dev->bus)) 1238 break; 1239 } 1240 1241 if (sd_dev) { 1242 pci_dev_put(sd_dev); 1243 dev_info(&chip->pdev->dev, "Refusing to bind to " 1244 "secondary interface.\n"); 1245 return -ENODEV; 1246 } 1247 } 1248 1249 /* 1250 * JMicron chips need a bit of a nudge to enable the power 1251 * output pins. 1252 */ 1253 ret = jmicron_pmos(chip, 1); 1254 if (ret) { 1255 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1256 return ret; 1257 } 1258 1259 /* quirk for unsable RO-detection on JM388 chips */ 1260 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 1261 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1262 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 1263 1264 return 0; 1265 } 1266 1267 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 1268 { 1269 u8 scratch; 1270 1271 scratch = readb(host->ioaddr + 0xC0); 1272 1273 if (on) 1274 scratch |= 0x01; 1275 else 1276 scratch &= ~0x01; 1277 1278 writeb(scratch, host->ioaddr + 0xC0); 1279 } 1280 1281 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 1282 { 1283 if (slot->chip->pdev->revision == 0) { 1284 u16 version; 1285 1286 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 1287 version = (version & SDHCI_VENDOR_VER_MASK) >> 1288 SDHCI_VENDOR_VER_SHIFT; 1289 1290 /* 1291 * Older versions of the chip have lots of nasty glitches 1292 * in the ADMA engine. It's best just to avoid it 1293 * completely. 1294 */ 1295 if (version < 0xAC) 1296 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 1297 } 1298 1299 /* JM388 MMC doesn't support 1.8V while SD supports it */ 1300 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1301 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 1302 MMC_VDD_29_30 | MMC_VDD_30_31 | 1303 MMC_VDD_165_195; /* allow 1.8V */ 1304 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 1305 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 1306 } 1307 1308 /* 1309 * The secondary interface requires a bit set to get the 1310 * interrupts. 1311 */ 1312 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1313 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1314 jmicron_enable_mmc(slot->host, 1); 1315 1316 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 1317 1318 return 0; 1319 } 1320 1321 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 1322 { 1323 if (dead) 1324 return; 1325 1326 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1327 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1328 jmicron_enable_mmc(slot->host, 0); 1329 } 1330 1331 #ifdef CONFIG_PM_SLEEP 1332 static int jmicron_suspend(struct sdhci_pci_chip *chip) 1333 { 1334 int i, ret; 1335 1336 ret = sdhci_pci_suspend_host(chip); 1337 if (ret) 1338 return ret; 1339 1340 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1341 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1342 for (i = 0; i < chip->num_slots; i++) 1343 jmicron_enable_mmc(chip->slots[i]->host, 0); 1344 } 1345 1346 return 0; 1347 } 1348 1349 static int jmicron_resume(struct sdhci_pci_chip *chip) 1350 { 1351 int ret, i; 1352 1353 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1354 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1355 for (i = 0; i < chip->num_slots; i++) 1356 jmicron_enable_mmc(chip->slots[i]->host, 1); 1357 } 1358 1359 ret = jmicron_pmos(chip, 1); 1360 if (ret) { 1361 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1362 return ret; 1363 } 1364 1365 return sdhci_pci_resume_host(chip); 1366 } 1367 #endif 1368 1369 static const struct sdhci_pci_fixes sdhci_jmicron = { 1370 .probe = jmicron_probe, 1371 1372 .probe_slot = jmicron_probe_slot, 1373 .remove_slot = jmicron_remove_slot, 1374 1375 #ifdef CONFIG_PM_SLEEP 1376 .suspend = jmicron_suspend, 1377 .resume = jmicron_resume, 1378 #endif 1379 }; 1380 1381 /* SysKonnect CardBus2SDIO extra registers */ 1382 #define SYSKT_CTRL 0x200 1383 #define SYSKT_RDFIFO_STAT 0x204 1384 #define SYSKT_WRFIFO_STAT 0x208 1385 #define SYSKT_POWER_DATA 0x20c 1386 #define SYSKT_POWER_330 0xef 1387 #define SYSKT_POWER_300 0xf8 1388 #define SYSKT_POWER_184 0xcc 1389 #define SYSKT_POWER_CMD 0x20d 1390 #define SYSKT_POWER_START (1 << 7) 1391 #define SYSKT_POWER_STATUS 0x20e 1392 #define SYSKT_POWER_STATUS_OK (1 << 0) 1393 #define SYSKT_BOARD_REV 0x210 1394 #define SYSKT_CHIP_REV 0x211 1395 #define SYSKT_CONF_DATA 0x212 1396 #define SYSKT_CONF_DATA_1V8 (1 << 2) 1397 #define SYSKT_CONF_DATA_2V5 (1 << 1) 1398 #define SYSKT_CONF_DATA_3V3 (1 << 0) 1399 1400 static int syskt_probe(struct sdhci_pci_chip *chip) 1401 { 1402 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1403 chip->pdev->class &= ~0x0000FF; 1404 chip->pdev->class |= PCI_SDHCI_IFDMA; 1405 } 1406 return 0; 1407 } 1408 1409 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 1410 { 1411 int tm, ps; 1412 1413 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 1414 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 1415 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 1416 "board rev %d.%d, chip rev %d.%d\n", 1417 board_rev >> 4, board_rev & 0xf, 1418 chip_rev >> 4, chip_rev & 0xf); 1419 if (chip_rev >= 0x20) 1420 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 1421 1422 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 1423 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 1424 udelay(50); 1425 tm = 10; /* Wait max 1 ms */ 1426 do { 1427 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 1428 if (ps & SYSKT_POWER_STATUS_OK) 1429 break; 1430 udelay(100); 1431 } while (--tm); 1432 if (!tm) { 1433 dev_err(&slot->chip->pdev->dev, 1434 "power regulator never stabilized"); 1435 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 1436 return -ENODEV; 1437 } 1438 1439 return 0; 1440 } 1441 1442 static const struct sdhci_pci_fixes sdhci_syskt = { 1443 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 1444 .probe = syskt_probe, 1445 .probe_slot = syskt_probe_slot, 1446 }; 1447 1448 static int via_probe(struct sdhci_pci_chip *chip) 1449 { 1450 if (chip->pdev->revision == 0x10) 1451 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 1452 1453 return 0; 1454 } 1455 1456 static const struct sdhci_pci_fixes sdhci_via = { 1457 .probe = via_probe, 1458 }; 1459 1460 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 1461 { 1462 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 1463 return 0; 1464 } 1465 1466 static const struct sdhci_pci_fixes sdhci_rtsx = { 1467 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1468 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 1469 SDHCI_QUIRK2_BROKEN_DDR50, 1470 .probe_slot = rtsx_probe_slot, 1471 }; 1472 1473 /*AMD chipset generation*/ 1474 enum amd_chipset_gen { 1475 AMD_CHIPSET_BEFORE_ML, 1476 AMD_CHIPSET_CZ, 1477 AMD_CHIPSET_NL, 1478 AMD_CHIPSET_UNKNOWN, 1479 }; 1480 1481 /* AMD registers */ 1482 #define AMD_SD_AUTO_PATTERN 0xB8 1483 #define AMD_MSLEEP_DURATION 4 1484 #define AMD_SD_MISC_CONTROL 0xD0 1485 #define AMD_MAX_TUNE_VALUE 0x0B 1486 #define AMD_AUTO_TUNE_SEL 0x10800 1487 #define AMD_FIFO_PTR 0x30 1488 #define AMD_BIT_MASK 0x1F 1489 1490 static void amd_tuning_reset(struct sdhci_host *host) 1491 { 1492 unsigned int val; 1493 1494 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1495 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 1496 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1497 1498 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1499 val &= ~SDHCI_CTRL_EXEC_TUNING; 1500 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1501 } 1502 1503 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 1504 { 1505 unsigned int val; 1506 1507 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 1508 val &= ~AMD_BIT_MASK; 1509 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 1510 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 1511 } 1512 1513 static void amd_enable_manual_tuning(struct pci_dev *pdev) 1514 { 1515 unsigned int val; 1516 1517 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 1518 val |= AMD_FIFO_PTR; 1519 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 1520 } 1521 1522 static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode) 1523 { 1524 struct sdhci_pci_slot *slot = sdhci_priv(host); 1525 struct pci_dev *pdev = slot->chip->pdev; 1526 u8 valid_win = 0; 1527 u8 valid_win_max = 0; 1528 u8 valid_win_end = 0; 1529 u8 ctrl, tune_around; 1530 1531 amd_tuning_reset(host); 1532 1533 for (tune_around = 0; tune_around < 12; tune_around++) { 1534 amd_config_tuning_phase(pdev, tune_around); 1535 1536 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1537 valid_win = 0; 1538 msleep(AMD_MSLEEP_DURATION); 1539 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 1540 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 1541 } else if (++valid_win > valid_win_max) { 1542 valid_win_max = valid_win; 1543 valid_win_end = tune_around; 1544 } 1545 } 1546 1547 if (!valid_win_max) { 1548 dev_err(&pdev->dev, "no tuning point found\n"); 1549 return -EIO; 1550 } 1551 1552 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 1553 1554 amd_enable_manual_tuning(pdev); 1555 1556 host->mmc->retune_period = 0; 1557 1558 return 0; 1559 } 1560 1561 static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode) 1562 { 1563 struct sdhci_host *host = mmc_priv(mmc); 1564 1565 /* AMD requires custom HS200 tuning */ 1566 if (host->timing == MMC_TIMING_MMC_HS200) 1567 return amd_execute_tuning_hs200(host, opcode); 1568 1569 /* Otherwise perform standard SDHCI tuning */ 1570 return sdhci_execute_tuning(mmc, opcode); 1571 } 1572 1573 static int amd_probe_slot(struct sdhci_pci_slot *slot) 1574 { 1575 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 1576 1577 ops->execute_tuning = amd_execute_tuning; 1578 1579 return 0; 1580 } 1581 1582 static int amd_probe(struct sdhci_pci_chip *chip) 1583 { 1584 struct pci_dev *smbus_dev; 1585 enum amd_chipset_gen gen; 1586 1587 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1588 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 1589 if (smbus_dev) { 1590 gen = AMD_CHIPSET_BEFORE_ML; 1591 } else { 1592 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1593 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1594 if (smbus_dev) { 1595 if (smbus_dev->revision < 0x51) 1596 gen = AMD_CHIPSET_CZ; 1597 else 1598 gen = AMD_CHIPSET_NL; 1599 } else { 1600 gen = AMD_CHIPSET_UNKNOWN; 1601 } 1602 } 1603 1604 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1605 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1606 1607 return 0; 1608 } 1609 1610 static u32 sdhci_read_present_state(struct sdhci_host *host) 1611 { 1612 return sdhci_readl(host, SDHCI_PRESENT_STATE); 1613 } 1614 1615 static void amd_sdhci_reset(struct sdhci_host *host, u8 mask) 1616 { 1617 struct sdhci_pci_slot *slot = sdhci_priv(host); 1618 struct pci_dev *pdev = slot->chip->pdev; 1619 u32 present_state; 1620 1621 /* 1622 * SDHC 0x7906 requires a hard reset to clear all internal state. 1623 * Otherwise it can get into a bad state where the DATA lines are always 1624 * read as zeros. 1625 */ 1626 if (pdev->device == 0x7906 && (mask & SDHCI_RESET_ALL)) { 1627 pci_clear_master(pdev); 1628 1629 pci_save_state(pdev); 1630 1631 pci_set_power_state(pdev, PCI_D3cold); 1632 pr_debug("%s: power_state=%u\n", mmc_hostname(host->mmc), 1633 pdev->current_state); 1634 pci_set_power_state(pdev, PCI_D0); 1635 1636 pci_restore_state(pdev); 1637 1638 /* 1639 * SDHCI_RESET_ALL says the card detect logic should not be 1640 * reset, but since we need to reset the entire controller 1641 * we should wait until the card detect logic has stabilized. 1642 * 1643 * This normally takes about 40ms. 1644 */ 1645 readx_poll_timeout( 1646 sdhci_read_present_state, 1647 host, 1648 present_state, 1649 present_state & SDHCI_CD_STABLE, 1650 10000, 1651 100000 1652 ); 1653 } 1654 1655 return sdhci_reset(host, mask); 1656 } 1657 1658 static const struct sdhci_ops amd_sdhci_pci_ops = { 1659 .set_clock = sdhci_set_clock, 1660 .enable_dma = sdhci_pci_enable_dma, 1661 .set_bus_width = sdhci_set_bus_width, 1662 .reset = amd_sdhci_reset, 1663 .set_uhs_signaling = sdhci_set_uhs_signaling, 1664 }; 1665 1666 static const struct sdhci_pci_fixes sdhci_amd = { 1667 .probe = amd_probe, 1668 .ops = &amd_sdhci_pci_ops, 1669 .probe_slot = amd_probe_slot, 1670 }; 1671 1672 static const struct pci_device_id pci_ids[] = { 1673 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh), 1674 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc), 1675 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc), 1676 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc), 1677 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712), 1678 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712), 1679 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714), 1680 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714), 1681 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe), 1682 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron), 1683 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron), 1684 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron), 1685 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron), 1686 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt), 1687 SDHCI_PCI_DEVICE(VIA, 95D0, via), 1688 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx), 1689 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk), 1690 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0), 1691 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2), 1692 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2), 1693 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd), 1694 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio), 1695 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio), 1696 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc), 1697 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc), 1698 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio), 1699 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio), 1700 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc), 1701 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio), 1702 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio), 1703 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd), 1704 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc), 1705 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc), 1706 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio), 1707 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd), 1708 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd), 1709 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio), 1710 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio), 1711 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc), 1712 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc), 1713 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc), 1714 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc), 1715 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio), 1716 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd), 1717 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc), 1718 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc), 1719 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc), 1720 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio), 1721 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd), 1722 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc), 1723 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio), 1724 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd), 1725 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc), 1726 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio), 1727 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd), 1728 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc), 1729 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio), 1730 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd), 1731 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc), 1732 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd), 1733 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd), 1734 SDHCI_PCI_DEVICE(INTEL, ICP_EMMC, intel_glk_emmc), 1735 SDHCI_PCI_DEVICE(INTEL, ICP_SD, intel_byt_sd), 1736 SDHCI_PCI_DEVICE(INTEL, EHL_EMMC, intel_glk_emmc), 1737 SDHCI_PCI_DEVICE(INTEL, EHL_SD, intel_byt_sd), 1738 SDHCI_PCI_DEVICE(INTEL, CML_EMMC, intel_glk_emmc), 1739 SDHCI_PCI_DEVICE(INTEL, CML_SD, intel_byt_sd), 1740 SDHCI_PCI_DEVICE(INTEL, CMLH_SD, intel_byt_sd), 1741 SDHCI_PCI_DEVICE(INTEL, JSL_EMMC, intel_glk_emmc), 1742 SDHCI_PCI_DEVICE(INTEL, JSL_SD, intel_byt_sd), 1743 SDHCI_PCI_DEVICE(O2, 8120, o2), 1744 SDHCI_PCI_DEVICE(O2, 8220, o2), 1745 SDHCI_PCI_DEVICE(O2, 8221, o2), 1746 SDHCI_PCI_DEVICE(O2, 8320, o2), 1747 SDHCI_PCI_DEVICE(O2, 8321, o2), 1748 SDHCI_PCI_DEVICE(O2, FUJIN2, o2), 1749 SDHCI_PCI_DEVICE(O2, SDS0, o2), 1750 SDHCI_PCI_DEVICE(O2, SDS1, o2), 1751 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2), 1752 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), 1753 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan), 1754 SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps), 1755 SDHCI_PCI_DEVICE(GLI, 9750, gl9750), 1756 SDHCI_PCI_DEVICE(GLI, 9755, gl9755), 1757 SDHCI_PCI_DEVICE(GLI, 9763E, gl9763e), 1758 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), 1759 /* Generic SD host controller */ 1760 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, 1761 { /* end: all zeroes */ }, 1762 }; 1763 1764 MODULE_DEVICE_TABLE(pci, pci_ids); 1765 1766 /*****************************************************************************\ 1767 * * 1768 * SDHCI core callbacks * 1769 * * 1770 \*****************************************************************************/ 1771 1772 int sdhci_pci_enable_dma(struct sdhci_host *host) 1773 { 1774 struct sdhci_pci_slot *slot; 1775 struct pci_dev *pdev; 1776 1777 slot = sdhci_priv(host); 1778 pdev = slot->chip->pdev; 1779 1780 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1781 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1782 (host->flags & SDHCI_USE_SDMA)) { 1783 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1784 "doesn't fully claim to support it.\n"); 1785 } 1786 1787 pci_set_master(pdev); 1788 1789 return 0; 1790 } 1791 1792 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1793 { 1794 struct sdhci_pci_slot *slot = sdhci_priv(host); 1795 int rst_n_gpio = slot->rst_n_gpio; 1796 1797 if (!gpio_is_valid(rst_n_gpio)) 1798 return; 1799 gpio_set_value_cansleep(rst_n_gpio, 0); 1800 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1801 udelay(10); 1802 gpio_set_value_cansleep(rst_n_gpio, 1); 1803 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1804 usleep_range(300, 1000); 1805 } 1806 1807 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1808 { 1809 struct sdhci_pci_slot *slot = sdhci_priv(host); 1810 1811 if (slot->hw_reset) 1812 slot->hw_reset(host); 1813 } 1814 1815 static const struct sdhci_ops sdhci_pci_ops = { 1816 .set_clock = sdhci_set_clock, 1817 .enable_dma = sdhci_pci_enable_dma, 1818 .set_bus_width = sdhci_set_bus_width, 1819 .reset = sdhci_reset, 1820 .set_uhs_signaling = sdhci_set_uhs_signaling, 1821 .hw_reset = sdhci_pci_hw_reset, 1822 }; 1823 1824 /*****************************************************************************\ 1825 * * 1826 * Suspend/resume * 1827 * * 1828 \*****************************************************************************/ 1829 1830 #ifdef CONFIG_PM_SLEEP 1831 static int sdhci_pci_suspend(struct device *dev) 1832 { 1833 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 1834 1835 if (!chip) 1836 return 0; 1837 1838 if (chip->fixes && chip->fixes->suspend) 1839 return chip->fixes->suspend(chip); 1840 1841 return sdhci_pci_suspend_host(chip); 1842 } 1843 1844 static int sdhci_pci_resume(struct device *dev) 1845 { 1846 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 1847 1848 if (!chip) 1849 return 0; 1850 1851 if (chip->fixes && chip->fixes->resume) 1852 return chip->fixes->resume(chip); 1853 1854 return sdhci_pci_resume_host(chip); 1855 } 1856 #endif 1857 1858 #ifdef CONFIG_PM 1859 static int sdhci_pci_runtime_suspend(struct device *dev) 1860 { 1861 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 1862 1863 if (!chip) 1864 return 0; 1865 1866 if (chip->fixes && chip->fixes->runtime_suspend) 1867 return chip->fixes->runtime_suspend(chip); 1868 1869 return sdhci_pci_runtime_suspend_host(chip); 1870 } 1871 1872 static int sdhci_pci_runtime_resume(struct device *dev) 1873 { 1874 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 1875 1876 if (!chip) 1877 return 0; 1878 1879 if (chip->fixes && chip->fixes->runtime_resume) 1880 return chip->fixes->runtime_resume(chip); 1881 1882 return sdhci_pci_runtime_resume_host(chip); 1883 } 1884 #endif 1885 1886 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1887 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1888 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1889 sdhci_pci_runtime_resume, NULL) 1890 }; 1891 1892 /*****************************************************************************\ 1893 * * 1894 * Device probing/removal * 1895 * * 1896 \*****************************************************************************/ 1897 1898 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1899 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1900 int slotno) 1901 { 1902 struct sdhci_pci_slot *slot; 1903 struct sdhci_host *host; 1904 int ret, bar = first_bar + slotno; 1905 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 1906 1907 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1908 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1909 return ERR_PTR(-ENODEV); 1910 } 1911 1912 if (pci_resource_len(pdev, bar) < 0x100) { 1913 dev_err(&pdev->dev, "Invalid iomem size. You may " 1914 "experience problems.\n"); 1915 } 1916 1917 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1918 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1919 return ERR_PTR(-ENODEV); 1920 } 1921 1922 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1923 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1924 return ERR_PTR(-ENODEV); 1925 } 1926 1927 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 1928 if (IS_ERR(host)) { 1929 dev_err(&pdev->dev, "cannot allocate host\n"); 1930 return ERR_CAST(host); 1931 } 1932 1933 slot = sdhci_priv(host); 1934 1935 slot->chip = chip; 1936 slot->host = host; 1937 slot->rst_n_gpio = -EINVAL; 1938 slot->cd_gpio = -EINVAL; 1939 slot->cd_idx = -1; 1940 1941 /* Retrieve platform data if there is any */ 1942 if (*sdhci_pci_get_data) 1943 slot->data = sdhci_pci_get_data(pdev, slotno); 1944 1945 if (slot->data) { 1946 if (slot->data->setup) { 1947 ret = slot->data->setup(slot->data); 1948 if (ret) { 1949 dev_err(&pdev->dev, "platform setup failed\n"); 1950 goto free; 1951 } 1952 } 1953 slot->rst_n_gpio = slot->data->rst_n_gpio; 1954 slot->cd_gpio = slot->data->cd_gpio; 1955 } 1956 1957 host->hw_name = "PCI"; 1958 host->ops = chip->fixes && chip->fixes->ops ? 1959 chip->fixes->ops : 1960 &sdhci_pci_ops; 1961 host->quirks = chip->quirks; 1962 host->quirks2 = chip->quirks2; 1963 1964 host->irq = pdev->irq; 1965 1966 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1967 if (ret) { 1968 dev_err(&pdev->dev, "cannot request region\n"); 1969 goto cleanup; 1970 } 1971 1972 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1973 1974 if (chip->fixes && chip->fixes->probe_slot) { 1975 ret = chip->fixes->probe_slot(slot); 1976 if (ret) 1977 goto cleanup; 1978 } 1979 1980 if (gpio_is_valid(slot->rst_n_gpio)) { 1981 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1982 gpio_direction_output(slot->rst_n_gpio, 1); 1983 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1984 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1985 } else { 1986 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1987 slot->rst_n_gpio = -EINVAL; 1988 } 1989 } 1990 1991 host->mmc->pm_caps = MMC_PM_KEEP_POWER; 1992 host->mmc->slotno = slotno; 1993 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1994 1995 if (device_can_wakeup(&pdev->dev)) 1996 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ; 1997 1998 if (host->mmc->caps & MMC_CAP_CD_WAKE) 1999 device_init_wakeup(&pdev->dev, true); 2000 2001 if (slot->cd_idx >= 0) { 2002 ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx, 2003 slot->cd_override_level, 0); 2004 if (ret && ret != -EPROBE_DEFER) 2005 ret = mmc_gpiod_request_cd(host->mmc, NULL, 2006 slot->cd_idx, 2007 slot->cd_override_level, 2008 0); 2009 if (ret == -EPROBE_DEFER) 2010 goto remove; 2011 2012 if (ret) { 2013 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 2014 slot->cd_idx = -1; 2015 } 2016 } 2017 2018 if (chip->fixes && chip->fixes->add_host) 2019 ret = chip->fixes->add_host(slot); 2020 else 2021 ret = sdhci_add_host(host); 2022 if (ret) 2023 goto remove; 2024 2025 sdhci_pci_add_own_cd(slot); 2026 2027 /* 2028 * Check if the chip needs a separate GPIO for card detect to wake up 2029 * from runtime suspend. If it is not there, don't allow runtime PM. 2030 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 2031 */ 2032 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 2033 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 2034 chip->allow_runtime_pm = false; 2035 2036 return slot; 2037 2038 remove: 2039 if (chip->fixes && chip->fixes->remove_slot) 2040 chip->fixes->remove_slot(slot, 0); 2041 2042 cleanup: 2043 if (slot->data && slot->data->cleanup) 2044 slot->data->cleanup(slot->data); 2045 2046 free: 2047 sdhci_free_host(host); 2048 2049 return ERR_PTR(ret); 2050 } 2051 2052 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 2053 { 2054 int dead; 2055 u32 scratch; 2056 2057 sdhci_pci_remove_own_cd(slot); 2058 2059 dead = 0; 2060 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 2061 if (scratch == (u32)-1) 2062 dead = 1; 2063 2064 sdhci_remove_host(slot->host, dead); 2065 2066 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 2067 slot->chip->fixes->remove_slot(slot, dead); 2068 2069 if (slot->data && slot->data->cleanup) 2070 slot->data->cleanup(slot->data); 2071 2072 sdhci_free_host(slot->host); 2073 } 2074 2075 static void sdhci_pci_runtime_pm_allow(struct device *dev) 2076 { 2077 pm_suspend_ignore_children(dev, 1); 2078 pm_runtime_set_autosuspend_delay(dev, 50); 2079 pm_runtime_use_autosuspend(dev); 2080 pm_runtime_allow(dev); 2081 /* Stay active until mmc core scans for a card */ 2082 pm_runtime_put_noidle(dev); 2083 } 2084 2085 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 2086 { 2087 pm_runtime_forbid(dev); 2088 pm_runtime_get_noresume(dev); 2089 } 2090 2091 static int sdhci_pci_probe(struct pci_dev *pdev, 2092 const struct pci_device_id *ent) 2093 { 2094 struct sdhci_pci_chip *chip; 2095 struct sdhci_pci_slot *slot; 2096 2097 u8 slots, first_bar; 2098 int ret, i; 2099 2100 BUG_ON(pdev == NULL); 2101 BUG_ON(ent == NULL); 2102 2103 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 2104 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 2105 2106 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 2107 if (ret) 2108 return ret; 2109 2110 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 2111 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 2112 2113 BUG_ON(slots > MAX_SLOTS); 2114 2115 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 2116 if (ret) 2117 return ret; 2118 2119 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 2120 2121 if (first_bar > 5) { 2122 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 2123 return -ENODEV; 2124 } 2125 2126 ret = pcim_enable_device(pdev); 2127 if (ret) 2128 return ret; 2129 2130 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 2131 if (!chip) 2132 return -ENOMEM; 2133 2134 chip->pdev = pdev; 2135 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 2136 if (chip->fixes) { 2137 chip->quirks = chip->fixes->quirks; 2138 chip->quirks2 = chip->fixes->quirks2; 2139 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 2140 } 2141 chip->num_slots = slots; 2142 chip->pm_retune = true; 2143 chip->rpm_retune = true; 2144 2145 pci_set_drvdata(pdev, chip); 2146 2147 if (chip->fixes && chip->fixes->probe) { 2148 ret = chip->fixes->probe(chip); 2149 if (ret) 2150 return ret; 2151 } 2152 2153 slots = chip->num_slots; /* Quirk may have changed this */ 2154 2155 for (i = 0; i < slots; i++) { 2156 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 2157 if (IS_ERR(slot)) { 2158 for (i--; i >= 0; i--) 2159 sdhci_pci_remove_slot(chip->slots[i]); 2160 return PTR_ERR(slot); 2161 } 2162 2163 chip->slots[i] = slot; 2164 } 2165 2166 if (chip->allow_runtime_pm) 2167 sdhci_pci_runtime_pm_allow(&pdev->dev); 2168 2169 return 0; 2170 } 2171 2172 static void sdhci_pci_remove(struct pci_dev *pdev) 2173 { 2174 int i; 2175 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 2176 2177 if (chip->allow_runtime_pm) 2178 sdhci_pci_runtime_pm_forbid(&pdev->dev); 2179 2180 for (i = 0; i < chip->num_slots; i++) 2181 sdhci_pci_remove_slot(chip->slots[i]); 2182 } 2183 2184 static struct pci_driver sdhci_driver = { 2185 .name = "sdhci-pci", 2186 .id_table = pci_ids, 2187 .probe = sdhci_pci_probe, 2188 .remove = sdhci_pci_remove, 2189 .driver = { 2190 .pm = &sdhci_pci_pm_ops 2191 }, 2192 }; 2193 2194 module_pci_driver(sdhci_driver); 2195 2196 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 2197 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 2198 MODULE_LICENSE("GPL"); 2199