1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 2 * 3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 * 10 * Thanks to the following companies for their support: 11 * 12 * - JMicron (hardware and technical support) 13 */ 14 15 #include <linux/string.h> 16 #include <linux/delay.h> 17 #include <linux/highmem.h> 18 #include <linux/module.h> 19 #include <linux/pci.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/slab.h> 22 #include <linux/device.h> 23 #include <linux/mmc/host.h> 24 #include <linux/mmc/mmc.h> 25 #include <linux/scatterlist.h> 26 #include <linux/io.h> 27 #include <linux/gpio.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/mmc/slot-gpio.h> 30 #include <linux/mmc/sdhci-pci-data.h> 31 #include <linux/acpi.h> 32 33 #include "cqhci.h" 34 35 #include "sdhci.h" 36 #include "sdhci-pci.h" 37 38 static void sdhci_pci_hw_reset(struct sdhci_host *host); 39 40 #ifdef CONFIG_PM_SLEEP 41 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip) 42 { 43 mmc_pm_flag_t pm_flags = 0; 44 bool cap_cd_wake = false; 45 int i; 46 47 for (i = 0; i < chip->num_slots; i++) { 48 struct sdhci_pci_slot *slot = chip->slots[i]; 49 50 if (slot) { 51 pm_flags |= slot->host->mmc->pm_flags; 52 if (slot->host->mmc->caps & MMC_CAP_CD_WAKE) 53 cap_cd_wake = true; 54 } 55 } 56 57 if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ)) 58 return device_wakeup_enable(&chip->pdev->dev); 59 else if (!cap_cd_wake) 60 return device_wakeup_disable(&chip->pdev->dev); 61 62 return 0; 63 } 64 65 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 66 { 67 int i, ret; 68 69 sdhci_pci_init_wakeup(chip); 70 71 for (i = 0; i < chip->num_slots; i++) { 72 struct sdhci_pci_slot *slot = chip->slots[i]; 73 struct sdhci_host *host; 74 75 if (!slot) 76 continue; 77 78 host = slot->host; 79 80 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 81 mmc_retune_needed(host->mmc); 82 83 ret = sdhci_suspend_host(host); 84 if (ret) 85 goto err_pci_suspend; 86 87 if (device_may_wakeup(&chip->pdev->dev)) 88 mmc_gpio_set_cd_wake(host->mmc, true); 89 } 90 91 return 0; 92 93 err_pci_suspend: 94 while (--i >= 0) 95 sdhci_resume_host(chip->slots[i]->host); 96 return ret; 97 } 98 99 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip) 100 { 101 struct sdhci_pci_slot *slot; 102 int i, ret; 103 104 for (i = 0; i < chip->num_slots; i++) { 105 slot = chip->slots[i]; 106 if (!slot) 107 continue; 108 109 ret = sdhci_resume_host(slot->host); 110 if (ret) 111 return ret; 112 113 mmc_gpio_set_cd_wake(slot->host->mmc, false); 114 } 115 116 return 0; 117 } 118 119 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip) 120 { 121 int ret; 122 123 ret = cqhci_suspend(chip->slots[0]->host->mmc); 124 if (ret) 125 return ret; 126 127 return sdhci_pci_suspend_host(chip); 128 } 129 130 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip) 131 { 132 int ret; 133 134 ret = sdhci_pci_resume_host(chip); 135 if (ret) 136 return ret; 137 138 return cqhci_resume(chip->slots[0]->host->mmc); 139 } 140 #endif 141 142 #ifdef CONFIG_PM 143 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip) 144 { 145 struct sdhci_pci_slot *slot; 146 struct sdhci_host *host; 147 int i, ret; 148 149 for (i = 0; i < chip->num_slots; i++) { 150 slot = chip->slots[i]; 151 if (!slot) 152 continue; 153 154 host = slot->host; 155 156 ret = sdhci_runtime_suspend_host(host); 157 if (ret) 158 goto err_pci_runtime_suspend; 159 160 if (chip->rpm_retune && 161 host->tuning_mode != SDHCI_TUNING_MODE_3) 162 mmc_retune_needed(host->mmc); 163 } 164 165 return 0; 166 167 err_pci_runtime_suspend: 168 while (--i >= 0) 169 sdhci_runtime_resume_host(chip->slots[i]->host); 170 return ret; 171 } 172 173 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip) 174 { 175 struct sdhci_pci_slot *slot; 176 int i, ret; 177 178 for (i = 0; i < chip->num_slots; i++) { 179 slot = chip->slots[i]; 180 if (!slot) 181 continue; 182 183 ret = sdhci_runtime_resume_host(slot->host); 184 if (ret) 185 return ret; 186 } 187 188 return 0; 189 } 190 191 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip) 192 { 193 int ret; 194 195 ret = cqhci_suspend(chip->slots[0]->host->mmc); 196 if (ret) 197 return ret; 198 199 return sdhci_pci_runtime_suspend_host(chip); 200 } 201 202 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip) 203 { 204 int ret; 205 206 ret = sdhci_pci_runtime_resume_host(chip); 207 if (ret) 208 return ret; 209 210 return cqhci_resume(chip->slots[0]->host->mmc); 211 } 212 #endif 213 214 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask) 215 { 216 int cmd_error = 0; 217 int data_error = 0; 218 219 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 220 return intmask; 221 222 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 223 224 return 0; 225 } 226 227 static void sdhci_pci_dumpregs(struct mmc_host *mmc) 228 { 229 sdhci_dumpregs(mmc_priv(mmc)); 230 } 231 232 /*****************************************************************************\ 233 * * 234 * Hardware specific quirk handling * 235 * * 236 \*****************************************************************************/ 237 238 static int ricoh_probe(struct sdhci_pci_chip *chip) 239 { 240 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 241 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 242 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 243 return 0; 244 } 245 246 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 247 { 248 slot->host->caps = 249 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 250 & SDHCI_TIMEOUT_CLK_MASK) | 251 252 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 253 & SDHCI_CLOCK_BASE_MASK) | 254 255 SDHCI_TIMEOUT_CLK_UNIT | 256 SDHCI_CAN_VDD_330 | 257 SDHCI_CAN_DO_HISPD | 258 SDHCI_CAN_DO_SDMA; 259 return 0; 260 } 261 262 #ifdef CONFIG_PM_SLEEP 263 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 264 { 265 /* Apply a delay to allow controller to settle */ 266 /* Otherwise it becomes confused if card state changed 267 during suspend */ 268 msleep(500); 269 return sdhci_pci_resume_host(chip); 270 } 271 #endif 272 273 static const struct sdhci_pci_fixes sdhci_ricoh = { 274 .probe = ricoh_probe, 275 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 276 SDHCI_QUIRK_FORCE_DMA | 277 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 278 }; 279 280 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 281 .probe_slot = ricoh_mmc_probe_slot, 282 #ifdef CONFIG_PM_SLEEP 283 .resume = ricoh_mmc_resume, 284 #endif 285 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 286 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 287 SDHCI_QUIRK_NO_CARD_NO_RESET | 288 SDHCI_QUIRK_MISSING_CAPS 289 }; 290 291 static const struct sdhci_pci_fixes sdhci_ene_712 = { 292 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 293 SDHCI_QUIRK_BROKEN_DMA, 294 }; 295 296 static const struct sdhci_pci_fixes sdhci_ene_714 = { 297 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 298 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 299 SDHCI_QUIRK_BROKEN_DMA, 300 }; 301 302 static const struct sdhci_pci_fixes sdhci_cafe = { 303 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 304 SDHCI_QUIRK_NO_BUSY_IRQ | 305 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 306 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 307 }; 308 309 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 310 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 311 }; 312 313 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 314 { 315 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 316 return 0; 317 } 318 319 /* 320 * ADMA operation is disabled for Moorestown platform due to 321 * hardware bugs. 322 */ 323 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 324 { 325 /* 326 * slots number is fixed here for MRST as SDIO3/5 are never used and 327 * have hardware bugs. 328 */ 329 chip->num_slots = 1; 330 return 0; 331 } 332 333 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 334 { 335 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 336 return 0; 337 } 338 339 #ifdef CONFIG_PM 340 341 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 342 { 343 struct sdhci_pci_slot *slot = dev_id; 344 struct sdhci_host *host = slot->host; 345 346 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 347 return IRQ_HANDLED; 348 } 349 350 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 351 { 352 int err, irq, gpio = slot->cd_gpio; 353 354 slot->cd_gpio = -EINVAL; 355 slot->cd_irq = -EINVAL; 356 357 if (!gpio_is_valid(gpio)) 358 return; 359 360 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 361 if (err < 0) 362 goto out; 363 364 err = gpio_direction_input(gpio); 365 if (err < 0) 366 goto out_free; 367 368 irq = gpio_to_irq(gpio); 369 if (irq < 0) 370 goto out_free; 371 372 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 373 IRQF_TRIGGER_FALLING, "sd_cd", slot); 374 if (err) 375 goto out_free; 376 377 slot->cd_gpio = gpio; 378 slot->cd_irq = irq; 379 380 return; 381 382 out_free: 383 devm_gpio_free(&slot->chip->pdev->dev, gpio); 384 out: 385 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 386 } 387 388 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 389 { 390 if (slot->cd_irq >= 0) 391 free_irq(slot->cd_irq, slot); 392 } 393 394 #else 395 396 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 397 { 398 } 399 400 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 401 { 402 } 403 404 #endif 405 406 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 407 { 408 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 409 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC; 410 return 0; 411 } 412 413 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 414 { 415 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 416 return 0; 417 } 418 419 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 420 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 421 .probe_slot = mrst_hc_probe_slot, 422 }; 423 424 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 425 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 426 .probe = mrst_hc_probe, 427 }; 428 429 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 430 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 431 .allow_runtime_pm = true, 432 .own_cd_for_runtime_pm = true, 433 }; 434 435 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 436 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 437 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 438 .allow_runtime_pm = true, 439 .probe_slot = mfd_sdio_probe_slot, 440 }; 441 442 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 443 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 444 .allow_runtime_pm = true, 445 .probe_slot = mfd_emmc_probe_slot, 446 }; 447 448 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 449 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 450 .probe_slot = pch_hc_probe_slot, 451 }; 452 453 enum { 454 INTEL_DSM_FNS = 0, 455 INTEL_DSM_V18_SWITCH = 3, 456 INTEL_DSM_DRV_STRENGTH = 9, 457 INTEL_DSM_D3_RETUNE = 10, 458 }; 459 460 struct intel_host { 461 u32 dsm_fns; 462 int drv_strength; 463 bool d3_retune; 464 }; 465 466 static const guid_t intel_dsm_guid = 467 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F, 468 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61); 469 470 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 471 unsigned int fn, u32 *result) 472 { 473 union acpi_object *obj; 474 int err = 0; 475 size_t len; 476 477 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL); 478 if (!obj) 479 return -EOPNOTSUPP; 480 481 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { 482 err = -EINVAL; 483 goto out; 484 } 485 486 len = min_t(size_t, obj->buffer.length, 4); 487 488 *result = 0; 489 memcpy(result, obj->buffer.pointer, len); 490 out: 491 ACPI_FREE(obj); 492 493 return err; 494 } 495 496 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 497 unsigned int fn, u32 *result) 498 { 499 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 500 return -EOPNOTSUPP; 501 502 return __intel_dsm(intel_host, dev, fn, result); 503 } 504 505 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 506 struct mmc_host *mmc) 507 { 508 int err; 509 u32 val; 510 511 intel_host->d3_retune = true; 512 513 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 514 if (err) { 515 pr_debug("%s: DSM not supported, error %d\n", 516 mmc_hostname(mmc), err); 517 return; 518 } 519 520 pr_debug("%s: DSM function mask %#x\n", 521 mmc_hostname(mmc), intel_host->dsm_fns); 522 523 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 524 intel_host->drv_strength = err ? 0 : val; 525 526 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 527 intel_host->d3_retune = err ? true : !!val; 528 } 529 530 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 531 { 532 u8 reg; 533 534 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 535 reg |= 0x10; 536 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 537 /* For eMMC, minimum is 1us but give it 9us for good measure */ 538 udelay(9); 539 reg &= ~0x10; 540 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 541 /* For eMMC, minimum is 200us but give it 300us for good measure */ 542 usleep_range(300, 1000); 543 } 544 545 static int intel_select_drive_strength(struct mmc_card *card, 546 unsigned int max_dtr, int host_drv, 547 int card_drv, int *drv_type) 548 { 549 struct sdhci_host *host = mmc_priv(card->host); 550 struct sdhci_pci_slot *slot = sdhci_priv(host); 551 struct intel_host *intel_host = sdhci_pci_priv(slot); 552 553 return intel_host->drv_strength; 554 } 555 556 static int bxt_get_cd(struct mmc_host *mmc) 557 { 558 int gpio_cd = mmc_gpio_get_cd(mmc); 559 struct sdhci_host *host = mmc_priv(mmc); 560 unsigned long flags; 561 int ret = 0; 562 563 if (!gpio_cd) 564 return 0; 565 566 spin_lock_irqsave(&host->lock, flags); 567 568 if (host->flags & SDHCI_DEVICE_DEAD) 569 goto out; 570 571 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 572 out: 573 spin_unlock_irqrestore(&host->lock, flags); 574 575 return ret; 576 } 577 578 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 579 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 580 581 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 582 unsigned short vdd) 583 { 584 int cntr; 585 u8 reg; 586 587 sdhci_set_power(host, mode, vdd); 588 589 if (mode == MMC_POWER_OFF) 590 return; 591 592 /* 593 * Bus power might not enable after D3 -> D0 transition due to the 594 * present state not yet having propagated. Retry for up to 2ms. 595 */ 596 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 597 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 598 if (reg & SDHCI_POWER_ON) 599 break; 600 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 601 reg |= SDHCI_POWER_ON; 602 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 603 } 604 } 605 606 #define INTEL_HS400_ES_REG 0x78 607 #define INTEL_HS400_ES_BIT BIT(0) 608 609 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc, 610 struct mmc_ios *ios) 611 { 612 struct sdhci_host *host = mmc_priv(mmc); 613 u32 val; 614 615 val = sdhci_readl(host, INTEL_HS400_ES_REG); 616 if (ios->enhanced_strobe) 617 val |= INTEL_HS400_ES_BIT; 618 else 619 val &= ~INTEL_HS400_ES_BIT; 620 sdhci_writel(host, val, INTEL_HS400_ES_REG); 621 } 622 623 static void sdhci_intel_voltage_switch(struct sdhci_host *host) 624 { 625 struct sdhci_pci_slot *slot = sdhci_priv(host); 626 struct intel_host *intel_host = sdhci_pci_priv(slot); 627 struct device *dev = &slot->chip->pdev->dev; 628 u32 result = 0; 629 int err; 630 631 err = intel_dsm(intel_host, dev, INTEL_DSM_V18_SWITCH, &result); 632 pr_debug("%s: %s DSM error %d result %u\n", 633 mmc_hostname(host->mmc), __func__, err, result); 634 } 635 636 static const struct sdhci_ops sdhci_intel_byt_ops = { 637 .set_clock = sdhci_set_clock, 638 .set_power = sdhci_intel_set_power, 639 .enable_dma = sdhci_pci_enable_dma, 640 .set_bus_width = sdhci_set_bus_width, 641 .reset = sdhci_reset, 642 .set_uhs_signaling = sdhci_set_uhs_signaling, 643 .hw_reset = sdhci_pci_hw_reset, 644 .voltage_switch = sdhci_intel_voltage_switch, 645 }; 646 647 static const struct sdhci_ops sdhci_intel_glk_ops = { 648 .set_clock = sdhci_set_clock, 649 .set_power = sdhci_intel_set_power, 650 .enable_dma = sdhci_pci_enable_dma, 651 .set_bus_width = sdhci_set_bus_width, 652 .reset = sdhci_reset, 653 .set_uhs_signaling = sdhci_set_uhs_signaling, 654 .hw_reset = sdhci_pci_hw_reset, 655 .voltage_switch = sdhci_intel_voltage_switch, 656 .irq = sdhci_cqhci_irq, 657 }; 658 659 static void byt_read_dsm(struct sdhci_pci_slot *slot) 660 { 661 struct intel_host *intel_host = sdhci_pci_priv(slot); 662 struct device *dev = &slot->chip->pdev->dev; 663 struct mmc_host *mmc = slot->host->mmc; 664 665 intel_dsm_init(intel_host, dev, mmc); 666 slot->chip->rpm_retune = intel_host->d3_retune; 667 } 668 669 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode) 670 { 671 int err = sdhci_execute_tuning(mmc, opcode); 672 struct sdhci_host *host = mmc_priv(mmc); 673 674 if (err) 675 return err; 676 677 /* 678 * Tuning can leave the IP in an active state (Buffer Read Enable bit 679 * set) which prevents the entry to low power states (i.e. S0i3). Data 680 * reset will clear it. 681 */ 682 sdhci_reset(host, SDHCI_RESET_DATA); 683 684 return 0; 685 } 686 687 static void byt_probe_slot(struct sdhci_pci_slot *slot) 688 { 689 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 690 691 byt_read_dsm(slot); 692 693 ops->execute_tuning = intel_execute_tuning; 694 } 695 696 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 697 { 698 byt_probe_slot(slot); 699 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 700 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 701 MMC_CAP_CMD_DURING_TFR | 702 MMC_CAP_WAIT_WHILE_BUSY; 703 slot->hw_reset = sdhci_pci_int_hw_reset; 704 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 705 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 706 slot->host->mmc_host_ops.select_drive_strength = 707 intel_select_drive_strength; 708 return 0; 709 } 710 711 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot) 712 { 713 int ret = byt_emmc_probe_slot(slot); 714 715 slot->host->mmc->caps2 |= MMC_CAP2_CQE; 716 717 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) { 718 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES, 719 slot->host->mmc_host_ops.hs400_enhanced_strobe = 720 intel_hs400_enhanced_strobe; 721 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; 722 } 723 724 return ret; 725 } 726 727 static const struct cqhci_host_ops glk_cqhci_ops = { 728 .enable = sdhci_cqe_enable, 729 .disable = sdhci_cqe_disable, 730 .dumpregs = sdhci_pci_dumpregs, 731 }; 732 733 static int glk_emmc_add_host(struct sdhci_pci_slot *slot) 734 { 735 struct device *dev = &slot->chip->pdev->dev; 736 struct sdhci_host *host = slot->host; 737 struct cqhci_host *cq_host; 738 bool dma64; 739 int ret; 740 741 ret = sdhci_setup_host(host); 742 if (ret) 743 return ret; 744 745 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); 746 if (!cq_host) { 747 ret = -ENOMEM; 748 goto cleanup; 749 } 750 751 cq_host->mmio = host->ioaddr + 0x200; 752 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 753 cq_host->ops = &glk_cqhci_ops; 754 755 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 756 if (dma64) 757 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 758 759 ret = cqhci_init(cq_host, host->mmc, dma64); 760 if (ret) 761 goto cleanup; 762 763 ret = __sdhci_add_host(host); 764 if (ret) 765 goto cleanup; 766 767 return 0; 768 769 cleanup: 770 sdhci_cleanup_host(host); 771 return ret; 772 } 773 774 #ifdef CONFIG_ACPI 775 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 776 { 777 acpi_status status; 778 unsigned long long max_freq; 779 780 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 781 "MXFQ", NULL, &max_freq); 782 if (ACPI_FAILURE(status)) { 783 dev_err(&slot->chip->pdev->dev, 784 "MXFQ not found in acpi table\n"); 785 return -EINVAL; 786 } 787 788 slot->host->mmc->f_max = max_freq * 1000000; 789 790 return 0; 791 } 792 #else 793 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 794 { 795 return 0; 796 } 797 #endif 798 799 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 800 { 801 int err; 802 803 byt_probe_slot(slot); 804 805 err = ni_set_max_freq(slot); 806 if (err) 807 return err; 808 809 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 810 MMC_CAP_WAIT_WHILE_BUSY; 811 return 0; 812 } 813 814 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 815 { 816 byt_probe_slot(slot); 817 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 818 MMC_CAP_WAIT_WHILE_BUSY; 819 return 0; 820 } 821 822 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 823 { 824 byt_probe_slot(slot); 825 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | 826 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE; 827 slot->cd_idx = 0; 828 slot->cd_override_level = true; 829 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 830 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 831 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 832 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) 833 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 834 835 return 0; 836 } 837 838 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 839 .allow_runtime_pm = true, 840 .probe_slot = byt_emmc_probe_slot, 841 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 842 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 843 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 844 SDHCI_QUIRK2_STOP_WITH_TC, 845 .ops = &sdhci_intel_byt_ops, 846 .priv_size = sizeof(struct intel_host), 847 }; 848 849 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = { 850 .allow_runtime_pm = true, 851 .probe_slot = glk_emmc_probe_slot, 852 .add_host = glk_emmc_add_host, 853 #ifdef CONFIG_PM_SLEEP 854 .suspend = sdhci_cqhci_suspend, 855 .resume = sdhci_cqhci_resume, 856 #endif 857 #ifdef CONFIG_PM 858 .runtime_suspend = sdhci_cqhci_runtime_suspend, 859 .runtime_resume = sdhci_cqhci_runtime_resume, 860 #endif 861 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 862 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 863 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 864 SDHCI_QUIRK2_STOP_WITH_TC, 865 .ops = &sdhci_intel_glk_ops, 866 .priv_size = sizeof(struct intel_host), 867 }; 868 869 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 870 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 871 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 872 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 873 .allow_runtime_pm = true, 874 .probe_slot = ni_byt_sdio_probe_slot, 875 .ops = &sdhci_intel_byt_ops, 876 .priv_size = sizeof(struct intel_host), 877 }; 878 879 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 880 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 881 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 882 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 883 .allow_runtime_pm = true, 884 .probe_slot = byt_sdio_probe_slot, 885 .ops = &sdhci_intel_byt_ops, 886 .priv_size = sizeof(struct intel_host), 887 }; 888 889 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 890 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 891 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 892 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 893 SDHCI_QUIRK2_STOP_WITH_TC, 894 .allow_runtime_pm = true, 895 .own_cd_for_runtime_pm = true, 896 .probe_slot = byt_sd_probe_slot, 897 .ops = &sdhci_intel_byt_ops, 898 .priv_size = sizeof(struct intel_host), 899 }; 900 901 /* Define Host controllers for Intel Merrifield platform */ 902 #define INTEL_MRFLD_EMMC_0 0 903 #define INTEL_MRFLD_EMMC_1 1 904 #define INTEL_MRFLD_SD 2 905 #define INTEL_MRFLD_SDIO 3 906 907 #ifdef CONFIG_ACPI 908 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) 909 { 910 struct acpi_device *device, *child; 911 912 device = ACPI_COMPANION(&slot->chip->pdev->dev); 913 if (!device) 914 return; 915 916 acpi_device_fix_up_power(device); 917 list_for_each_entry(child, &device->children, node) 918 if (child->status.present && child->status.enabled) 919 acpi_device_fix_up_power(child); 920 } 921 #else 922 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {} 923 #endif 924 925 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 926 { 927 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 928 929 switch (func) { 930 case INTEL_MRFLD_EMMC_0: 931 case INTEL_MRFLD_EMMC_1: 932 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 933 MMC_CAP_8_BIT_DATA | 934 MMC_CAP_1_8V_DDR; 935 break; 936 case INTEL_MRFLD_SD: 937 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 938 break; 939 case INTEL_MRFLD_SDIO: 940 /* Advertise 2.0v for compatibility with the SDIO card's OCR */ 941 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195; 942 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 943 MMC_CAP_POWER_OFF_CARD; 944 break; 945 default: 946 return -ENODEV; 947 } 948 949 intel_mrfld_mmc_fix_up_power_slot(slot); 950 return 0; 951 } 952 953 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 954 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 955 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 956 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 957 .allow_runtime_pm = true, 958 .probe_slot = intel_mrfld_mmc_probe_slot, 959 }; 960 961 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 962 { 963 u8 scratch; 964 int ret; 965 966 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 967 if (ret) 968 return ret; 969 970 /* 971 * Turn PMOS on [bit 0], set over current detection to 2.4 V 972 * [bit 1:2] and enable over current debouncing [bit 6]. 973 */ 974 if (on) 975 scratch |= 0x47; 976 else 977 scratch &= ~0x47; 978 979 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 980 } 981 982 static int jmicron_probe(struct sdhci_pci_chip *chip) 983 { 984 int ret; 985 u16 mmcdev = 0; 986 987 if (chip->pdev->revision == 0) { 988 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 989 SDHCI_QUIRK_32BIT_DMA_SIZE | 990 SDHCI_QUIRK_32BIT_ADMA_SIZE | 991 SDHCI_QUIRK_RESET_AFTER_REQUEST | 992 SDHCI_QUIRK_BROKEN_SMALL_PIO; 993 } 994 995 /* 996 * JMicron chips can have two interfaces to the same hardware 997 * in order to work around limitations in Microsoft's driver. 998 * We need to make sure we only bind to one of them. 999 * 1000 * This code assumes two things: 1001 * 1002 * 1. The PCI code adds subfunctions in order. 1003 * 1004 * 2. The MMC interface has a lower subfunction number 1005 * than the SD interface. 1006 */ 1007 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 1008 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 1009 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 1010 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 1011 1012 if (mmcdev) { 1013 struct pci_dev *sd_dev; 1014 1015 sd_dev = NULL; 1016 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 1017 mmcdev, sd_dev)) != NULL) { 1018 if ((PCI_SLOT(chip->pdev->devfn) == 1019 PCI_SLOT(sd_dev->devfn)) && 1020 (chip->pdev->bus == sd_dev->bus)) 1021 break; 1022 } 1023 1024 if (sd_dev) { 1025 pci_dev_put(sd_dev); 1026 dev_info(&chip->pdev->dev, "Refusing to bind to " 1027 "secondary interface.\n"); 1028 return -ENODEV; 1029 } 1030 } 1031 1032 /* 1033 * JMicron chips need a bit of a nudge to enable the power 1034 * output pins. 1035 */ 1036 ret = jmicron_pmos(chip, 1); 1037 if (ret) { 1038 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1039 return ret; 1040 } 1041 1042 /* quirk for unsable RO-detection on JM388 chips */ 1043 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 1044 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1045 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 1046 1047 return 0; 1048 } 1049 1050 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 1051 { 1052 u8 scratch; 1053 1054 scratch = readb(host->ioaddr + 0xC0); 1055 1056 if (on) 1057 scratch |= 0x01; 1058 else 1059 scratch &= ~0x01; 1060 1061 writeb(scratch, host->ioaddr + 0xC0); 1062 } 1063 1064 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 1065 { 1066 if (slot->chip->pdev->revision == 0) { 1067 u16 version; 1068 1069 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 1070 version = (version & SDHCI_VENDOR_VER_MASK) >> 1071 SDHCI_VENDOR_VER_SHIFT; 1072 1073 /* 1074 * Older versions of the chip have lots of nasty glitches 1075 * in the ADMA engine. It's best just to avoid it 1076 * completely. 1077 */ 1078 if (version < 0xAC) 1079 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 1080 } 1081 1082 /* JM388 MMC doesn't support 1.8V while SD supports it */ 1083 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1084 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 1085 MMC_VDD_29_30 | MMC_VDD_30_31 | 1086 MMC_VDD_165_195; /* allow 1.8V */ 1087 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 1088 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 1089 } 1090 1091 /* 1092 * The secondary interface requires a bit set to get the 1093 * interrupts. 1094 */ 1095 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1096 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1097 jmicron_enable_mmc(slot->host, 1); 1098 1099 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 1100 1101 return 0; 1102 } 1103 1104 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 1105 { 1106 if (dead) 1107 return; 1108 1109 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1110 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1111 jmicron_enable_mmc(slot->host, 0); 1112 } 1113 1114 #ifdef CONFIG_PM_SLEEP 1115 static int jmicron_suspend(struct sdhci_pci_chip *chip) 1116 { 1117 int i, ret; 1118 1119 ret = sdhci_pci_suspend_host(chip); 1120 if (ret) 1121 return ret; 1122 1123 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1124 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1125 for (i = 0; i < chip->num_slots; i++) 1126 jmicron_enable_mmc(chip->slots[i]->host, 0); 1127 } 1128 1129 return 0; 1130 } 1131 1132 static int jmicron_resume(struct sdhci_pci_chip *chip) 1133 { 1134 int ret, i; 1135 1136 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1137 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1138 for (i = 0; i < chip->num_slots; i++) 1139 jmicron_enable_mmc(chip->slots[i]->host, 1); 1140 } 1141 1142 ret = jmicron_pmos(chip, 1); 1143 if (ret) { 1144 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1145 return ret; 1146 } 1147 1148 return sdhci_pci_resume_host(chip); 1149 } 1150 #endif 1151 1152 static const struct sdhci_pci_fixes sdhci_o2 = { 1153 .probe = sdhci_pci_o2_probe, 1154 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1155 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 1156 .probe_slot = sdhci_pci_o2_probe_slot, 1157 #ifdef CONFIG_PM_SLEEP 1158 .resume = sdhci_pci_o2_resume, 1159 #endif 1160 }; 1161 1162 static const struct sdhci_pci_fixes sdhci_jmicron = { 1163 .probe = jmicron_probe, 1164 1165 .probe_slot = jmicron_probe_slot, 1166 .remove_slot = jmicron_remove_slot, 1167 1168 #ifdef CONFIG_PM_SLEEP 1169 .suspend = jmicron_suspend, 1170 .resume = jmicron_resume, 1171 #endif 1172 }; 1173 1174 /* SysKonnect CardBus2SDIO extra registers */ 1175 #define SYSKT_CTRL 0x200 1176 #define SYSKT_RDFIFO_STAT 0x204 1177 #define SYSKT_WRFIFO_STAT 0x208 1178 #define SYSKT_POWER_DATA 0x20c 1179 #define SYSKT_POWER_330 0xef 1180 #define SYSKT_POWER_300 0xf8 1181 #define SYSKT_POWER_184 0xcc 1182 #define SYSKT_POWER_CMD 0x20d 1183 #define SYSKT_POWER_START (1 << 7) 1184 #define SYSKT_POWER_STATUS 0x20e 1185 #define SYSKT_POWER_STATUS_OK (1 << 0) 1186 #define SYSKT_BOARD_REV 0x210 1187 #define SYSKT_CHIP_REV 0x211 1188 #define SYSKT_CONF_DATA 0x212 1189 #define SYSKT_CONF_DATA_1V8 (1 << 2) 1190 #define SYSKT_CONF_DATA_2V5 (1 << 1) 1191 #define SYSKT_CONF_DATA_3V3 (1 << 0) 1192 1193 static int syskt_probe(struct sdhci_pci_chip *chip) 1194 { 1195 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1196 chip->pdev->class &= ~0x0000FF; 1197 chip->pdev->class |= PCI_SDHCI_IFDMA; 1198 } 1199 return 0; 1200 } 1201 1202 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 1203 { 1204 int tm, ps; 1205 1206 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 1207 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 1208 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 1209 "board rev %d.%d, chip rev %d.%d\n", 1210 board_rev >> 4, board_rev & 0xf, 1211 chip_rev >> 4, chip_rev & 0xf); 1212 if (chip_rev >= 0x20) 1213 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 1214 1215 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 1216 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 1217 udelay(50); 1218 tm = 10; /* Wait max 1 ms */ 1219 do { 1220 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 1221 if (ps & SYSKT_POWER_STATUS_OK) 1222 break; 1223 udelay(100); 1224 } while (--tm); 1225 if (!tm) { 1226 dev_err(&slot->chip->pdev->dev, 1227 "power regulator never stabilized"); 1228 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 1229 return -ENODEV; 1230 } 1231 1232 return 0; 1233 } 1234 1235 static const struct sdhci_pci_fixes sdhci_syskt = { 1236 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 1237 .probe = syskt_probe, 1238 .probe_slot = syskt_probe_slot, 1239 }; 1240 1241 static int via_probe(struct sdhci_pci_chip *chip) 1242 { 1243 if (chip->pdev->revision == 0x10) 1244 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 1245 1246 return 0; 1247 } 1248 1249 static const struct sdhci_pci_fixes sdhci_via = { 1250 .probe = via_probe, 1251 }; 1252 1253 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 1254 { 1255 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 1256 return 0; 1257 } 1258 1259 static const struct sdhci_pci_fixes sdhci_rtsx = { 1260 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1261 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 1262 SDHCI_QUIRK2_BROKEN_DDR50, 1263 .probe_slot = rtsx_probe_slot, 1264 }; 1265 1266 /*AMD chipset generation*/ 1267 enum amd_chipset_gen { 1268 AMD_CHIPSET_BEFORE_ML, 1269 AMD_CHIPSET_CZ, 1270 AMD_CHIPSET_NL, 1271 AMD_CHIPSET_UNKNOWN, 1272 }; 1273 1274 /* AMD registers */ 1275 #define AMD_SD_AUTO_PATTERN 0xB8 1276 #define AMD_MSLEEP_DURATION 4 1277 #define AMD_SD_MISC_CONTROL 0xD0 1278 #define AMD_MAX_TUNE_VALUE 0x0B 1279 #define AMD_AUTO_TUNE_SEL 0x10800 1280 #define AMD_FIFO_PTR 0x30 1281 #define AMD_BIT_MASK 0x1F 1282 1283 static void amd_tuning_reset(struct sdhci_host *host) 1284 { 1285 unsigned int val; 1286 1287 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1288 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 1289 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1290 1291 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1292 val &= ~SDHCI_CTRL_EXEC_TUNING; 1293 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1294 } 1295 1296 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 1297 { 1298 unsigned int val; 1299 1300 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 1301 val &= ~AMD_BIT_MASK; 1302 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 1303 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 1304 } 1305 1306 static void amd_enable_manual_tuning(struct pci_dev *pdev) 1307 { 1308 unsigned int val; 1309 1310 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 1311 val |= AMD_FIFO_PTR; 1312 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 1313 } 1314 1315 static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode) 1316 { 1317 struct sdhci_pci_slot *slot = sdhci_priv(host); 1318 struct pci_dev *pdev = slot->chip->pdev; 1319 u8 valid_win = 0; 1320 u8 valid_win_max = 0; 1321 u8 valid_win_end = 0; 1322 u8 ctrl, tune_around; 1323 1324 amd_tuning_reset(host); 1325 1326 for (tune_around = 0; tune_around < 12; tune_around++) { 1327 amd_config_tuning_phase(pdev, tune_around); 1328 1329 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1330 valid_win = 0; 1331 msleep(AMD_MSLEEP_DURATION); 1332 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 1333 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 1334 } else if (++valid_win > valid_win_max) { 1335 valid_win_max = valid_win; 1336 valid_win_end = tune_around; 1337 } 1338 } 1339 1340 if (!valid_win_max) { 1341 dev_err(&pdev->dev, "no tuning point found\n"); 1342 return -EIO; 1343 } 1344 1345 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 1346 1347 amd_enable_manual_tuning(pdev); 1348 1349 host->mmc->retune_period = 0; 1350 1351 return 0; 1352 } 1353 1354 static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode) 1355 { 1356 struct sdhci_host *host = mmc_priv(mmc); 1357 1358 /* AMD requires custom HS200 tuning */ 1359 if (host->timing == MMC_TIMING_MMC_HS200) 1360 return amd_execute_tuning_hs200(host, opcode); 1361 1362 /* Otherwise perform standard SDHCI tuning */ 1363 return sdhci_execute_tuning(mmc, opcode); 1364 } 1365 1366 static int amd_probe_slot(struct sdhci_pci_slot *slot) 1367 { 1368 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 1369 1370 ops->execute_tuning = amd_execute_tuning; 1371 1372 return 0; 1373 } 1374 1375 static int amd_probe(struct sdhci_pci_chip *chip) 1376 { 1377 struct pci_dev *smbus_dev; 1378 enum amd_chipset_gen gen; 1379 1380 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1381 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 1382 if (smbus_dev) { 1383 gen = AMD_CHIPSET_BEFORE_ML; 1384 } else { 1385 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1386 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1387 if (smbus_dev) { 1388 if (smbus_dev->revision < 0x51) 1389 gen = AMD_CHIPSET_CZ; 1390 else 1391 gen = AMD_CHIPSET_NL; 1392 } else { 1393 gen = AMD_CHIPSET_UNKNOWN; 1394 } 1395 } 1396 1397 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1398 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1399 1400 return 0; 1401 } 1402 1403 static const struct sdhci_ops amd_sdhci_pci_ops = { 1404 .set_clock = sdhci_set_clock, 1405 .enable_dma = sdhci_pci_enable_dma, 1406 .set_bus_width = sdhci_set_bus_width, 1407 .reset = sdhci_reset, 1408 .set_uhs_signaling = sdhci_set_uhs_signaling, 1409 }; 1410 1411 static const struct sdhci_pci_fixes sdhci_amd = { 1412 .probe = amd_probe, 1413 .ops = &amd_sdhci_pci_ops, 1414 .probe_slot = amd_probe_slot, 1415 }; 1416 1417 static const struct pci_device_id pci_ids[] = { 1418 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh), 1419 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc), 1420 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc), 1421 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc), 1422 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712), 1423 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712), 1424 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714), 1425 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714), 1426 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe), 1427 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron), 1428 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron), 1429 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron), 1430 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron), 1431 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt), 1432 SDHCI_PCI_DEVICE(VIA, 95D0, via), 1433 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx), 1434 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk), 1435 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0), 1436 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2), 1437 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2), 1438 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd), 1439 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio), 1440 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio), 1441 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc), 1442 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc), 1443 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio), 1444 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio), 1445 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc), 1446 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio), 1447 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio), 1448 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd), 1449 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc), 1450 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc), 1451 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio), 1452 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd), 1453 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd), 1454 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio), 1455 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio), 1456 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc), 1457 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc), 1458 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc), 1459 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc), 1460 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio), 1461 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd), 1462 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc), 1463 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc), 1464 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc), 1465 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio), 1466 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd), 1467 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc), 1468 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio), 1469 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd), 1470 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc), 1471 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio), 1472 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd), 1473 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc), 1474 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio), 1475 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd), 1476 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc), 1477 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd), 1478 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd), 1479 SDHCI_PCI_DEVICE(O2, 8120, o2), 1480 SDHCI_PCI_DEVICE(O2, 8220, o2), 1481 SDHCI_PCI_DEVICE(O2, 8221, o2), 1482 SDHCI_PCI_DEVICE(O2, 8320, o2), 1483 SDHCI_PCI_DEVICE(O2, 8321, o2), 1484 SDHCI_PCI_DEVICE(O2, FUJIN2, o2), 1485 SDHCI_PCI_DEVICE(O2, SDS0, o2), 1486 SDHCI_PCI_DEVICE(O2, SDS1, o2), 1487 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2), 1488 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), 1489 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan), 1490 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), 1491 /* Generic SD host controller */ 1492 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, 1493 { /* end: all zeroes */ }, 1494 }; 1495 1496 MODULE_DEVICE_TABLE(pci, pci_ids); 1497 1498 /*****************************************************************************\ 1499 * * 1500 * SDHCI core callbacks * 1501 * * 1502 \*****************************************************************************/ 1503 1504 int sdhci_pci_enable_dma(struct sdhci_host *host) 1505 { 1506 struct sdhci_pci_slot *slot; 1507 struct pci_dev *pdev; 1508 1509 slot = sdhci_priv(host); 1510 pdev = slot->chip->pdev; 1511 1512 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1513 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1514 (host->flags & SDHCI_USE_SDMA)) { 1515 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1516 "doesn't fully claim to support it.\n"); 1517 } 1518 1519 pci_set_master(pdev); 1520 1521 return 0; 1522 } 1523 1524 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1525 { 1526 struct sdhci_pci_slot *slot = sdhci_priv(host); 1527 int rst_n_gpio = slot->rst_n_gpio; 1528 1529 if (!gpio_is_valid(rst_n_gpio)) 1530 return; 1531 gpio_set_value_cansleep(rst_n_gpio, 0); 1532 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1533 udelay(10); 1534 gpio_set_value_cansleep(rst_n_gpio, 1); 1535 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1536 usleep_range(300, 1000); 1537 } 1538 1539 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1540 { 1541 struct sdhci_pci_slot *slot = sdhci_priv(host); 1542 1543 if (slot->hw_reset) 1544 slot->hw_reset(host); 1545 } 1546 1547 static const struct sdhci_ops sdhci_pci_ops = { 1548 .set_clock = sdhci_set_clock, 1549 .enable_dma = sdhci_pci_enable_dma, 1550 .set_bus_width = sdhci_set_bus_width, 1551 .reset = sdhci_reset, 1552 .set_uhs_signaling = sdhci_set_uhs_signaling, 1553 .hw_reset = sdhci_pci_hw_reset, 1554 }; 1555 1556 /*****************************************************************************\ 1557 * * 1558 * Suspend/resume * 1559 * * 1560 \*****************************************************************************/ 1561 1562 #ifdef CONFIG_PM_SLEEP 1563 static int sdhci_pci_suspend(struct device *dev) 1564 { 1565 struct pci_dev *pdev = to_pci_dev(dev); 1566 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1567 1568 if (!chip) 1569 return 0; 1570 1571 if (chip->fixes && chip->fixes->suspend) 1572 return chip->fixes->suspend(chip); 1573 1574 return sdhci_pci_suspend_host(chip); 1575 } 1576 1577 static int sdhci_pci_resume(struct device *dev) 1578 { 1579 struct pci_dev *pdev = to_pci_dev(dev); 1580 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1581 1582 if (!chip) 1583 return 0; 1584 1585 if (chip->fixes && chip->fixes->resume) 1586 return chip->fixes->resume(chip); 1587 1588 return sdhci_pci_resume_host(chip); 1589 } 1590 #endif 1591 1592 #ifdef CONFIG_PM 1593 static int sdhci_pci_runtime_suspend(struct device *dev) 1594 { 1595 struct pci_dev *pdev = to_pci_dev(dev); 1596 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1597 1598 if (!chip) 1599 return 0; 1600 1601 if (chip->fixes && chip->fixes->runtime_suspend) 1602 return chip->fixes->runtime_suspend(chip); 1603 1604 return sdhci_pci_runtime_suspend_host(chip); 1605 } 1606 1607 static int sdhci_pci_runtime_resume(struct device *dev) 1608 { 1609 struct pci_dev *pdev = to_pci_dev(dev); 1610 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1611 1612 if (!chip) 1613 return 0; 1614 1615 if (chip->fixes && chip->fixes->runtime_resume) 1616 return chip->fixes->runtime_resume(chip); 1617 1618 return sdhci_pci_runtime_resume_host(chip); 1619 } 1620 #endif 1621 1622 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1623 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1624 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1625 sdhci_pci_runtime_resume, NULL) 1626 }; 1627 1628 /*****************************************************************************\ 1629 * * 1630 * Device probing/removal * 1631 * * 1632 \*****************************************************************************/ 1633 1634 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1635 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1636 int slotno) 1637 { 1638 struct sdhci_pci_slot *slot; 1639 struct sdhci_host *host; 1640 int ret, bar = first_bar + slotno; 1641 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 1642 1643 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1644 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1645 return ERR_PTR(-ENODEV); 1646 } 1647 1648 if (pci_resource_len(pdev, bar) < 0x100) { 1649 dev_err(&pdev->dev, "Invalid iomem size. You may " 1650 "experience problems.\n"); 1651 } 1652 1653 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1654 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1655 return ERR_PTR(-ENODEV); 1656 } 1657 1658 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1659 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1660 return ERR_PTR(-ENODEV); 1661 } 1662 1663 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 1664 if (IS_ERR(host)) { 1665 dev_err(&pdev->dev, "cannot allocate host\n"); 1666 return ERR_CAST(host); 1667 } 1668 1669 slot = sdhci_priv(host); 1670 1671 slot->chip = chip; 1672 slot->host = host; 1673 slot->rst_n_gpio = -EINVAL; 1674 slot->cd_gpio = -EINVAL; 1675 slot->cd_idx = -1; 1676 1677 /* Retrieve platform data if there is any */ 1678 if (*sdhci_pci_get_data) 1679 slot->data = sdhci_pci_get_data(pdev, slotno); 1680 1681 if (slot->data) { 1682 if (slot->data->setup) { 1683 ret = slot->data->setup(slot->data); 1684 if (ret) { 1685 dev_err(&pdev->dev, "platform setup failed\n"); 1686 goto free; 1687 } 1688 } 1689 slot->rst_n_gpio = slot->data->rst_n_gpio; 1690 slot->cd_gpio = slot->data->cd_gpio; 1691 } 1692 1693 host->hw_name = "PCI"; 1694 host->ops = chip->fixes && chip->fixes->ops ? 1695 chip->fixes->ops : 1696 &sdhci_pci_ops; 1697 host->quirks = chip->quirks; 1698 host->quirks2 = chip->quirks2; 1699 1700 host->irq = pdev->irq; 1701 1702 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1703 if (ret) { 1704 dev_err(&pdev->dev, "cannot request region\n"); 1705 goto cleanup; 1706 } 1707 1708 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1709 1710 if (chip->fixes && chip->fixes->probe_slot) { 1711 ret = chip->fixes->probe_slot(slot); 1712 if (ret) 1713 goto cleanup; 1714 } 1715 1716 if (gpio_is_valid(slot->rst_n_gpio)) { 1717 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1718 gpio_direction_output(slot->rst_n_gpio, 1); 1719 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1720 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1721 } else { 1722 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1723 slot->rst_n_gpio = -EINVAL; 1724 } 1725 } 1726 1727 host->mmc->pm_caps = MMC_PM_KEEP_POWER; 1728 host->mmc->slotno = slotno; 1729 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1730 1731 if (device_can_wakeup(&pdev->dev)) 1732 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ; 1733 1734 if (host->mmc->caps & MMC_CAP_CD_WAKE) 1735 device_init_wakeup(&pdev->dev, true); 1736 1737 if (slot->cd_idx >= 0) { 1738 ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx, 1739 slot->cd_override_level, 0, NULL); 1740 if (ret == -EPROBE_DEFER) 1741 goto remove; 1742 1743 if (ret) { 1744 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 1745 slot->cd_idx = -1; 1746 } 1747 } 1748 1749 if (chip->fixes && chip->fixes->add_host) 1750 ret = chip->fixes->add_host(slot); 1751 else 1752 ret = sdhci_add_host(host); 1753 if (ret) 1754 goto remove; 1755 1756 sdhci_pci_add_own_cd(slot); 1757 1758 /* 1759 * Check if the chip needs a separate GPIO for card detect to wake up 1760 * from runtime suspend. If it is not there, don't allow runtime PM. 1761 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 1762 */ 1763 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 1764 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 1765 chip->allow_runtime_pm = false; 1766 1767 return slot; 1768 1769 remove: 1770 if (chip->fixes && chip->fixes->remove_slot) 1771 chip->fixes->remove_slot(slot, 0); 1772 1773 cleanup: 1774 if (slot->data && slot->data->cleanup) 1775 slot->data->cleanup(slot->data); 1776 1777 free: 1778 sdhci_free_host(host); 1779 1780 return ERR_PTR(ret); 1781 } 1782 1783 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 1784 { 1785 int dead; 1786 u32 scratch; 1787 1788 sdhci_pci_remove_own_cd(slot); 1789 1790 dead = 0; 1791 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 1792 if (scratch == (u32)-1) 1793 dead = 1; 1794 1795 sdhci_remove_host(slot->host, dead); 1796 1797 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 1798 slot->chip->fixes->remove_slot(slot, dead); 1799 1800 if (slot->data && slot->data->cleanup) 1801 slot->data->cleanup(slot->data); 1802 1803 sdhci_free_host(slot->host); 1804 } 1805 1806 static void sdhci_pci_runtime_pm_allow(struct device *dev) 1807 { 1808 pm_suspend_ignore_children(dev, 1); 1809 pm_runtime_set_autosuspend_delay(dev, 50); 1810 pm_runtime_use_autosuspend(dev); 1811 pm_runtime_allow(dev); 1812 /* Stay active until mmc core scans for a card */ 1813 pm_runtime_put_noidle(dev); 1814 } 1815 1816 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 1817 { 1818 pm_runtime_forbid(dev); 1819 pm_runtime_get_noresume(dev); 1820 } 1821 1822 static int sdhci_pci_probe(struct pci_dev *pdev, 1823 const struct pci_device_id *ent) 1824 { 1825 struct sdhci_pci_chip *chip; 1826 struct sdhci_pci_slot *slot; 1827 1828 u8 slots, first_bar; 1829 int ret, i; 1830 1831 BUG_ON(pdev == NULL); 1832 BUG_ON(ent == NULL); 1833 1834 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 1835 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 1836 1837 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 1838 if (ret) 1839 return ret; 1840 1841 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 1842 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 1843 if (slots == 0) 1844 return -ENODEV; 1845 1846 BUG_ON(slots > MAX_SLOTS); 1847 1848 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 1849 if (ret) 1850 return ret; 1851 1852 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 1853 1854 if (first_bar > 5) { 1855 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 1856 return -ENODEV; 1857 } 1858 1859 ret = pcim_enable_device(pdev); 1860 if (ret) 1861 return ret; 1862 1863 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 1864 if (!chip) 1865 return -ENOMEM; 1866 1867 chip->pdev = pdev; 1868 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 1869 if (chip->fixes) { 1870 chip->quirks = chip->fixes->quirks; 1871 chip->quirks2 = chip->fixes->quirks2; 1872 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 1873 } 1874 chip->num_slots = slots; 1875 chip->pm_retune = true; 1876 chip->rpm_retune = true; 1877 1878 pci_set_drvdata(pdev, chip); 1879 1880 if (chip->fixes && chip->fixes->probe) { 1881 ret = chip->fixes->probe(chip); 1882 if (ret) 1883 return ret; 1884 } 1885 1886 slots = chip->num_slots; /* Quirk may have changed this */ 1887 1888 for (i = 0; i < slots; i++) { 1889 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 1890 if (IS_ERR(slot)) { 1891 for (i--; i >= 0; i--) 1892 sdhci_pci_remove_slot(chip->slots[i]); 1893 return PTR_ERR(slot); 1894 } 1895 1896 chip->slots[i] = slot; 1897 } 1898 1899 if (chip->allow_runtime_pm) 1900 sdhci_pci_runtime_pm_allow(&pdev->dev); 1901 1902 return 0; 1903 } 1904 1905 static void sdhci_pci_remove(struct pci_dev *pdev) 1906 { 1907 int i; 1908 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1909 1910 if (chip->allow_runtime_pm) 1911 sdhci_pci_runtime_pm_forbid(&pdev->dev); 1912 1913 for (i = 0; i < chip->num_slots; i++) 1914 sdhci_pci_remove_slot(chip->slots[i]); 1915 } 1916 1917 static struct pci_driver sdhci_driver = { 1918 .name = "sdhci-pci", 1919 .id_table = pci_ids, 1920 .probe = sdhci_pci_probe, 1921 .remove = sdhci_pci_remove, 1922 .driver = { 1923 .pm = &sdhci_pci_pm_ops 1924 }, 1925 }; 1926 1927 module_pci_driver(sdhci_driver); 1928 1929 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 1930 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 1931 MODULE_LICENSE("GPL"); 1932