1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 2 * 3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 * 10 * Thanks to the following companies for their support: 11 * 12 * - JMicron (hardware and technical support) 13 */ 14 15 #include <linux/string.h> 16 #include <linux/delay.h> 17 #include <linux/highmem.h> 18 #include <linux/module.h> 19 #include <linux/pci.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/slab.h> 22 #include <linux/device.h> 23 #include <linux/mmc/host.h> 24 #include <linux/mmc/mmc.h> 25 #include <linux/scatterlist.h> 26 #include <linux/io.h> 27 #include <linux/gpio.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/mmc/slot-gpio.h> 30 #include <linux/mmc/sdhci-pci-data.h> 31 #include <linux/acpi.h> 32 33 #include "sdhci.h" 34 #include "sdhci-pci.h" 35 #include "sdhci-pci-o2micro.h" 36 37 static int sdhci_pci_enable_dma(struct sdhci_host *host); 38 static void sdhci_pci_hw_reset(struct sdhci_host *host); 39 40 #ifdef CONFIG_PM_SLEEP 41 static int __sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 42 { 43 int i, ret; 44 45 for (i = 0; i < chip->num_slots; i++) { 46 struct sdhci_pci_slot *slot = chip->slots[i]; 47 struct sdhci_host *host; 48 49 if (!slot) 50 continue; 51 52 host = slot->host; 53 54 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 55 mmc_retune_needed(host->mmc); 56 57 ret = sdhci_suspend_host(host); 58 if (ret) 59 goto err_pci_suspend; 60 61 if (host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ) 62 sdhci_enable_irq_wakeups(host); 63 } 64 65 return 0; 66 67 err_pci_suspend: 68 while (--i >= 0) 69 sdhci_resume_host(chip->slots[i]->host); 70 return ret; 71 } 72 73 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip) 74 { 75 mmc_pm_flag_t pm_flags = 0; 76 int i; 77 78 for (i = 0; i < chip->num_slots; i++) { 79 struct sdhci_pci_slot *slot = chip->slots[i]; 80 81 if (slot) 82 pm_flags |= slot->host->mmc->pm_flags; 83 } 84 85 return device_init_wakeup(&chip->pdev->dev, 86 (pm_flags & MMC_PM_KEEP_POWER) && 87 (pm_flags & MMC_PM_WAKE_SDIO_IRQ)); 88 } 89 90 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 91 { 92 int ret; 93 94 ret = __sdhci_pci_suspend_host(chip); 95 if (ret) 96 return ret; 97 98 sdhci_pci_init_wakeup(chip); 99 100 return 0; 101 } 102 103 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip) 104 { 105 struct sdhci_pci_slot *slot; 106 int i, ret; 107 108 for (i = 0; i < chip->num_slots; i++) { 109 slot = chip->slots[i]; 110 if (!slot) 111 continue; 112 113 ret = sdhci_resume_host(slot->host); 114 if (ret) 115 return ret; 116 } 117 118 return 0; 119 } 120 #endif 121 122 #ifdef CONFIG_PM 123 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip) 124 { 125 struct sdhci_pci_slot *slot; 126 struct sdhci_host *host; 127 int i, ret; 128 129 for (i = 0; i < chip->num_slots; i++) { 130 slot = chip->slots[i]; 131 if (!slot) 132 continue; 133 134 host = slot->host; 135 136 ret = sdhci_runtime_suspend_host(host); 137 if (ret) 138 goto err_pci_runtime_suspend; 139 140 if (chip->rpm_retune && 141 host->tuning_mode != SDHCI_TUNING_MODE_3) 142 mmc_retune_needed(host->mmc); 143 } 144 145 return 0; 146 147 err_pci_runtime_suspend: 148 while (--i >= 0) 149 sdhci_runtime_resume_host(chip->slots[i]->host); 150 return ret; 151 } 152 153 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip) 154 { 155 struct sdhci_pci_slot *slot; 156 int i, ret; 157 158 for (i = 0; i < chip->num_slots; i++) { 159 slot = chip->slots[i]; 160 if (!slot) 161 continue; 162 163 ret = sdhci_runtime_resume_host(slot->host); 164 if (ret) 165 return ret; 166 } 167 168 return 0; 169 } 170 #endif 171 172 /*****************************************************************************\ 173 * * 174 * Hardware specific quirk handling * 175 * * 176 \*****************************************************************************/ 177 178 static int ricoh_probe(struct sdhci_pci_chip *chip) 179 { 180 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 181 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 182 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 183 return 0; 184 } 185 186 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 187 { 188 slot->host->caps = 189 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 190 & SDHCI_TIMEOUT_CLK_MASK) | 191 192 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 193 & SDHCI_CLOCK_BASE_MASK) | 194 195 SDHCI_TIMEOUT_CLK_UNIT | 196 SDHCI_CAN_VDD_330 | 197 SDHCI_CAN_DO_HISPD | 198 SDHCI_CAN_DO_SDMA; 199 return 0; 200 } 201 202 #ifdef CONFIG_PM_SLEEP 203 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 204 { 205 /* Apply a delay to allow controller to settle */ 206 /* Otherwise it becomes confused if card state changed 207 during suspend */ 208 msleep(500); 209 return sdhci_pci_resume_host(chip); 210 } 211 #endif 212 213 static const struct sdhci_pci_fixes sdhci_ricoh = { 214 .probe = ricoh_probe, 215 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 216 SDHCI_QUIRK_FORCE_DMA | 217 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 218 }; 219 220 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 221 .probe_slot = ricoh_mmc_probe_slot, 222 #ifdef CONFIG_PM_SLEEP 223 .resume = ricoh_mmc_resume, 224 #endif 225 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 226 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 227 SDHCI_QUIRK_NO_CARD_NO_RESET | 228 SDHCI_QUIRK_MISSING_CAPS 229 }; 230 231 static const struct sdhci_pci_fixes sdhci_ene_712 = { 232 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 233 SDHCI_QUIRK_BROKEN_DMA, 234 }; 235 236 static const struct sdhci_pci_fixes sdhci_ene_714 = { 237 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 238 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 239 SDHCI_QUIRK_BROKEN_DMA, 240 }; 241 242 static const struct sdhci_pci_fixes sdhci_cafe = { 243 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 244 SDHCI_QUIRK_NO_BUSY_IRQ | 245 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 246 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 247 }; 248 249 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 250 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 251 }; 252 253 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 254 { 255 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 256 return 0; 257 } 258 259 /* 260 * ADMA operation is disabled for Moorestown platform due to 261 * hardware bugs. 262 */ 263 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 264 { 265 /* 266 * slots number is fixed here for MRST as SDIO3/5 are never used and 267 * have hardware bugs. 268 */ 269 chip->num_slots = 1; 270 return 0; 271 } 272 273 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 274 { 275 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 276 return 0; 277 } 278 279 #ifdef CONFIG_PM 280 281 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 282 { 283 struct sdhci_pci_slot *slot = dev_id; 284 struct sdhci_host *host = slot->host; 285 286 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 287 return IRQ_HANDLED; 288 } 289 290 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 291 { 292 int err, irq, gpio = slot->cd_gpio; 293 294 slot->cd_gpio = -EINVAL; 295 slot->cd_irq = -EINVAL; 296 297 if (!gpio_is_valid(gpio)) 298 return; 299 300 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 301 if (err < 0) 302 goto out; 303 304 err = gpio_direction_input(gpio); 305 if (err < 0) 306 goto out_free; 307 308 irq = gpio_to_irq(gpio); 309 if (irq < 0) 310 goto out_free; 311 312 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 313 IRQF_TRIGGER_FALLING, "sd_cd", slot); 314 if (err) 315 goto out_free; 316 317 slot->cd_gpio = gpio; 318 slot->cd_irq = irq; 319 320 return; 321 322 out_free: 323 devm_gpio_free(&slot->chip->pdev->dev, gpio); 324 out: 325 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 326 } 327 328 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 329 { 330 if (slot->cd_irq >= 0) 331 free_irq(slot->cd_irq, slot); 332 } 333 334 #else 335 336 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 337 { 338 } 339 340 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 341 { 342 } 343 344 #endif 345 346 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 347 { 348 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 349 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC; 350 return 0; 351 } 352 353 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 354 { 355 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 356 return 0; 357 } 358 359 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 360 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 361 .probe_slot = mrst_hc_probe_slot, 362 }; 363 364 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 365 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 366 .probe = mrst_hc_probe, 367 }; 368 369 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 370 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 371 .allow_runtime_pm = true, 372 .own_cd_for_runtime_pm = true, 373 }; 374 375 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 376 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 377 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 378 .allow_runtime_pm = true, 379 .probe_slot = mfd_sdio_probe_slot, 380 }; 381 382 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 383 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 384 .allow_runtime_pm = true, 385 .probe_slot = mfd_emmc_probe_slot, 386 }; 387 388 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 389 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 390 .probe_slot = pch_hc_probe_slot, 391 }; 392 393 enum { 394 INTEL_DSM_FNS = 0, 395 INTEL_DSM_DRV_STRENGTH = 9, 396 INTEL_DSM_D3_RETUNE = 10, 397 }; 398 399 struct intel_host { 400 u32 dsm_fns; 401 int drv_strength; 402 bool d3_retune; 403 }; 404 405 static const guid_t intel_dsm_guid = 406 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F, 407 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61); 408 409 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 410 unsigned int fn, u32 *result) 411 { 412 union acpi_object *obj; 413 int err = 0; 414 size_t len; 415 416 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL); 417 if (!obj) 418 return -EOPNOTSUPP; 419 420 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { 421 err = -EINVAL; 422 goto out; 423 } 424 425 len = min_t(size_t, obj->buffer.length, 4); 426 427 *result = 0; 428 memcpy(result, obj->buffer.pointer, len); 429 out: 430 ACPI_FREE(obj); 431 432 return err; 433 } 434 435 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 436 unsigned int fn, u32 *result) 437 { 438 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 439 return -EOPNOTSUPP; 440 441 return __intel_dsm(intel_host, dev, fn, result); 442 } 443 444 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 445 struct mmc_host *mmc) 446 { 447 int err; 448 u32 val; 449 450 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 451 if (err) { 452 pr_debug("%s: DSM not supported, error %d\n", 453 mmc_hostname(mmc), err); 454 return; 455 } 456 457 pr_debug("%s: DSM function mask %#x\n", 458 mmc_hostname(mmc), intel_host->dsm_fns); 459 460 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 461 intel_host->drv_strength = err ? 0 : val; 462 463 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 464 intel_host->d3_retune = err ? true : !!val; 465 } 466 467 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 468 { 469 u8 reg; 470 471 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 472 reg |= 0x10; 473 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 474 /* For eMMC, minimum is 1us but give it 9us for good measure */ 475 udelay(9); 476 reg &= ~0x10; 477 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 478 /* For eMMC, minimum is 200us but give it 300us for good measure */ 479 usleep_range(300, 1000); 480 } 481 482 static int intel_select_drive_strength(struct mmc_card *card, 483 unsigned int max_dtr, int host_drv, 484 int card_drv, int *drv_type) 485 { 486 struct sdhci_host *host = mmc_priv(card->host); 487 struct sdhci_pci_slot *slot = sdhci_priv(host); 488 struct intel_host *intel_host = sdhci_pci_priv(slot); 489 490 return intel_host->drv_strength; 491 } 492 493 static int bxt_get_cd(struct mmc_host *mmc) 494 { 495 int gpio_cd = mmc_gpio_get_cd(mmc); 496 struct sdhci_host *host = mmc_priv(mmc); 497 unsigned long flags; 498 int ret = 0; 499 500 if (!gpio_cd) 501 return 0; 502 503 spin_lock_irqsave(&host->lock, flags); 504 505 if (host->flags & SDHCI_DEVICE_DEAD) 506 goto out; 507 508 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 509 out: 510 spin_unlock_irqrestore(&host->lock, flags); 511 512 return ret; 513 } 514 515 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 516 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 517 518 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 519 unsigned short vdd) 520 { 521 int cntr; 522 u8 reg; 523 524 sdhci_set_power(host, mode, vdd); 525 526 if (mode == MMC_POWER_OFF) 527 return; 528 529 /* 530 * Bus power might not enable after D3 -> D0 transition due to the 531 * present state not yet having propagated. Retry for up to 2ms. 532 */ 533 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 534 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 535 if (reg & SDHCI_POWER_ON) 536 break; 537 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 538 reg |= SDHCI_POWER_ON; 539 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 540 } 541 } 542 543 #define INTEL_HS400_ES_REG 0x78 544 #define INTEL_HS400_ES_BIT BIT(0) 545 546 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc, 547 struct mmc_ios *ios) 548 { 549 struct sdhci_host *host = mmc_priv(mmc); 550 u32 val; 551 552 val = sdhci_readl(host, INTEL_HS400_ES_REG); 553 if (ios->enhanced_strobe) 554 val |= INTEL_HS400_ES_BIT; 555 else 556 val &= ~INTEL_HS400_ES_BIT; 557 sdhci_writel(host, val, INTEL_HS400_ES_REG); 558 } 559 560 static const struct sdhci_ops sdhci_intel_byt_ops = { 561 .set_clock = sdhci_set_clock, 562 .set_power = sdhci_intel_set_power, 563 .enable_dma = sdhci_pci_enable_dma, 564 .set_bus_width = sdhci_set_bus_width, 565 .reset = sdhci_reset, 566 .set_uhs_signaling = sdhci_set_uhs_signaling, 567 .hw_reset = sdhci_pci_hw_reset, 568 }; 569 570 static void byt_read_dsm(struct sdhci_pci_slot *slot) 571 { 572 struct intel_host *intel_host = sdhci_pci_priv(slot); 573 struct device *dev = &slot->chip->pdev->dev; 574 struct mmc_host *mmc = slot->host->mmc; 575 576 intel_dsm_init(intel_host, dev, mmc); 577 slot->chip->rpm_retune = intel_host->d3_retune; 578 } 579 580 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 581 { 582 byt_read_dsm(slot); 583 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 584 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 585 MMC_CAP_CMD_DURING_TFR | 586 MMC_CAP_WAIT_WHILE_BUSY; 587 slot->hw_reset = sdhci_pci_int_hw_reset; 588 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 589 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 590 slot->host->mmc_host_ops.select_drive_strength = 591 intel_select_drive_strength; 592 return 0; 593 } 594 595 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot) 596 { 597 int ret = byt_emmc_probe_slot(slot); 598 599 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) { 600 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES, 601 slot->host->mmc_host_ops.hs400_enhanced_strobe = 602 intel_hs400_enhanced_strobe; 603 } 604 605 return ret; 606 } 607 608 #ifdef CONFIG_ACPI 609 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 610 { 611 acpi_status status; 612 unsigned long long max_freq; 613 614 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 615 "MXFQ", NULL, &max_freq); 616 if (ACPI_FAILURE(status)) { 617 dev_err(&slot->chip->pdev->dev, 618 "MXFQ not found in acpi table\n"); 619 return -EINVAL; 620 } 621 622 slot->host->mmc->f_max = max_freq * 1000000; 623 624 return 0; 625 } 626 #else 627 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 628 { 629 return 0; 630 } 631 #endif 632 633 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 634 { 635 int err; 636 637 byt_read_dsm(slot); 638 639 err = ni_set_max_freq(slot); 640 if (err) 641 return err; 642 643 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 644 MMC_CAP_WAIT_WHILE_BUSY; 645 return 0; 646 } 647 648 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 649 { 650 byt_read_dsm(slot); 651 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 652 MMC_CAP_WAIT_WHILE_BUSY; 653 return 0; 654 } 655 656 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 657 { 658 byt_read_dsm(slot); 659 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | 660 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE; 661 slot->cd_idx = 0; 662 slot->cd_override_level = true; 663 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 664 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 665 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 666 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) 667 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 668 669 return 0; 670 } 671 672 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 673 .allow_runtime_pm = true, 674 .probe_slot = byt_emmc_probe_slot, 675 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 676 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 677 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 678 SDHCI_QUIRK2_STOP_WITH_TC, 679 .ops = &sdhci_intel_byt_ops, 680 .priv_size = sizeof(struct intel_host), 681 }; 682 683 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = { 684 .allow_runtime_pm = true, 685 .probe_slot = glk_emmc_probe_slot, 686 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 687 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 688 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 689 SDHCI_QUIRK2_STOP_WITH_TC, 690 .ops = &sdhci_intel_byt_ops, 691 .priv_size = sizeof(struct intel_host), 692 }; 693 694 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 695 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 696 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 697 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 698 .allow_runtime_pm = true, 699 .probe_slot = ni_byt_sdio_probe_slot, 700 .ops = &sdhci_intel_byt_ops, 701 .priv_size = sizeof(struct intel_host), 702 }; 703 704 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 705 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 706 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 707 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 708 .allow_runtime_pm = true, 709 .probe_slot = byt_sdio_probe_slot, 710 .ops = &sdhci_intel_byt_ops, 711 .priv_size = sizeof(struct intel_host), 712 }; 713 714 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 715 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 716 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 717 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 718 SDHCI_QUIRK2_STOP_WITH_TC, 719 .allow_runtime_pm = true, 720 .own_cd_for_runtime_pm = true, 721 .probe_slot = byt_sd_probe_slot, 722 .ops = &sdhci_intel_byt_ops, 723 .priv_size = sizeof(struct intel_host), 724 }; 725 726 /* Define Host controllers for Intel Merrifield platform */ 727 #define INTEL_MRFLD_EMMC_0 0 728 #define INTEL_MRFLD_EMMC_1 1 729 #define INTEL_MRFLD_SD 2 730 #define INTEL_MRFLD_SDIO 3 731 732 #ifdef CONFIG_ACPI 733 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) 734 { 735 struct acpi_device *device, *child; 736 737 device = ACPI_COMPANION(&slot->chip->pdev->dev); 738 if (!device) 739 return; 740 741 acpi_device_fix_up_power(device); 742 list_for_each_entry(child, &device->children, node) 743 if (child->status.present && child->status.enabled) 744 acpi_device_fix_up_power(child); 745 } 746 #else 747 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {} 748 #endif 749 750 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 751 { 752 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 753 754 switch (func) { 755 case INTEL_MRFLD_EMMC_0: 756 case INTEL_MRFLD_EMMC_1: 757 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 758 MMC_CAP_8_BIT_DATA | 759 MMC_CAP_1_8V_DDR; 760 break; 761 case INTEL_MRFLD_SD: 762 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 763 break; 764 case INTEL_MRFLD_SDIO: 765 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 766 MMC_CAP_POWER_OFF_CARD; 767 break; 768 default: 769 return -ENODEV; 770 } 771 772 intel_mrfld_mmc_fix_up_power_slot(slot); 773 return 0; 774 } 775 776 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 777 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 778 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 779 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 780 .allow_runtime_pm = true, 781 .probe_slot = intel_mrfld_mmc_probe_slot, 782 }; 783 784 /* O2Micro extra registers */ 785 #define O2_SD_LOCK_WP 0xD3 786 #define O2_SD_MULTI_VCC3V 0xEE 787 #define O2_SD_CLKREQ 0xEC 788 #define O2_SD_CAPS 0xE0 789 #define O2_SD_ADMA1 0xE2 790 #define O2_SD_ADMA2 0xE7 791 #define O2_SD_INF_MOD 0xF1 792 793 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 794 { 795 u8 scratch; 796 int ret; 797 798 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 799 if (ret) 800 return ret; 801 802 /* 803 * Turn PMOS on [bit 0], set over current detection to 2.4 V 804 * [bit 1:2] and enable over current debouncing [bit 6]. 805 */ 806 if (on) 807 scratch |= 0x47; 808 else 809 scratch &= ~0x47; 810 811 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 812 } 813 814 static int jmicron_probe(struct sdhci_pci_chip *chip) 815 { 816 int ret; 817 u16 mmcdev = 0; 818 819 if (chip->pdev->revision == 0) { 820 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 821 SDHCI_QUIRK_32BIT_DMA_SIZE | 822 SDHCI_QUIRK_32BIT_ADMA_SIZE | 823 SDHCI_QUIRK_RESET_AFTER_REQUEST | 824 SDHCI_QUIRK_BROKEN_SMALL_PIO; 825 } 826 827 /* 828 * JMicron chips can have two interfaces to the same hardware 829 * in order to work around limitations in Microsoft's driver. 830 * We need to make sure we only bind to one of them. 831 * 832 * This code assumes two things: 833 * 834 * 1. The PCI code adds subfunctions in order. 835 * 836 * 2. The MMC interface has a lower subfunction number 837 * than the SD interface. 838 */ 839 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 840 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 841 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 842 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 843 844 if (mmcdev) { 845 struct pci_dev *sd_dev; 846 847 sd_dev = NULL; 848 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 849 mmcdev, sd_dev)) != NULL) { 850 if ((PCI_SLOT(chip->pdev->devfn) == 851 PCI_SLOT(sd_dev->devfn)) && 852 (chip->pdev->bus == sd_dev->bus)) 853 break; 854 } 855 856 if (sd_dev) { 857 pci_dev_put(sd_dev); 858 dev_info(&chip->pdev->dev, "Refusing to bind to " 859 "secondary interface.\n"); 860 return -ENODEV; 861 } 862 } 863 864 /* 865 * JMicron chips need a bit of a nudge to enable the power 866 * output pins. 867 */ 868 ret = jmicron_pmos(chip, 1); 869 if (ret) { 870 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 871 return ret; 872 } 873 874 /* quirk for unsable RO-detection on JM388 chips */ 875 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 876 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 877 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 878 879 return 0; 880 } 881 882 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 883 { 884 u8 scratch; 885 886 scratch = readb(host->ioaddr + 0xC0); 887 888 if (on) 889 scratch |= 0x01; 890 else 891 scratch &= ~0x01; 892 893 writeb(scratch, host->ioaddr + 0xC0); 894 } 895 896 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 897 { 898 if (slot->chip->pdev->revision == 0) { 899 u16 version; 900 901 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 902 version = (version & SDHCI_VENDOR_VER_MASK) >> 903 SDHCI_VENDOR_VER_SHIFT; 904 905 /* 906 * Older versions of the chip have lots of nasty glitches 907 * in the ADMA engine. It's best just to avoid it 908 * completely. 909 */ 910 if (version < 0xAC) 911 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 912 } 913 914 /* JM388 MMC doesn't support 1.8V while SD supports it */ 915 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 916 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 917 MMC_VDD_29_30 | MMC_VDD_30_31 | 918 MMC_VDD_165_195; /* allow 1.8V */ 919 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 920 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 921 } 922 923 /* 924 * The secondary interface requires a bit set to get the 925 * interrupts. 926 */ 927 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 928 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 929 jmicron_enable_mmc(slot->host, 1); 930 931 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 932 933 return 0; 934 } 935 936 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 937 { 938 if (dead) 939 return; 940 941 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 942 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 943 jmicron_enable_mmc(slot->host, 0); 944 } 945 946 #ifdef CONFIG_PM_SLEEP 947 static int jmicron_suspend(struct sdhci_pci_chip *chip) 948 { 949 int i, ret; 950 951 ret = __sdhci_pci_suspend_host(chip); 952 if (ret) 953 return ret; 954 955 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 956 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 957 for (i = 0; i < chip->num_slots; i++) 958 jmicron_enable_mmc(chip->slots[i]->host, 0); 959 } 960 961 sdhci_pci_init_wakeup(chip); 962 963 return 0; 964 } 965 966 static int jmicron_resume(struct sdhci_pci_chip *chip) 967 { 968 int ret, i; 969 970 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 971 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 972 for (i = 0; i < chip->num_slots; i++) 973 jmicron_enable_mmc(chip->slots[i]->host, 1); 974 } 975 976 ret = jmicron_pmos(chip, 1); 977 if (ret) { 978 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 979 return ret; 980 } 981 982 return sdhci_pci_resume_host(chip); 983 } 984 #endif 985 986 static const struct sdhci_pci_fixes sdhci_o2 = { 987 .probe = sdhci_pci_o2_probe, 988 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 989 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 990 .probe_slot = sdhci_pci_o2_probe_slot, 991 #ifdef CONFIG_PM_SLEEP 992 .resume = sdhci_pci_o2_resume, 993 #endif 994 }; 995 996 static const struct sdhci_pci_fixes sdhci_jmicron = { 997 .probe = jmicron_probe, 998 999 .probe_slot = jmicron_probe_slot, 1000 .remove_slot = jmicron_remove_slot, 1001 1002 #ifdef CONFIG_PM_SLEEP 1003 .suspend = jmicron_suspend, 1004 .resume = jmicron_resume, 1005 #endif 1006 }; 1007 1008 /* SysKonnect CardBus2SDIO extra registers */ 1009 #define SYSKT_CTRL 0x200 1010 #define SYSKT_RDFIFO_STAT 0x204 1011 #define SYSKT_WRFIFO_STAT 0x208 1012 #define SYSKT_POWER_DATA 0x20c 1013 #define SYSKT_POWER_330 0xef 1014 #define SYSKT_POWER_300 0xf8 1015 #define SYSKT_POWER_184 0xcc 1016 #define SYSKT_POWER_CMD 0x20d 1017 #define SYSKT_POWER_START (1 << 7) 1018 #define SYSKT_POWER_STATUS 0x20e 1019 #define SYSKT_POWER_STATUS_OK (1 << 0) 1020 #define SYSKT_BOARD_REV 0x210 1021 #define SYSKT_CHIP_REV 0x211 1022 #define SYSKT_CONF_DATA 0x212 1023 #define SYSKT_CONF_DATA_1V8 (1 << 2) 1024 #define SYSKT_CONF_DATA_2V5 (1 << 1) 1025 #define SYSKT_CONF_DATA_3V3 (1 << 0) 1026 1027 static int syskt_probe(struct sdhci_pci_chip *chip) 1028 { 1029 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1030 chip->pdev->class &= ~0x0000FF; 1031 chip->pdev->class |= PCI_SDHCI_IFDMA; 1032 } 1033 return 0; 1034 } 1035 1036 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 1037 { 1038 int tm, ps; 1039 1040 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 1041 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 1042 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 1043 "board rev %d.%d, chip rev %d.%d\n", 1044 board_rev >> 4, board_rev & 0xf, 1045 chip_rev >> 4, chip_rev & 0xf); 1046 if (chip_rev >= 0x20) 1047 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 1048 1049 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 1050 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 1051 udelay(50); 1052 tm = 10; /* Wait max 1 ms */ 1053 do { 1054 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 1055 if (ps & SYSKT_POWER_STATUS_OK) 1056 break; 1057 udelay(100); 1058 } while (--tm); 1059 if (!tm) { 1060 dev_err(&slot->chip->pdev->dev, 1061 "power regulator never stabilized"); 1062 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 1063 return -ENODEV; 1064 } 1065 1066 return 0; 1067 } 1068 1069 static const struct sdhci_pci_fixes sdhci_syskt = { 1070 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 1071 .probe = syskt_probe, 1072 .probe_slot = syskt_probe_slot, 1073 }; 1074 1075 static int via_probe(struct sdhci_pci_chip *chip) 1076 { 1077 if (chip->pdev->revision == 0x10) 1078 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 1079 1080 return 0; 1081 } 1082 1083 static const struct sdhci_pci_fixes sdhci_via = { 1084 .probe = via_probe, 1085 }; 1086 1087 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 1088 { 1089 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 1090 return 0; 1091 } 1092 1093 static const struct sdhci_pci_fixes sdhci_rtsx = { 1094 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1095 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 1096 SDHCI_QUIRK2_BROKEN_DDR50, 1097 .probe_slot = rtsx_probe_slot, 1098 }; 1099 1100 /*AMD chipset generation*/ 1101 enum amd_chipset_gen { 1102 AMD_CHIPSET_BEFORE_ML, 1103 AMD_CHIPSET_CZ, 1104 AMD_CHIPSET_NL, 1105 AMD_CHIPSET_UNKNOWN, 1106 }; 1107 1108 /* AMD registers */ 1109 #define AMD_SD_AUTO_PATTERN 0xB8 1110 #define AMD_MSLEEP_DURATION 4 1111 #define AMD_SD_MISC_CONTROL 0xD0 1112 #define AMD_MAX_TUNE_VALUE 0x0B 1113 #define AMD_AUTO_TUNE_SEL 0x10800 1114 #define AMD_FIFO_PTR 0x30 1115 #define AMD_BIT_MASK 0x1F 1116 1117 static void amd_tuning_reset(struct sdhci_host *host) 1118 { 1119 unsigned int val; 1120 1121 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1122 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 1123 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1124 1125 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1126 val &= ~SDHCI_CTRL_EXEC_TUNING; 1127 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1128 } 1129 1130 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 1131 { 1132 unsigned int val; 1133 1134 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 1135 val &= ~AMD_BIT_MASK; 1136 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 1137 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 1138 } 1139 1140 static void amd_enable_manual_tuning(struct pci_dev *pdev) 1141 { 1142 unsigned int val; 1143 1144 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 1145 val |= AMD_FIFO_PTR; 1146 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 1147 } 1148 1149 static int amd_execute_tuning(struct sdhci_host *host, u32 opcode) 1150 { 1151 struct sdhci_pci_slot *slot = sdhci_priv(host); 1152 struct pci_dev *pdev = slot->chip->pdev; 1153 u8 valid_win = 0; 1154 u8 valid_win_max = 0; 1155 u8 valid_win_end = 0; 1156 u8 ctrl, tune_around; 1157 1158 amd_tuning_reset(host); 1159 1160 for (tune_around = 0; tune_around < 12; tune_around++) { 1161 amd_config_tuning_phase(pdev, tune_around); 1162 1163 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1164 valid_win = 0; 1165 msleep(AMD_MSLEEP_DURATION); 1166 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 1167 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 1168 } else if (++valid_win > valid_win_max) { 1169 valid_win_max = valid_win; 1170 valid_win_end = tune_around; 1171 } 1172 } 1173 1174 if (!valid_win_max) { 1175 dev_err(&pdev->dev, "no tuning point found\n"); 1176 return -EIO; 1177 } 1178 1179 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 1180 1181 amd_enable_manual_tuning(pdev); 1182 1183 host->mmc->retune_period = 0; 1184 1185 return 0; 1186 } 1187 1188 static int amd_probe(struct sdhci_pci_chip *chip) 1189 { 1190 struct pci_dev *smbus_dev; 1191 enum amd_chipset_gen gen; 1192 1193 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1194 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 1195 if (smbus_dev) { 1196 gen = AMD_CHIPSET_BEFORE_ML; 1197 } else { 1198 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1199 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1200 if (smbus_dev) { 1201 if (smbus_dev->revision < 0x51) 1202 gen = AMD_CHIPSET_CZ; 1203 else 1204 gen = AMD_CHIPSET_NL; 1205 } else { 1206 gen = AMD_CHIPSET_UNKNOWN; 1207 } 1208 } 1209 1210 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1211 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1212 1213 return 0; 1214 } 1215 1216 static const struct sdhci_ops amd_sdhci_pci_ops = { 1217 .set_clock = sdhci_set_clock, 1218 .enable_dma = sdhci_pci_enable_dma, 1219 .set_bus_width = sdhci_set_bus_width, 1220 .reset = sdhci_reset, 1221 .set_uhs_signaling = sdhci_set_uhs_signaling, 1222 .platform_execute_tuning = amd_execute_tuning, 1223 }; 1224 1225 static const struct sdhci_pci_fixes sdhci_amd = { 1226 .probe = amd_probe, 1227 .ops = &amd_sdhci_pci_ops, 1228 }; 1229 1230 static const struct pci_device_id pci_ids[] = { 1231 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh), 1232 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc), 1233 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc), 1234 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc), 1235 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712), 1236 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712), 1237 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714), 1238 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714), 1239 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe), 1240 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron), 1241 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron), 1242 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron), 1243 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron), 1244 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt), 1245 SDHCI_PCI_DEVICE(VIA, 95D0, via), 1246 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx), 1247 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk), 1248 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0), 1249 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2), 1250 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2), 1251 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd), 1252 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio), 1253 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio), 1254 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc), 1255 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc), 1256 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio), 1257 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio), 1258 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc), 1259 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio), 1260 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio), 1261 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd), 1262 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc), 1263 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc), 1264 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio), 1265 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd), 1266 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd), 1267 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio), 1268 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio), 1269 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc), 1270 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc), 1271 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc), 1272 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc), 1273 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio), 1274 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd), 1275 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc), 1276 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc), 1277 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio), 1278 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd), 1279 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc), 1280 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio), 1281 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd), 1282 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc), 1283 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio), 1284 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd), 1285 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc), 1286 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio), 1287 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd), 1288 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc), 1289 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd), 1290 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd), 1291 SDHCI_PCI_DEVICE(O2, 8120, o2), 1292 SDHCI_PCI_DEVICE(O2, 8220, o2), 1293 SDHCI_PCI_DEVICE(O2, 8221, o2), 1294 SDHCI_PCI_DEVICE(O2, 8320, o2), 1295 SDHCI_PCI_DEVICE(O2, 8321, o2), 1296 SDHCI_PCI_DEVICE(O2, FUJIN2, o2), 1297 SDHCI_PCI_DEVICE(O2, SDS0, o2), 1298 SDHCI_PCI_DEVICE(O2, SDS1, o2), 1299 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2), 1300 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), 1301 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), 1302 /* Generic SD host controller */ 1303 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, 1304 { /* end: all zeroes */ }, 1305 }; 1306 1307 MODULE_DEVICE_TABLE(pci, pci_ids); 1308 1309 /*****************************************************************************\ 1310 * * 1311 * SDHCI core callbacks * 1312 * * 1313 \*****************************************************************************/ 1314 1315 static int sdhci_pci_enable_dma(struct sdhci_host *host) 1316 { 1317 struct sdhci_pci_slot *slot; 1318 struct pci_dev *pdev; 1319 1320 slot = sdhci_priv(host); 1321 pdev = slot->chip->pdev; 1322 1323 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1324 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1325 (host->flags & SDHCI_USE_SDMA)) { 1326 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1327 "doesn't fully claim to support it.\n"); 1328 } 1329 1330 pci_set_master(pdev); 1331 1332 return 0; 1333 } 1334 1335 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1336 { 1337 struct sdhci_pci_slot *slot = sdhci_priv(host); 1338 int rst_n_gpio = slot->rst_n_gpio; 1339 1340 if (!gpio_is_valid(rst_n_gpio)) 1341 return; 1342 gpio_set_value_cansleep(rst_n_gpio, 0); 1343 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1344 udelay(10); 1345 gpio_set_value_cansleep(rst_n_gpio, 1); 1346 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1347 usleep_range(300, 1000); 1348 } 1349 1350 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1351 { 1352 struct sdhci_pci_slot *slot = sdhci_priv(host); 1353 1354 if (slot->hw_reset) 1355 slot->hw_reset(host); 1356 } 1357 1358 static const struct sdhci_ops sdhci_pci_ops = { 1359 .set_clock = sdhci_set_clock, 1360 .enable_dma = sdhci_pci_enable_dma, 1361 .set_bus_width = sdhci_set_bus_width, 1362 .reset = sdhci_reset, 1363 .set_uhs_signaling = sdhci_set_uhs_signaling, 1364 .hw_reset = sdhci_pci_hw_reset, 1365 }; 1366 1367 /*****************************************************************************\ 1368 * * 1369 * Suspend/resume * 1370 * * 1371 \*****************************************************************************/ 1372 1373 #ifdef CONFIG_PM_SLEEP 1374 static int sdhci_pci_suspend(struct device *dev) 1375 { 1376 struct pci_dev *pdev = to_pci_dev(dev); 1377 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1378 1379 if (!chip) 1380 return 0; 1381 1382 if (chip->fixes && chip->fixes->suspend) 1383 return chip->fixes->suspend(chip); 1384 1385 return sdhci_pci_suspend_host(chip); 1386 } 1387 1388 static int sdhci_pci_resume(struct device *dev) 1389 { 1390 struct pci_dev *pdev = to_pci_dev(dev); 1391 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1392 1393 if (!chip) 1394 return 0; 1395 1396 if (chip->fixes && chip->fixes->resume) 1397 return chip->fixes->resume(chip); 1398 1399 return sdhci_pci_resume_host(chip); 1400 } 1401 #endif 1402 1403 #ifdef CONFIG_PM 1404 static int sdhci_pci_runtime_suspend(struct device *dev) 1405 { 1406 struct pci_dev *pdev = to_pci_dev(dev); 1407 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1408 1409 if (!chip) 1410 return 0; 1411 1412 if (chip->fixes && chip->fixes->runtime_suspend) 1413 return chip->fixes->runtime_suspend(chip); 1414 1415 return sdhci_pci_runtime_suspend_host(chip); 1416 } 1417 1418 static int sdhci_pci_runtime_resume(struct device *dev) 1419 { 1420 struct pci_dev *pdev = to_pci_dev(dev); 1421 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1422 1423 if (!chip) 1424 return 0; 1425 1426 if (chip->fixes && chip->fixes->runtime_resume) 1427 return chip->fixes->runtime_resume(chip); 1428 1429 return sdhci_pci_runtime_resume_host(chip); 1430 } 1431 #endif 1432 1433 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1434 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1435 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1436 sdhci_pci_runtime_resume, NULL) 1437 }; 1438 1439 /*****************************************************************************\ 1440 * * 1441 * Device probing/removal * 1442 * * 1443 \*****************************************************************************/ 1444 1445 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1446 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1447 int slotno) 1448 { 1449 struct sdhci_pci_slot *slot; 1450 struct sdhci_host *host; 1451 int ret, bar = first_bar + slotno; 1452 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 1453 1454 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1455 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1456 return ERR_PTR(-ENODEV); 1457 } 1458 1459 if (pci_resource_len(pdev, bar) < 0x100) { 1460 dev_err(&pdev->dev, "Invalid iomem size. You may " 1461 "experience problems.\n"); 1462 } 1463 1464 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1465 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1466 return ERR_PTR(-ENODEV); 1467 } 1468 1469 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1470 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1471 return ERR_PTR(-ENODEV); 1472 } 1473 1474 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 1475 if (IS_ERR(host)) { 1476 dev_err(&pdev->dev, "cannot allocate host\n"); 1477 return ERR_CAST(host); 1478 } 1479 1480 slot = sdhci_priv(host); 1481 1482 slot->chip = chip; 1483 slot->host = host; 1484 slot->rst_n_gpio = -EINVAL; 1485 slot->cd_gpio = -EINVAL; 1486 slot->cd_idx = -1; 1487 1488 /* Retrieve platform data if there is any */ 1489 if (*sdhci_pci_get_data) 1490 slot->data = sdhci_pci_get_data(pdev, slotno); 1491 1492 if (slot->data) { 1493 if (slot->data->setup) { 1494 ret = slot->data->setup(slot->data); 1495 if (ret) { 1496 dev_err(&pdev->dev, "platform setup failed\n"); 1497 goto free; 1498 } 1499 } 1500 slot->rst_n_gpio = slot->data->rst_n_gpio; 1501 slot->cd_gpio = slot->data->cd_gpio; 1502 } 1503 1504 host->hw_name = "PCI"; 1505 host->ops = chip->fixes && chip->fixes->ops ? 1506 chip->fixes->ops : 1507 &sdhci_pci_ops; 1508 host->quirks = chip->quirks; 1509 host->quirks2 = chip->quirks2; 1510 1511 host->irq = pdev->irq; 1512 1513 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1514 if (ret) { 1515 dev_err(&pdev->dev, "cannot request region\n"); 1516 goto cleanup; 1517 } 1518 1519 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1520 1521 if (chip->fixes && chip->fixes->probe_slot) { 1522 ret = chip->fixes->probe_slot(slot); 1523 if (ret) 1524 goto cleanup; 1525 } 1526 1527 if (gpio_is_valid(slot->rst_n_gpio)) { 1528 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1529 gpio_direction_output(slot->rst_n_gpio, 1); 1530 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1531 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1532 } else { 1533 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1534 slot->rst_n_gpio = -EINVAL; 1535 } 1536 } 1537 1538 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; 1539 host->mmc->slotno = slotno; 1540 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1541 1542 if (slot->cd_idx >= 0) { 1543 ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx, 1544 slot->cd_override_level, 0, NULL); 1545 if (ret == -EPROBE_DEFER) 1546 goto remove; 1547 1548 if (ret) { 1549 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 1550 slot->cd_idx = -1; 1551 } 1552 } 1553 1554 if (chip->fixes && chip->fixes->add_host) 1555 ret = chip->fixes->add_host(slot); 1556 else 1557 ret = sdhci_add_host(host); 1558 if (ret) 1559 goto remove; 1560 1561 sdhci_pci_add_own_cd(slot); 1562 1563 /* 1564 * Check if the chip needs a separate GPIO for card detect to wake up 1565 * from runtime suspend. If it is not there, don't allow runtime PM. 1566 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 1567 */ 1568 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 1569 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 1570 chip->allow_runtime_pm = false; 1571 1572 return slot; 1573 1574 remove: 1575 if (chip->fixes && chip->fixes->remove_slot) 1576 chip->fixes->remove_slot(slot, 0); 1577 1578 cleanup: 1579 if (slot->data && slot->data->cleanup) 1580 slot->data->cleanup(slot->data); 1581 1582 free: 1583 sdhci_free_host(host); 1584 1585 return ERR_PTR(ret); 1586 } 1587 1588 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 1589 { 1590 int dead; 1591 u32 scratch; 1592 1593 sdhci_pci_remove_own_cd(slot); 1594 1595 dead = 0; 1596 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 1597 if (scratch == (u32)-1) 1598 dead = 1; 1599 1600 sdhci_remove_host(slot->host, dead); 1601 1602 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 1603 slot->chip->fixes->remove_slot(slot, dead); 1604 1605 if (slot->data && slot->data->cleanup) 1606 slot->data->cleanup(slot->data); 1607 1608 sdhci_free_host(slot->host); 1609 } 1610 1611 static void sdhci_pci_runtime_pm_allow(struct device *dev) 1612 { 1613 pm_suspend_ignore_children(dev, 1); 1614 pm_runtime_set_autosuspend_delay(dev, 50); 1615 pm_runtime_use_autosuspend(dev); 1616 pm_runtime_allow(dev); 1617 /* Stay active until mmc core scans for a card */ 1618 pm_runtime_put_noidle(dev); 1619 } 1620 1621 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 1622 { 1623 pm_runtime_forbid(dev); 1624 pm_runtime_get_noresume(dev); 1625 } 1626 1627 static int sdhci_pci_probe(struct pci_dev *pdev, 1628 const struct pci_device_id *ent) 1629 { 1630 struct sdhci_pci_chip *chip; 1631 struct sdhci_pci_slot *slot; 1632 1633 u8 slots, first_bar; 1634 int ret, i; 1635 1636 BUG_ON(pdev == NULL); 1637 BUG_ON(ent == NULL); 1638 1639 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 1640 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 1641 1642 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 1643 if (ret) 1644 return ret; 1645 1646 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 1647 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 1648 if (slots == 0) 1649 return -ENODEV; 1650 1651 BUG_ON(slots > MAX_SLOTS); 1652 1653 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 1654 if (ret) 1655 return ret; 1656 1657 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 1658 1659 if (first_bar > 5) { 1660 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 1661 return -ENODEV; 1662 } 1663 1664 ret = pcim_enable_device(pdev); 1665 if (ret) 1666 return ret; 1667 1668 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 1669 if (!chip) 1670 return -ENOMEM; 1671 1672 chip->pdev = pdev; 1673 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 1674 if (chip->fixes) { 1675 chip->quirks = chip->fixes->quirks; 1676 chip->quirks2 = chip->fixes->quirks2; 1677 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 1678 } 1679 chip->num_slots = slots; 1680 chip->pm_retune = true; 1681 chip->rpm_retune = true; 1682 1683 pci_set_drvdata(pdev, chip); 1684 1685 if (chip->fixes && chip->fixes->probe) { 1686 ret = chip->fixes->probe(chip); 1687 if (ret) 1688 return ret; 1689 } 1690 1691 slots = chip->num_slots; /* Quirk may have changed this */ 1692 1693 for (i = 0; i < slots; i++) { 1694 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 1695 if (IS_ERR(slot)) { 1696 for (i--; i >= 0; i--) 1697 sdhci_pci_remove_slot(chip->slots[i]); 1698 return PTR_ERR(slot); 1699 } 1700 1701 chip->slots[i] = slot; 1702 } 1703 1704 if (chip->allow_runtime_pm) 1705 sdhci_pci_runtime_pm_allow(&pdev->dev); 1706 1707 return 0; 1708 } 1709 1710 static void sdhci_pci_remove(struct pci_dev *pdev) 1711 { 1712 int i; 1713 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1714 1715 if (chip->allow_runtime_pm) 1716 sdhci_pci_runtime_pm_forbid(&pdev->dev); 1717 1718 for (i = 0; i < chip->num_slots; i++) 1719 sdhci_pci_remove_slot(chip->slots[i]); 1720 } 1721 1722 static struct pci_driver sdhci_driver = { 1723 .name = "sdhci-pci", 1724 .id_table = pci_ids, 1725 .probe = sdhci_pci_probe, 1726 .remove = sdhci_pci_remove, 1727 .driver = { 1728 .pm = &sdhci_pci_pm_ops 1729 }, 1730 }; 1731 1732 module_pci_driver(sdhci_driver); 1733 1734 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 1735 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 1736 MODULE_LICENSE("GPL"); 1737