1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 3 * 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 5 * 6 * Thanks to the following companies for their support: 7 * 8 * - JMicron (hardware and technical support) 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/string.h> 13 #include <linux/delay.h> 14 #include <linux/highmem.h> 15 #include <linux/module.h> 16 #include <linux/pci.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/slab.h> 19 #include <linux/device.h> 20 #include <linux/mmc/host.h> 21 #include <linux/mmc/mmc.h> 22 #include <linux/scatterlist.h> 23 #include <linux/io.h> 24 #include <linux/iopoll.h> 25 #include <linux/gpio.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/pm_qos.h> 28 #include <linux/debugfs.h> 29 #include <linux/mmc/slot-gpio.h> 30 #include <linux/mmc/sdhci-pci-data.h> 31 #include <linux/acpi.h> 32 #include <linux/dmi.h> 33 34 #ifdef CONFIG_X86 35 #include <asm/iosf_mbi.h> 36 #endif 37 38 #include "cqhci.h" 39 40 #include "sdhci.h" 41 #include "sdhci-pci.h" 42 43 static void sdhci_pci_hw_reset(struct sdhci_host *host); 44 45 #ifdef CONFIG_PM_SLEEP 46 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip) 47 { 48 mmc_pm_flag_t pm_flags = 0; 49 bool cap_cd_wake = false; 50 int i; 51 52 for (i = 0; i < chip->num_slots; i++) { 53 struct sdhci_pci_slot *slot = chip->slots[i]; 54 55 if (slot) { 56 pm_flags |= slot->host->mmc->pm_flags; 57 if (slot->host->mmc->caps & MMC_CAP_CD_WAKE) 58 cap_cd_wake = true; 59 } 60 } 61 62 if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ)) 63 return device_wakeup_enable(&chip->pdev->dev); 64 else if (!cap_cd_wake) 65 return device_wakeup_disable(&chip->pdev->dev); 66 67 return 0; 68 } 69 70 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 71 { 72 int i, ret; 73 74 sdhci_pci_init_wakeup(chip); 75 76 for (i = 0; i < chip->num_slots; i++) { 77 struct sdhci_pci_slot *slot = chip->slots[i]; 78 struct sdhci_host *host; 79 80 if (!slot) 81 continue; 82 83 host = slot->host; 84 85 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 86 mmc_retune_needed(host->mmc); 87 88 ret = sdhci_suspend_host(host); 89 if (ret) 90 goto err_pci_suspend; 91 92 if (device_may_wakeup(&chip->pdev->dev)) 93 mmc_gpio_set_cd_wake(host->mmc, true); 94 } 95 96 return 0; 97 98 err_pci_suspend: 99 while (--i >= 0) 100 sdhci_resume_host(chip->slots[i]->host); 101 return ret; 102 } 103 104 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip) 105 { 106 struct sdhci_pci_slot *slot; 107 int i, ret; 108 109 for (i = 0; i < chip->num_slots; i++) { 110 slot = chip->slots[i]; 111 if (!slot) 112 continue; 113 114 ret = sdhci_resume_host(slot->host); 115 if (ret) 116 return ret; 117 118 mmc_gpio_set_cd_wake(slot->host->mmc, false); 119 } 120 121 return 0; 122 } 123 124 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip) 125 { 126 int ret; 127 128 ret = cqhci_suspend(chip->slots[0]->host->mmc); 129 if (ret) 130 return ret; 131 132 return sdhci_pci_suspend_host(chip); 133 } 134 135 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip) 136 { 137 int ret; 138 139 ret = sdhci_pci_resume_host(chip); 140 if (ret) 141 return ret; 142 143 return cqhci_resume(chip->slots[0]->host->mmc); 144 } 145 #endif 146 147 #ifdef CONFIG_PM 148 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip) 149 { 150 struct sdhci_pci_slot *slot; 151 struct sdhci_host *host; 152 int i, ret; 153 154 for (i = 0; i < chip->num_slots; i++) { 155 slot = chip->slots[i]; 156 if (!slot) 157 continue; 158 159 host = slot->host; 160 161 ret = sdhci_runtime_suspend_host(host); 162 if (ret) 163 goto err_pci_runtime_suspend; 164 165 if (chip->rpm_retune && 166 host->tuning_mode != SDHCI_TUNING_MODE_3) 167 mmc_retune_needed(host->mmc); 168 } 169 170 return 0; 171 172 err_pci_runtime_suspend: 173 while (--i >= 0) 174 sdhci_runtime_resume_host(chip->slots[i]->host, 0); 175 return ret; 176 } 177 178 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip) 179 { 180 struct sdhci_pci_slot *slot; 181 int i, ret; 182 183 for (i = 0; i < chip->num_slots; i++) { 184 slot = chip->slots[i]; 185 if (!slot) 186 continue; 187 188 ret = sdhci_runtime_resume_host(slot->host, 0); 189 if (ret) 190 return ret; 191 } 192 193 return 0; 194 } 195 196 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip) 197 { 198 int ret; 199 200 ret = cqhci_suspend(chip->slots[0]->host->mmc); 201 if (ret) 202 return ret; 203 204 return sdhci_pci_runtime_suspend_host(chip); 205 } 206 207 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip) 208 { 209 int ret; 210 211 ret = sdhci_pci_runtime_resume_host(chip); 212 if (ret) 213 return ret; 214 215 return cqhci_resume(chip->slots[0]->host->mmc); 216 } 217 #endif 218 219 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask) 220 { 221 int cmd_error = 0; 222 int data_error = 0; 223 224 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 225 return intmask; 226 227 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 228 229 return 0; 230 } 231 232 static void sdhci_pci_dumpregs(struct mmc_host *mmc) 233 { 234 sdhci_dumpregs(mmc_priv(mmc)); 235 } 236 237 static void sdhci_cqhci_reset(struct sdhci_host *host, u8 mask) 238 { 239 if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) && 240 host->mmc->cqe_private) 241 cqhci_deactivate(host->mmc); 242 sdhci_reset(host, mask); 243 } 244 245 /*****************************************************************************\ 246 * * 247 * Hardware specific quirk handling * 248 * * 249 \*****************************************************************************/ 250 251 static int ricoh_probe(struct sdhci_pci_chip *chip) 252 { 253 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 254 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 255 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 256 return 0; 257 } 258 259 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 260 { 261 slot->host->caps = 262 FIELD_PREP(SDHCI_TIMEOUT_CLK_MASK, 0x21) | 263 FIELD_PREP(SDHCI_CLOCK_BASE_MASK, 0x21) | 264 SDHCI_TIMEOUT_CLK_UNIT | 265 SDHCI_CAN_VDD_330 | 266 SDHCI_CAN_DO_HISPD | 267 SDHCI_CAN_DO_SDMA; 268 return 0; 269 } 270 271 #ifdef CONFIG_PM_SLEEP 272 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 273 { 274 /* Apply a delay to allow controller to settle */ 275 /* Otherwise it becomes confused if card state changed 276 during suspend */ 277 msleep(500); 278 return sdhci_pci_resume_host(chip); 279 } 280 #endif 281 282 static const struct sdhci_pci_fixes sdhci_ricoh = { 283 .probe = ricoh_probe, 284 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 285 SDHCI_QUIRK_FORCE_DMA | 286 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 287 }; 288 289 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 290 .probe_slot = ricoh_mmc_probe_slot, 291 #ifdef CONFIG_PM_SLEEP 292 .resume = ricoh_mmc_resume, 293 #endif 294 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 295 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 296 SDHCI_QUIRK_NO_CARD_NO_RESET | 297 SDHCI_QUIRK_MISSING_CAPS 298 }; 299 300 static const struct sdhci_pci_fixes sdhci_ene_712 = { 301 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 302 SDHCI_QUIRK_BROKEN_DMA, 303 }; 304 305 static const struct sdhci_pci_fixes sdhci_ene_714 = { 306 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 307 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 308 SDHCI_QUIRK_BROKEN_DMA, 309 }; 310 311 static const struct sdhci_pci_fixes sdhci_cafe = { 312 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 313 SDHCI_QUIRK_NO_BUSY_IRQ | 314 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 315 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 316 }; 317 318 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 319 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 320 }; 321 322 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 323 { 324 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 325 return 0; 326 } 327 328 /* 329 * ADMA operation is disabled for Moorestown platform due to 330 * hardware bugs. 331 */ 332 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 333 { 334 /* 335 * slots number is fixed here for MRST as SDIO3/5 are never used and 336 * have hardware bugs. 337 */ 338 chip->num_slots = 1; 339 return 0; 340 } 341 342 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 343 { 344 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 345 return 0; 346 } 347 348 #ifdef CONFIG_PM 349 350 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 351 { 352 struct sdhci_pci_slot *slot = dev_id; 353 struct sdhci_host *host = slot->host; 354 355 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 356 return IRQ_HANDLED; 357 } 358 359 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 360 { 361 int err, irq, gpio = slot->cd_gpio; 362 363 slot->cd_gpio = -EINVAL; 364 slot->cd_irq = -EINVAL; 365 366 if (!gpio_is_valid(gpio)) 367 return; 368 369 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 370 if (err < 0) 371 goto out; 372 373 err = gpio_direction_input(gpio); 374 if (err < 0) 375 goto out_free; 376 377 irq = gpio_to_irq(gpio); 378 if (irq < 0) 379 goto out_free; 380 381 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 382 IRQF_TRIGGER_FALLING, "sd_cd", slot); 383 if (err) 384 goto out_free; 385 386 slot->cd_gpio = gpio; 387 slot->cd_irq = irq; 388 389 return; 390 391 out_free: 392 devm_gpio_free(&slot->chip->pdev->dev, gpio); 393 out: 394 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 395 } 396 397 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 398 { 399 if (slot->cd_irq >= 0) 400 free_irq(slot->cd_irq, slot); 401 } 402 403 #else 404 405 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 406 { 407 } 408 409 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 410 { 411 } 412 413 #endif 414 415 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 416 { 417 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 418 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC; 419 return 0; 420 } 421 422 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 423 { 424 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 425 return 0; 426 } 427 428 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 429 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 430 .probe_slot = mrst_hc_probe_slot, 431 }; 432 433 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 434 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 435 .probe = mrst_hc_probe, 436 }; 437 438 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 439 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 440 .allow_runtime_pm = true, 441 .own_cd_for_runtime_pm = true, 442 }; 443 444 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 445 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 446 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 447 .allow_runtime_pm = true, 448 .probe_slot = mfd_sdio_probe_slot, 449 }; 450 451 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 452 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 453 .allow_runtime_pm = true, 454 .probe_slot = mfd_emmc_probe_slot, 455 }; 456 457 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 458 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 459 .probe_slot = pch_hc_probe_slot, 460 }; 461 462 #ifdef CONFIG_X86 463 464 #define BYT_IOSF_SCCEP 0x63 465 #define BYT_IOSF_OCP_NETCTRL0 0x1078 466 #define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8) 467 468 static void byt_ocp_setting(struct pci_dev *pdev) 469 { 470 u32 val = 0; 471 472 if (pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC && 473 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SDIO && 474 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SD && 475 pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC2) 476 return; 477 478 if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0, 479 &val)) { 480 dev_err(&pdev->dev, "%s read error\n", __func__); 481 return; 482 } 483 484 if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE)) 485 return; 486 487 val &= ~BYT_IOSF_OCP_TIMEOUT_BASE; 488 489 if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0, 490 val)) { 491 dev_err(&pdev->dev, "%s write error\n", __func__); 492 return; 493 } 494 495 dev_dbg(&pdev->dev, "%s completed\n", __func__); 496 } 497 498 #else 499 500 static inline void byt_ocp_setting(struct pci_dev *pdev) 501 { 502 } 503 504 #endif 505 506 enum { 507 INTEL_DSM_FNS = 0, 508 INTEL_DSM_V18_SWITCH = 3, 509 INTEL_DSM_V33_SWITCH = 4, 510 INTEL_DSM_DRV_STRENGTH = 9, 511 INTEL_DSM_D3_RETUNE = 10, 512 }; 513 514 struct intel_host { 515 u32 dsm_fns; 516 int drv_strength; 517 bool d3_retune; 518 bool rpm_retune_ok; 519 bool needs_pwr_off; 520 u32 glk_rx_ctrl1; 521 u32 glk_tun_val; 522 u32 active_ltr; 523 u32 idle_ltr; 524 }; 525 526 static const guid_t intel_dsm_guid = 527 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F, 528 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61); 529 530 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 531 unsigned int fn, u32 *result) 532 { 533 union acpi_object *obj; 534 int err = 0; 535 size_t len; 536 537 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL); 538 if (!obj) 539 return -EOPNOTSUPP; 540 541 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { 542 err = -EINVAL; 543 goto out; 544 } 545 546 len = min_t(size_t, obj->buffer.length, 4); 547 548 *result = 0; 549 memcpy(result, obj->buffer.pointer, len); 550 out: 551 ACPI_FREE(obj); 552 553 return err; 554 } 555 556 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 557 unsigned int fn, u32 *result) 558 { 559 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 560 return -EOPNOTSUPP; 561 562 return __intel_dsm(intel_host, dev, fn, result); 563 } 564 565 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 566 struct mmc_host *mmc) 567 { 568 int err; 569 u32 val; 570 571 intel_host->d3_retune = true; 572 573 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 574 if (err) { 575 pr_debug("%s: DSM not supported, error %d\n", 576 mmc_hostname(mmc), err); 577 return; 578 } 579 580 pr_debug("%s: DSM function mask %#x\n", 581 mmc_hostname(mmc), intel_host->dsm_fns); 582 583 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 584 intel_host->drv_strength = err ? 0 : val; 585 586 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 587 intel_host->d3_retune = err ? true : !!val; 588 } 589 590 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 591 { 592 u8 reg; 593 594 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 595 reg |= 0x10; 596 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 597 /* For eMMC, minimum is 1us but give it 9us for good measure */ 598 udelay(9); 599 reg &= ~0x10; 600 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 601 /* For eMMC, minimum is 200us but give it 300us for good measure */ 602 usleep_range(300, 1000); 603 } 604 605 static int intel_select_drive_strength(struct mmc_card *card, 606 unsigned int max_dtr, int host_drv, 607 int card_drv, int *drv_type) 608 { 609 struct sdhci_host *host = mmc_priv(card->host); 610 struct sdhci_pci_slot *slot = sdhci_priv(host); 611 struct intel_host *intel_host = sdhci_pci_priv(slot); 612 613 if (!(mmc_driver_type_mask(intel_host->drv_strength) & card_drv)) 614 return 0; 615 616 return intel_host->drv_strength; 617 } 618 619 static int sdhci_get_cd_nogpio(struct mmc_host *mmc) 620 { 621 struct sdhci_host *host = mmc_priv(mmc); 622 unsigned long flags; 623 int ret = 0; 624 625 spin_lock_irqsave(&host->lock, flags); 626 627 if (host->flags & SDHCI_DEVICE_DEAD) 628 goto out; 629 630 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 631 out: 632 spin_unlock_irqrestore(&host->lock, flags); 633 634 return ret; 635 } 636 637 static int bxt_get_cd(struct mmc_host *mmc) 638 { 639 int gpio_cd = mmc_gpio_get_cd(mmc); 640 641 if (!gpio_cd) 642 return 0; 643 644 return sdhci_get_cd_nogpio(mmc); 645 } 646 647 static int mrfld_get_cd(struct mmc_host *mmc) 648 { 649 return sdhci_get_cd_nogpio(mmc); 650 } 651 652 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 653 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 654 655 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 656 unsigned short vdd) 657 { 658 struct sdhci_pci_slot *slot = sdhci_priv(host); 659 struct intel_host *intel_host = sdhci_pci_priv(slot); 660 int cntr; 661 u8 reg; 662 663 /* 664 * Bus power may control card power, but a full reset still may not 665 * reset the power, whereas a direct write to SDHCI_POWER_CONTROL can. 666 * That might be needed to initialize correctly, if the card was left 667 * powered on previously. 668 */ 669 if (intel_host->needs_pwr_off) { 670 intel_host->needs_pwr_off = false; 671 if (mode != MMC_POWER_OFF) { 672 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 673 usleep_range(10000, 12500); 674 } 675 } 676 677 sdhci_set_power(host, mode, vdd); 678 679 if (mode == MMC_POWER_OFF) 680 return; 681 682 /* 683 * Bus power might not enable after D3 -> D0 transition due to the 684 * present state not yet having propagated. Retry for up to 2ms. 685 */ 686 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 687 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 688 if (reg & SDHCI_POWER_ON) 689 break; 690 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 691 reg |= SDHCI_POWER_ON; 692 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 693 } 694 } 695 696 static void sdhci_intel_set_uhs_signaling(struct sdhci_host *host, 697 unsigned int timing) 698 { 699 /* Set UHS timing to SDR25 for High Speed mode */ 700 if (timing == MMC_TIMING_MMC_HS || timing == MMC_TIMING_SD_HS) 701 timing = MMC_TIMING_UHS_SDR25; 702 sdhci_set_uhs_signaling(host, timing); 703 } 704 705 #define INTEL_HS400_ES_REG 0x78 706 #define INTEL_HS400_ES_BIT BIT(0) 707 708 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc, 709 struct mmc_ios *ios) 710 { 711 struct sdhci_host *host = mmc_priv(mmc); 712 u32 val; 713 714 val = sdhci_readl(host, INTEL_HS400_ES_REG); 715 if (ios->enhanced_strobe) 716 val |= INTEL_HS400_ES_BIT; 717 else 718 val &= ~INTEL_HS400_ES_BIT; 719 sdhci_writel(host, val, INTEL_HS400_ES_REG); 720 } 721 722 static int intel_start_signal_voltage_switch(struct mmc_host *mmc, 723 struct mmc_ios *ios) 724 { 725 struct device *dev = mmc_dev(mmc); 726 struct sdhci_host *host = mmc_priv(mmc); 727 struct sdhci_pci_slot *slot = sdhci_priv(host); 728 struct intel_host *intel_host = sdhci_pci_priv(slot); 729 unsigned int fn; 730 u32 result = 0; 731 int err; 732 733 err = sdhci_start_signal_voltage_switch(mmc, ios); 734 if (err) 735 return err; 736 737 switch (ios->signal_voltage) { 738 case MMC_SIGNAL_VOLTAGE_330: 739 fn = INTEL_DSM_V33_SWITCH; 740 break; 741 case MMC_SIGNAL_VOLTAGE_180: 742 fn = INTEL_DSM_V18_SWITCH; 743 break; 744 default: 745 return 0; 746 } 747 748 err = intel_dsm(intel_host, dev, fn, &result); 749 pr_debug("%s: %s DSM fn %u error %d result %u\n", 750 mmc_hostname(mmc), __func__, fn, err, result); 751 752 return 0; 753 } 754 755 static const struct sdhci_ops sdhci_intel_byt_ops = { 756 .set_clock = sdhci_set_clock, 757 .set_power = sdhci_intel_set_power, 758 .enable_dma = sdhci_pci_enable_dma, 759 .set_bus_width = sdhci_set_bus_width, 760 .reset = sdhci_reset, 761 .set_uhs_signaling = sdhci_intel_set_uhs_signaling, 762 .hw_reset = sdhci_pci_hw_reset, 763 }; 764 765 static const struct sdhci_ops sdhci_intel_glk_ops = { 766 .set_clock = sdhci_set_clock, 767 .set_power = sdhci_intel_set_power, 768 .enable_dma = sdhci_pci_enable_dma, 769 .set_bus_width = sdhci_set_bus_width, 770 .reset = sdhci_cqhci_reset, 771 .set_uhs_signaling = sdhci_intel_set_uhs_signaling, 772 .hw_reset = sdhci_pci_hw_reset, 773 .irq = sdhci_cqhci_irq, 774 }; 775 776 static void byt_read_dsm(struct sdhci_pci_slot *slot) 777 { 778 struct intel_host *intel_host = sdhci_pci_priv(slot); 779 struct device *dev = &slot->chip->pdev->dev; 780 struct mmc_host *mmc = slot->host->mmc; 781 782 intel_dsm_init(intel_host, dev, mmc); 783 slot->chip->rpm_retune = intel_host->d3_retune; 784 } 785 786 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode) 787 { 788 int err = sdhci_execute_tuning(mmc, opcode); 789 struct sdhci_host *host = mmc_priv(mmc); 790 791 if (err) 792 return err; 793 794 /* 795 * Tuning can leave the IP in an active state (Buffer Read Enable bit 796 * set) which prevents the entry to low power states (i.e. S0i3). Data 797 * reset will clear it. 798 */ 799 sdhci_reset(host, SDHCI_RESET_DATA); 800 801 return 0; 802 } 803 804 #define INTEL_ACTIVELTR 0x804 805 #define INTEL_IDLELTR 0x808 806 807 #define INTEL_LTR_REQ BIT(15) 808 #define INTEL_LTR_SCALE_MASK GENMASK(11, 10) 809 #define INTEL_LTR_SCALE_1US (2 << 10) 810 #define INTEL_LTR_SCALE_32US (3 << 10) 811 #define INTEL_LTR_VALUE_MASK GENMASK(9, 0) 812 813 static void intel_cache_ltr(struct sdhci_pci_slot *slot) 814 { 815 struct intel_host *intel_host = sdhci_pci_priv(slot); 816 struct sdhci_host *host = slot->host; 817 818 intel_host->active_ltr = readl(host->ioaddr + INTEL_ACTIVELTR); 819 intel_host->idle_ltr = readl(host->ioaddr + INTEL_IDLELTR); 820 } 821 822 static void intel_ltr_set(struct device *dev, s32 val) 823 { 824 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 825 struct sdhci_pci_slot *slot = chip->slots[0]; 826 struct intel_host *intel_host = sdhci_pci_priv(slot); 827 struct sdhci_host *host = slot->host; 828 u32 ltr; 829 830 pm_runtime_get_sync(dev); 831 832 /* 833 * Program latency tolerance (LTR) accordingly what has been asked 834 * by the PM QoS layer or disable it in case we were passed 835 * negative value or PM_QOS_LATENCY_ANY. 836 */ 837 ltr = readl(host->ioaddr + INTEL_ACTIVELTR); 838 839 if (val == PM_QOS_LATENCY_ANY || val < 0) { 840 ltr &= ~INTEL_LTR_REQ; 841 } else { 842 ltr |= INTEL_LTR_REQ; 843 ltr &= ~INTEL_LTR_SCALE_MASK; 844 ltr &= ~INTEL_LTR_VALUE_MASK; 845 846 if (val > INTEL_LTR_VALUE_MASK) { 847 val >>= 5; 848 if (val > INTEL_LTR_VALUE_MASK) 849 val = INTEL_LTR_VALUE_MASK; 850 ltr |= INTEL_LTR_SCALE_32US | val; 851 } else { 852 ltr |= INTEL_LTR_SCALE_1US | val; 853 } 854 } 855 856 if (ltr == intel_host->active_ltr) 857 goto out; 858 859 writel(ltr, host->ioaddr + INTEL_ACTIVELTR); 860 writel(ltr, host->ioaddr + INTEL_IDLELTR); 861 862 /* Cache the values into lpss structure */ 863 intel_cache_ltr(slot); 864 out: 865 pm_runtime_put_autosuspend(dev); 866 } 867 868 static bool intel_use_ltr(struct sdhci_pci_chip *chip) 869 { 870 switch (chip->pdev->device) { 871 case PCI_DEVICE_ID_INTEL_BYT_EMMC: 872 case PCI_DEVICE_ID_INTEL_BYT_EMMC2: 873 case PCI_DEVICE_ID_INTEL_BYT_SDIO: 874 case PCI_DEVICE_ID_INTEL_BYT_SD: 875 case PCI_DEVICE_ID_INTEL_BSW_EMMC: 876 case PCI_DEVICE_ID_INTEL_BSW_SDIO: 877 case PCI_DEVICE_ID_INTEL_BSW_SD: 878 return false; 879 default: 880 return true; 881 } 882 } 883 884 static void intel_ltr_expose(struct sdhci_pci_chip *chip) 885 { 886 struct device *dev = &chip->pdev->dev; 887 888 if (!intel_use_ltr(chip)) 889 return; 890 891 dev->power.set_latency_tolerance = intel_ltr_set; 892 dev_pm_qos_expose_latency_tolerance(dev); 893 } 894 895 static void intel_ltr_hide(struct sdhci_pci_chip *chip) 896 { 897 struct device *dev = &chip->pdev->dev; 898 899 if (!intel_use_ltr(chip)) 900 return; 901 902 dev_pm_qos_hide_latency_tolerance(dev); 903 dev->power.set_latency_tolerance = NULL; 904 } 905 906 static void byt_probe_slot(struct sdhci_pci_slot *slot) 907 { 908 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 909 struct device *dev = &slot->chip->pdev->dev; 910 struct mmc_host *mmc = slot->host->mmc; 911 912 byt_read_dsm(slot); 913 914 byt_ocp_setting(slot->chip->pdev); 915 916 ops->execute_tuning = intel_execute_tuning; 917 ops->start_signal_voltage_switch = intel_start_signal_voltage_switch; 918 919 device_property_read_u32(dev, "max-frequency", &mmc->f_max); 920 921 if (!mmc->slotno) { 922 slot->chip->slots[mmc->slotno] = slot; 923 intel_ltr_expose(slot->chip); 924 } 925 } 926 927 static void byt_add_debugfs(struct sdhci_pci_slot *slot) 928 { 929 struct intel_host *intel_host = sdhci_pci_priv(slot); 930 struct mmc_host *mmc = slot->host->mmc; 931 struct dentry *dir = mmc->debugfs_root; 932 933 if (!intel_use_ltr(slot->chip)) 934 return; 935 936 debugfs_create_x32("active_ltr", 0444, dir, &intel_host->active_ltr); 937 debugfs_create_x32("idle_ltr", 0444, dir, &intel_host->idle_ltr); 938 939 intel_cache_ltr(slot); 940 } 941 942 static int byt_add_host(struct sdhci_pci_slot *slot) 943 { 944 int ret = sdhci_add_host(slot->host); 945 946 if (!ret) 947 byt_add_debugfs(slot); 948 return ret; 949 } 950 951 static void byt_remove_slot(struct sdhci_pci_slot *slot, int dead) 952 { 953 struct mmc_host *mmc = slot->host->mmc; 954 955 if (!mmc->slotno) 956 intel_ltr_hide(slot->chip); 957 } 958 959 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 960 { 961 byt_probe_slot(slot); 962 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 963 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 964 MMC_CAP_CMD_DURING_TFR | 965 MMC_CAP_WAIT_WHILE_BUSY; 966 slot->hw_reset = sdhci_pci_int_hw_reset; 967 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 968 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 969 slot->host->mmc_host_ops.select_drive_strength = 970 intel_select_drive_strength; 971 return 0; 972 } 973 974 static bool glk_broken_cqhci(struct sdhci_pci_slot *slot) 975 { 976 return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 977 (dmi_match(DMI_BIOS_VENDOR, "LENOVO") || 978 dmi_match(DMI_SYS_VENDOR, "IRBIS")); 979 } 980 981 static bool jsl_broken_hs400es(struct sdhci_pci_slot *slot) 982 { 983 return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_JSL_EMMC && 984 dmi_match(DMI_BIOS_VENDOR, "ASUSTeK COMPUTER INC."); 985 } 986 987 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot) 988 { 989 int ret = byt_emmc_probe_slot(slot); 990 991 if (!glk_broken_cqhci(slot)) 992 slot->host->mmc->caps2 |= MMC_CAP2_CQE; 993 994 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) { 995 if (!jsl_broken_hs400es(slot)) { 996 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES; 997 slot->host->mmc_host_ops.hs400_enhanced_strobe = 998 intel_hs400_enhanced_strobe; 999 } 1000 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; 1001 } 1002 1003 return ret; 1004 } 1005 1006 static const struct cqhci_host_ops glk_cqhci_ops = { 1007 .enable = sdhci_cqe_enable, 1008 .disable = sdhci_cqe_disable, 1009 .dumpregs = sdhci_pci_dumpregs, 1010 }; 1011 1012 static int glk_emmc_add_host(struct sdhci_pci_slot *slot) 1013 { 1014 struct device *dev = &slot->chip->pdev->dev; 1015 struct sdhci_host *host = slot->host; 1016 struct cqhci_host *cq_host; 1017 bool dma64; 1018 int ret; 1019 1020 ret = sdhci_setup_host(host); 1021 if (ret) 1022 return ret; 1023 1024 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); 1025 if (!cq_host) { 1026 ret = -ENOMEM; 1027 goto cleanup; 1028 } 1029 1030 cq_host->mmio = host->ioaddr + 0x200; 1031 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 1032 cq_host->ops = &glk_cqhci_ops; 1033 1034 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 1035 if (dma64) 1036 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 1037 1038 ret = cqhci_init(cq_host, host->mmc, dma64); 1039 if (ret) 1040 goto cleanup; 1041 1042 ret = __sdhci_add_host(host); 1043 if (ret) 1044 goto cleanup; 1045 1046 byt_add_debugfs(slot); 1047 1048 return 0; 1049 1050 cleanup: 1051 sdhci_cleanup_host(host); 1052 return ret; 1053 } 1054 1055 #ifdef CONFIG_PM 1056 #define GLK_RX_CTRL1 0x834 1057 #define GLK_TUN_VAL 0x840 1058 #define GLK_PATH_PLL GENMASK(13, 8) 1059 #define GLK_DLY GENMASK(6, 0) 1060 /* Workaround firmware failing to restore the tuning value */ 1061 static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp) 1062 { 1063 struct sdhci_pci_slot *slot = chip->slots[0]; 1064 struct intel_host *intel_host = sdhci_pci_priv(slot); 1065 struct sdhci_host *host = slot->host; 1066 u32 glk_rx_ctrl1; 1067 u32 glk_tun_val; 1068 u32 dly; 1069 1070 if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc)) 1071 return; 1072 1073 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1); 1074 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL); 1075 1076 if (susp) { 1077 intel_host->glk_rx_ctrl1 = glk_rx_ctrl1; 1078 intel_host->glk_tun_val = glk_tun_val; 1079 return; 1080 } 1081 1082 if (!intel_host->glk_tun_val) 1083 return; 1084 1085 if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) { 1086 intel_host->rpm_retune_ok = true; 1087 return; 1088 } 1089 1090 dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) + 1091 (intel_host->glk_tun_val << 1)); 1092 if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1)) 1093 return; 1094 1095 glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly; 1096 sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1); 1097 1098 intel_host->rpm_retune_ok = true; 1099 chip->rpm_retune = true; 1100 mmc_retune_needed(host->mmc); 1101 pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc)); 1102 } 1103 1104 static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp) 1105 { 1106 if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 1107 !chip->rpm_retune) 1108 glk_rpm_retune_wa(chip, susp); 1109 } 1110 1111 static int glk_runtime_suspend(struct sdhci_pci_chip *chip) 1112 { 1113 glk_rpm_retune_chk(chip, true); 1114 1115 return sdhci_cqhci_runtime_suspend(chip); 1116 } 1117 1118 static int glk_runtime_resume(struct sdhci_pci_chip *chip) 1119 { 1120 glk_rpm_retune_chk(chip, false); 1121 1122 return sdhci_cqhci_runtime_resume(chip); 1123 } 1124 #endif 1125 1126 #ifdef CONFIG_ACPI 1127 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 1128 { 1129 acpi_status status; 1130 unsigned long long max_freq; 1131 1132 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 1133 "MXFQ", NULL, &max_freq); 1134 if (ACPI_FAILURE(status)) { 1135 dev_err(&slot->chip->pdev->dev, 1136 "MXFQ not found in acpi table\n"); 1137 return -EINVAL; 1138 } 1139 1140 slot->host->mmc->f_max = max_freq * 1000000; 1141 1142 return 0; 1143 } 1144 #else 1145 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 1146 { 1147 return 0; 1148 } 1149 #endif 1150 1151 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 1152 { 1153 int err; 1154 1155 byt_probe_slot(slot); 1156 1157 err = ni_set_max_freq(slot); 1158 if (err) 1159 return err; 1160 1161 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 1162 MMC_CAP_WAIT_WHILE_BUSY; 1163 return 0; 1164 } 1165 1166 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 1167 { 1168 byt_probe_slot(slot); 1169 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 1170 MMC_CAP_WAIT_WHILE_BUSY; 1171 return 0; 1172 } 1173 1174 static void byt_needs_pwr_off(struct sdhci_pci_slot *slot) 1175 { 1176 struct intel_host *intel_host = sdhci_pci_priv(slot); 1177 u8 reg = sdhci_readb(slot->host, SDHCI_POWER_CONTROL); 1178 1179 intel_host->needs_pwr_off = reg & SDHCI_POWER_ON; 1180 } 1181 1182 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 1183 { 1184 byt_probe_slot(slot); 1185 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | 1186 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE; 1187 slot->cd_idx = 0; 1188 slot->cd_override_level = true; 1189 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 1190 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 1191 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 1192 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) 1193 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 1194 1195 if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI && 1196 slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3) 1197 slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V; 1198 1199 byt_needs_pwr_off(slot); 1200 1201 return 0; 1202 } 1203 1204 #ifdef CONFIG_PM_SLEEP 1205 1206 static int byt_resume(struct sdhci_pci_chip *chip) 1207 { 1208 byt_ocp_setting(chip->pdev); 1209 1210 return sdhci_pci_resume_host(chip); 1211 } 1212 1213 #endif 1214 1215 #ifdef CONFIG_PM 1216 1217 static int byt_runtime_resume(struct sdhci_pci_chip *chip) 1218 { 1219 byt_ocp_setting(chip->pdev); 1220 1221 return sdhci_pci_runtime_resume_host(chip); 1222 } 1223 1224 #endif 1225 1226 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 1227 #ifdef CONFIG_PM_SLEEP 1228 .resume = byt_resume, 1229 #endif 1230 #ifdef CONFIG_PM 1231 .runtime_resume = byt_runtime_resume, 1232 #endif 1233 .allow_runtime_pm = true, 1234 .probe_slot = byt_emmc_probe_slot, 1235 .add_host = byt_add_host, 1236 .remove_slot = byt_remove_slot, 1237 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1238 SDHCI_QUIRK_NO_LED, 1239 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1240 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1241 SDHCI_QUIRK2_STOP_WITH_TC, 1242 .ops = &sdhci_intel_byt_ops, 1243 .priv_size = sizeof(struct intel_host), 1244 }; 1245 1246 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = { 1247 .allow_runtime_pm = true, 1248 .probe_slot = glk_emmc_probe_slot, 1249 .add_host = glk_emmc_add_host, 1250 .remove_slot = byt_remove_slot, 1251 #ifdef CONFIG_PM_SLEEP 1252 .suspend = sdhci_cqhci_suspend, 1253 .resume = sdhci_cqhci_resume, 1254 #endif 1255 #ifdef CONFIG_PM 1256 .runtime_suspend = glk_runtime_suspend, 1257 .runtime_resume = glk_runtime_resume, 1258 #endif 1259 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1260 SDHCI_QUIRK_NO_LED, 1261 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1262 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1263 SDHCI_QUIRK2_STOP_WITH_TC, 1264 .ops = &sdhci_intel_glk_ops, 1265 .priv_size = sizeof(struct intel_host), 1266 }; 1267 1268 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 1269 #ifdef CONFIG_PM_SLEEP 1270 .resume = byt_resume, 1271 #endif 1272 #ifdef CONFIG_PM 1273 .runtime_resume = byt_runtime_resume, 1274 #endif 1275 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1276 SDHCI_QUIRK_NO_LED, 1277 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1278 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1279 .allow_runtime_pm = true, 1280 .probe_slot = ni_byt_sdio_probe_slot, 1281 .add_host = byt_add_host, 1282 .remove_slot = byt_remove_slot, 1283 .ops = &sdhci_intel_byt_ops, 1284 .priv_size = sizeof(struct intel_host), 1285 }; 1286 1287 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 1288 #ifdef CONFIG_PM_SLEEP 1289 .resume = byt_resume, 1290 #endif 1291 #ifdef CONFIG_PM 1292 .runtime_resume = byt_runtime_resume, 1293 #endif 1294 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1295 SDHCI_QUIRK_NO_LED, 1296 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1297 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1298 .allow_runtime_pm = true, 1299 .probe_slot = byt_sdio_probe_slot, 1300 .add_host = byt_add_host, 1301 .remove_slot = byt_remove_slot, 1302 .ops = &sdhci_intel_byt_ops, 1303 .priv_size = sizeof(struct intel_host), 1304 }; 1305 1306 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 1307 #ifdef CONFIG_PM_SLEEP 1308 .resume = byt_resume, 1309 #endif 1310 #ifdef CONFIG_PM 1311 .runtime_resume = byt_runtime_resume, 1312 #endif 1313 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1314 SDHCI_QUIRK_NO_LED, 1315 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 1316 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1317 SDHCI_QUIRK2_STOP_WITH_TC, 1318 .allow_runtime_pm = true, 1319 .own_cd_for_runtime_pm = true, 1320 .probe_slot = byt_sd_probe_slot, 1321 .add_host = byt_add_host, 1322 .remove_slot = byt_remove_slot, 1323 .ops = &sdhci_intel_byt_ops, 1324 .priv_size = sizeof(struct intel_host), 1325 }; 1326 1327 /* Define Host controllers for Intel Merrifield platform */ 1328 #define INTEL_MRFLD_EMMC_0 0 1329 #define INTEL_MRFLD_EMMC_1 1 1330 #define INTEL_MRFLD_SD 2 1331 #define INTEL_MRFLD_SDIO 3 1332 1333 #ifdef CONFIG_ACPI 1334 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) 1335 { 1336 struct acpi_device *device, *child; 1337 1338 device = ACPI_COMPANION(&slot->chip->pdev->dev); 1339 if (!device) 1340 return; 1341 1342 acpi_device_fix_up_power(device); 1343 list_for_each_entry(child, &device->children, node) 1344 if (child->status.present && child->status.enabled) 1345 acpi_device_fix_up_power(child); 1346 } 1347 #else 1348 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {} 1349 #endif 1350 1351 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 1352 { 1353 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 1354 1355 switch (func) { 1356 case INTEL_MRFLD_EMMC_0: 1357 case INTEL_MRFLD_EMMC_1: 1358 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1359 MMC_CAP_8_BIT_DATA | 1360 MMC_CAP_1_8V_DDR; 1361 break; 1362 case INTEL_MRFLD_SD: 1363 slot->cd_idx = 0; 1364 slot->cd_override_level = true; 1365 /* 1366 * There are two PCB designs of SD card slot with the opposite 1367 * card detection sense. Quirk this out by ignoring GPIO state 1368 * completely in the custom ->get_cd() callback. 1369 */ 1370 slot->host->mmc_host_ops.get_cd = mrfld_get_cd; 1371 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1372 break; 1373 case INTEL_MRFLD_SDIO: 1374 /* Advertise 2.0v for compatibility with the SDIO card's OCR */ 1375 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195; 1376 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1377 MMC_CAP_POWER_OFF_CARD; 1378 break; 1379 default: 1380 return -ENODEV; 1381 } 1382 1383 intel_mrfld_mmc_fix_up_power_slot(slot); 1384 return 0; 1385 } 1386 1387 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 1388 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1389 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 1390 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1391 .allow_runtime_pm = true, 1392 .probe_slot = intel_mrfld_mmc_probe_slot, 1393 }; 1394 1395 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 1396 { 1397 u8 scratch; 1398 int ret; 1399 1400 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 1401 if (ret) 1402 return ret; 1403 1404 /* 1405 * Turn PMOS on [bit 0], set over current detection to 2.4 V 1406 * [bit 1:2] and enable over current debouncing [bit 6]. 1407 */ 1408 if (on) 1409 scratch |= 0x47; 1410 else 1411 scratch &= ~0x47; 1412 1413 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 1414 } 1415 1416 static int jmicron_probe(struct sdhci_pci_chip *chip) 1417 { 1418 int ret; 1419 u16 mmcdev = 0; 1420 1421 if (chip->pdev->revision == 0) { 1422 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 1423 SDHCI_QUIRK_32BIT_DMA_SIZE | 1424 SDHCI_QUIRK_32BIT_ADMA_SIZE | 1425 SDHCI_QUIRK_RESET_AFTER_REQUEST | 1426 SDHCI_QUIRK_BROKEN_SMALL_PIO; 1427 } 1428 1429 /* 1430 * JMicron chips can have two interfaces to the same hardware 1431 * in order to work around limitations in Microsoft's driver. 1432 * We need to make sure we only bind to one of them. 1433 * 1434 * This code assumes two things: 1435 * 1436 * 1. The PCI code adds subfunctions in order. 1437 * 1438 * 2. The MMC interface has a lower subfunction number 1439 * than the SD interface. 1440 */ 1441 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 1442 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 1443 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 1444 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 1445 1446 if (mmcdev) { 1447 struct pci_dev *sd_dev; 1448 1449 sd_dev = NULL; 1450 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 1451 mmcdev, sd_dev)) != NULL) { 1452 if ((PCI_SLOT(chip->pdev->devfn) == 1453 PCI_SLOT(sd_dev->devfn)) && 1454 (chip->pdev->bus == sd_dev->bus)) 1455 break; 1456 } 1457 1458 if (sd_dev) { 1459 pci_dev_put(sd_dev); 1460 dev_info(&chip->pdev->dev, "Refusing to bind to " 1461 "secondary interface.\n"); 1462 return -ENODEV; 1463 } 1464 } 1465 1466 /* 1467 * JMicron chips need a bit of a nudge to enable the power 1468 * output pins. 1469 */ 1470 ret = jmicron_pmos(chip, 1); 1471 if (ret) { 1472 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1473 return ret; 1474 } 1475 1476 /* quirk for unsable RO-detection on JM388 chips */ 1477 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 1478 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1479 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 1480 1481 return 0; 1482 } 1483 1484 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 1485 { 1486 u8 scratch; 1487 1488 scratch = readb(host->ioaddr + 0xC0); 1489 1490 if (on) 1491 scratch |= 0x01; 1492 else 1493 scratch &= ~0x01; 1494 1495 writeb(scratch, host->ioaddr + 0xC0); 1496 } 1497 1498 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 1499 { 1500 if (slot->chip->pdev->revision == 0) { 1501 u16 version; 1502 1503 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 1504 version = (version & SDHCI_VENDOR_VER_MASK) >> 1505 SDHCI_VENDOR_VER_SHIFT; 1506 1507 /* 1508 * Older versions of the chip have lots of nasty glitches 1509 * in the ADMA engine. It's best just to avoid it 1510 * completely. 1511 */ 1512 if (version < 0xAC) 1513 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 1514 } 1515 1516 /* JM388 MMC doesn't support 1.8V while SD supports it */ 1517 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1518 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 1519 MMC_VDD_29_30 | MMC_VDD_30_31 | 1520 MMC_VDD_165_195; /* allow 1.8V */ 1521 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 1522 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 1523 } 1524 1525 /* 1526 * The secondary interface requires a bit set to get the 1527 * interrupts. 1528 */ 1529 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1530 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1531 jmicron_enable_mmc(slot->host, 1); 1532 1533 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 1534 1535 return 0; 1536 } 1537 1538 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 1539 { 1540 if (dead) 1541 return; 1542 1543 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1544 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1545 jmicron_enable_mmc(slot->host, 0); 1546 } 1547 1548 #ifdef CONFIG_PM_SLEEP 1549 static int jmicron_suspend(struct sdhci_pci_chip *chip) 1550 { 1551 int i, ret; 1552 1553 ret = sdhci_pci_suspend_host(chip); 1554 if (ret) 1555 return ret; 1556 1557 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1558 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1559 for (i = 0; i < chip->num_slots; i++) 1560 jmicron_enable_mmc(chip->slots[i]->host, 0); 1561 } 1562 1563 return 0; 1564 } 1565 1566 static int jmicron_resume(struct sdhci_pci_chip *chip) 1567 { 1568 int ret, i; 1569 1570 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1571 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1572 for (i = 0; i < chip->num_slots; i++) 1573 jmicron_enable_mmc(chip->slots[i]->host, 1); 1574 } 1575 1576 ret = jmicron_pmos(chip, 1); 1577 if (ret) { 1578 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1579 return ret; 1580 } 1581 1582 return sdhci_pci_resume_host(chip); 1583 } 1584 #endif 1585 1586 static const struct sdhci_pci_fixes sdhci_jmicron = { 1587 .probe = jmicron_probe, 1588 1589 .probe_slot = jmicron_probe_slot, 1590 .remove_slot = jmicron_remove_slot, 1591 1592 #ifdef CONFIG_PM_SLEEP 1593 .suspend = jmicron_suspend, 1594 .resume = jmicron_resume, 1595 #endif 1596 }; 1597 1598 /* SysKonnect CardBus2SDIO extra registers */ 1599 #define SYSKT_CTRL 0x200 1600 #define SYSKT_RDFIFO_STAT 0x204 1601 #define SYSKT_WRFIFO_STAT 0x208 1602 #define SYSKT_POWER_DATA 0x20c 1603 #define SYSKT_POWER_330 0xef 1604 #define SYSKT_POWER_300 0xf8 1605 #define SYSKT_POWER_184 0xcc 1606 #define SYSKT_POWER_CMD 0x20d 1607 #define SYSKT_POWER_START (1 << 7) 1608 #define SYSKT_POWER_STATUS 0x20e 1609 #define SYSKT_POWER_STATUS_OK (1 << 0) 1610 #define SYSKT_BOARD_REV 0x210 1611 #define SYSKT_CHIP_REV 0x211 1612 #define SYSKT_CONF_DATA 0x212 1613 #define SYSKT_CONF_DATA_1V8 (1 << 2) 1614 #define SYSKT_CONF_DATA_2V5 (1 << 1) 1615 #define SYSKT_CONF_DATA_3V3 (1 << 0) 1616 1617 static int syskt_probe(struct sdhci_pci_chip *chip) 1618 { 1619 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1620 chip->pdev->class &= ~0x0000FF; 1621 chip->pdev->class |= PCI_SDHCI_IFDMA; 1622 } 1623 return 0; 1624 } 1625 1626 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 1627 { 1628 int tm, ps; 1629 1630 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 1631 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 1632 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 1633 "board rev %d.%d, chip rev %d.%d\n", 1634 board_rev >> 4, board_rev & 0xf, 1635 chip_rev >> 4, chip_rev & 0xf); 1636 if (chip_rev >= 0x20) 1637 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 1638 1639 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 1640 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 1641 udelay(50); 1642 tm = 10; /* Wait max 1 ms */ 1643 do { 1644 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 1645 if (ps & SYSKT_POWER_STATUS_OK) 1646 break; 1647 udelay(100); 1648 } while (--tm); 1649 if (!tm) { 1650 dev_err(&slot->chip->pdev->dev, 1651 "power regulator never stabilized"); 1652 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 1653 return -ENODEV; 1654 } 1655 1656 return 0; 1657 } 1658 1659 static const struct sdhci_pci_fixes sdhci_syskt = { 1660 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 1661 .probe = syskt_probe, 1662 .probe_slot = syskt_probe_slot, 1663 }; 1664 1665 static int via_probe(struct sdhci_pci_chip *chip) 1666 { 1667 if (chip->pdev->revision == 0x10) 1668 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 1669 1670 return 0; 1671 } 1672 1673 static const struct sdhci_pci_fixes sdhci_via = { 1674 .probe = via_probe, 1675 }; 1676 1677 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 1678 { 1679 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 1680 return 0; 1681 } 1682 1683 static const struct sdhci_pci_fixes sdhci_rtsx = { 1684 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1685 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 1686 SDHCI_QUIRK2_BROKEN_DDR50, 1687 .probe_slot = rtsx_probe_slot, 1688 }; 1689 1690 /*AMD chipset generation*/ 1691 enum amd_chipset_gen { 1692 AMD_CHIPSET_BEFORE_ML, 1693 AMD_CHIPSET_CZ, 1694 AMD_CHIPSET_NL, 1695 AMD_CHIPSET_UNKNOWN, 1696 }; 1697 1698 /* AMD registers */ 1699 #define AMD_SD_AUTO_PATTERN 0xB8 1700 #define AMD_MSLEEP_DURATION 4 1701 #define AMD_SD_MISC_CONTROL 0xD0 1702 #define AMD_MAX_TUNE_VALUE 0x0B 1703 #define AMD_AUTO_TUNE_SEL 0x10800 1704 #define AMD_FIFO_PTR 0x30 1705 #define AMD_BIT_MASK 0x1F 1706 1707 static void amd_tuning_reset(struct sdhci_host *host) 1708 { 1709 unsigned int val; 1710 1711 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1712 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 1713 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1714 1715 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1716 val &= ~SDHCI_CTRL_EXEC_TUNING; 1717 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1718 } 1719 1720 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 1721 { 1722 unsigned int val; 1723 1724 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 1725 val &= ~AMD_BIT_MASK; 1726 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 1727 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 1728 } 1729 1730 static void amd_enable_manual_tuning(struct pci_dev *pdev) 1731 { 1732 unsigned int val; 1733 1734 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 1735 val |= AMD_FIFO_PTR; 1736 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 1737 } 1738 1739 static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode) 1740 { 1741 struct sdhci_pci_slot *slot = sdhci_priv(host); 1742 struct pci_dev *pdev = slot->chip->pdev; 1743 u8 valid_win = 0; 1744 u8 valid_win_max = 0; 1745 u8 valid_win_end = 0; 1746 u8 ctrl, tune_around; 1747 1748 amd_tuning_reset(host); 1749 1750 for (tune_around = 0; tune_around < 12; tune_around++) { 1751 amd_config_tuning_phase(pdev, tune_around); 1752 1753 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1754 valid_win = 0; 1755 msleep(AMD_MSLEEP_DURATION); 1756 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 1757 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 1758 } else if (++valid_win > valid_win_max) { 1759 valid_win_max = valid_win; 1760 valid_win_end = tune_around; 1761 } 1762 } 1763 1764 if (!valid_win_max) { 1765 dev_err(&pdev->dev, "no tuning point found\n"); 1766 return -EIO; 1767 } 1768 1769 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 1770 1771 amd_enable_manual_tuning(pdev); 1772 1773 host->mmc->retune_period = 0; 1774 1775 return 0; 1776 } 1777 1778 static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode) 1779 { 1780 struct sdhci_host *host = mmc_priv(mmc); 1781 1782 /* AMD requires custom HS200 tuning */ 1783 if (host->timing == MMC_TIMING_MMC_HS200) 1784 return amd_execute_tuning_hs200(host, opcode); 1785 1786 /* Otherwise perform standard SDHCI tuning */ 1787 return sdhci_execute_tuning(mmc, opcode); 1788 } 1789 1790 static int amd_probe_slot(struct sdhci_pci_slot *slot) 1791 { 1792 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 1793 1794 ops->execute_tuning = amd_execute_tuning; 1795 1796 return 0; 1797 } 1798 1799 static int amd_probe(struct sdhci_pci_chip *chip) 1800 { 1801 struct pci_dev *smbus_dev; 1802 enum amd_chipset_gen gen; 1803 1804 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1805 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 1806 if (smbus_dev) { 1807 gen = AMD_CHIPSET_BEFORE_ML; 1808 } else { 1809 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1810 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1811 if (smbus_dev) { 1812 if (smbus_dev->revision < 0x51) 1813 gen = AMD_CHIPSET_CZ; 1814 else 1815 gen = AMD_CHIPSET_NL; 1816 } else { 1817 gen = AMD_CHIPSET_UNKNOWN; 1818 } 1819 } 1820 1821 pci_dev_put(smbus_dev); 1822 1823 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1824 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1825 1826 return 0; 1827 } 1828 1829 static u32 sdhci_read_present_state(struct sdhci_host *host) 1830 { 1831 return sdhci_readl(host, SDHCI_PRESENT_STATE); 1832 } 1833 1834 static void amd_sdhci_reset(struct sdhci_host *host, u8 mask) 1835 { 1836 struct sdhci_pci_slot *slot = sdhci_priv(host); 1837 struct pci_dev *pdev = slot->chip->pdev; 1838 u32 present_state; 1839 1840 /* 1841 * SDHC 0x7906 requires a hard reset to clear all internal state. 1842 * Otherwise it can get into a bad state where the DATA lines are always 1843 * read as zeros. 1844 */ 1845 if (pdev->device == 0x7906 && (mask & SDHCI_RESET_ALL)) { 1846 pci_clear_master(pdev); 1847 1848 pci_save_state(pdev); 1849 1850 pci_set_power_state(pdev, PCI_D3cold); 1851 pr_debug("%s: power_state=%u\n", mmc_hostname(host->mmc), 1852 pdev->current_state); 1853 pci_set_power_state(pdev, PCI_D0); 1854 1855 pci_restore_state(pdev); 1856 1857 /* 1858 * SDHCI_RESET_ALL says the card detect logic should not be 1859 * reset, but since we need to reset the entire controller 1860 * we should wait until the card detect logic has stabilized. 1861 * 1862 * This normally takes about 40ms. 1863 */ 1864 readx_poll_timeout( 1865 sdhci_read_present_state, 1866 host, 1867 present_state, 1868 present_state & SDHCI_CD_STABLE, 1869 10000, 1870 100000 1871 ); 1872 } 1873 1874 return sdhci_reset(host, mask); 1875 } 1876 1877 static const struct sdhci_ops amd_sdhci_pci_ops = { 1878 .set_clock = sdhci_set_clock, 1879 .enable_dma = sdhci_pci_enable_dma, 1880 .set_bus_width = sdhci_set_bus_width, 1881 .reset = amd_sdhci_reset, 1882 .set_uhs_signaling = sdhci_set_uhs_signaling, 1883 }; 1884 1885 static const struct sdhci_pci_fixes sdhci_amd = { 1886 .probe = amd_probe, 1887 .ops = &amd_sdhci_pci_ops, 1888 .probe_slot = amd_probe_slot, 1889 }; 1890 1891 static const struct pci_device_id pci_ids[] = { 1892 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh), 1893 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc), 1894 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc), 1895 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc), 1896 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712), 1897 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712), 1898 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714), 1899 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714), 1900 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe), 1901 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron), 1902 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron), 1903 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron), 1904 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron), 1905 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt), 1906 SDHCI_PCI_DEVICE(VIA, 95D0, via), 1907 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx), 1908 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk), 1909 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0), 1910 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2), 1911 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2), 1912 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd), 1913 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio), 1914 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio), 1915 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc), 1916 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc), 1917 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio), 1918 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio), 1919 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc), 1920 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio), 1921 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio), 1922 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd), 1923 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc), 1924 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc), 1925 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio), 1926 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd), 1927 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd), 1928 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio), 1929 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio), 1930 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc), 1931 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc), 1932 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc), 1933 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc), 1934 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio), 1935 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd), 1936 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc), 1937 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc), 1938 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc), 1939 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio), 1940 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd), 1941 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc), 1942 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio), 1943 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd), 1944 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc), 1945 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio), 1946 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd), 1947 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc), 1948 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio), 1949 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd), 1950 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc), 1951 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd), 1952 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd), 1953 SDHCI_PCI_DEVICE(INTEL, ICP_EMMC, intel_glk_emmc), 1954 SDHCI_PCI_DEVICE(INTEL, ICP_SD, intel_byt_sd), 1955 SDHCI_PCI_DEVICE(INTEL, EHL_EMMC, intel_glk_emmc), 1956 SDHCI_PCI_DEVICE(INTEL, EHL_SD, intel_byt_sd), 1957 SDHCI_PCI_DEVICE(INTEL, CML_EMMC, intel_glk_emmc), 1958 SDHCI_PCI_DEVICE(INTEL, CML_SD, intel_byt_sd), 1959 SDHCI_PCI_DEVICE(INTEL, CMLH_SD, intel_byt_sd), 1960 SDHCI_PCI_DEVICE(INTEL, JSL_EMMC, intel_glk_emmc), 1961 SDHCI_PCI_DEVICE(INTEL, JSL_SD, intel_byt_sd), 1962 SDHCI_PCI_DEVICE(INTEL, LKF_EMMC, intel_glk_emmc), 1963 SDHCI_PCI_DEVICE(INTEL, LKF_SD, intel_byt_sd), 1964 SDHCI_PCI_DEVICE(INTEL, ADL_EMMC, intel_glk_emmc), 1965 SDHCI_PCI_DEVICE(O2, 8120, o2), 1966 SDHCI_PCI_DEVICE(O2, 8220, o2), 1967 SDHCI_PCI_DEVICE(O2, 8221, o2), 1968 SDHCI_PCI_DEVICE(O2, 8320, o2), 1969 SDHCI_PCI_DEVICE(O2, 8321, o2), 1970 SDHCI_PCI_DEVICE(O2, FUJIN2, o2), 1971 SDHCI_PCI_DEVICE(O2, SDS0, o2), 1972 SDHCI_PCI_DEVICE(O2, SDS1, o2), 1973 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2), 1974 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), 1975 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan), 1976 SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps), 1977 SDHCI_PCI_DEVICE(GLI, 9750, gl9750), 1978 SDHCI_PCI_DEVICE(GLI, 9755, gl9755), 1979 SDHCI_PCI_DEVICE(GLI, 9763E, gl9763e), 1980 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), 1981 /* Generic SD host controller */ 1982 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, 1983 { /* end: all zeroes */ }, 1984 }; 1985 1986 MODULE_DEVICE_TABLE(pci, pci_ids); 1987 1988 /*****************************************************************************\ 1989 * * 1990 * SDHCI core callbacks * 1991 * * 1992 \*****************************************************************************/ 1993 1994 int sdhci_pci_enable_dma(struct sdhci_host *host) 1995 { 1996 struct sdhci_pci_slot *slot; 1997 struct pci_dev *pdev; 1998 1999 slot = sdhci_priv(host); 2000 pdev = slot->chip->pdev; 2001 2002 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 2003 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 2004 (host->flags & SDHCI_USE_SDMA)) { 2005 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 2006 "doesn't fully claim to support it.\n"); 2007 } 2008 2009 pci_set_master(pdev); 2010 2011 return 0; 2012 } 2013 2014 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 2015 { 2016 struct sdhci_pci_slot *slot = sdhci_priv(host); 2017 int rst_n_gpio = slot->rst_n_gpio; 2018 2019 if (!gpio_is_valid(rst_n_gpio)) 2020 return; 2021 gpio_set_value_cansleep(rst_n_gpio, 0); 2022 /* For eMMC, minimum is 1us but give it 10us for good measure */ 2023 udelay(10); 2024 gpio_set_value_cansleep(rst_n_gpio, 1); 2025 /* For eMMC, minimum is 200us but give it 300us for good measure */ 2026 usleep_range(300, 1000); 2027 } 2028 2029 static void sdhci_pci_hw_reset(struct sdhci_host *host) 2030 { 2031 struct sdhci_pci_slot *slot = sdhci_priv(host); 2032 2033 if (slot->hw_reset) 2034 slot->hw_reset(host); 2035 } 2036 2037 static const struct sdhci_ops sdhci_pci_ops = { 2038 .set_clock = sdhci_set_clock, 2039 .enable_dma = sdhci_pci_enable_dma, 2040 .set_bus_width = sdhci_set_bus_width, 2041 .reset = sdhci_reset, 2042 .set_uhs_signaling = sdhci_set_uhs_signaling, 2043 .hw_reset = sdhci_pci_hw_reset, 2044 }; 2045 2046 /*****************************************************************************\ 2047 * * 2048 * Suspend/resume * 2049 * * 2050 \*****************************************************************************/ 2051 2052 #ifdef CONFIG_PM_SLEEP 2053 static int sdhci_pci_suspend(struct device *dev) 2054 { 2055 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2056 2057 if (!chip) 2058 return 0; 2059 2060 if (chip->fixes && chip->fixes->suspend) 2061 return chip->fixes->suspend(chip); 2062 2063 return sdhci_pci_suspend_host(chip); 2064 } 2065 2066 static int sdhci_pci_resume(struct device *dev) 2067 { 2068 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2069 2070 if (!chip) 2071 return 0; 2072 2073 if (chip->fixes && chip->fixes->resume) 2074 return chip->fixes->resume(chip); 2075 2076 return sdhci_pci_resume_host(chip); 2077 } 2078 #endif 2079 2080 #ifdef CONFIG_PM 2081 static int sdhci_pci_runtime_suspend(struct device *dev) 2082 { 2083 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2084 2085 if (!chip) 2086 return 0; 2087 2088 if (chip->fixes && chip->fixes->runtime_suspend) 2089 return chip->fixes->runtime_suspend(chip); 2090 2091 return sdhci_pci_runtime_suspend_host(chip); 2092 } 2093 2094 static int sdhci_pci_runtime_resume(struct device *dev) 2095 { 2096 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2097 2098 if (!chip) 2099 return 0; 2100 2101 if (chip->fixes && chip->fixes->runtime_resume) 2102 return chip->fixes->runtime_resume(chip); 2103 2104 return sdhci_pci_runtime_resume_host(chip); 2105 } 2106 #endif 2107 2108 static const struct dev_pm_ops sdhci_pci_pm_ops = { 2109 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 2110 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 2111 sdhci_pci_runtime_resume, NULL) 2112 }; 2113 2114 /*****************************************************************************\ 2115 * * 2116 * Device probing/removal * 2117 * * 2118 \*****************************************************************************/ 2119 2120 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 2121 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 2122 int slotno) 2123 { 2124 struct sdhci_pci_slot *slot; 2125 struct sdhci_host *host; 2126 int ret, bar = first_bar + slotno; 2127 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 2128 2129 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 2130 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 2131 return ERR_PTR(-ENODEV); 2132 } 2133 2134 if (pci_resource_len(pdev, bar) < 0x100) { 2135 dev_err(&pdev->dev, "Invalid iomem size. You may " 2136 "experience problems.\n"); 2137 } 2138 2139 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 2140 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 2141 return ERR_PTR(-ENODEV); 2142 } 2143 2144 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 2145 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 2146 return ERR_PTR(-ENODEV); 2147 } 2148 2149 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 2150 if (IS_ERR(host)) { 2151 dev_err(&pdev->dev, "cannot allocate host\n"); 2152 return ERR_CAST(host); 2153 } 2154 2155 slot = sdhci_priv(host); 2156 2157 slot->chip = chip; 2158 slot->host = host; 2159 slot->rst_n_gpio = -EINVAL; 2160 slot->cd_gpio = -EINVAL; 2161 slot->cd_idx = -1; 2162 2163 /* Retrieve platform data if there is any */ 2164 if (*sdhci_pci_get_data) 2165 slot->data = sdhci_pci_get_data(pdev, slotno); 2166 2167 if (slot->data) { 2168 if (slot->data->setup) { 2169 ret = slot->data->setup(slot->data); 2170 if (ret) { 2171 dev_err(&pdev->dev, "platform setup failed\n"); 2172 goto free; 2173 } 2174 } 2175 slot->rst_n_gpio = slot->data->rst_n_gpio; 2176 slot->cd_gpio = slot->data->cd_gpio; 2177 } 2178 2179 host->hw_name = "PCI"; 2180 host->ops = chip->fixes && chip->fixes->ops ? 2181 chip->fixes->ops : 2182 &sdhci_pci_ops; 2183 host->quirks = chip->quirks; 2184 host->quirks2 = chip->quirks2; 2185 2186 host->irq = pdev->irq; 2187 2188 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 2189 if (ret) { 2190 dev_err(&pdev->dev, "cannot request region\n"); 2191 goto cleanup; 2192 } 2193 2194 host->ioaddr = pcim_iomap_table(pdev)[bar]; 2195 2196 if (chip->fixes && chip->fixes->probe_slot) { 2197 ret = chip->fixes->probe_slot(slot); 2198 if (ret) 2199 goto cleanup; 2200 } 2201 2202 if (gpio_is_valid(slot->rst_n_gpio)) { 2203 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 2204 gpio_direction_output(slot->rst_n_gpio, 1); 2205 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 2206 slot->hw_reset = sdhci_pci_gpio_hw_reset; 2207 } else { 2208 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 2209 slot->rst_n_gpio = -EINVAL; 2210 } 2211 } 2212 2213 host->mmc->pm_caps = MMC_PM_KEEP_POWER; 2214 host->mmc->slotno = slotno; 2215 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 2216 2217 if (device_can_wakeup(&pdev->dev)) 2218 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ; 2219 2220 if (host->mmc->caps & MMC_CAP_CD_WAKE) 2221 device_init_wakeup(&pdev->dev, true); 2222 2223 if (slot->cd_idx >= 0) { 2224 ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx, 2225 slot->cd_override_level, 0); 2226 if (ret && ret != -EPROBE_DEFER) 2227 ret = mmc_gpiod_request_cd(host->mmc, NULL, 2228 slot->cd_idx, 2229 slot->cd_override_level, 2230 0); 2231 if (ret == -EPROBE_DEFER) 2232 goto remove; 2233 2234 if (ret) { 2235 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 2236 slot->cd_idx = -1; 2237 } 2238 } 2239 2240 if (chip->fixes && chip->fixes->add_host) 2241 ret = chip->fixes->add_host(slot); 2242 else 2243 ret = sdhci_add_host(host); 2244 if (ret) 2245 goto remove; 2246 2247 sdhci_pci_add_own_cd(slot); 2248 2249 /* 2250 * Check if the chip needs a separate GPIO for card detect to wake up 2251 * from runtime suspend. If it is not there, don't allow runtime PM. 2252 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 2253 */ 2254 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 2255 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 2256 chip->allow_runtime_pm = false; 2257 2258 return slot; 2259 2260 remove: 2261 if (chip->fixes && chip->fixes->remove_slot) 2262 chip->fixes->remove_slot(slot, 0); 2263 2264 cleanup: 2265 if (slot->data && slot->data->cleanup) 2266 slot->data->cleanup(slot->data); 2267 2268 free: 2269 sdhci_free_host(host); 2270 2271 return ERR_PTR(ret); 2272 } 2273 2274 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 2275 { 2276 int dead; 2277 u32 scratch; 2278 2279 sdhci_pci_remove_own_cd(slot); 2280 2281 dead = 0; 2282 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 2283 if (scratch == (u32)-1) 2284 dead = 1; 2285 2286 sdhci_remove_host(slot->host, dead); 2287 2288 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 2289 slot->chip->fixes->remove_slot(slot, dead); 2290 2291 if (slot->data && slot->data->cleanup) 2292 slot->data->cleanup(slot->data); 2293 2294 sdhci_free_host(slot->host); 2295 } 2296 2297 static void sdhci_pci_runtime_pm_allow(struct device *dev) 2298 { 2299 pm_suspend_ignore_children(dev, 1); 2300 pm_runtime_set_autosuspend_delay(dev, 50); 2301 pm_runtime_use_autosuspend(dev); 2302 pm_runtime_allow(dev); 2303 /* Stay active until mmc core scans for a card */ 2304 pm_runtime_put_noidle(dev); 2305 } 2306 2307 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 2308 { 2309 pm_runtime_forbid(dev); 2310 pm_runtime_get_noresume(dev); 2311 } 2312 2313 static int sdhci_pci_probe(struct pci_dev *pdev, 2314 const struct pci_device_id *ent) 2315 { 2316 struct sdhci_pci_chip *chip; 2317 struct sdhci_pci_slot *slot; 2318 2319 u8 slots, first_bar; 2320 int ret, i; 2321 2322 BUG_ON(pdev == NULL); 2323 BUG_ON(ent == NULL); 2324 2325 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 2326 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 2327 2328 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 2329 if (ret) 2330 return ret; 2331 2332 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 2333 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 2334 2335 BUG_ON(slots > MAX_SLOTS); 2336 2337 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 2338 if (ret) 2339 return ret; 2340 2341 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 2342 2343 if (first_bar > 5) { 2344 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 2345 return -ENODEV; 2346 } 2347 2348 ret = pcim_enable_device(pdev); 2349 if (ret) 2350 return ret; 2351 2352 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 2353 if (!chip) 2354 return -ENOMEM; 2355 2356 chip->pdev = pdev; 2357 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 2358 if (chip->fixes) { 2359 chip->quirks = chip->fixes->quirks; 2360 chip->quirks2 = chip->fixes->quirks2; 2361 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 2362 } 2363 chip->num_slots = slots; 2364 chip->pm_retune = true; 2365 chip->rpm_retune = true; 2366 2367 pci_set_drvdata(pdev, chip); 2368 2369 if (chip->fixes && chip->fixes->probe) { 2370 ret = chip->fixes->probe(chip); 2371 if (ret) 2372 return ret; 2373 } 2374 2375 slots = chip->num_slots; /* Quirk may have changed this */ 2376 2377 for (i = 0; i < slots; i++) { 2378 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 2379 if (IS_ERR(slot)) { 2380 for (i--; i >= 0; i--) 2381 sdhci_pci_remove_slot(chip->slots[i]); 2382 return PTR_ERR(slot); 2383 } 2384 2385 chip->slots[i] = slot; 2386 } 2387 2388 if (chip->allow_runtime_pm) 2389 sdhci_pci_runtime_pm_allow(&pdev->dev); 2390 2391 return 0; 2392 } 2393 2394 static void sdhci_pci_remove(struct pci_dev *pdev) 2395 { 2396 int i; 2397 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 2398 2399 if (chip->allow_runtime_pm) 2400 sdhci_pci_runtime_pm_forbid(&pdev->dev); 2401 2402 for (i = 0; i < chip->num_slots; i++) 2403 sdhci_pci_remove_slot(chip->slots[i]); 2404 } 2405 2406 static struct pci_driver sdhci_driver = { 2407 .name = "sdhci-pci", 2408 .id_table = pci_ids, 2409 .probe = sdhci_pci_probe, 2410 .remove = sdhci_pci_remove, 2411 .driver = { 2412 .pm = &sdhci_pci_pm_ops 2413 }, 2414 }; 2415 2416 module_pci_driver(sdhci_driver); 2417 2418 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 2419 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 2420 MODULE_LICENSE("GPL"); 2421