1 /*  linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2  *
3  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation; either version 2 of the License, or (at
8  * your option) any later version.
9  *
10  * Thanks to the following companies for their support:
11  *
12  *     - JMicron (hardware and technical support)
13  */
14 
15 #include <linux/delay.h>
16 #include <linux/highmem.h>
17 #include <linux/module.h>
18 #include <linux/pci.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/device.h>
22 #include <linux/mmc/host.h>
23 #include <linux/mmc/mmc.h>
24 #include <linux/scatterlist.h>
25 #include <linux/io.h>
26 #include <linux/gpio.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/mmc/slot-gpio.h>
29 #include <linux/mmc/sdhci-pci-data.h>
30 
31 #include "sdhci.h"
32 #include "sdhci-pci.h"
33 #include "sdhci-pci-o2micro.h"
34 
35 /*****************************************************************************\
36  *                                                                           *
37  * Hardware specific quirk handling                                          *
38  *                                                                           *
39 \*****************************************************************************/
40 
41 static int ricoh_probe(struct sdhci_pci_chip *chip)
42 {
43 	if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
44 	    chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
45 		chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
46 	return 0;
47 }
48 
49 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
50 {
51 	slot->host->caps =
52 		((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
53 			& SDHCI_TIMEOUT_CLK_MASK) |
54 
55 		((0x21 << SDHCI_CLOCK_BASE_SHIFT)
56 			& SDHCI_CLOCK_BASE_MASK) |
57 
58 		SDHCI_TIMEOUT_CLK_UNIT |
59 		SDHCI_CAN_VDD_330 |
60 		SDHCI_CAN_DO_HISPD |
61 		SDHCI_CAN_DO_SDMA;
62 	return 0;
63 }
64 
65 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
66 {
67 	/* Apply a delay to allow controller to settle */
68 	/* Otherwise it becomes confused if card state changed
69 		during suspend */
70 	msleep(500);
71 	return 0;
72 }
73 
74 static const struct sdhci_pci_fixes sdhci_ricoh = {
75 	.probe		= ricoh_probe,
76 	.quirks		= SDHCI_QUIRK_32BIT_DMA_ADDR |
77 			  SDHCI_QUIRK_FORCE_DMA |
78 			  SDHCI_QUIRK_CLOCK_BEFORE_RESET,
79 };
80 
81 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
82 	.probe_slot	= ricoh_mmc_probe_slot,
83 	.resume		= ricoh_mmc_resume,
84 	.quirks		= SDHCI_QUIRK_32BIT_DMA_ADDR |
85 			  SDHCI_QUIRK_CLOCK_BEFORE_RESET |
86 			  SDHCI_QUIRK_NO_CARD_NO_RESET |
87 			  SDHCI_QUIRK_MISSING_CAPS
88 };
89 
90 static const struct sdhci_pci_fixes sdhci_ene_712 = {
91 	.quirks		= SDHCI_QUIRK_SINGLE_POWER_WRITE |
92 			  SDHCI_QUIRK_BROKEN_DMA,
93 };
94 
95 static const struct sdhci_pci_fixes sdhci_ene_714 = {
96 	.quirks		= SDHCI_QUIRK_SINGLE_POWER_WRITE |
97 			  SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
98 			  SDHCI_QUIRK_BROKEN_DMA,
99 };
100 
101 static const struct sdhci_pci_fixes sdhci_cafe = {
102 	.quirks		= SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
103 			  SDHCI_QUIRK_NO_BUSY_IRQ |
104 			  SDHCI_QUIRK_BROKEN_CARD_DETECTION |
105 			  SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
106 };
107 
108 static const struct sdhci_pci_fixes sdhci_intel_qrk = {
109 	.quirks		= SDHCI_QUIRK_NO_HISPD_BIT,
110 };
111 
112 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
113 {
114 	slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
115 	return 0;
116 }
117 
118 /*
119  * ADMA operation is disabled for Moorestown platform due to
120  * hardware bugs.
121  */
122 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
123 {
124 	/*
125 	 * slots number is fixed here for MRST as SDIO3/5 are never used and
126 	 * have hardware bugs.
127 	 */
128 	chip->num_slots = 1;
129 	return 0;
130 }
131 
132 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
133 {
134 	slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
135 	return 0;
136 }
137 
138 #ifdef CONFIG_PM
139 
140 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
141 {
142 	struct sdhci_pci_slot *slot = dev_id;
143 	struct sdhci_host *host = slot->host;
144 
145 	mmc_detect_change(host->mmc, msecs_to_jiffies(200));
146 	return IRQ_HANDLED;
147 }
148 
149 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
150 {
151 	int err, irq, gpio = slot->cd_gpio;
152 
153 	slot->cd_gpio = -EINVAL;
154 	slot->cd_irq = -EINVAL;
155 
156 	if (!gpio_is_valid(gpio))
157 		return;
158 
159 	err = gpio_request(gpio, "sd_cd");
160 	if (err < 0)
161 		goto out;
162 
163 	err = gpio_direction_input(gpio);
164 	if (err < 0)
165 		goto out_free;
166 
167 	irq = gpio_to_irq(gpio);
168 	if (irq < 0)
169 		goto out_free;
170 
171 	err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
172 			  IRQF_TRIGGER_FALLING, "sd_cd", slot);
173 	if (err)
174 		goto out_free;
175 
176 	slot->cd_gpio = gpio;
177 	slot->cd_irq = irq;
178 
179 	return;
180 
181 out_free:
182 	gpio_free(gpio);
183 out:
184 	dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
185 }
186 
187 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
188 {
189 	if (slot->cd_irq >= 0)
190 		free_irq(slot->cd_irq, slot);
191 	if (gpio_is_valid(slot->cd_gpio))
192 		gpio_free(slot->cd_gpio);
193 }
194 
195 #else
196 
197 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
198 {
199 }
200 
201 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
202 {
203 }
204 
205 #endif
206 
207 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
208 {
209 	slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
210 	slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC |
211 				  MMC_CAP2_HC_ERASE_SZ;
212 	return 0;
213 }
214 
215 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
216 {
217 	slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
218 	return 0;
219 }
220 
221 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
222 	.quirks		= SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
223 	.probe_slot	= mrst_hc_probe_slot,
224 };
225 
226 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
227 	.quirks		= SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
228 	.probe		= mrst_hc_probe,
229 };
230 
231 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
232 	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
233 	.allow_runtime_pm = true,
234 	.own_cd_for_runtime_pm = true,
235 };
236 
237 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
238 	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
239 	.quirks2	= SDHCI_QUIRK2_HOST_OFF_CARD_ON,
240 	.allow_runtime_pm = true,
241 	.probe_slot	= mfd_sdio_probe_slot,
242 };
243 
244 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
245 	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
246 	.allow_runtime_pm = true,
247 	.probe_slot	= mfd_emmc_probe_slot,
248 };
249 
250 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
251 	.quirks		= SDHCI_QUIRK_BROKEN_ADMA,
252 	.probe_slot	= pch_hc_probe_slot,
253 };
254 
255 static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
256 {
257 	u8 reg;
258 
259 	reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
260 	reg |= 0x10;
261 	sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
262 	/* For eMMC, minimum is 1us but give it 9us for good measure */
263 	udelay(9);
264 	reg &= ~0x10;
265 	sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
266 	/* For eMMC, minimum is 200us but give it 300us for good measure */
267 	usleep_range(300, 1000);
268 }
269 
270 static int spt_select_drive_strength(struct sdhci_host *host,
271 				     struct mmc_card *card,
272 				     unsigned int max_dtr,
273 				     int host_drv, int card_drv, int *drv_type)
274 {
275 	int drive_strength;
276 
277 	if (sdhci_pci_spt_drive_strength > 0)
278 		drive_strength = sdhci_pci_spt_drive_strength & 0xf;
279 	else
280 		drive_strength = 1; /* 33-ohm */
281 
282 	if ((mmc_driver_type_mask(drive_strength) & card_drv) == 0)
283 		drive_strength = 0; /* Default 50-ohm */
284 
285 	return drive_strength;
286 }
287 
288 /* Try to read the drive strength from the card */
289 static void spt_read_drive_strength(struct sdhci_host *host)
290 {
291 	u32 val, i, t;
292 	u16 m;
293 
294 	if (sdhci_pci_spt_drive_strength)
295 		return;
296 
297 	sdhci_pci_spt_drive_strength = -1;
298 
299 	m = sdhci_readw(host, SDHCI_HOST_CONTROL2) & 0x7;
300 	if (m != 3 && m != 5)
301 		return;
302 	val = sdhci_readl(host, SDHCI_PRESENT_STATE);
303 	if (val & 0x3)
304 		return;
305 	sdhci_writel(host, 0x007f0023, SDHCI_INT_ENABLE);
306 	sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
307 	sdhci_writew(host, 0x10, SDHCI_TRANSFER_MODE);
308 	sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
309 	sdhci_writew(host, 512, SDHCI_BLOCK_SIZE);
310 	sdhci_writew(host, 1, SDHCI_BLOCK_COUNT);
311 	sdhci_writel(host, 0, SDHCI_ARGUMENT);
312 	sdhci_writew(host, 0x83b, SDHCI_COMMAND);
313 	for (i = 0; i < 1000; i++) {
314 		val = sdhci_readl(host, SDHCI_INT_STATUS);
315 		if (val & 0xffff8000)
316 			return;
317 		if (val & 0x20)
318 			break;
319 		udelay(1);
320 	}
321 	val = sdhci_readl(host, SDHCI_PRESENT_STATE);
322 	if (!(val & 0x800))
323 		return;
324 	for (i = 0; i < 47; i++)
325 		val = sdhci_readl(host, SDHCI_BUFFER);
326 	t = val & 0xf00;
327 	if (t != 0x200 && t != 0x300)
328 		return;
329 
330 	sdhci_pci_spt_drive_strength = 0x10 | ((val >> 12) & 0xf);
331 }
332 
333 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
334 {
335 	slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
336 				 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
337 				 MMC_CAP_BUS_WIDTH_TEST |
338 				 MMC_CAP_WAIT_WHILE_BUSY;
339 	slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
340 	slot->hw_reset = sdhci_pci_int_hw_reset;
341 	if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
342 		slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
343 	if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_SPT_EMMC) {
344 		spt_read_drive_strength(slot->host);
345 		slot->select_drive_strength = spt_select_drive_strength;
346 	}
347 	return 0;
348 }
349 
350 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
351 {
352 	slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
353 				 MMC_CAP_BUS_WIDTH_TEST |
354 				 MMC_CAP_WAIT_WHILE_BUSY;
355 	return 0;
356 }
357 
358 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
359 {
360 	slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST |
361 				 MMC_CAP_WAIT_WHILE_BUSY;
362 	slot->cd_con_id = NULL;
363 	slot->cd_idx = 0;
364 	slot->cd_override_level = true;
365 	return 0;
366 }
367 
368 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
369 	.allow_runtime_pm = true,
370 	.probe_slot	= byt_emmc_probe_slot,
371 	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
372 	.quirks2	= SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
373 			  SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
374 			  SDHCI_QUIRK2_STOP_WITH_TC,
375 };
376 
377 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
378 	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
379 	.quirks2	= SDHCI_QUIRK2_HOST_OFF_CARD_ON |
380 			SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
381 	.allow_runtime_pm = true,
382 	.probe_slot	= byt_sdio_probe_slot,
383 };
384 
385 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
386 	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
387 	.quirks2	= SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
388 			  SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
389 			  SDHCI_QUIRK2_STOP_WITH_TC,
390 	.allow_runtime_pm = true,
391 	.own_cd_for_runtime_pm = true,
392 	.probe_slot	= byt_sd_probe_slot,
393 };
394 
395 /* Define Host controllers for Intel Merrifield platform */
396 #define INTEL_MRFL_EMMC_0	0
397 #define INTEL_MRFL_EMMC_1	1
398 
399 static int intel_mrfl_mmc_probe_slot(struct sdhci_pci_slot *slot)
400 {
401 	if ((PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_0) &&
402 	    (PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_1))
403 		/* SD support is not ready yet */
404 		return -ENODEV;
405 
406 	slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
407 				 MMC_CAP_1_8V_DDR;
408 
409 	return 0;
410 }
411 
412 static const struct sdhci_pci_fixes sdhci_intel_mrfl_mmc = {
413 	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
414 	.quirks2	= SDHCI_QUIRK2_BROKEN_HS200 |
415 			SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
416 	.allow_runtime_pm = true,
417 	.probe_slot	= intel_mrfl_mmc_probe_slot,
418 };
419 
420 /* O2Micro extra registers */
421 #define O2_SD_LOCK_WP		0xD3
422 #define O2_SD_MULTI_VCC3V	0xEE
423 #define O2_SD_CLKREQ		0xEC
424 #define O2_SD_CAPS		0xE0
425 #define O2_SD_ADMA1		0xE2
426 #define O2_SD_ADMA2		0xE7
427 #define O2_SD_INF_MOD		0xF1
428 
429 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
430 {
431 	u8 scratch;
432 	int ret;
433 
434 	ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
435 	if (ret)
436 		return ret;
437 
438 	/*
439 	 * Turn PMOS on [bit 0], set over current detection to 2.4 V
440 	 * [bit 1:2] and enable over current debouncing [bit 6].
441 	 */
442 	if (on)
443 		scratch |= 0x47;
444 	else
445 		scratch &= ~0x47;
446 
447 	return pci_write_config_byte(chip->pdev, 0xAE, scratch);
448 }
449 
450 static int jmicron_probe(struct sdhci_pci_chip *chip)
451 {
452 	int ret;
453 	u16 mmcdev = 0;
454 
455 	if (chip->pdev->revision == 0) {
456 		chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
457 			  SDHCI_QUIRK_32BIT_DMA_SIZE |
458 			  SDHCI_QUIRK_32BIT_ADMA_SIZE |
459 			  SDHCI_QUIRK_RESET_AFTER_REQUEST |
460 			  SDHCI_QUIRK_BROKEN_SMALL_PIO;
461 	}
462 
463 	/*
464 	 * JMicron chips can have two interfaces to the same hardware
465 	 * in order to work around limitations in Microsoft's driver.
466 	 * We need to make sure we only bind to one of them.
467 	 *
468 	 * This code assumes two things:
469 	 *
470 	 * 1. The PCI code adds subfunctions in order.
471 	 *
472 	 * 2. The MMC interface has a lower subfunction number
473 	 *    than the SD interface.
474 	 */
475 	if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
476 		mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
477 	else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
478 		mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
479 
480 	if (mmcdev) {
481 		struct pci_dev *sd_dev;
482 
483 		sd_dev = NULL;
484 		while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
485 						mmcdev, sd_dev)) != NULL) {
486 			if ((PCI_SLOT(chip->pdev->devfn) ==
487 				PCI_SLOT(sd_dev->devfn)) &&
488 				(chip->pdev->bus == sd_dev->bus))
489 				break;
490 		}
491 
492 		if (sd_dev) {
493 			pci_dev_put(sd_dev);
494 			dev_info(&chip->pdev->dev, "Refusing to bind to "
495 				"secondary interface.\n");
496 			return -ENODEV;
497 		}
498 	}
499 
500 	/*
501 	 * JMicron chips need a bit of a nudge to enable the power
502 	 * output pins.
503 	 */
504 	ret = jmicron_pmos(chip, 1);
505 	if (ret) {
506 		dev_err(&chip->pdev->dev, "Failure enabling card power\n");
507 		return ret;
508 	}
509 
510 	/* quirk for unsable RO-detection on JM388 chips */
511 	if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
512 	    chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
513 		chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
514 
515 	return 0;
516 }
517 
518 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
519 {
520 	u8 scratch;
521 
522 	scratch = readb(host->ioaddr + 0xC0);
523 
524 	if (on)
525 		scratch |= 0x01;
526 	else
527 		scratch &= ~0x01;
528 
529 	writeb(scratch, host->ioaddr + 0xC0);
530 }
531 
532 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
533 {
534 	if (slot->chip->pdev->revision == 0) {
535 		u16 version;
536 
537 		version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
538 		version = (version & SDHCI_VENDOR_VER_MASK) >>
539 			SDHCI_VENDOR_VER_SHIFT;
540 
541 		/*
542 		 * Older versions of the chip have lots of nasty glitches
543 		 * in the ADMA engine. It's best just to avoid it
544 		 * completely.
545 		 */
546 		if (version < 0xAC)
547 			slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
548 	}
549 
550 	/* JM388 MMC doesn't support 1.8V while SD supports it */
551 	if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
552 		slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
553 			MMC_VDD_29_30 | MMC_VDD_30_31 |
554 			MMC_VDD_165_195; /* allow 1.8V */
555 		slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
556 			MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
557 	}
558 
559 	/*
560 	 * The secondary interface requires a bit set to get the
561 	 * interrupts.
562 	 */
563 	if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
564 	    slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
565 		jmicron_enable_mmc(slot->host, 1);
566 
567 	slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
568 
569 	return 0;
570 }
571 
572 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
573 {
574 	if (dead)
575 		return;
576 
577 	if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
578 	    slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
579 		jmicron_enable_mmc(slot->host, 0);
580 }
581 
582 static int jmicron_suspend(struct sdhci_pci_chip *chip)
583 {
584 	int i;
585 
586 	if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
587 	    chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
588 		for (i = 0; i < chip->num_slots; i++)
589 			jmicron_enable_mmc(chip->slots[i]->host, 0);
590 	}
591 
592 	return 0;
593 }
594 
595 static int jmicron_resume(struct sdhci_pci_chip *chip)
596 {
597 	int ret, i;
598 
599 	if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
600 	    chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
601 		for (i = 0; i < chip->num_slots; i++)
602 			jmicron_enable_mmc(chip->slots[i]->host, 1);
603 	}
604 
605 	ret = jmicron_pmos(chip, 1);
606 	if (ret) {
607 		dev_err(&chip->pdev->dev, "Failure enabling card power\n");
608 		return ret;
609 	}
610 
611 	return 0;
612 }
613 
614 static const struct sdhci_pci_fixes sdhci_o2 = {
615 	.probe = sdhci_pci_o2_probe,
616 	.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
617 	.quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
618 	.probe_slot = sdhci_pci_o2_probe_slot,
619 	.resume = sdhci_pci_o2_resume,
620 };
621 
622 static const struct sdhci_pci_fixes sdhci_jmicron = {
623 	.probe		= jmicron_probe,
624 
625 	.probe_slot	= jmicron_probe_slot,
626 	.remove_slot	= jmicron_remove_slot,
627 
628 	.suspend	= jmicron_suspend,
629 	.resume		= jmicron_resume,
630 };
631 
632 /* SysKonnect CardBus2SDIO extra registers */
633 #define SYSKT_CTRL		0x200
634 #define SYSKT_RDFIFO_STAT	0x204
635 #define SYSKT_WRFIFO_STAT	0x208
636 #define SYSKT_POWER_DATA	0x20c
637 #define   SYSKT_POWER_330	0xef
638 #define   SYSKT_POWER_300	0xf8
639 #define   SYSKT_POWER_184	0xcc
640 #define SYSKT_POWER_CMD		0x20d
641 #define   SYSKT_POWER_START	(1 << 7)
642 #define SYSKT_POWER_STATUS	0x20e
643 #define   SYSKT_POWER_STATUS_OK	(1 << 0)
644 #define SYSKT_BOARD_REV		0x210
645 #define SYSKT_CHIP_REV		0x211
646 #define SYSKT_CONF_DATA		0x212
647 #define   SYSKT_CONF_DATA_1V8	(1 << 2)
648 #define   SYSKT_CONF_DATA_2V5	(1 << 1)
649 #define   SYSKT_CONF_DATA_3V3	(1 << 0)
650 
651 static int syskt_probe(struct sdhci_pci_chip *chip)
652 {
653 	if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
654 		chip->pdev->class &= ~0x0000FF;
655 		chip->pdev->class |= PCI_SDHCI_IFDMA;
656 	}
657 	return 0;
658 }
659 
660 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
661 {
662 	int tm, ps;
663 
664 	u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
665 	u8  chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
666 	dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
667 					 "board rev %d.%d, chip rev %d.%d\n",
668 					 board_rev >> 4, board_rev & 0xf,
669 					 chip_rev >> 4,  chip_rev & 0xf);
670 	if (chip_rev >= 0x20)
671 		slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
672 
673 	writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
674 	writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
675 	udelay(50);
676 	tm = 10;  /* Wait max 1 ms */
677 	do {
678 		ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
679 		if (ps & SYSKT_POWER_STATUS_OK)
680 			break;
681 		udelay(100);
682 	} while (--tm);
683 	if (!tm) {
684 		dev_err(&slot->chip->pdev->dev,
685 			"power regulator never stabilized");
686 		writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
687 		return -ENODEV;
688 	}
689 
690 	return 0;
691 }
692 
693 static const struct sdhci_pci_fixes sdhci_syskt = {
694 	.quirks		= SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
695 	.probe		= syskt_probe,
696 	.probe_slot	= syskt_probe_slot,
697 };
698 
699 static int via_probe(struct sdhci_pci_chip *chip)
700 {
701 	if (chip->pdev->revision == 0x10)
702 		chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
703 
704 	return 0;
705 }
706 
707 static const struct sdhci_pci_fixes sdhci_via = {
708 	.probe		= via_probe,
709 };
710 
711 static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
712 {
713 	slot->host->mmc->caps2 |= MMC_CAP2_HS200;
714 	return 0;
715 }
716 
717 static const struct sdhci_pci_fixes sdhci_rtsx = {
718 	.quirks2	= SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
719 			SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
720 			SDHCI_QUIRK2_BROKEN_DDR50,
721 	.probe_slot	= rtsx_probe_slot,
722 };
723 
724 /*AMD chipset generation*/
725 enum amd_chipset_gen {
726 	AMD_CHIPSET_BEFORE_ML,
727 	AMD_CHIPSET_CZ,
728 	AMD_CHIPSET_NL,
729 	AMD_CHIPSET_UNKNOWN,
730 };
731 
732 static int amd_probe(struct sdhci_pci_chip *chip)
733 {
734 	struct pci_dev	*smbus_dev;
735 	enum amd_chipset_gen gen;
736 
737 	smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
738 			PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
739 	if (smbus_dev) {
740 		gen = AMD_CHIPSET_BEFORE_ML;
741 	} else {
742 		smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
743 				PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
744 		if (smbus_dev) {
745 			if (smbus_dev->revision < 0x51)
746 				gen = AMD_CHIPSET_CZ;
747 			else
748 				gen = AMD_CHIPSET_NL;
749 		} else {
750 			gen = AMD_CHIPSET_UNKNOWN;
751 		}
752 	}
753 
754 	if ((gen == AMD_CHIPSET_BEFORE_ML) || (gen == AMD_CHIPSET_CZ)) {
755 		chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
756 		chip->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
757 	}
758 
759 	return 0;
760 }
761 
762 static const struct sdhci_pci_fixes sdhci_amd = {
763 	.probe		= amd_probe,
764 };
765 
766 static const struct pci_device_id pci_ids[] = {
767 	{
768 		.vendor		= PCI_VENDOR_ID_RICOH,
769 		.device		= PCI_DEVICE_ID_RICOH_R5C822,
770 		.subvendor	= PCI_ANY_ID,
771 		.subdevice	= PCI_ANY_ID,
772 		.driver_data	= (kernel_ulong_t)&sdhci_ricoh,
773 	},
774 
775 	{
776 		.vendor         = PCI_VENDOR_ID_RICOH,
777 		.device         = 0x843,
778 		.subvendor      = PCI_ANY_ID,
779 		.subdevice      = PCI_ANY_ID,
780 		.driver_data    = (kernel_ulong_t)&sdhci_ricoh_mmc,
781 	},
782 
783 	{
784 		.vendor         = PCI_VENDOR_ID_RICOH,
785 		.device         = 0xe822,
786 		.subvendor      = PCI_ANY_ID,
787 		.subdevice      = PCI_ANY_ID,
788 		.driver_data    = (kernel_ulong_t)&sdhci_ricoh_mmc,
789 	},
790 
791 	{
792 		.vendor         = PCI_VENDOR_ID_RICOH,
793 		.device         = 0xe823,
794 		.subvendor      = PCI_ANY_ID,
795 		.subdevice      = PCI_ANY_ID,
796 		.driver_data    = (kernel_ulong_t)&sdhci_ricoh_mmc,
797 	},
798 
799 	{
800 		.vendor		= PCI_VENDOR_ID_ENE,
801 		.device		= PCI_DEVICE_ID_ENE_CB712_SD,
802 		.subvendor	= PCI_ANY_ID,
803 		.subdevice	= PCI_ANY_ID,
804 		.driver_data	= (kernel_ulong_t)&sdhci_ene_712,
805 	},
806 
807 	{
808 		.vendor		= PCI_VENDOR_ID_ENE,
809 		.device		= PCI_DEVICE_ID_ENE_CB712_SD_2,
810 		.subvendor	= PCI_ANY_ID,
811 		.subdevice	= PCI_ANY_ID,
812 		.driver_data	= (kernel_ulong_t)&sdhci_ene_712,
813 	},
814 
815 	{
816 		.vendor		= PCI_VENDOR_ID_ENE,
817 		.device		= PCI_DEVICE_ID_ENE_CB714_SD,
818 		.subvendor	= PCI_ANY_ID,
819 		.subdevice	= PCI_ANY_ID,
820 		.driver_data	= (kernel_ulong_t)&sdhci_ene_714,
821 	},
822 
823 	{
824 		.vendor		= PCI_VENDOR_ID_ENE,
825 		.device		= PCI_DEVICE_ID_ENE_CB714_SD_2,
826 		.subvendor	= PCI_ANY_ID,
827 		.subdevice	= PCI_ANY_ID,
828 		.driver_data	= (kernel_ulong_t)&sdhci_ene_714,
829 	},
830 
831 	{
832 		.vendor         = PCI_VENDOR_ID_MARVELL,
833 		.device         = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
834 		.subvendor      = PCI_ANY_ID,
835 		.subdevice      = PCI_ANY_ID,
836 		.driver_data    = (kernel_ulong_t)&sdhci_cafe,
837 	},
838 
839 	{
840 		.vendor		= PCI_VENDOR_ID_JMICRON,
841 		.device		= PCI_DEVICE_ID_JMICRON_JMB38X_SD,
842 		.subvendor	= PCI_ANY_ID,
843 		.subdevice	= PCI_ANY_ID,
844 		.driver_data	= (kernel_ulong_t)&sdhci_jmicron,
845 	},
846 
847 	{
848 		.vendor		= PCI_VENDOR_ID_JMICRON,
849 		.device		= PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
850 		.subvendor	= PCI_ANY_ID,
851 		.subdevice	= PCI_ANY_ID,
852 		.driver_data	= (kernel_ulong_t)&sdhci_jmicron,
853 	},
854 
855 	{
856 		.vendor		= PCI_VENDOR_ID_JMICRON,
857 		.device		= PCI_DEVICE_ID_JMICRON_JMB388_SD,
858 		.subvendor	= PCI_ANY_ID,
859 		.subdevice	= PCI_ANY_ID,
860 		.driver_data	= (kernel_ulong_t)&sdhci_jmicron,
861 	},
862 
863 	{
864 		.vendor		= PCI_VENDOR_ID_JMICRON,
865 		.device		= PCI_DEVICE_ID_JMICRON_JMB388_ESD,
866 		.subvendor	= PCI_ANY_ID,
867 		.subdevice	= PCI_ANY_ID,
868 		.driver_data	= (kernel_ulong_t)&sdhci_jmicron,
869 	},
870 
871 	{
872 		.vendor		= PCI_VENDOR_ID_SYSKONNECT,
873 		.device		= 0x8000,
874 		.subvendor	= PCI_ANY_ID,
875 		.subdevice	= PCI_ANY_ID,
876 		.driver_data	= (kernel_ulong_t)&sdhci_syskt,
877 	},
878 
879 	{
880 		.vendor		= PCI_VENDOR_ID_VIA,
881 		.device		= 0x95d0,
882 		.subvendor	= PCI_ANY_ID,
883 		.subdevice	= PCI_ANY_ID,
884 		.driver_data	= (kernel_ulong_t)&sdhci_via,
885 	},
886 
887 	{
888 		.vendor		= PCI_VENDOR_ID_REALTEK,
889 		.device		= 0x5250,
890 		.subvendor	= PCI_ANY_ID,
891 		.subdevice	= PCI_ANY_ID,
892 		.driver_data	= (kernel_ulong_t)&sdhci_rtsx,
893 	},
894 
895 	{
896 		.vendor		= PCI_VENDOR_ID_INTEL,
897 		.device		= PCI_DEVICE_ID_INTEL_QRK_SD,
898 		.subvendor	= PCI_ANY_ID,
899 		.subdevice	= PCI_ANY_ID,
900 		.driver_data	= (kernel_ulong_t)&sdhci_intel_qrk,
901 	},
902 
903 	{
904 		.vendor		= PCI_VENDOR_ID_INTEL,
905 		.device		= PCI_DEVICE_ID_INTEL_MRST_SD0,
906 		.subvendor	= PCI_ANY_ID,
907 		.subdevice	= PCI_ANY_ID,
908 		.driver_data	= (kernel_ulong_t)&sdhci_intel_mrst_hc0,
909 	},
910 
911 	{
912 		.vendor		= PCI_VENDOR_ID_INTEL,
913 		.device		= PCI_DEVICE_ID_INTEL_MRST_SD1,
914 		.subvendor	= PCI_ANY_ID,
915 		.subdevice	= PCI_ANY_ID,
916 		.driver_data	= (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
917 	},
918 
919 	{
920 		.vendor		= PCI_VENDOR_ID_INTEL,
921 		.device		= PCI_DEVICE_ID_INTEL_MRST_SD2,
922 		.subvendor	= PCI_ANY_ID,
923 		.subdevice	= PCI_ANY_ID,
924 		.driver_data	= (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
925 	},
926 
927 	{
928 		.vendor		= PCI_VENDOR_ID_INTEL,
929 		.device		= PCI_DEVICE_ID_INTEL_MFD_SD,
930 		.subvendor	= PCI_ANY_ID,
931 		.subdevice	= PCI_ANY_ID,
932 		.driver_data	= (kernel_ulong_t)&sdhci_intel_mfd_sd,
933 	},
934 
935 	{
936 		.vendor		= PCI_VENDOR_ID_INTEL,
937 		.device		= PCI_DEVICE_ID_INTEL_MFD_SDIO1,
938 		.subvendor	= PCI_ANY_ID,
939 		.subdevice	= PCI_ANY_ID,
940 		.driver_data	= (kernel_ulong_t)&sdhci_intel_mfd_sdio,
941 	},
942 
943 	{
944 		.vendor		= PCI_VENDOR_ID_INTEL,
945 		.device		= PCI_DEVICE_ID_INTEL_MFD_SDIO2,
946 		.subvendor	= PCI_ANY_ID,
947 		.subdevice	= PCI_ANY_ID,
948 		.driver_data	= (kernel_ulong_t)&sdhci_intel_mfd_sdio,
949 	},
950 
951 	{
952 		.vendor		= PCI_VENDOR_ID_INTEL,
953 		.device		= PCI_DEVICE_ID_INTEL_MFD_EMMC0,
954 		.subvendor	= PCI_ANY_ID,
955 		.subdevice	= PCI_ANY_ID,
956 		.driver_data	= (kernel_ulong_t)&sdhci_intel_mfd_emmc,
957 	},
958 
959 	{
960 		.vendor		= PCI_VENDOR_ID_INTEL,
961 		.device		= PCI_DEVICE_ID_INTEL_MFD_EMMC1,
962 		.subvendor	= PCI_ANY_ID,
963 		.subdevice	= PCI_ANY_ID,
964 		.driver_data	= (kernel_ulong_t)&sdhci_intel_mfd_emmc,
965 	},
966 
967 	{
968 		.vendor		= PCI_VENDOR_ID_INTEL,
969 		.device		= PCI_DEVICE_ID_INTEL_PCH_SDIO0,
970 		.subvendor	= PCI_ANY_ID,
971 		.subdevice	= PCI_ANY_ID,
972 		.driver_data	= (kernel_ulong_t)&sdhci_intel_pch_sdio,
973 	},
974 
975 	{
976 		.vendor		= PCI_VENDOR_ID_INTEL,
977 		.device		= PCI_DEVICE_ID_INTEL_PCH_SDIO1,
978 		.subvendor	= PCI_ANY_ID,
979 		.subdevice	= PCI_ANY_ID,
980 		.driver_data	= (kernel_ulong_t)&sdhci_intel_pch_sdio,
981 	},
982 
983 	{
984 		.vendor		= PCI_VENDOR_ID_INTEL,
985 		.device		= PCI_DEVICE_ID_INTEL_BYT_EMMC,
986 		.subvendor	= PCI_ANY_ID,
987 		.subdevice	= PCI_ANY_ID,
988 		.driver_data	= (kernel_ulong_t)&sdhci_intel_byt_emmc,
989 	},
990 
991 	{
992 		.vendor		= PCI_VENDOR_ID_INTEL,
993 		.device		= PCI_DEVICE_ID_INTEL_BYT_SDIO,
994 		.subvendor	= PCI_ANY_ID,
995 		.subdevice	= PCI_ANY_ID,
996 		.driver_data	= (kernel_ulong_t)&sdhci_intel_byt_sdio,
997 	},
998 
999 	{
1000 		.vendor		= PCI_VENDOR_ID_INTEL,
1001 		.device		= PCI_DEVICE_ID_INTEL_BYT_SD,
1002 		.subvendor	= PCI_ANY_ID,
1003 		.subdevice	= PCI_ANY_ID,
1004 		.driver_data	= (kernel_ulong_t)&sdhci_intel_byt_sd,
1005 	},
1006 
1007 	{
1008 		.vendor		= PCI_VENDOR_ID_INTEL,
1009 		.device		= PCI_DEVICE_ID_INTEL_BYT_EMMC2,
1010 		.subvendor	= PCI_ANY_ID,
1011 		.subdevice	= PCI_ANY_ID,
1012 		.driver_data	= (kernel_ulong_t)&sdhci_intel_byt_emmc,
1013 	},
1014 
1015 	{
1016 		.vendor		= PCI_VENDOR_ID_INTEL,
1017 		.device		= PCI_DEVICE_ID_INTEL_BSW_EMMC,
1018 		.subvendor	= PCI_ANY_ID,
1019 		.subdevice	= PCI_ANY_ID,
1020 		.driver_data	= (kernel_ulong_t)&sdhci_intel_byt_emmc,
1021 	},
1022 
1023 	{
1024 		.vendor		= PCI_VENDOR_ID_INTEL,
1025 		.device		= PCI_DEVICE_ID_INTEL_BSW_SDIO,
1026 		.subvendor	= PCI_ANY_ID,
1027 		.subdevice	= PCI_ANY_ID,
1028 		.driver_data	= (kernel_ulong_t)&sdhci_intel_byt_sdio,
1029 	},
1030 
1031 	{
1032 		.vendor		= PCI_VENDOR_ID_INTEL,
1033 		.device		= PCI_DEVICE_ID_INTEL_BSW_SD,
1034 		.subvendor	= PCI_ANY_ID,
1035 		.subdevice	= PCI_ANY_ID,
1036 		.driver_data	= (kernel_ulong_t)&sdhci_intel_byt_sd,
1037 	},
1038 
1039 	{
1040 		.vendor		= PCI_VENDOR_ID_INTEL,
1041 		.device		= PCI_DEVICE_ID_INTEL_CLV_SDIO0,
1042 		.subvendor	= PCI_ANY_ID,
1043 		.subdevice	= PCI_ANY_ID,
1044 		.driver_data	= (kernel_ulong_t)&sdhci_intel_mfd_sd,
1045 	},
1046 
1047 	{
1048 		.vendor		= PCI_VENDOR_ID_INTEL,
1049 		.device		= PCI_DEVICE_ID_INTEL_CLV_SDIO1,
1050 		.subvendor	= PCI_ANY_ID,
1051 		.subdevice	= PCI_ANY_ID,
1052 		.driver_data	= (kernel_ulong_t)&sdhci_intel_mfd_sdio,
1053 	},
1054 
1055 	{
1056 		.vendor		= PCI_VENDOR_ID_INTEL,
1057 		.device		= PCI_DEVICE_ID_INTEL_CLV_SDIO2,
1058 		.subvendor	= PCI_ANY_ID,
1059 		.subdevice	= PCI_ANY_ID,
1060 		.driver_data	= (kernel_ulong_t)&sdhci_intel_mfd_sdio,
1061 	},
1062 
1063 	{
1064 		.vendor		= PCI_VENDOR_ID_INTEL,
1065 		.device		= PCI_DEVICE_ID_INTEL_CLV_EMMC0,
1066 		.subvendor	= PCI_ANY_ID,
1067 		.subdevice	= PCI_ANY_ID,
1068 		.driver_data	= (kernel_ulong_t)&sdhci_intel_mfd_emmc,
1069 	},
1070 
1071 	{
1072 		.vendor		= PCI_VENDOR_ID_INTEL,
1073 		.device		= PCI_DEVICE_ID_INTEL_CLV_EMMC1,
1074 		.subvendor	= PCI_ANY_ID,
1075 		.subdevice	= PCI_ANY_ID,
1076 		.driver_data	= (kernel_ulong_t)&sdhci_intel_mfd_emmc,
1077 	},
1078 
1079 	{
1080 		.vendor		= PCI_VENDOR_ID_INTEL,
1081 		.device		= PCI_DEVICE_ID_INTEL_MRFL_MMC,
1082 		.subvendor	= PCI_ANY_ID,
1083 		.subdevice	= PCI_ANY_ID,
1084 		.driver_data	= (kernel_ulong_t)&sdhci_intel_mrfl_mmc,
1085 	},
1086 
1087 	{
1088 		.vendor		= PCI_VENDOR_ID_INTEL,
1089 		.device		= PCI_DEVICE_ID_INTEL_SPT_EMMC,
1090 		.subvendor	= PCI_ANY_ID,
1091 		.subdevice	= PCI_ANY_ID,
1092 		.driver_data	= (kernel_ulong_t)&sdhci_intel_byt_emmc,
1093 	},
1094 
1095 	{
1096 		.vendor		= PCI_VENDOR_ID_INTEL,
1097 		.device		= PCI_DEVICE_ID_INTEL_SPT_SDIO,
1098 		.subvendor	= PCI_ANY_ID,
1099 		.subdevice	= PCI_ANY_ID,
1100 		.driver_data	= (kernel_ulong_t)&sdhci_intel_byt_sdio,
1101 	},
1102 
1103 	{
1104 		.vendor		= PCI_VENDOR_ID_INTEL,
1105 		.device		= PCI_DEVICE_ID_INTEL_SPT_SD,
1106 		.subvendor	= PCI_ANY_ID,
1107 		.subdevice	= PCI_ANY_ID,
1108 		.driver_data	= (kernel_ulong_t)&sdhci_intel_byt_sd,
1109 	},
1110 
1111 	{
1112 		.vendor		= PCI_VENDOR_ID_INTEL,
1113 		.device		= PCI_DEVICE_ID_INTEL_DNV_EMMC,
1114 		.subvendor	= PCI_ANY_ID,
1115 		.subdevice	= PCI_ANY_ID,
1116 		.driver_data	= (kernel_ulong_t)&sdhci_intel_byt_emmc,
1117 	},
1118 
1119 	{
1120 		.vendor		= PCI_VENDOR_ID_INTEL,
1121 		.device		= PCI_DEVICE_ID_INTEL_BXT_EMMC,
1122 		.subvendor	= PCI_ANY_ID,
1123 		.subdevice	= PCI_ANY_ID,
1124 		.driver_data	= (kernel_ulong_t)&sdhci_intel_byt_emmc,
1125 	},
1126 
1127 	{
1128 		.vendor		= PCI_VENDOR_ID_INTEL,
1129 		.device		= PCI_DEVICE_ID_INTEL_BXT_SDIO,
1130 		.subvendor	= PCI_ANY_ID,
1131 		.subdevice	= PCI_ANY_ID,
1132 		.driver_data	= (kernel_ulong_t)&sdhci_intel_byt_sdio,
1133 	},
1134 
1135 	{
1136 		.vendor		= PCI_VENDOR_ID_INTEL,
1137 		.device		= PCI_DEVICE_ID_INTEL_BXT_SD,
1138 		.subvendor	= PCI_ANY_ID,
1139 		.subdevice	= PCI_ANY_ID,
1140 		.driver_data	= (kernel_ulong_t)&sdhci_intel_byt_sd,
1141 	},
1142 
1143 	{
1144 		.vendor		= PCI_VENDOR_ID_INTEL,
1145 		.device		= PCI_DEVICE_ID_INTEL_APL_EMMC,
1146 		.subvendor	= PCI_ANY_ID,
1147 		.subdevice	= PCI_ANY_ID,
1148 		.driver_data	= (kernel_ulong_t)&sdhci_intel_byt_emmc,
1149 	},
1150 
1151 	{
1152 		.vendor		= PCI_VENDOR_ID_INTEL,
1153 		.device		= PCI_DEVICE_ID_INTEL_APL_SDIO,
1154 		.subvendor	= PCI_ANY_ID,
1155 		.subdevice	= PCI_ANY_ID,
1156 		.driver_data	= (kernel_ulong_t)&sdhci_intel_byt_sdio,
1157 	},
1158 
1159 	{
1160 		.vendor		= PCI_VENDOR_ID_INTEL,
1161 		.device		= PCI_DEVICE_ID_INTEL_APL_SD,
1162 		.subvendor	= PCI_ANY_ID,
1163 		.subdevice	= PCI_ANY_ID,
1164 		.driver_data	= (kernel_ulong_t)&sdhci_intel_byt_sd,
1165 	},
1166 
1167 	{
1168 		.vendor		= PCI_VENDOR_ID_O2,
1169 		.device		= PCI_DEVICE_ID_O2_8120,
1170 		.subvendor	= PCI_ANY_ID,
1171 		.subdevice	= PCI_ANY_ID,
1172 		.driver_data	= (kernel_ulong_t)&sdhci_o2,
1173 	},
1174 
1175 	{
1176 		.vendor		= PCI_VENDOR_ID_O2,
1177 		.device		= PCI_DEVICE_ID_O2_8220,
1178 		.subvendor	= PCI_ANY_ID,
1179 		.subdevice	= PCI_ANY_ID,
1180 		.driver_data	= (kernel_ulong_t)&sdhci_o2,
1181 	},
1182 
1183 	{
1184 		.vendor		= PCI_VENDOR_ID_O2,
1185 		.device		= PCI_DEVICE_ID_O2_8221,
1186 		.subvendor	= PCI_ANY_ID,
1187 		.subdevice	= PCI_ANY_ID,
1188 		.driver_data	= (kernel_ulong_t)&sdhci_o2,
1189 	},
1190 
1191 	{
1192 		.vendor		= PCI_VENDOR_ID_O2,
1193 		.device		= PCI_DEVICE_ID_O2_8320,
1194 		.subvendor	= PCI_ANY_ID,
1195 		.subdevice	= PCI_ANY_ID,
1196 		.driver_data	= (kernel_ulong_t)&sdhci_o2,
1197 	},
1198 
1199 	{
1200 		.vendor		= PCI_VENDOR_ID_O2,
1201 		.device		= PCI_DEVICE_ID_O2_8321,
1202 		.subvendor	= PCI_ANY_ID,
1203 		.subdevice	= PCI_ANY_ID,
1204 		.driver_data	= (kernel_ulong_t)&sdhci_o2,
1205 	},
1206 
1207 	{
1208 		.vendor		= PCI_VENDOR_ID_O2,
1209 		.device		= PCI_DEVICE_ID_O2_FUJIN2,
1210 		.subvendor	= PCI_ANY_ID,
1211 		.subdevice	= PCI_ANY_ID,
1212 		.driver_data	= (kernel_ulong_t)&sdhci_o2,
1213 	},
1214 
1215 	{
1216 		.vendor		= PCI_VENDOR_ID_O2,
1217 		.device		= PCI_DEVICE_ID_O2_SDS0,
1218 		.subvendor	= PCI_ANY_ID,
1219 		.subdevice	= PCI_ANY_ID,
1220 		.driver_data	= (kernel_ulong_t)&sdhci_o2,
1221 	},
1222 
1223 	{
1224 		.vendor		= PCI_VENDOR_ID_O2,
1225 		.device		= PCI_DEVICE_ID_O2_SDS1,
1226 		.subvendor	= PCI_ANY_ID,
1227 		.subdevice	= PCI_ANY_ID,
1228 		.driver_data	= (kernel_ulong_t)&sdhci_o2,
1229 	},
1230 
1231 	{
1232 		.vendor		= PCI_VENDOR_ID_O2,
1233 		.device		= PCI_DEVICE_ID_O2_SEABIRD0,
1234 		.subvendor	= PCI_ANY_ID,
1235 		.subdevice	= PCI_ANY_ID,
1236 		.driver_data	= (kernel_ulong_t)&sdhci_o2,
1237 	},
1238 
1239 	{
1240 		.vendor		= PCI_VENDOR_ID_O2,
1241 		.device		= PCI_DEVICE_ID_O2_SEABIRD1,
1242 		.subvendor	= PCI_ANY_ID,
1243 		.subdevice	= PCI_ANY_ID,
1244 		.driver_data	= (kernel_ulong_t)&sdhci_o2,
1245 	},
1246 	{
1247 		.vendor		= PCI_VENDOR_ID_AMD,
1248 		.device		= PCI_ANY_ID,
1249 		.class		= PCI_CLASS_SYSTEM_SDHCI << 8,
1250 		.class_mask	= 0xFFFF00,
1251 		.subvendor	= PCI_ANY_ID,
1252 		.subdevice	= PCI_ANY_ID,
1253 		.driver_data	= (kernel_ulong_t)&sdhci_amd,
1254 	},
1255 	{	/* Generic SD host controller */
1256 		PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
1257 	},
1258 
1259 	{ /* end: all zeroes */ },
1260 };
1261 
1262 MODULE_DEVICE_TABLE(pci, pci_ids);
1263 
1264 /*****************************************************************************\
1265  *                                                                           *
1266  * SDHCI core callbacks                                                      *
1267  *                                                                           *
1268 \*****************************************************************************/
1269 
1270 static int sdhci_pci_enable_dma(struct sdhci_host *host)
1271 {
1272 	struct sdhci_pci_slot *slot;
1273 	struct pci_dev *pdev;
1274 	int ret = -1;
1275 
1276 	slot = sdhci_priv(host);
1277 	pdev = slot->chip->pdev;
1278 
1279 	if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1280 		((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1281 		(host->flags & SDHCI_USE_SDMA)) {
1282 		dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1283 			"doesn't fully claim to support it.\n");
1284 	}
1285 
1286 	if (host->flags & SDHCI_USE_64_BIT_DMA) {
1287 		if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA) {
1288 			host->flags &= ~SDHCI_USE_64_BIT_DMA;
1289 		} else {
1290 			ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1291 			if (ret)
1292 				dev_warn(&pdev->dev, "Failed to set 64-bit DMA mask\n");
1293 		}
1294 	}
1295 	if (ret)
1296 		ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1297 	if (ret)
1298 		return ret;
1299 
1300 	pci_set_master(pdev);
1301 
1302 	return 0;
1303 }
1304 
1305 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width)
1306 {
1307 	u8 ctrl;
1308 
1309 	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1310 
1311 	switch (width) {
1312 	case MMC_BUS_WIDTH_8:
1313 		ctrl |= SDHCI_CTRL_8BITBUS;
1314 		ctrl &= ~SDHCI_CTRL_4BITBUS;
1315 		break;
1316 	case MMC_BUS_WIDTH_4:
1317 		ctrl |= SDHCI_CTRL_4BITBUS;
1318 		ctrl &= ~SDHCI_CTRL_8BITBUS;
1319 		break;
1320 	default:
1321 		ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
1322 		break;
1323 	}
1324 
1325 	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1326 }
1327 
1328 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
1329 {
1330 	struct sdhci_pci_slot *slot = sdhci_priv(host);
1331 	int rst_n_gpio = slot->rst_n_gpio;
1332 
1333 	if (!gpio_is_valid(rst_n_gpio))
1334 		return;
1335 	gpio_set_value_cansleep(rst_n_gpio, 0);
1336 	/* For eMMC, minimum is 1us but give it 10us for good measure */
1337 	udelay(10);
1338 	gpio_set_value_cansleep(rst_n_gpio, 1);
1339 	/* For eMMC, minimum is 200us but give it 300us for good measure */
1340 	usleep_range(300, 1000);
1341 }
1342 
1343 static void sdhci_pci_hw_reset(struct sdhci_host *host)
1344 {
1345 	struct sdhci_pci_slot *slot = sdhci_priv(host);
1346 
1347 	if (slot->hw_reset)
1348 		slot->hw_reset(host);
1349 }
1350 
1351 static int sdhci_pci_select_drive_strength(struct sdhci_host *host,
1352 					   struct mmc_card *card,
1353 					   unsigned int max_dtr, int host_drv,
1354 					   int card_drv, int *drv_type)
1355 {
1356 	struct sdhci_pci_slot *slot = sdhci_priv(host);
1357 
1358 	if (!slot->select_drive_strength)
1359 		return 0;
1360 
1361 	return slot->select_drive_strength(host, card, max_dtr, host_drv,
1362 					   card_drv, drv_type);
1363 }
1364 
1365 static const struct sdhci_ops sdhci_pci_ops = {
1366 	.set_clock	= sdhci_set_clock,
1367 	.enable_dma	= sdhci_pci_enable_dma,
1368 	.set_bus_width	= sdhci_pci_set_bus_width,
1369 	.reset		= sdhci_reset,
1370 	.set_uhs_signaling = sdhci_set_uhs_signaling,
1371 	.hw_reset		= sdhci_pci_hw_reset,
1372 	.select_drive_strength	= sdhci_pci_select_drive_strength,
1373 };
1374 
1375 /*****************************************************************************\
1376  *                                                                           *
1377  * Suspend/resume                                                            *
1378  *                                                                           *
1379 \*****************************************************************************/
1380 
1381 #ifdef CONFIG_PM
1382 
1383 static int sdhci_pci_suspend(struct device *dev)
1384 {
1385 	struct pci_dev *pdev = to_pci_dev(dev);
1386 	struct sdhci_pci_chip *chip;
1387 	struct sdhci_pci_slot *slot;
1388 	mmc_pm_flag_t slot_pm_flags;
1389 	mmc_pm_flag_t pm_flags = 0;
1390 	int i, ret;
1391 
1392 	chip = pci_get_drvdata(pdev);
1393 	if (!chip)
1394 		return 0;
1395 
1396 	for (i = 0; i < chip->num_slots; i++) {
1397 		slot = chip->slots[i];
1398 		if (!slot)
1399 			continue;
1400 
1401 		ret = sdhci_suspend_host(slot->host);
1402 
1403 		if (ret)
1404 			goto err_pci_suspend;
1405 
1406 		slot_pm_flags = slot->host->mmc->pm_flags;
1407 		if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1408 			sdhci_enable_irq_wakeups(slot->host);
1409 
1410 		pm_flags |= slot_pm_flags;
1411 	}
1412 
1413 	if (chip->fixes && chip->fixes->suspend) {
1414 		ret = chip->fixes->suspend(chip);
1415 		if (ret)
1416 			goto err_pci_suspend;
1417 	}
1418 
1419 	if (pm_flags & MMC_PM_KEEP_POWER) {
1420 		if (pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1421 			device_init_wakeup(dev, true);
1422 		else
1423 			device_init_wakeup(dev, false);
1424 	} else
1425 		device_init_wakeup(dev, false);
1426 
1427 	return 0;
1428 
1429 err_pci_suspend:
1430 	while (--i >= 0)
1431 		sdhci_resume_host(chip->slots[i]->host);
1432 	return ret;
1433 }
1434 
1435 static int sdhci_pci_resume(struct device *dev)
1436 {
1437 	struct pci_dev *pdev = to_pci_dev(dev);
1438 	struct sdhci_pci_chip *chip;
1439 	struct sdhci_pci_slot *slot;
1440 	int i, ret;
1441 
1442 	chip = pci_get_drvdata(pdev);
1443 	if (!chip)
1444 		return 0;
1445 
1446 	if (chip->fixes && chip->fixes->resume) {
1447 		ret = chip->fixes->resume(chip);
1448 		if (ret)
1449 			return ret;
1450 	}
1451 
1452 	for (i = 0; i < chip->num_slots; i++) {
1453 		slot = chip->slots[i];
1454 		if (!slot)
1455 			continue;
1456 
1457 		ret = sdhci_resume_host(slot->host);
1458 		if (ret)
1459 			return ret;
1460 	}
1461 
1462 	return 0;
1463 }
1464 
1465 static int sdhci_pci_runtime_suspend(struct device *dev)
1466 {
1467 	struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1468 	struct sdhci_pci_chip *chip;
1469 	struct sdhci_pci_slot *slot;
1470 	int i, ret;
1471 
1472 	chip = pci_get_drvdata(pdev);
1473 	if (!chip)
1474 		return 0;
1475 
1476 	for (i = 0; i < chip->num_slots; i++) {
1477 		slot = chip->slots[i];
1478 		if (!slot)
1479 			continue;
1480 
1481 		ret = sdhci_runtime_suspend_host(slot->host);
1482 
1483 		if (ret)
1484 			goto err_pci_runtime_suspend;
1485 	}
1486 
1487 	if (chip->fixes && chip->fixes->suspend) {
1488 		ret = chip->fixes->suspend(chip);
1489 		if (ret)
1490 			goto err_pci_runtime_suspend;
1491 	}
1492 
1493 	return 0;
1494 
1495 err_pci_runtime_suspend:
1496 	while (--i >= 0)
1497 		sdhci_runtime_resume_host(chip->slots[i]->host);
1498 	return ret;
1499 }
1500 
1501 static int sdhci_pci_runtime_resume(struct device *dev)
1502 {
1503 	struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1504 	struct sdhci_pci_chip *chip;
1505 	struct sdhci_pci_slot *slot;
1506 	int i, ret;
1507 
1508 	chip = pci_get_drvdata(pdev);
1509 	if (!chip)
1510 		return 0;
1511 
1512 	if (chip->fixes && chip->fixes->resume) {
1513 		ret = chip->fixes->resume(chip);
1514 		if (ret)
1515 			return ret;
1516 	}
1517 
1518 	for (i = 0; i < chip->num_slots; i++) {
1519 		slot = chip->slots[i];
1520 		if (!slot)
1521 			continue;
1522 
1523 		ret = sdhci_runtime_resume_host(slot->host);
1524 		if (ret)
1525 			return ret;
1526 	}
1527 
1528 	return 0;
1529 }
1530 
1531 #else /* CONFIG_PM */
1532 
1533 #define sdhci_pci_suspend NULL
1534 #define sdhci_pci_resume NULL
1535 
1536 #endif /* CONFIG_PM */
1537 
1538 static const struct dev_pm_ops sdhci_pci_pm_ops = {
1539 	.suspend = sdhci_pci_suspend,
1540 	.resume = sdhci_pci_resume,
1541 	SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1542 			sdhci_pci_runtime_resume, NULL)
1543 };
1544 
1545 /*****************************************************************************\
1546  *                                                                           *
1547  * Device probing/removal                                                    *
1548  *                                                                           *
1549 \*****************************************************************************/
1550 
1551 static struct sdhci_pci_slot *sdhci_pci_probe_slot(
1552 	struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1553 	int slotno)
1554 {
1555 	struct sdhci_pci_slot *slot;
1556 	struct sdhci_host *host;
1557 	int ret, bar = first_bar + slotno;
1558 
1559 	if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1560 		dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1561 		return ERR_PTR(-ENODEV);
1562 	}
1563 
1564 	if (pci_resource_len(pdev, bar) < 0x100) {
1565 		dev_err(&pdev->dev, "Invalid iomem size. You may "
1566 			"experience problems.\n");
1567 	}
1568 
1569 	if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1570 		dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1571 		return ERR_PTR(-ENODEV);
1572 	}
1573 
1574 	if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1575 		dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1576 		return ERR_PTR(-ENODEV);
1577 	}
1578 
1579 	host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
1580 	if (IS_ERR(host)) {
1581 		dev_err(&pdev->dev, "cannot allocate host\n");
1582 		return ERR_CAST(host);
1583 	}
1584 
1585 	slot = sdhci_priv(host);
1586 
1587 	slot->chip = chip;
1588 	slot->host = host;
1589 	slot->pci_bar = bar;
1590 	slot->rst_n_gpio = -EINVAL;
1591 	slot->cd_gpio = -EINVAL;
1592 	slot->cd_idx = -1;
1593 
1594 	/* Retrieve platform data if there is any */
1595 	if (*sdhci_pci_get_data)
1596 		slot->data = sdhci_pci_get_data(pdev, slotno);
1597 
1598 	if (slot->data) {
1599 		if (slot->data->setup) {
1600 			ret = slot->data->setup(slot->data);
1601 			if (ret) {
1602 				dev_err(&pdev->dev, "platform setup failed\n");
1603 				goto free;
1604 			}
1605 		}
1606 		slot->rst_n_gpio = slot->data->rst_n_gpio;
1607 		slot->cd_gpio = slot->data->cd_gpio;
1608 	}
1609 
1610 	host->hw_name = "PCI";
1611 	host->ops = &sdhci_pci_ops;
1612 	host->quirks = chip->quirks;
1613 	host->quirks2 = chip->quirks2;
1614 
1615 	host->irq = pdev->irq;
1616 
1617 	ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
1618 	if (ret) {
1619 		dev_err(&pdev->dev, "cannot request region\n");
1620 		goto cleanup;
1621 	}
1622 
1623 	host->ioaddr = pci_ioremap_bar(pdev, bar);
1624 	if (!host->ioaddr) {
1625 		dev_err(&pdev->dev, "failed to remap registers\n");
1626 		ret = -ENOMEM;
1627 		goto release;
1628 	}
1629 
1630 	if (chip->fixes && chip->fixes->probe_slot) {
1631 		ret = chip->fixes->probe_slot(slot);
1632 		if (ret)
1633 			goto unmap;
1634 	}
1635 
1636 	if (gpio_is_valid(slot->rst_n_gpio)) {
1637 		if (!gpio_request(slot->rst_n_gpio, "eMMC_reset")) {
1638 			gpio_direction_output(slot->rst_n_gpio, 1);
1639 			slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1640 			slot->hw_reset = sdhci_pci_gpio_hw_reset;
1641 		} else {
1642 			dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1643 			slot->rst_n_gpio = -EINVAL;
1644 		}
1645 	}
1646 
1647 	host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1648 	host->mmc->slotno = slotno;
1649 	host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
1650 
1651 	if (slot->cd_idx >= 0 &&
1652 	    mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx,
1653 				 slot->cd_override_level, 0, NULL)) {
1654 		dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1655 		slot->cd_idx = -1;
1656 	}
1657 
1658 	ret = sdhci_add_host(host);
1659 	if (ret)
1660 		goto remove;
1661 
1662 	sdhci_pci_add_own_cd(slot);
1663 
1664 	/*
1665 	 * Check if the chip needs a separate GPIO for card detect to wake up
1666 	 * from runtime suspend.  If it is not there, don't allow runtime PM.
1667 	 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1668 	 */
1669 	if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
1670 	    !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
1671 		chip->allow_runtime_pm = false;
1672 
1673 	return slot;
1674 
1675 remove:
1676 	if (gpio_is_valid(slot->rst_n_gpio))
1677 		gpio_free(slot->rst_n_gpio);
1678 
1679 	if (chip->fixes && chip->fixes->remove_slot)
1680 		chip->fixes->remove_slot(slot, 0);
1681 
1682 unmap:
1683 	iounmap(host->ioaddr);
1684 
1685 release:
1686 	pci_release_region(pdev, bar);
1687 
1688 cleanup:
1689 	if (slot->data && slot->data->cleanup)
1690 		slot->data->cleanup(slot->data);
1691 
1692 free:
1693 	sdhci_free_host(host);
1694 
1695 	return ERR_PTR(ret);
1696 }
1697 
1698 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1699 {
1700 	int dead;
1701 	u32 scratch;
1702 
1703 	sdhci_pci_remove_own_cd(slot);
1704 
1705 	dead = 0;
1706 	scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1707 	if (scratch == (u32)-1)
1708 		dead = 1;
1709 
1710 	sdhci_remove_host(slot->host, dead);
1711 
1712 	if (gpio_is_valid(slot->rst_n_gpio))
1713 		gpio_free(slot->rst_n_gpio);
1714 
1715 	if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1716 		slot->chip->fixes->remove_slot(slot, dead);
1717 
1718 	if (slot->data && slot->data->cleanup)
1719 		slot->data->cleanup(slot->data);
1720 
1721 	pci_release_region(slot->chip->pdev, slot->pci_bar);
1722 
1723 	sdhci_free_host(slot->host);
1724 }
1725 
1726 static void sdhci_pci_runtime_pm_allow(struct device *dev)
1727 {
1728 	pm_runtime_put_noidle(dev);
1729 	pm_runtime_allow(dev);
1730 	pm_runtime_set_autosuspend_delay(dev, 50);
1731 	pm_runtime_use_autosuspend(dev);
1732 	pm_suspend_ignore_children(dev, 1);
1733 }
1734 
1735 static void sdhci_pci_runtime_pm_forbid(struct device *dev)
1736 {
1737 	pm_runtime_forbid(dev);
1738 	pm_runtime_get_noresume(dev);
1739 }
1740 
1741 static int sdhci_pci_probe(struct pci_dev *pdev,
1742 				     const struct pci_device_id *ent)
1743 {
1744 	struct sdhci_pci_chip *chip;
1745 	struct sdhci_pci_slot *slot;
1746 
1747 	u8 slots, first_bar;
1748 	int ret, i;
1749 
1750 	BUG_ON(pdev == NULL);
1751 	BUG_ON(ent == NULL);
1752 
1753 	dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1754 		 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1755 
1756 	ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1757 	if (ret)
1758 		return ret;
1759 
1760 	slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1761 	dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1762 	if (slots == 0)
1763 		return -ENODEV;
1764 
1765 	BUG_ON(slots > MAX_SLOTS);
1766 
1767 	ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1768 	if (ret)
1769 		return ret;
1770 
1771 	first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1772 
1773 	if (first_bar > 5) {
1774 		dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1775 		return -ENODEV;
1776 	}
1777 
1778 	ret = pci_enable_device(pdev);
1779 	if (ret)
1780 		return ret;
1781 
1782 	chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
1783 	if (!chip) {
1784 		ret = -ENOMEM;
1785 		goto err;
1786 	}
1787 
1788 	chip->pdev = pdev;
1789 	chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1790 	if (chip->fixes) {
1791 		chip->quirks = chip->fixes->quirks;
1792 		chip->quirks2 = chip->fixes->quirks2;
1793 		chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1794 	}
1795 	chip->num_slots = slots;
1796 
1797 	pci_set_drvdata(pdev, chip);
1798 
1799 	if (chip->fixes && chip->fixes->probe) {
1800 		ret = chip->fixes->probe(chip);
1801 		if (ret)
1802 			goto free;
1803 	}
1804 
1805 	slots = chip->num_slots;	/* Quirk may have changed this */
1806 
1807 	for (i = 0; i < slots; i++) {
1808 		slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
1809 		if (IS_ERR(slot)) {
1810 			for (i--; i >= 0; i--)
1811 				sdhci_pci_remove_slot(chip->slots[i]);
1812 			ret = PTR_ERR(slot);
1813 			goto free;
1814 		}
1815 
1816 		chip->slots[i] = slot;
1817 	}
1818 
1819 	if (chip->allow_runtime_pm)
1820 		sdhci_pci_runtime_pm_allow(&pdev->dev);
1821 
1822 	return 0;
1823 
1824 free:
1825 	pci_set_drvdata(pdev, NULL);
1826 	kfree(chip);
1827 
1828 err:
1829 	pci_disable_device(pdev);
1830 	return ret;
1831 }
1832 
1833 static void sdhci_pci_remove(struct pci_dev *pdev)
1834 {
1835 	int i;
1836 	struct sdhci_pci_chip *chip;
1837 
1838 	chip = pci_get_drvdata(pdev);
1839 
1840 	if (chip) {
1841 		if (chip->allow_runtime_pm)
1842 			sdhci_pci_runtime_pm_forbid(&pdev->dev);
1843 
1844 		for (i = 0; i < chip->num_slots; i++)
1845 			sdhci_pci_remove_slot(chip->slots[i]);
1846 
1847 		pci_set_drvdata(pdev, NULL);
1848 		kfree(chip);
1849 	}
1850 
1851 	pci_disable_device(pdev);
1852 }
1853 
1854 static struct pci_driver sdhci_driver = {
1855 	.name =		"sdhci-pci",
1856 	.id_table =	pci_ids,
1857 	.probe =	sdhci_pci_probe,
1858 	.remove =	sdhci_pci_remove,
1859 	.driver =	{
1860 		.pm =   &sdhci_pci_pm_ops
1861 	},
1862 };
1863 
1864 module_pci_driver(sdhci_driver);
1865 
1866 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
1867 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1868 MODULE_LICENSE("GPL");
1869