1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 2 * 3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 * 10 * Thanks to the following companies for their support: 11 * 12 * - JMicron (hardware and technical support) 13 */ 14 15 #include <linux/string.h> 16 #include <linux/delay.h> 17 #include <linux/highmem.h> 18 #include <linux/module.h> 19 #include <linux/pci.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/slab.h> 22 #include <linux/device.h> 23 #include <linux/mmc/host.h> 24 #include <linux/mmc/mmc.h> 25 #include <linux/scatterlist.h> 26 #include <linux/io.h> 27 #include <linux/gpio.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/mmc/slot-gpio.h> 30 #include <linux/mmc/sdhci-pci-data.h> 31 #include <linux/acpi.h> 32 33 #include "sdhci.h" 34 #include "sdhci-pci.h" 35 #include "sdhci-pci-o2micro.h" 36 37 static int sdhci_pci_enable_dma(struct sdhci_host *host); 38 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width); 39 static void sdhci_pci_hw_reset(struct sdhci_host *host); 40 41 #ifdef CONFIG_PM_SLEEP 42 static int __sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 43 { 44 int i, ret; 45 46 for (i = 0; i < chip->num_slots; i++) { 47 struct sdhci_pci_slot *slot = chip->slots[i]; 48 struct sdhci_host *host; 49 50 if (!slot) 51 continue; 52 53 host = slot->host; 54 55 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 56 mmc_retune_needed(host->mmc); 57 58 ret = sdhci_suspend_host(host); 59 if (ret) 60 goto err_pci_suspend; 61 62 if (host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ) 63 sdhci_enable_irq_wakeups(host); 64 } 65 66 return 0; 67 68 err_pci_suspend: 69 while (--i >= 0) 70 sdhci_resume_host(chip->slots[i]->host); 71 return ret; 72 } 73 74 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip) 75 { 76 mmc_pm_flag_t pm_flags = 0; 77 int i; 78 79 for (i = 0; i < chip->num_slots; i++) { 80 struct sdhci_pci_slot *slot = chip->slots[i]; 81 82 if (slot) 83 pm_flags |= slot->host->mmc->pm_flags; 84 } 85 86 return device_init_wakeup(&chip->pdev->dev, 87 (pm_flags & MMC_PM_KEEP_POWER) && 88 (pm_flags & MMC_PM_WAKE_SDIO_IRQ)); 89 } 90 91 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 92 { 93 int ret; 94 95 ret = __sdhci_pci_suspend_host(chip); 96 if (ret) 97 return ret; 98 99 sdhci_pci_init_wakeup(chip); 100 101 return 0; 102 } 103 104 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip) 105 { 106 struct sdhci_pci_slot *slot; 107 int i, ret; 108 109 for (i = 0; i < chip->num_slots; i++) { 110 slot = chip->slots[i]; 111 if (!slot) 112 continue; 113 114 ret = sdhci_resume_host(slot->host); 115 if (ret) 116 return ret; 117 } 118 119 return 0; 120 } 121 #endif 122 123 #ifdef CONFIG_PM 124 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip) 125 { 126 struct sdhci_pci_slot *slot; 127 struct sdhci_host *host; 128 int i, ret; 129 130 for (i = 0; i < chip->num_slots; i++) { 131 slot = chip->slots[i]; 132 if (!slot) 133 continue; 134 135 host = slot->host; 136 137 ret = sdhci_runtime_suspend_host(host); 138 if (ret) 139 goto err_pci_runtime_suspend; 140 141 if (chip->rpm_retune && 142 host->tuning_mode != SDHCI_TUNING_MODE_3) 143 mmc_retune_needed(host->mmc); 144 } 145 146 return 0; 147 148 err_pci_runtime_suspend: 149 while (--i >= 0) 150 sdhci_runtime_resume_host(chip->slots[i]->host); 151 return ret; 152 } 153 154 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip) 155 { 156 struct sdhci_pci_slot *slot; 157 int i, ret; 158 159 for (i = 0; i < chip->num_slots; i++) { 160 slot = chip->slots[i]; 161 if (!slot) 162 continue; 163 164 ret = sdhci_runtime_resume_host(slot->host); 165 if (ret) 166 return ret; 167 } 168 169 return 0; 170 } 171 #endif 172 173 /*****************************************************************************\ 174 * * 175 * Hardware specific quirk handling * 176 * * 177 \*****************************************************************************/ 178 179 static int ricoh_probe(struct sdhci_pci_chip *chip) 180 { 181 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 182 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 183 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 184 return 0; 185 } 186 187 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 188 { 189 slot->host->caps = 190 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 191 & SDHCI_TIMEOUT_CLK_MASK) | 192 193 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 194 & SDHCI_CLOCK_BASE_MASK) | 195 196 SDHCI_TIMEOUT_CLK_UNIT | 197 SDHCI_CAN_VDD_330 | 198 SDHCI_CAN_DO_HISPD | 199 SDHCI_CAN_DO_SDMA; 200 return 0; 201 } 202 203 #ifdef CONFIG_PM_SLEEP 204 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 205 { 206 /* Apply a delay to allow controller to settle */ 207 /* Otherwise it becomes confused if card state changed 208 during suspend */ 209 msleep(500); 210 return sdhci_pci_resume_host(chip); 211 } 212 #endif 213 214 static const struct sdhci_pci_fixes sdhci_ricoh = { 215 .probe = ricoh_probe, 216 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 217 SDHCI_QUIRK_FORCE_DMA | 218 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 219 }; 220 221 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 222 .probe_slot = ricoh_mmc_probe_slot, 223 #ifdef CONFIG_PM_SLEEP 224 .resume = ricoh_mmc_resume, 225 #endif 226 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 227 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 228 SDHCI_QUIRK_NO_CARD_NO_RESET | 229 SDHCI_QUIRK_MISSING_CAPS 230 }; 231 232 static const struct sdhci_pci_fixes sdhci_ene_712 = { 233 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 234 SDHCI_QUIRK_BROKEN_DMA, 235 }; 236 237 static const struct sdhci_pci_fixes sdhci_ene_714 = { 238 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 239 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 240 SDHCI_QUIRK_BROKEN_DMA, 241 }; 242 243 static const struct sdhci_pci_fixes sdhci_cafe = { 244 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 245 SDHCI_QUIRK_NO_BUSY_IRQ | 246 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 247 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 248 }; 249 250 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 251 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 252 }; 253 254 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 255 { 256 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 257 return 0; 258 } 259 260 /* 261 * ADMA operation is disabled for Moorestown platform due to 262 * hardware bugs. 263 */ 264 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 265 { 266 /* 267 * slots number is fixed here for MRST as SDIO3/5 are never used and 268 * have hardware bugs. 269 */ 270 chip->num_slots = 1; 271 return 0; 272 } 273 274 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 275 { 276 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 277 return 0; 278 } 279 280 #ifdef CONFIG_PM 281 282 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 283 { 284 struct sdhci_pci_slot *slot = dev_id; 285 struct sdhci_host *host = slot->host; 286 287 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 288 return IRQ_HANDLED; 289 } 290 291 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 292 { 293 int err, irq, gpio = slot->cd_gpio; 294 295 slot->cd_gpio = -EINVAL; 296 slot->cd_irq = -EINVAL; 297 298 if (!gpio_is_valid(gpio)) 299 return; 300 301 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 302 if (err < 0) 303 goto out; 304 305 err = gpio_direction_input(gpio); 306 if (err < 0) 307 goto out_free; 308 309 irq = gpio_to_irq(gpio); 310 if (irq < 0) 311 goto out_free; 312 313 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 314 IRQF_TRIGGER_FALLING, "sd_cd", slot); 315 if (err) 316 goto out_free; 317 318 slot->cd_gpio = gpio; 319 slot->cd_irq = irq; 320 321 return; 322 323 out_free: 324 devm_gpio_free(&slot->chip->pdev->dev, gpio); 325 out: 326 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 327 } 328 329 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 330 { 331 if (slot->cd_irq >= 0) 332 free_irq(slot->cd_irq, slot); 333 } 334 335 #else 336 337 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 338 { 339 } 340 341 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 342 { 343 } 344 345 #endif 346 347 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 348 { 349 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 350 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC | 351 MMC_CAP2_HC_ERASE_SZ; 352 return 0; 353 } 354 355 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 356 { 357 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 358 return 0; 359 } 360 361 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 362 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 363 .probe_slot = mrst_hc_probe_slot, 364 }; 365 366 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 367 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 368 .probe = mrst_hc_probe, 369 }; 370 371 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 372 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 373 .allow_runtime_pm = true, 374 .own_cd_for_runtime_pm = true, 375 }; 376 377 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 378 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 379 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 380 .allow_runtime_pm = true, 381 .probe_slot = mfd_sdio_probe_slot, 382 }; 383 384 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 385 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 386 .allow_runtime_pm = true, 387 .probe_slot = mfd_emmc_probe_slot, 388 }; 389 390 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 391 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 392 .probe_slot = pch_hc_probe_slot, 393 }; 394 395 enum { 396 INTEL_DSM_FNS = 0, 397 INTEL_DSM_DRV_STRENGTH = 9, 398 INTEL_DSM_D3_RETUNE = 10, 399 }; 400 401 struct intel_host { 402 u32 dsm_fns; 403 int drv_strength; 404 bool d3_retune; 405 }; 406 407 const guid_t intel_dsm_guid = 408 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F, 409 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61); 410 411 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 412 unsigned int fn, u32 *result) 413 { 414 union acpi_object *obj; 415 int err = 0; 416 size_t len; 417 418 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL); 419 if (!obj) 420 return -EOPNOTSUPP; 421 422 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { 423 err = -EINVAL; 424 goto out; 425 } 426 427 len = min_t(size_t, obj->buffer.length, 4); 428 429 *result = 0; 430 memcpy(result, obj->buffer.pointer, len); 431 out: 432 ACPI_FREE(obj); 433 434 return err; 435 } 436 437 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 438 unsigned int fn, u32 *result) 439 { 440 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 441 return -EOPNOTSUPP; 442 443 return __intel_dsm(intel_host, dev, fn, result); 444 } 445 446 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 447 struct mmc_host *mmc) 448 { 449 int err; 450 u32 val; 451 452 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 453 if (err) { 454 pr_debug("%s: DSM not supported, error %d\n", 455 mmc_hostname(mmc), err); 456 return; 457 } 458 459 pr_debug("%s: DSM function mask %#x\n", 460 mmc_hostname(mmc), intel_host->dsm_fns); 461 462 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 463 intel_host->drv_strength = err ? 0 : val; 464 465 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 466 intel_host->d3_retune = err ? true : !!val; 467 } 468 469 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 470 { 471 u8 reg; 472 473 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 474 reg |= 0x10; 475 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 476 /* For eMMC, minimum is 1us but give it 9us for good measure */ 477 udelay(9); 478 reg &= ~0x10; 479 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 480 /* For eMMC, minimum is 200us but give it 300us for good measure */ 481 usleep_range(300, 1000); 482 } 483 484 static int intel_select_drive_strength(struct mmc_card *card, 485 unsigned int max_dtr, int host_drv, 486 int card_drv, int *drv_type) 487 { 488 struct sdhci_host *host = mmc_priv(card->host); 489 struct sdhci_pci_slot *slot = sdhci_priv(host); 490 struct intel_host *intel_host = sdhci_pci_priv(slot); 491 492 return intel_host->drv_strength; 493 } 494 495 static int bxt_get_cd(struct mmc_host *mmc) 496 { 497 int gpio_cd = mmc_gpio_get_cd(mmc); 498 struct sdhci_host *host = mmc_priv(mmc); 499 unsigned long flags; 500 int ret = 0; 501 502 if (!gpio_cd) 503 return 0; 504 505 spin_lock_irqsave(&host->lock, flags); 506 507 if (host->flags & SDHCI_DEVICE_DEAD) 508 goto out; 509 510 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 511 out: 512 spin_unlock_irqrestore(&host->lock, flags); 513 514 return ret; 515 } 516 517 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 518 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 519 520 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 521 unsigned short vdd) 522 { 523 int cntr; 524 u8 reg; 525 526 sdhci_set_power(host, mode, vdd); 527 528 if (mode == MMC_POWER_OFF) 529 return; 530 531 /* 532 * Bus power might not enable after D3 -> D0 transition due to the 533 * present state not yet having propagated. Retry for up to 2ms. 534 */ 535 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 536 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 537 if (reg & SDHCI_POWER_ON) 538 break; 539 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 540 reg |= SDHCI_POWER_ON; 541 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 542 } 543 } 544 545 static const struct sdhci_ops sdhci_intel_byt_ops = { 546 .set_clock = sdhci_set_clock, 547 .set_power = sdhci_intel_set_power, 548 .enable_dma = sdhci_pci_enable_dma, 549 .set_bus_width = sdhci_pci_set_bus_width, 550 .reset = sdhci_reset, 551 .set_uhs_signaling = sdhci_set_uhs_signaling, 552 .hw_reset = sdhci_pci_hw_reset, 553 }; 554 555 static void byt_read_dsm(struct sdhci_pci_slot *slot) 556 { 557 struct intel_host *intel_host = sdhci_pci_priv(slot); 558 struct device *dev = &slot->chip->pdev->dev; 559 struct mmc_host *mmc = slot->host->mmc; 560 561 intel_dsm_init(intel_host, dev, mmc); 562 slot->chip->rpm_retune = intel_host->d3_retune; 563 } 564 565 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 566 { 567 byt_read_dsm(slot); 568 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 569 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 570 MMC_CAP_CMD_DURING_TFR | 571 MMC_CAP_WAIT_WHILE_BUSY; 572 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ; 573 slot->hw_reset = sdhci_pci_int_hw_reset; 574 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 575 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 576 slot->host->mmc_host_ops.select_drive_strength = 577 intel_select_drive_strength; 578 return 0; 579 } 580 581 #ifdef CONFIG_ACPI 582 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 583 { 584 acpi_status status; 585 unsigned long long max_freq; 586 587 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 588 "MXFQ", NULL, &max_freq); 589 if (ACPI_FAILURE(status)) { 590 dev_err(&slot->chip->pdev->dev, 591 "MXFQ not found in acpi table\n"); 592 return -EINVAL; 593 } 594 595 slot->host->mmc->f_max = max_freq * 1000000; 596 597 return 0; 598 } 599 #else 600 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 601 { 602 return 0; 603 } 604 #endif 605 606 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 607 { 608 int err; 609 610 byt_read_dsm(slot); 611 612 err = ni_set_max_freq(slot); 613 if (err) 614 return err; 615 616 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 617 MMC_CAP_WAIT_WHILE_BUSY; 618 return 0; 619 } 620 621 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 622 { 623 byt_read_dsm(slot); 624 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 625 MMC_CAP_WAIT_WHILE_BUSY; 626 return 0; 627 } 628 629 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 630 { 631 byt_read_dsm(slot); 632 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | 633 MMC_CAP_AGGRESSIVE_PM; 634 slot->cd_idx = 0; 635 slot->cd_override_level = true; 636 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 637 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 638 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 639 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) 640 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 641 642 return 0; 643 } 644 645 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 646 .allow_runtime_pm = true, 647 .probe_slot = byt_emmc_probe_slot, 648 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 649 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 650 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 651 SDHCI_QUIRK2_STOP_WITH_TC, 652 .ops = &sdhci_intel_byt_ops, 653 .priv_size = sizeof(struct intel_host), 654 }; 655 656 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 657 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 658 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 659 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 660 .allow_runtime_pm = true, 661 .probe_slot = ni_byt_sdio_probe_slot, 662 .ops = &sdhci_intel_byt_ops, 663 .priv_size = sizeof(struct intel_host), 664 }; 665 666 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 667 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 668 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 669 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 670 .allow_runtime_pm = true, 671 .probe_slot = byt_sdio_probe_slot, 672 .ops = &sdhci_intel_byt_ops, 673 .priv_size = sizeof(struct intel_host), 674 }; 675 676 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 677 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 678 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 679 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 680 SDHCI_QUIRK2_STOP_WITH_TC, 681 .allow_runtime_pm = true, 682 .own_cd_for_runtime_pm = true, 683 .probe_slot = byt_sd_probe_slot, 684 .ops = &sdhci_intel_byt_ops, 685 .priv_size = sizeof(struct intel_host), 686 }; 687 688 /* Define Host controllers for Intel Merrifield platform */ 689 #define INTEL_MRFLD_EMMC_0 0 690 #define INTEL_MRFLD_EMMC_1 1 691 #define INTEL_MRFLD_SD 2 692 #define INTEL_MRFLD_SDIO 3 693 694 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 695 { 696 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 697 698 switch (func) { 699 case INTEL_MRFLD_EMMC_0: 700 case INTEL_MRFLD_EMMC_1: 701 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 702 MMC_CAP_8_BIT_DATA | 703 MMC_CAP_1_8V_DDR; 704 break; 705 case INTEL_MRFLD_SD: 706 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 707 break; 708 case INTEL_MRFLD_SDIO: 709 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 710 MMC_CAP_POWER_OFF_CARD; 711 break; 712 default: 713 return -ENODEV; 714 } 715 return 0; 716 } 717 718 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 719 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 720 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 721 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 722 .allow_runtime_pm = true, 723 .probe_slot = intel_mrfld_mmc_probe_slot, 724 }; 725 726 /* O2Micro extra registers */ 727 #define O2_SD_LOCK_WP 0xD3 728 #define O2_SD_MULTI_VCC3V 0xEE 729 #define O2_SD_CLKREQ 0xEC 730 #define O2_SD_CAPS 0xE0 731 #define O2_SD_ADMA1 0xE2 732 #define O2_SD_ADMA2 0xE7 733 #define O2_SD_INF_MOD 0xF1 734 735 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 736 { 737 u8 scratch; 738 int ret; 739 740 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 741 if (ret) 742 return ret; 743 744 /* 745 * Turn PMOS on [bit 0], set over current detection to 2.4 V 746 * [bit 1:2] and enable over current debouncing [bit 6]. 747 */ 748 if (on) 749 scratch |= 0x47; 750 else 751 scratch &= ~0x47; 752 753 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 754 } 755 756 static int jmicron_probe(struct sdhci_pci_chip *chip) 757 { 758 int ret; 759 u16 mmcdev = 0; 760 761 if (chip->pdev->revision == 0) { 762 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 763 SDHCI_QUIRK_32BIT_DMA_SIZE | 764 SDHCI_QUIRK_32BIT_ADMA_SIZE | 765 SDHCI_QUIRK_RESET_AFTER_REQUEST | 766 SDHCI_QUIRK_BROKEN_SMALL_PIO; 767 } 768 769 /* 770 * JMicron chips can have two interfaces to the same hardware 771 * in order to work around limitations in Microsoft's driver. 772 * We need to make sure we only bind to one of them. 773 * 774 * This code assumes two things: 775 * 776 * 1. The PCI code adds subfunctions in order. 777 * 778 * 2. The MMC interface has a lower subfunction number 779 * than the SD interface. 780 */ 781 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 782 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 783 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 784 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 785 786 if (mmcdev) { 787 struct pci_dev *sd_dev; 788 789 sd_dev = NULL; 790 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 791 mmcdev, sd_dev)) != NULL) { 792 if ((PCI_SLOT(chip->pdev->devfn) == 793 PCI_SLOT(sd_dev->devfn)) && 794 (chip->pdev->bus == sd_dev->bus)) 795 break; 796 } 797 798 if (sd_dev) { 799 pci_dev_put(sd_dev); 800 dev_info(&chip->pdev->dev, "Refusing to bind to " 801 "secondary interface.\n"); 802 return -ENODEV; 803 } 804 } 805 806 /* 807 * JMicron chips need a bit of a nudge to enable the power 808 * output pins. 809 */ 810 ret = jmicron_pmos(chip, 1); 811 if (ret) { 812 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 813 return ret; 814 } 815 816 /* quirk for unsable RO-detection on JM388 chips */ 817 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 818 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 819 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 820 821 return 0; 822 } 823 824 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 825 { 826 u8 scratch; 827 828 scratch = readb(host->ioaddr + 0xC0); 829 830 if (on) 831 scratch |= 0x01; 832 else 833 scratch &= ~0x01; 834 835 writeb(scratch, host->ioaddr + 0xC0); 836 } 837 838 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 839 { 840 if (slot->chip->pdev->revision == 0) { 841 u16 version; 842 843 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 844 version = (version & SDHCI_VENDOR_VER_MASK) >> 845 SDHCI_VENDOR_VER_SHIFT; 846 847 /* 848 * Older versions of the chip have lots of nasty glitches 849 * in the ADMA engine. It's best just to avoid it 850 * completely. 851 */ 852 if (version < 0xAC) 853 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 854 } 855 856 /* JM388 MMC doesn't support 1.8V while SD supports it */ 857 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 858 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 859 MMC_VDD_29_30 | MMC_VDD_30_31 | 860 MMC_VDD_165_195; /* allow 1.8V */ 861 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 862 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 863 } 864 865 /* 866 * The secondary interface requires a bit set to get the 867 * interrupts. 868 */ 869 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 870 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 871 jmicron_enable_mmc(slot->host, 1); 872 873 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 874 875 return 0; 876 } 877 878 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 879 { 880 if (dead) 881 return; 882 883 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 884 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 885 jmicron_enable_mmc(slot->host, 0); 886 } 887 888 #ifdef CONFIG_PM_SLEEP 889 static int jmicron_suspend(struct sdhci_pci_chip *chip) 890 { 891 int i, ret; 892 893 ret = __sdhci_pci_suspend_host(chip); 894 if (ret) 895 return ret; 896 897 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 898 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 899 for (i = 0; i < chip->num_slots; i++) 900 jmicron_enable_mmc(chip->slots[i]->host, 0); 901 } 902 903 sdhci_pci_init_wakeup(chip); 904 905 return 0; 906 } 907 908 static int jmicron_resume(struct sdhci_pci_chip *chip) 909 { 910 int ret, i; 911 912 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 913 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 914 for (i = 0; i < chip->num_slots; i++) 915 jmicron_enable_mmc(chip->slots[i]->host, 1); 916 } 917 918 ret = jmicron_pmos(chip, 1); 919 if (ret) { 920 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 921 return ret; 922 } 923 924 return sdhci_pci_resume_host(chip); 925 } 926 #endif 927 928 static const struct sdhci_pci_fixes sdhci_o2 = { 929 .probe = sdhci_pci_o2_probe, 930 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 931 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 932 .probe_slot = sdhci_pci_o2_probe_slot, 933 #ifdef CONFIG_PM_SLEEP 934 .resume = sdhci_pci_o2_resume, 935 #endif 936 }; 937 938 static const struct sdhci_pci_fixes sdhci_jmicron = { 939 .probe = jmicron_probe, 940 941 .probe_slot = jmicron_probe_slot, 942 .remove_slot = jmicron_remove_slot, 943 944 #ifdef CONFIG_PM_SLEEP 945 .suspend = jmicron_suspend, 946 .resume = jmicron_resume, 947 #endif 948 }; 949 950 /* SysKonnect CardBus2SDIO extra registers */ 951 #define SYSKT_CTRL 0x200 952 #define SYSKT_RDFIFO_STAT 0x204 953 #define SYSKT_WRFIFO_STAT 0x208 954 #define SYSKT_POWER_DATA 0x20c 955 #define SYSKT_POWER_330 0xef 956 #define SYSKT_POWER_300 0xf8 957 #define SYSKT_POWER_184 0xcc 958 #define SYSKT_POWER_CMD 0x20d 959 #define SYSKT_POWER_START (1 << 7) 960 #define SYSKT_POWER_STATUS 0x20e 961 #define SYSKT_POWER_STATUS_OK (1 << 0) 962 #define SYSKT_BOARD_REV 0x210 963 #define SYSKT_CHIP_REV 0x211 964 #define SYSKT_CONF_DATA 0x212 965 #define SYSKT_CONF_DATA_1V8 (1 << 2) 966 #define SYSKT_CONF_DATA_2V5 (1 << 1) 967 #define SYSKT_CONF_DATA_3V3 (1 << 0) 968 969 static int syskt_probe(struct sdhci_pci_chip *chip) 970 { 971 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 972 chip->pdev->class &= ~0x0000FF; 973 chip->pdev->class |= PCI_SDHCI_IFDMA; 974 } 975 return 0; 976 } 977 978 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 979 { 980 int tm, ps; 981 982 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 983 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 984 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 985 "board rev %d.%d, chip rev %d.%d\n", 986 board_rev >> 4, board_rev & 0xf, 987 chip_rev >> 4, chip_rev & 0xf); 988 if (chip_rev >= 0x20) 989 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 990 991 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 992 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 993 udelay(50); 994 tm = 10; /* Wait max 1 ms */ 995 do { 996 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 997 if (ps & SYSKT_POWER_STATUS_OK) 998 break; 999 udelay(100); 1000 } while (--tm); 1001 if (!tm) { 1002 dev_err(&slot->chip->pdev->dev, 1003 "power regulator never stabilized"); 1004 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 1005 return -ENODEV; 1006 } 1007 1008 return 0; 1009 } 1010 1011 static const struct sdhci_pci_fixes sdhci_syskt = { 1012 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 1013 .probe = syskt_probe, 1014 .probe_slot = syskt_probe_slot, 1015 }; 1016 1017 static int via_probe(struct sdhci_pci_chip *chip) 1018 { 1019 if (chip->pdev->revision == 0x10) 1020 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 1021 1022 return 0; 1023 } 1024 1025 static const struct sdhci_pci_fixes sdhci_via = { 1026 .probe = via_probe, 1027 }; 1028 1029 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 1030 { 1031 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 1032 return 0; 1033 } 1034 1035 static const struct sdhci_pci_fixes sdhci_rtsx = { 1036 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1037 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 1038 SDHCI_QUIRK2_BROKEN_DDR50, 1039 .probe_slot = rtsx_probe_slot, 1040 }; 1041 1042 /*AMD chipset generation*/ 1043 enum amd_chipset_gen { 1044 AMD_CHIPSET_BEFORE_ML, 1045 AMD_CHIPSET_CZ, 1046 AMD_CHIPSET_NL, 1047 AMD_CHIPSET_UNKNOWN, 1048 }; 1049 1050 /* AMD registers */ 1051 #define AMD_SD_AUTO_PATTERN 0xB8 1052 #define AMD_MSLEEP_DURATION 4 1053 #define AMD_SD_MISC_CONTROL 0xD0 1054 #define AMD_MAX_TUNE_VALUE 0x0B 1055 #define AMD_AUTO_TUNE_SEL 0x10800 1056 #define AMD_FIFO_PTR 0x30 1057 #define AMD_BIT_MASK 0x1F 1058 1059 static void amd_tuning_reset(struct sdhci_host *host) 1060 { 1061 unsigned int val; 1062 1063 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1064 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 1065 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1066 1067 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1068 val &= ~SDHCI_CTRL_EXEC_TUNING; 1069 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1070 } 1071 1072 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 1073 { 1074 unsigned int val; 1075 1076 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 1077 val &= ~AMD_BIT_MASK; 1078 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 1079 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 1080 } 1081 1082 static void amd_enable_manual_tuning(struct pci_dev *pdev) 1083 { 1084 unsigned int val; 1085 1086 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 1087 val |= AMD_FIFO_PTR; 1088 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 1089 } 1090 1091 static int amd_execute_tuning(struct sdhci_host *host, u32 opcode) 1092 { 1093 struct sdhci_pci_slot *slot = sdhci_priv(host); 1094 struct pci_dev *pdev = slot->chip->pdev; 1095 u8 valid_win = 0; 1096 u8 valid_win_max = 0; 1097 u8 valid_win_end = 0; 1098 u8 ctrl, tune_around; 1099 1100 amd_tuning_reset(host); 1101 1102 for (tune_around = 0; tune_around < 12; tune_around++) { 1103 amd_config_tuning_phase(pdev, tune_around); 1104 1105 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1106 valid_win = 0; 1107 msleep(AMD_MSLEEP_DURATION); 1108 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 1109 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 1110 } else if (++valid_win > valid_win_max) { 1111 valid_win_max = valid_win; 1112 valid_win_end = tune_around; 1113 } 1114 } 1115 1116 if (!valid_win_max) { 1117 dev_err(&pdev->dev, "no tuning point found\n"); 1118 return -EIO; 1119 } 1120 1121 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 1122 1123 amd_enable_manual_tuning(pdev); 1124 1125 host->mmc->retune_period = 0; 1126 1127 return 0; 1128 } 1129 1130 static int amd_probe(struct sdhci_pci_chip *chip) 1131 { 1132 struct pci_dev *smbus_dev; 1133 enum amd_chipset_gen gen; 1134 1135 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1136 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 1137 if (smbus_dev) { 1138 gen = AMD_CHIPSET_BEFORE_ML; 1139 } else { 1140 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1141 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1142 if (smbus_dev) { 1143 if (smbus_dev->revision < 0x51) 1144 gen = AMD_CHIPSET_CZ; 1145 else 1146 gen = AMD_CHIPSET_NL; 1147 } else { 1148 gen = AMD_CHIPSET_UNKNOWN; 1149 } 1150 } 1151 1152 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1153 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1154 1155 return 0; 1156 } 1157 1158 static const struct sdhci_ops amd_sdhci_pci_ops = { 1159 .set_clock = sdhci_set_clock, 1160 .enable_dma = sdhci_pci_enable_dma, 1161 .set_bus_width = sdhci_pci_set_bus_width, 1162 .reset = sdhci_reset, 1163 .set_uhs_signaling = sdhci_set_uhs_signaling, 1164 .platform_execute_tuning = amd_execute_tuning, 1165 }; 1166 1167 static const struct sdhci_pci_fixes sdhci_amd = { 1168 .probe = amd_probe, 1169 .ops = &amd_sdhci_pci_ops, 1170 }; 1171 1172 static const struct pci_device_id pci_ids[] = { 1173 { 1174 .vendor = PCI_VENDOR_ID_RICOH, 1175 .device = PCI_DEVICE_ID_RICOH_R5C822, 1176 .subvendor = PCI_ANY_ID, 1177 .subdevice = PCI_ANY_ID, 1178 .driver_data = (kernel_ulong_t)&sdhci_ricoh, 1179 }, 1180 1181 { 1182 .vendor = PCI_VENDOR_ID_RICOH, 1183 .device = 0x843, 1184 .subvendor = PCI_ANY_ID, 1185 .subdevice = PCI_ANY_ID, 1186 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 1187 }, 1188 1189 { 1190 .vendor = PCI_VENDOR_ID_RICOH, 1191 .device = 0xe822, 1192 .subvendor = PCI_ANY_ID, 1193 .subdevice = PCI_ANY_ID, 1194 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 1195 }, 1196 1197 { 1198 .vendor = PCI_VENDOR_ID_RICOH, 1199 .device = 0xe823, 1200 .subvendor = PCI_ANY_ID, 1201 .subdevice = PCI_ANY_ID, 1202 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 1203 }, 1204 1205 { 1206 .vendor = PCI_VENDOR_ID_ENE, 1207 .device = PCI_DEVICE_ID_ENE_CB712_SD, 1208 .subvendor = PCI_ANY_ID, 1209 .subdevice = PCI_ANY_ID, 1210 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 1211 }, 1212 1213 { 1214 .vendor = PCI_VENDOR_ID_ENE, 1215 .device = PCI_DEVICE_ID_ENE_CB712_SD_2, 1216 .subvendor = PCI_ANY_ID, 1217 .subdevice = PCI_ANY_ID, 1218 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 1219 }, 1220 1221 { 1222 .vendor = PCI_VENDOR_ID_ENE, 1223 .device = PCI_DEVICE_ID_ENE_CB714_SD, 1224 .subvendor = PCI_ANY_ID, 1225 .subdevice = PCI_ANY_ID, 1226 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 1227 }, 1228 1229 { 1230 .vendor = PCI_VENDOR_ID_ENE, 1231 .device = PCI_DEVICE_ID_ENE_CB714_SD_2, 1232 .subvendor = PCI_ANY_ID, 1233 .subdevice = PCI_ANY_ID, 1234 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 1235 }, 1236 1237 { 1238 .vendor = PCI_VENDOR_ID_MARVELL, 1239 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD, 1240 .subvendor = PCI_ANY_ID, 1241 .subdevice = PCI_ANY_ID, 1242 .driver_data = (kernel_ulong_t)&sdhci_cafe, 1243 }, 1244 1245 { 1246 .vendor = PCI_VENDOR_ID_JMICRON, 1247 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD, 1248 .subvendor = PCI_ANY_ID, 1249 .subdevice = PCI_ANY_ID, 1250 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1251 }, 1252 1253 { 1254 .vendor = PCI_VENDOR_ID_JMICRON, 1255 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC, 1256 .subvendor = PCI_ANY_ID, 1257 .subdevice = PCI_ANY_ID, 1258 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1259 }, 1260 1261 { 1262 .vendor = PCI_VENDOR_ID_JMICRON, 1263 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD, 1264 .subvendor = PCI_ANY_ID, 1265 .subdevice = PCI_ANY_ID, 1266 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1267 }, 1268 1269 { 1270 .vendor = PCI_VENDOR_ID_JMICRON, 1271 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD, 1272 .subvendor = PCI_ANY_ID, 1273 .subdevice = PCI_ANY_ID, 1274 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1275 }, 1276 1277 { 1278 .vendor = PCI_VENDOR_ID_SYSKONNECT, 1279 .device = 0x8000, 1280 .subvendor = PCI_ANY_ID, 1281 .subdevice = PCI_ANY_ID, 1282 .driver_data = (kernel_ulong_t)&sdhci_syskt, 1283 }, 1284 1285 { 1286 .vendor = PCI_VENDOR_ID_VIA, 1287 .device = 0x95d0, 1288 .subvendor = PCI_ANY_ID, 1289 .subdevice = PCI_ANY_ID, 1290 .driver_data = (kernel_ulong_t)&sdhci_via, 1291 }, 1292 1293 { 1294 .vendor = PCI_VENDOR_ID_REALTEK, 1295 .device = 0x5250, 1296 .subvendor = PCI_ANY_ID, 1297 .subdevice = PCI_ANY_ID, 1298 .driver_data = (kernel_ulong_t)&sdhci_rtsx, 1299 }, 1300 1301 { 1302 .vendor = PCI_VENDOR_ID_INTEL, 1303 .device = PCI_DEVICE_ID_INTEL_QRK_SD, 1304 .subvendor = PCI_ANY_ID, 1305 .subdevice = PCI_ANY_ID, 1306 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk, 1307 }, 1308 1309 { 1310 .vendor = PCI_VENDOR_ID_INTEL, 1311 .device = PCI_DEVICE_ID_INTEL_MRST_SD0, 1312 .subvendor = PCI_ANY_ID, 1313 .subdevice = PCI_ANY_ID, 1314 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0, 1315 }, 1316 1317 { 1318 .vendor = PCI_VENDOR_ID_INTEL, 1319 .device = PCI_DEVICE_ID_INTEL_MRST_SD1, 1320 .subvendor = PCI_ANY_ID, 1321 .subdevice = PCI_ANY_ID, 1322 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 1323 }, 1324 1325 { 1326 .vendor = PCI_VENDOR_ID_INTEL, 1327 .device = PCI_DEVICE_ID_INTEL_MRST_SD2, 1328 .subvendor = PCI_ANY_ID, 1329 .subdevice = PCI_ANY_ID, 1330 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 1331 }, 1332 1333 { 1334 .vendor = PCI_VENDOR_ID_INTEL, 1335 .device = PCI_DEVICE_ID_INTEL_MFD_SD, 1336 .subvendor = PCI_ANY_ID, 1337 .subdevice = PCI_ANY_ID, 1338 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1339 }, 1340 1341 { 1342 .vendor = PCI_VENDOR_ID_INTEL, 1343 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1, 1344 .subvendor = PCI_ANY_ID, 1345 .subdevice = PCI_ANY_ID, 1346 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1347 }, 1348 1349 { 1350 .vendor = PCI_VENDOR_ID_INTEL, 1351 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2, 1352 .subvendor = PCI_ANY_ID, 1353 .subdevice = PCI_ANY_ID, 1354 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1355 }, 1356 1357 { 1358 .vendor = PCI_VENDOR_ID_INTEL, 1359 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0, 1360 .subvendor = PCI_ANY_ID, 1361 .subdevice = PCI_ANY_ID, 1362 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1363 }, 1364 1365 { 1366 .vendor = PCI_VENDOR_ID_INTEL, 1367 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1, 1368 .subvendor = PCI_ANY_ID, 1369 .subdevice = PCI_ANY_ID, 1370 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1371 }, 1372 1373 { 1374 .vendor = PCI_VENDOR_ID_INTEL, 1375 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0, 1376 .subvendor = PCI_ANY_ID, 1377 .subdevice = PCI_ANY_ID, 1378 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1379 }, 1380 1381 { 1382 .vendor = PCI_VENDOR_ID_INTEL, 1383 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1, 1384 .subvendor = PCI_ANY_ID, 1385 .subdevice = PCI_ANY_ID, 1386 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1387 }, 1388 1389 { 1390 .vendor = PCI_VENDOR_ID_INTEL, 1391 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC, 1392 .subvendor = PCI_ANY_ID, 1393 .subdevice = PCI_ANY_ID, 1394 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1395 }, 1396 1397 { 1398 .vendor = PCI_VENDOR_ID_INTEL, 1399 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, 1400 .subvendor = PCI_VENDOR_ID_NI, 1401 .subdevice = 0x7884, 1402 .driver_data = (kernel_ulong_t)&sdhci_ni_byt_sdio, 1403 }, 1404 1405 { 1406 .vendor = PCI_VENDOR_ID_INTEL, 1407 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, 1408 .subvendor = PCI_ANY_ID, 1409 .subdevice = PCI_ANY_ID, 1410 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1411 }, 1412 1413 { 1414 .vendor = PCI_VENDOR_ID_INTEL, 1415 .device = PCI_DEVICE_ID_INTEL_BYT_SD, 1416 .subvendor = PCI_ANY_ID, 1417 .subdevice = PCI_ANY_ID, 1418 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1419 }, 1420 1421 { 1422 .vendor = PCI_VENDOR_ID_INTEL, 1423 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2, 1424 .subvendor = PCI_ANY_ID, 1425 .subdevice = PCI_ANY_ID, 1426 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1427 }, 1428 1429 { 1430 .vendor = PCI_VENDOR_ID_INTEL, 1431 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC, 1432 .subvendor = PCI_ANY_ID, 1433 .subdevice = PCI_ANY_ID, 1434 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1435 }, 1436 1437 { 1438 .vendor = PCI_VENDOR_ID_INTEL, 1439 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO, 1440 .subvendor = PCI_ANY_ID, 1441 .subdevice = PCI_ANY_ID, 1442 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1443 }, 1444 1445 { 1446 .vendor = PCI_VENDOR_ID_INTEL, 1447 .device = PCI_DEVICE_ID_INTEL_BSW_SD, 1448 .subvendor = PCI_ANY_ID, 1449 .subdevice = PCI_ANY_ID, 1450 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1451 }, 1452 1453 { 1454 .vendor = PCI_VENDOR_ID_INTEL, 1455 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0, 1456 .subvendor = PCI_ANY_ID, 1457 .subdevice = PCI_ANY_ID, 1458 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1459 }, 1460 1461 { 1462 .vendor = PCI_VENDOR_ID_INTEL, 1463 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1, 1464 .subvendor = PCI_ANY_ID, 1465 .subdevice = PCI_ANY_ID, 1466 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1467 }, 1468 1469 { 1470 .vendor = PCI_VENDOR_ID_INTEL, 1471 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2, 1472 .subvendor = PCI_ANY_ID, 1473 .subdevice = PCI_ANY_ID, 1474 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1475 }, 1476 1477 { 1478 .vendor = PCI_VENDOR_ID_INTEL, 1479 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0, 1480 .subvendor = PCI_ANY_ID, 1481 .subdevice = PCI_ANY_ID, 1482 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1483 }, 1484 1485 { 1486 .vendor = PCI_VENDOR_ID_INTEL, 1487 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1, 1488 .subvendor = PCI_ANY_ID, 1489 .subdevice = PCI_ANY_ID, 1490 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1491 }, 1492 1493 { 1494 .vendor = PCI_VENDOR_ID_INTEL, 1495 .device = PCI_DEVICE_ID_INTEL_MRFLD_MMC, 1496 .subvendor = PCI_ANY_ID, 1497 .subdevice = PCI_ANY_ID, 1498 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfld_mmc, 1499 }, 1500 1501 { 1502 .vendor = PCI_VENDOR_ID_INTEL, 1503 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC, 1504 .subvendor = PCI_ANY_ID, 1505 .subdevice = PCI_ANY_ID, 1506 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1507 }, 1508 1509 { 1510 .vendor = PCI_VENDOR_ID_INTEL, 1511 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO, 1512 .subvendor = PCI_ANY_ID, 1513 .subdevice = PCI_ANY_ID, 1514 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1515 }, 1516 1517 { 1518 .vendor = PCI_VENDOR_ID_INTEL, 1519 .device = PCI_DEVICE_ID_INTEL_SPT_SD, 1520 .subvendor = PCI_ANY_ID, 1521 .subdevice = PCI_ANY_ID, 1522 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1523 }, 1524 1525 { 1526 .vendor = PCI_VENDOR_ID_INTEL, 1527 .device = PCI_DEVICE_ID_INTEL_DNV_EMMC, 1528 .subvendor = PCI_ANY_ID, 1529 .subdevice = PCI_ANY_ID, 1530 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1531 }, 1532 1533 { 1534 .vendor = PCI_VENDOR_ID_INTEL, 1535 .device = PCI_DEVICE_ID_INTEL_BXT_EMMC, 1536 .subvendor = PCI_ANY_ID, 1537 .subdevice = PCI_ANY_ID, 1538 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1539 }, 1540 1541 { 1542 .vendor = PCI_VENDOR_ID_INTEL, 1543 .device = PCI_DEVICE_ID_INTEL_BXT_SDIO, 1544 .subvendor = PCI_ANY_ID, 1545 .subdevice = PCI_ANY_ID, 1546 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1547 }, 1548 1549 { 1550 .vendor = PCI_VENDOR_ID_INTEL, 1551 .device = PCI_DEVICE_ID_INTEL_BXT_SD, 1552 .subvendor = PCI_ANY_ID, 1553 .subdevice = PCI_ANY_ID, 1554 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1555 }, 1556 1557 { 1558 .vendor = PCI_VENDOR_ID_INTEL, 1559 .device = PCI_DEVICE_ID_INTEL_BXTM_EMMC, 1560 .subvendor = PCI_ANY_ID, 1561 .subdevice = PCI_ANY_ID, 1562 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1563 }, 1564 1565 { 1566 .vendor = PCI_VENDOR_ID_INTEL, 1567 .device = PCI_DEVICE_ID_INTEL_BXTM_SDIO, 1568 .subvendor = PCI_ANY_ID, 1569 .subdevice = PCI_ANY_ID, 1570 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1571 }, 1572 1573 { 1574 .vendor = PCI_VENDOR_ID_INTEL, 1575 .device = PCI_DEVICE_ID_INTEL_BXTM_SD, 1576 .subvendor = PCI_ANY_ID, 1577 .subdevice = PCI_ANY_ID, 1578 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1579 }, 1580 1581 { 1582 .vendor = PCI_VENDOR_ID_INTEL, 1583 .device = PCI_DEVICE_ID_INTEL_APL_EMMC, 1584 .subvendor = PCI_ANY_ID, 1585 .subdevice = PCI_ANY_ID, 1586 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1587 }, 1588 1589 { 1590 .vendor = PCI_VENDOR_ID_INTEL, 1591 .device = PCI_DEVICE_ID_INTEL_APL_SDIO, 1592 .subvendor = PCI_ANY_ID, 1593 .subdevice = PCI_ANY_ID, 1594 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1595 }, 1596 1597 { 1598 .vendor = PCI_VENDOR_ID_INTEL, 1599 .device = PCI_DEVICE_ID_INTEL_APL_SD, 1600 .subvendor = PCI_ANY_ID, 1601 .subdevice = PCI_ANY_ID, 1602 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1603 }, 1604 1605 { 1606 .vendor = PCI_VENDOR_ID_INTEL, 1607 .device = PCI_DEVICE_ID_INTEL_GLK_EMMC, 1608 .subvendor = PCI_ANY_ID, 1609 .subdevice = PCI_ANY_ID, 1610 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1611 }, 1612 1613 { 1614 .vendor = PCI_VENDOR_ID_INTEL, 1615 .device = PCI_DEVICE_ID_INTEL_GLK_SDIO, 1616 .subvendor = PCI_ANY_ID, 1617 .subdevice = PCI_ANY_ID, 1618 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1619 }, 1620 1621 { 1622 .vendor = PCI_VENDOR_ID_INTEL, 1623 .device = PCI_DEVICE_ID_INTEL_GLK_SD, 1624 .subvendor = PCI_ANY_ID, 1625 .subdevice = PCI_ANY_ID, 1626 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1627 }, 1628 1629 { 1630 .vendor = PCI_VENDOR_ID_O2, 1631 .device = PCI_DEVICE_ID_O2_8120, 1632 .subvendor = PCI_ANY_ID, 1633 .subdevice = PCI_ANY_ID, 1634 .driver_data = (kernel_ulong_t)&sdhci_o2, 1635 }, 1636 1637 { 1638 .vendor = PCI_VENDOR_ID_O2, 1639 .device = PCI_DEVICE_ID_O2_8220, 1640 .subvendor = PCI_ANY_ID, 1641 .subdevice = PCI_ANY_ID, 1642 .driver_data = (kernel_ulong_t)&sdhci_o2, 1643 }, 1644 1645 { 1646 .vendor = PCI_VENDOR_ID_O2, 1647 .device = PCI_DEVICE_ID_O2_8221, 1648 .subvendor = PCI_ANY_ID, 1649 .subdevice = PCI_ANY_ID, 1650 .driver_data = (kernel_ulong_t)&sdhci_o2, 1651 }, 1652 1653 { 1654 .vendor = PCI_VENDOR_ID_O2, 1655 .device = PCI_DEVICE_ID_O2_8320, 1656 .subvendor = PCI_ANY_ID, 1657 .subdevice = PCI_ANY_ID, 1658 .driver_data = (kernel_ulong_t)&sdhci_o2, 1659 }, 1660 1661 { 1662 .vendor = PCI_VENDOR_ID_O2, 1663 .device = PCI_DEVICE_ID_O2_8321, 1664 .subvendor = PCI_ANY_ID, 1665 .subdevice = PCI_ANY_ID, 1666 .driver_data = (kernel_ulong_t)&sdhci_o2, 1667 }, 1668 1669 { 1670 .vendor = PCI_VENDOR_ID_O2, 1671 .device = PCI_DEVICE_ID_O2_FUJIN2, 1672 .subvendor = PCI_ANY_ID, 1673 .subdevice = PCI_ANY_ID, 1674 .driver_data = (kernel_ulong_t)&sdhci_o2, 1675 }, 1676 1677 { 1678 .vendor = PCI_VENDOR_ID_O2, 1679 .device = PCI_DEVICE_ID_O2_SDS0, 1680 .subvendor = PCI_ANY_ID, 1681 .subdevice = PCI_ANY_ID, 1682 .driver_data = (kernel_ulong_t)&sdhci_o2, 1683 }, 1684 1685 { 1686 .vendor = PCI_VENDOR_ID_O2, 1687 .device = PCI_DEVICE_ID_O2_SDS1, 1688 .subvendor = PCI_ANY_ID, 1689 .subdevice = PCI_ANY_ID, 1690 .driver_data = (kernel_ulong_t)&sdhci_o2, 1691 }, 1692 1693 { 1694 .vendor = PCI_VENDOR_ID_O2, 1695 .device = PCI_DEVICE_ID_O2_SEABIRD0, 1696 .subvendor = PCI_ANY_ID, 1697 .subdevice = PCI_ANY_ID, 1698 .driver_data = (kernel_ulong_t)&sdhci_o2, 1699 }, 1700 1701 { 1702 .vendor = PCI_VENDOR_ID_O2, 1703 .device = PCI_DEVICE_ID_O2_SEABIRD1, 1704 .subvendor = PCI_ANY_ID, 1705 .subdevice = PCI_ANY_ID, 1706 .driver_data = (kernel_ulong_t)&sdhci_o2, 1707 }, 1708 { 1709 .vendor = PCI_VENDOR_ID_AMD, 1710 .device = PCI_ANY_ID, 1711 .class = PCI_CLASS_SYSTEM_SDHCI << 8, 1712 .class_mask = 0xFFFF00, 1713 .subvendor = PCI_ANY_ID, 1714 .subdevice = PCI_ANY_ID, 1715 .driver_data = (kernel_ulong_t)&sdhci_amd, 1716 }, 1717 { /* Generic SD host controller */ 1718 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) 1719 }, 1720 1721 { /* end: all zeroes */ }, 1722 }; 1723 1724 MODULE_DEVICE_TABLE(pci, pci_ids); 1725 1726 /*****************************************************************************\ 1727 * * 1728 * SDHCI core callbacks * 1729 * * 1730 \*****************************************************************************/ 1731 1732 static int sdhci_pci_enable_dma(struct sdhci_host *host) 1733 { 1734 struct sdhci_pci_slot *slot; 1735 struct pci_dev *pdev; 1736 1737 slot = sdhci_priv(host); 1738 pdev = slot->chip->pdev; 1739 1740 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1741 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1742 (host->flags & SDHCI_USE_SDMA)) { 1743 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1744 "doesn't fully claim to support it.\n"); 1745 } 1746 1747 pci_set_master(pdev); 1748 1749 return 0; 1750 } 1751 1752 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width) 1753 { 1754 u8 ctrl; 1755 1756 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1757 1758 switch (width) { 1759 case MMC_BUS_WIDTH_8: 1760 ctrl |= SDHCI_CTRL_8BITBUS; 1761 ctrl &= ~SDHCI_CTRL_4BITBUS; 1762 break; 1763 case MMC_BUS_WIDTH_4: 1764 ctrl |= SDHCI_CTRL_4BITBUS; 1765 ctrl &= ~SDHCI_CTRL_8BITBUS; 1766 break; 1767 default: 1768 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS); 1769 break; 1770 } 1771 1772 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1773 } 1774 1775 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1776 { 1777 struct sdhci_pci_slot *slot = sdhci_priv(host); 1778 int rst_n_gpio = slot->rst_n_gpio; 1779 1780 if (!gpio_is_valid(rst_n_gpio)) 1781 return; 1782 gpio_set_value_cansleep(rst_n_gpio, 0); 1783 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1784 udelay(10); 1785 gpio_set_value_cansleep(rst_n_gpio, 1); 1786 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1787 usleep_range(300, 1000); 1788 } 1789 1790 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1791 { 1792 struct sdhci_pci_slot *slot = sdhci_priv(host); 1793 1794 if (slot->hw_reset) 1795 slot->hw_reset(host); 1796 } 1797 1798 static const struct sdhci_ops sdhci_pci_ops = { 1799 .set_clock = sdhci_set_clock, 1800 .enable_dma = sdhci_pci_enable_dma, 1801 .set_bus_width = sdhci_pci_set_bus_width, 1802 .reset = sdhci_reset, 1803 .set_uhs_signaling = sdhci_set_uhs_signaling, 1804 .hw_reset = sdhci_pci_hw_reset, 1805 }; 1806 1807 /*****************************************************************************\ 1808 * * 1809 * Suspend/resume * 1810 * * 1811 \*****************************************************************************/ 1812 1813 #ifdef CONFIG_PM_SLEEP 1814 static int sdhci_pci_suspend(struct device *dev) 1815 { 1816 struct pci_dev *pdev = to_pci_dev(dev); 1817 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1818 1819 if (!chip) 1820 return 0; 1821 1822 if (chip->fixes && chip->fixes->suspend) 1823 return chip->fixes->suspend(chip); 1824 1825 return sdhci_pci_suspend_host(chip); 1826 } 1827 1828 static int sdhci_pci_resume(struct device *dev) 1829 { 1830 struct pci_dev *pdev = to_pci_dev(dev); 1831 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1832 1833 if (!chip) 1834 return 0; 1835 1836 if (chip->fixes && chip->fixes->resume) 1837 return chip->fixes->resume(chip); 1838 1839 return sdhci_pci_resume_host(chip); 1840 } 1841 #endif 1842 1843 #ifdef CONFIG_PM 1844 static int sdhci_pci_runtime_suspend(struct device *dev) 1845 { 1846 struct pci_dev *pdev = to_pci_dev(dev); 1847 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1848 1849 if (!chip) 1850 return 0; 1851 1852 if (chip->fixes && chip->fixes->runtime_suspend) 1853 return chip->fixes->runtime_suspend(chip); 1854 1855 return sdhci_pci_runtime_suspend_host(chip); 1856 } 1857 1858 static int sdhci_pci_runtime_resume(struct device *dev) 1859 { 1860 struct pci_dev *pdev = to_pci_dev(dev); 1861 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1862 1863 if (!chip) 1864 return 0; 1865 1866 if (chip->fixes && chip->fixes->runtime_resume) 1867 return chip->fixes->runtime_resume(chip); 1868 1869 return sdhci_pci_runtime_resume_host(chip); 1870 } 1871 #endif 1872 1873 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1874 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1875 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1876 sdhci_pci_runtime_resume, NULL) 1877 }; 1878 1879 /*****************************************************************************\ 1880 * * 1881 * Device probing/removal * 1882 * * 1883 \*****************************************************************************/ 1884 1885 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1886 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1887 int slotno) 1888 { 1889 struct sdhci_pci_slot *slot; 1890 struct sdhci_host *host; 1891 int ret, bar = first_bar + slotno; 1892 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 1893 1894 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1895 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1896 return ERR_PTR(-ENODEV); 1897 } 1898 1899 if (pci_resource_len(pdev, bar) < 0x100) { 1900 dev_err(&pdev->dev, "Invalid iomem size. You may " 1901 "experience problems.\n"); 1902 } 1903 1904 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1905 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1906 return ERR_PTR(-ENODEV); 1907 } 1908 1909 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1910 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1911 return ERR_PTR(-ENODEV); 1912 } 1913 1914 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 1915 if (IS_ERR(host)) { 1916 dev_err(&pdev->dev, "cannot allocate host\n"); 1917 return ERR_CAST(host); 1918 } 1919 1920 slot = sdhci_priv(host); 1921 1922 slot->chip = chip; 1923 slot->host = host; 1924 slot->rst_n_gpio = -EINVAL; 1925 slot->cd_gpio = -EINVAL; 1926 slot->cd_idx = -1; 1927 1928 /* Retrieve platform data if there is any */ 1929 if (*sdhci_pci_get_data) 1930 slot->data = sdhci_pci_get_data(pdev, slotno); 1931 1932 if (slot->data) { 1933 if (slot->data->setup) { 1934 ret = slot->data->setup(slot->data); 1935 if (ret) { 1936 dev_err(&pdev->dev, "platform setup failed\n"); 1937 goto free; 1938 } 1939 } 1940 slot->rst_n_gpio = slot->data->rst_n_gpio; 1941 slot->cd_gpio = slot->data->cd_gpio; 1942 } 1943 1944 host->hw_name = "PCI"; 1945 host->ops = chip->fixes && chip->fixes->ops ? 1946 chip->fixes->ops : 1947 &sdhci_pci_ops; 1948 host->quirks = chip->quirks; 1949 host->quirks2 = chip->quirks2; 1950 1951 host->irq = pdev->irq; 1952 1953 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1954 if (ret) { 1955 dev_err(&pdev->dev, "cannot request region\n"); 1956 goto cleanup; 1957 } 1958 1959 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1960 1961 if (chip->fixes && chip->fixes->probe_slot) { 1962 ret = chip->fixes->probe_slot(slot); 1963 if (ret) 1964 goto cleanup; 1965 } 1966 1967 if (gpio_is_valid(slot->rst_n_gpio)) { 1968 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1969 gpio_direction_output(slot->rst_n_gpio, 1); 1970 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1971 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1972 } else { 1973 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1974 slot->rst_n_gpio = -EINVAL; 1975 } 1976 } 1977 1978 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; 1979 host->mmc->slotno = slotno; 1980 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1981 1982 if (slot->cd_idx >= 0) { 1983 ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx, 1984 slot->cd_override_level, 0, NULL); 1985 if (ret == -EPROBE_DEFER) 1986 goto remove; 1987 1988 if (ret) { 1989 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 1990 slot->cd_idx = -1; 1991 } 1992 } 1993 1994 if (chip->fixes && chip->fixes->add_host) 1995 ret = chip->fixes->add_host(slot); 1996 else 1997 ret = sdhci_add_host(host); 1998 if (ret) 1999 goto remove; 2000 2001 sdhci_pci_add_own_cd(slot); 2002 2003 /* 2004 * Check if the chip needs a separate GPIO for card detect to wake up 2005 * from runtime suspend. If it is not there, don't allow runtime PM. 2006 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 2007 */ 2008 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 2009 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 2010 chip->allow_runtime_pm = false; 2011 2012 return slot; 2013 2014 remove: 2015 if (chip->fixes && chip->fixes->remove_slot) 2016 chip->fixes->remove_slot(slot, 0); 2017 2018 cleanup: 2019 if (slot->data && slot->data->cleanup) 2020 slot->data->cleanup(slot->data); 2021 2022 free: 2023 sdhci_free_host(host); 2024 2025 return ERR_PTR(ret); 2026 } 2027 2028 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 2029 { 2030 int dead; 2031 u32 scratch; 2032 2033 sdhci_pci_remove_own_cd(slot); 2034 2035 dead = 0; 2036 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 2037 if (scratch == (u32)-1) 2038 dead = 1; 2039 2040 sdhci_remove_host(slot->host, dead); 2041 2042 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 2043 slot->chip->fixes->remove_slot(slot, dead); 2044 2045 if (slot->data && slot->data->cleanup) 2046 slot->data->cleanup(slot->data); 2047 2048 sdhci_free_host(slot->host); 2049 } 2050 2051 static void sdhci_pci_runtime_pm_allow(struct device *dev) 2052 { 2053 pm_suspend_ignore_children(dev, 1); 2054 pm_runtime_set_autosuspend_delay(dev, 50); 2055 pm_runtime_use_autosuspend(dev); 2056 pm_runtime_allow(dev); 2057 /* Stay active until mmc core scans for a card */ 2058 pm_runtime_put_noidle(dev); 2059 } 2060 2061 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 2062 { 2063 pm_runtime_forbid(dev); 2064 pm_runtime_get_noresume(dev); 2065 } 2066 2067 static int sdhci_pci_probe(struct pci_dev *pdev, 2068 const struct pci_device_id *ent) 2069 { 2070 struct sdhci_pci_chip *chip; 2071 struct sdhci_pci_slot *slot; 2072 2073 u8 slots, first_bar; 2074 int ret, i; 2075 2076 BUG_ON(pdev == NULL); 2077 BUG_ON(ent == NULL); 2078 2079 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 2080 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 2081 2082 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 2083 if (ret) 2084 return ret; 2085 2086 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 2087 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 2088 if (slots == 0) 2089 return -ENODEV; 2090 2091 BUG_ON(slots > MAX_SLOTS); 2092 2093 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 2094 if (ret) 2095 return ret; 2096 2097 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 2098 2099 if (first_bar > 5) { 2100 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 2101 return -ENODEV; 2102 } 2103 2104 ret = pcim_enable_device(pdev); 2105 if (ret) 2106 return ret; 2107 2108 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 2109 if (!chip) 2110 return -ENOMEM; 2111 2112 chip->pdev = pdev; 2113 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 2114 if (chip->fixes) { 2115 chip->quirks = chip->fixes->quirks; 2116 chip->quirks2 = chip->fixes->quirks2; 2117 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 2118 } 2119 chip->num_slots = slots; 2120 chip->pm_retune = true; 2121 chip->rpm_retune = true; 2122 2123 pci_set_drvdata(pdev, chip); 2124 2125 if (chip->fixes && chip->fixes->probe) { 2126 ret = chip->fixes->probe(chip); 2127 if (ret) 2128 return ret; 2129 } 2130 2131 slots = chip->num_slots; /* Quirk may have changed this */ 2132 2133 for (i = 0; i < slots; i++) { 2134 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 2135 if (IS_ERR(slot)) { 2136 for (i--; i >= 0; i--) 2137 sdhci_pci_remove_slot(chip->slots[i]); 2138 return PTR_ERR(slot); 2139 } 2140 2141 chip->slots[i] = slot; 2142 } 2143 2144 if (chip->allow_runtime_pm) 2145 sdhci_pci_runtime_pm_allow(&pdev->dev); 2146 2147 return 0; 2148 } 2149 2150 static void sdhci_pci_remove(struct pci_dev *pdev) 2151 { 2152 int i; 2153 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 2154 2155 if (chip->allow_runtime_pm) 2156 sdhci_pci_runtime_pm_forbid(&pdev->dev); 2157 2158 for (i = 0; i < chip->num_slots; i++) 2159 sdhci_pci_remove_slot(chip->slots[i]); 2160 } 2161 2162 static struct pci_driver sdhci_driver = { 2163 .name = "sdhci-pci", 2164 .id_table = pci_ids, 2165 .probe = sdhci_pci_probe, 2166 .remove = sdhci_pci_remove, 2167 .driver = { 2168 .pm = &sdhci_pci_pm_ops 2169 }, 2170 }; 2171 2172 module_pci_driver(sdhci_driver); 2173 2174 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 2175 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 2176 MODULE_LICENSE("GPL"); 2177