1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 2 * 3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 * 10 * Thanks to the following companies for their support: 11 * 12 * - JMicron (hardware and technical support) 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/highmem.h> 17 #include <linux/module.h> 18 #include <linux/pci.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/slab.h> 21 #include <linux/device.h> 22 #include <linux/mmc/host.h> 23 #include <linux/mmc/mmc.h> 24 #include <linux/scatterlist.h> 25 #include <linux/io.h> 26 #include <linux/gpio.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/mmc/slot-gpio.h> 29 #include <linux/mmc/sdhci-pci-data.h> 30 31 #include "sdhci.h" 32 #include "sdhci-pci.h" 33 #include "sdhci-pci-o2micro.h" 34 35 static int sdhci_pci_enable_dma(struct sdhci_host *host); 36 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width); 37 static void sdhci_pci_hw_reset(struct sdhci_host *host); 38 static int sdhci_pci_select_drive_strength(struct sdhci_host *host, 39 struct mmc_card *card, 40 unsigned int max_dtr, int host_drv, 41 int card_drv, int *drv_type); 42 43 /*****************************************************************************\ 44 * * 45 * Hardware specific quirk handling * 46 * * 47 \*****************************************************************************/ 48 49 static int ricoh_probe(struct sdhci_pci_chip *chip) 50 { 51 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 52 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 53 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 54 return 0; 55 } 56 57 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 58 { 59 slot->host->caps = 60 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 61 & SDHCI_TIMEOUT_CLK_MASK) | 62 63 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 64 & SDHCI_CLOCK_BASE_MASK) | 65 66 SDHCI_TIMEOUT_CLK_UNIT | 67 SDHCI_CAN_VDD_330 | 68 SDHCI_CAN_DO_HISPD | 69 SDHCI_CAN_DO_SDMA; 70 return 0; 71 } 72 73 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 74 { 75 /* Apply a delay to allow controller to settle */ 76 /* Otherwise it becomes confused if card state changed 77 during suspend */ 78 msleep(500); 79 return 0; 80 } 81 82 static const struct sdhci_pci_fixes sdhci_ricoh = { 83 .probe = ricoh_probe, 84 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 85 SDHCI_QUIRK_FORCE_DMA | 86 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 87 }; 88 89 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 90 .probe_slot = ricoh_mmc_probe_slot, 91 .resume = ricoh_mmc_resume, 92 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 93 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 94 SDHCI_QUIRK_NO_CARD_NO_RESET | 95 SDHCI_QUIRK_MISSING_CAPS 96 }; 97 98 static const struct sdhci_pci_fixes sdhci_ene_712 = { 99 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 100 SDHCI_QUIRK_BROKEN_DMA, 101 }; 102 103 static const struct sdhci_pci_fixes sdhci_ene_714 = { 104 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 105 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 106 SDHCI_QUIRK_BROKEN_DMA, 107 }; 108 109 static const struct sdhci_pci_fixes sdhci_cafe = { 110 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 111 SDHCI_QUIRK_NO_BUSY_IRQ | 112 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 113 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 114 }; 115 116 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 117 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 118 }; 119 120 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 121 { 122 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 123 return 0; 124 } 125 126 /* 127 * ADMA operation is disabled for Moorestown platform due to 128 * hardware bugs. 129 */ 130 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 131 { 132 /* 133 * slots number is fixed here for MRST as SDIO3/5 are never used and 134 * have hardware bugs. 135 */ 136 chip->num_slots = 1; 137 return 0; 138 } 139 140 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 141 { 142 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 143 return 0; 144 } 145 146 #ifdef CONFIG_PM 147 148 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 149 { 150 struct sdhci_pci_slot *slot = dev_id; 151 struct sdhci_host *host = slot->host; 152 153 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 154 return IRQ_HANDLED; 155 } 156 157 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 158 { 159 int err, irq, gpio = slot->cd_gpio; 160 161 slot->cd_gpio = -EINVAL; 162 slot->cd_irq = -EINVAL; 163 164 if (!gpio_is_valid(gpio)) 165 return; 166 167 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 168 if (err < 0) 169 goto out; 170 171 err = gpio_direction_input(gpio); 172 if (err < 0) 173 goto out_free; 174 175 irq = gpio_to_irq(gpio); 176 if (irq < 0) 177 goto out_free; 178 179 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 180 IRQF_TRIGGER_FALLING, "sd_cd", slot); 181 if (err) 182 goto out_free; 183 184 slot->cd_gpio = gpio; 185 slot->cd_irq = irq; 186 187 return; 188 189 out_free: 190 devm_gpio_free(&slot->chip->pdev->dev, gpio); 191 out: 192 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 193 } 194 195 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 196 { 197 if (slot->cd_irq >= 0) 198 free_irq(slot->cd_irq, slot); 199 } 200 201 #else 202 203 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 204 { 205 } 206 207 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 208 { 209 } 210 211 #endif 212 213 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 214 { 215 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 216 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC | 217 MMC_CAP2_HC_ERASE_SZ; 218 return 0; 219 } 220 221 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 222 { 223 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 224 return 0; 225 } 226 227 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 228 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 229 .probe_slot = mrst_hc_probe_slot, 230 }; 231 232 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 233 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 234 .probe = mrst_hc_probe, 235 }; 236 237 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 238 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 239 .allow_runtime_pm = true, 240 .own_cd_for_runtime_pm = true, 241 }; 242 243 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 244 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 245 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 246 .allow_runtime_pm = true, 247 .probe_slot = mfd_sdio_probe_slot, 248 }; 249 250 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 251 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 252 .allow_runtime_pm = true, 253 .probe_slot = mfd_emmc_probe_slot, 254 }; 255 256 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 257 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 258 .probe_slot = pch_hc_probe_slot, 259 }; 260 261 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 262 { 263 u8 reg; 264 265 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 266 reg |= 0x10; 267 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 268 /* For eMMC, minimum is 1us but give it 9us for good measure */ 269 udelay(9); 270 reg &= ~0x10; 271 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 272 /* For eMMC, minimum is 200us but give it 300us for good measure */ 273 usleep_range(300, 1000); 274 } 275 276 static int spt_select_drive_strength(struct sdhci_host *host, 277 struct mmc_card *card, 278 unsigned int max_dtr, 279 int host_drv, int card_drv, int *drv_type) 280 { 281 int drive_strength; 282 283 if (sdhci_pci_spt_drive_strength > 0) 284 drive_strength = sdhci_pci_spt_drive_strength & 0xf; 285 else 286 drive_strength = 0; /* Default 50-ohm */ 287 288 if ((mmc_driver_type_mask(drive_strength) & card_drv) == 0) 289 drive_strength = 0; /* Default 50-ohm */ 290 291 return drive_strength; 292 } 293 294 /* Try to read the drive strength from the card */ 295 static void spt_read_drive_strength(struct sdhci_host *host) 296 { 297 u32 val, i, t; 298 u16 m; 299 300 if (sdhci_pci_spt_drive_strength) 301 return; 302 303 sdhci_pci_spt_drive_strength = -1; 304 305 m = sdhci_readw(host, SDHCI_HOST_CONTROL2) & 0x7; 306 if (m != 3 && m != 5) 307 return; 308 val = sdhci_readl(host, SDHCI_PRESENT_STATE); 309 if (val & 0x3) 310 return; 311 sdhci_writel(host, 0x007f0023, SDHCI_INT_ENABLE); 312 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 313 sdhci_writew(host, 0x10, SDHCI_TRANSFER_MODE); 314 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 315 sdhci_writew(host, 512, SDHCI_BLOCK_SIZE); 316 sdhci_writew(host, 1, SDHCI_BLOCK_COUNT); 317 sdhci_writel(host, 0, SDHCI_ARGUMENT); 318 sdhci_writew(host, 0x83b, SDHCI_COMMAND); 319 for (i = 0; i < 1000; i++) { 320 val = sdhci_readl(host, SDHCI_INT_STATUS); 321 if (val & 0xffff8000) 322 return; 323 if (val & 0x20) 324 break; 325 udelay(1); 326 } 327 val = sdhci_readl(host, SDHCI_PRESENT_STATE); 328 if (!(val & 0x800)) 329 return; 330 for (i = 0; i < 47; i++) 331 val = sdhci_readl(host, SDHCI_BUFFER); 332 t = val & 0xf00; 333 if (t != 0x200 && t != 0x300) 334 return; 335 336 sdhci_pci_spt_drive_strength = 0x10 | ((val >> 12) & 0xf); 337 } 338 339 static int bxt_get_cd(struct mmc_host *mmc) 340 { 341 int gpio_cd = mmc_gpio_get_cd(mmc); 342 struct sdhci_host *host = mmc_priv(mmc); 343 unsigned long flags; 344 int ret = 0; 345 346 if (!gpio_cd) 347 return 0; 348 349 spin_lock_irqsave(&host->lock, flags); 350 351 if (host->flags & SDHCI_DEVICE_DEAD) 352 goto out; 353 354 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 355 out: 356 spin_unlock_irqrestore(&host->lock, flags); 357 358 return ret; 359 } 360 361 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 362 { 363 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 364 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 365 MMC_CAP_CMD_DURING_TFR | 366 MMC_CAP_WAIT_WHILE_BUSY; 367 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ; 368 slot->hw_reset = sdhci_pci_int_hw_reset; 369 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 370 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 371 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_SPT_EMMC) { 372 spt_read_drive_strength(slot->host); 373 slot->select_drive_strength = spt_select_drive_strength; 374 } 375 return 0; 376 } 377 378 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 379 { 380 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 381 MMC_CAP_WAIT_WHILE_BUSY; 382 return 0; 383 } 384 385 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 386 { 387 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 388 slot->cd_con_id = NULL; 389 slot->cd_idx = 0; 390 slot->cd_override_level = true; 391 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 392 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 393 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 394 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) { 395 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 396 slot->host->mmc->caps |= MMC_CAP_AGGRESSIVE_PM; 397 } 398 399 return 0; 400 } 401 402 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 403 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 404 405 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 406 unsigned short vdd) 407 { 408 int cntr; 409 u8 reg; 410 411 sdhci_set_power(host, mode, vdd); 412 413 if (mode == MMC_POWER_OFF) 414 return; 415 416 /* 417 * Bus power might not enable after D3 -> D0 transition due to the 418 * present state not yet having propagated. Retry for up to 2ms. 419 */ 420 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 421 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 422 if (reg & SDHCI_POWER_ON) 423 break; 424 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 425 reg |= SDHCI_POWER_ON; 426 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 427 } 428 } 429 430 static const struct sdhci_ops sdhci_intel_byt_ops = { 431 .set_clock = sdhci_set_clock, 432 .set_power = sdhci_intel_set_power, 433 .enable_dma = sdhci_pci_enable_dma, 434 .set_bus_width = sdhci_pci_set_bus_width, 435 .reset = sdhci_reset, 436 .set_uhs_signaling = sdhci_set_uhs_signaling, 437 .hw_reset = sdhci_pci_hw_reset, 438 .select_drive_strength = sdhci_pci_select_drive_strength, 439 }; 440 441 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 442 .allow_runtime_pm = true, 443 .probe_slot = byt_emmc_probe_slot, 444 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 445 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 446 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 447 SDHCI_QUIRK2_STOP_WITH_TC, 448 .ops = &sdhci_intel_byt_ops, 449 }; 450 451 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 452 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 453 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 454 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 455 .allow_runtime_pm = true, 456 .probe_slot = byt_sdio_probe_slot, 457 .ops = &sdhci_intel_byt_ops, 458 }; 459 460 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 461 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 462 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 463 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 464 SDHCI_QUIRK2_STOP_WITH_TC, 465 .allow_runtime_pm = true, 466 .own_cd_for_runtime_pm = true, 467 .probe_slot = byt_sd_probe_slot, 468 .ops = &sdhci_intel_byt_ops, 469 }; 470 471 /* Define Host controllers for Intel Merrifield platform */ 472 #define INTEL_MRFLD_EMMC_0 0 473 #define INTEL_MRFLD_EMMC_1 1 474 #define INTEL_MRFLD_SD 2 475 #define INTEL_MRFLD_SDIO 3 476 477 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 478 { 479 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 480 481 switch (func) { 482 case INTEL_MRFLD_EMMC_0: 483 case INTEL_MRFLD_EMMC_1: 484 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 485 MMC_CAP_8_BIT_DATA | 486 MMC_CAP_1_8V_DDR; 487 break; 488 case INTEL_MRFLD_SD: 489 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 490 break; 491 case INTEL_MRFLD_SDIO: 492 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 493 MMC_CAP_POWER_OFF_CARD; 494 break; 495 default: 496 return -ENODEV; 497 } 498 return 0; 499 } 500 501 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 502 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 503 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 504 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 505 .allow_runtime_pm = true, 506 .probe_slot = intel_mrfld_mmc_probe_slot, 507 }; 508 509 /* O2Micro extra registers */ 510 #define O2_SD_LOCK_WP 0xD3 511 #define O2_SD_MULTI_VCC3V 0xEE 512 #define O2_SD_CLKREQ 0xEC 513 #define O2_SD_CAPS 0xE0 514 #define O2_SD_ADMA1 0xE2 515 #define O2_SD_ADMA2 0xE7 516 #define O2_SD_INF_MOD 0xF1 517 518 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 519 { 520 u8 scratch; 521 int ret; 522 523 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 524 if (ret) 525 return ret; 526 527 /* 528 * Turn PMOS on [bit 0], set over current detection to 2.4 V 529 * [bit 1:2] and enable over current debouncing [bit 6]. 530 */ 531 if (on) 532 scratch |= 0x47; 533 else 534 scratch &= ~0x47; 535 536 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 537 } 538 539 static int jmicron_probe(struct sdhci_pci_chip *chip) 540 { 541 int ret; 542 u16 mmcdev = 0; 543 544 if (chip->pdev->revision == 0) { 545 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 546 SDHCI_QUIRK_32BIT_DMA_SIZE | 547 SDHCI_QUIRK_32BIT_ADMA_SIZE | 548 SDHCI_QUIRK_RESET_AFTER_REQUEST | 549 SDHCI_QUIRK_BROKEN_SMALL_PIO; 550 } 551 552 /* 553 * JMicron chips can have two interfaces to the same hardware 554 * in order to work around limitations in Microsoft's driver. 555 * We need to make sure we only bind to one of them. 556 * 557 * This code assumes two things: 558 * 559 * 1. The PCI code adds subfunctions in order. 560 * 561 * 2. The MMC interface has a lower subfunction number 562 * than the SD interface. 563 */ 564 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 565 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 566 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 567 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 568 569 if (mmcdev) { 570 struct pci_dev *sd_dev; 571 572 sd_dev = NULL; 573 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 574 mmcdev, sd_dev)) != NULL) { 575 if ((PCI_SLOT(chip->pdev->devfn) == 576 PCI_SLOT(sd_dev->devfn)) && 577 (chip->pdev->bus == sd_dev->bus)) 578 break; 579 } 580 581 if (sd_dev) { 582 pci_dev_put(sd_dev); 583 dev_info(&chip->pdev->dev, "Refusing to bind to " 584 "secondary interface.\n"); 585 return -ENODEV; 586 } 587 } 588 589 /* 590 * JMicron chips need a bit of a nudge to enable the power 591 * output pins. 592 */ 593 ret = jmicron_pmos(chip, 1); 594 if (ret) { 595 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 596 return ret; 597 } 598 599 /* quirk for unsable RO-detection on JM388 chips */ 600 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 601 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 602 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 603 604 return 0; 605 } 606 607 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 608 { 609 u8 scratch; 610 611 scratch = readb(host->ioaddr + 0xC0); 612 613 if (on) 614 scratch |= 0x01; 615 else 616 scratch &= ~0x01; 617 618 writeb(scratch, host->ioaddr + 0xC0); 619 } 620 621 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 622 { 623 if (slot->chip->pdev->revision == 0) { 624 u16 version; 625 626 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 627 version = (version & SDHCI_VENDOR_VER_MASK) >> 628 SDHCI_VENDOR_VER_SHIFT; 629 630 /* 631 * Older versions of the chip have lots of nasty glitches 632 * in the ADMA engine. It's best just to avoid it 633 * completely. 634 */ 635 if (version < 0xAC) 636 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 637 } 638 639 /* JM388 MMC doesn't support 1.8V while SD supports it */ 640 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 641 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 642 MMC_VDD_29_30 | MMC_VDD_30_31 | 643 MMC_VDD_165_195; /* allow 1.8V */ 644 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 645 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 646 } 647 648 /* 649 * The secondary interface requires a bit set to get the 650 * interrupts. 651 */ 652 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 653 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 654 jmicron_enable_mmc(slot->host, 1); 655 656 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 657 658 return 0; 659 } 660 661 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 662 { 663 if (dead) 664 return; 665 666 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 667 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 668 jmicron_enable_mmc(slot->host, 0); 669 } 670 671 static int jmicron_suspend(struct sdhci_pci_chip *chip) 672 { 673 int i; 674 675 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 676 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 677 for (i = 0; i < chip->num_slots; i++) 678 jmicron_enable_mmc(chip->slots[i]->host, 0); 679 } 680 681 return 0; 682 } 683 684 static int jmicron_resume(struct sdhci_pci_chip *chip) 685 { 686 int ret, i; 687 688 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 689 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 690 for (i = 0; i < chip->num_slots; i++) 691 jmicron_enable_mmc(chip->slots[i]->host, 1); 692 } 693 694 ret = jmicron_pmos(chip, 1); 695 if (ret) { 696 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 697 return ret; 698 } 699 700 return 0; 701 } 702 703 static const struct sdhci_pci_fixes sdhci_o2 = { 704 .probe = sdhci_pci_o2_probe, 705 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 706 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 707 .probe_slot = sdhci_pci_o2_probe_slot, 708 .resume = sdhci_pci_o2_resume, 709 }; 710 711 static const struct sdhci_pci_fixes sdhci_jmicron = { 712 .probe = jmicron_probe, 713 714 .probe_slot = jmicron_probe_slot, 715 .remove_slot = jmicron_remove_slot, 716 717 .suspend = jmicron_suspend, 718 .resume = jmicron_resume, 719 }; 720 721 /* SysKonnect CardBus2SDIO extra registers */ 722 #define SYSKT_CTRL 0x200 723 #define SYSKT_RDFIFO_STAT 0x204 724 #define SYSKT_WRFIFO_STAT 0x208 725 #define SYSKT_POWER_DATA 0x20c 726 #define SYSKT_POWER_330 0xef 727 #define SYSKT_POWER_300 0xf8 728 #define SYSKT_POWER_184 0xcc 729 #define SYSKT_POWER_CMD 0x20d 730 #define SYSKT_POWER_START (1 << 7) 731 #define SYSKT_POWER_STATUS 0x20e 732 #define SYSKT_POWER_STATUS_OK (1 << 0) 733 #define SYSKT_BOARD_REV 0x210 734 #define SYSKT_CHIP_REV 0x211 735 #define SYSKT_CONF_DATA 0x212 736 #define SYSKT_CONF_DATA_1V8 (1 << 2) 737 #define SYSKT_CONF_DATA_2V5 (1 << 1) 738 #define SYSKT_CONF_DATA_3V3 (1 << 0) 739 740 static int syskt_probe(struct sdhci_pci_chip *chip) 741 { 742 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 743 chip->pdev->class &= ~0x0000FF; 744 chip->pdev->class |= PCI_SDHCI_IFDMA; 745 } 746 return 0; 747 } 748 749 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 750 { 751 int tm, ps; 752 753 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 754 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 755 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 756 "board rev %d.%d, chip rev %d.%d\n", 757 board_rev >> 4, board_rev & 0xf, 758 chip_rev >> 4, chip_rev & 0xf); 759 if (chip_rev >= 0x20) 760 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 761 762 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 763 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 764 udelay(50); 765 tm = 10; /* Wait max 1 ms */ 766 do { 767 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 768 if (ps & SYSKT_POWER_STATUS_OK) 769 break; 770 udelay(100); 771 } while (--tm); 772 if (!tm) { 773 dev_err(&slot->chip->pdev->dev, 774 "power regulator never stabilized"); 775 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 776 return -ENODEV; 777 } 778 779 return 0; 780 } 781 782 static const struct sdhci_pci_fixes sdhci_syskt = { 783 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 784 .probe = syskt_probe, 785 .probe_slot = syskt_probe_slot, 786 }; 787 788 static int via_probe(struct sdhci_pci_chip *chip) 789 { 790 if (chip->pdev->revision == 0x10) 791 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 792 793 return 0; 794 } 795 796 static const struct sdhci_pci_fixes sdhci_via = { 797 .probe = via_probe, 798 }; 799 800 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 801 { 802 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 803 return 0; 804 } 805 806 static const struct sdhci_pci_fixes sdhci_rtsx = { 807 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 808 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 809 SDHCI_QUIRK2_BROKEN_DDR50, 810 .probe_slot = rtsx_probe_slot, 811 }; 812 813 /*AMD chipset generation*/ 814 enum amd_chipset_gen { 815 AMD_CHIPSET_BEFORE_ML, 816 AMD_CHIPSET_CZ, 817 AMD_CHIPSET_NL, 818 AMD_CHIPSET_UNKNOWN, 819 }; 820 821 static int amd_probe(struct sdhci_pci_chip *chip) 822 { 823 struct pci_dev *smbus_dev; 824 enum amd_chipset_gen gen; 825 826 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 827 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 828 if (smbus_dev) { 829 gen = AMD_CHIPSET_BEFORE_ML; 830 } else { 831 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 832 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 833 if (smbus_dev) { 834 if (smbus_dev->revision < 0x51) 835 gen = AMD_CHIPSET_CZ; 836 else 837 gen = AMD_CHIPSET_NL; 838 } else { 839 gen = AMD_CHIPSET_UNKNOWN; 840 } 841 } 842 843 if ((gen == AMD_CHIPSET_BEFORE_ML) || (gen == AMD_CHIPSET_CZ)) { 844 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 845 chip->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 846 } 847 848 return 0; 849 } 850 851 static const struct sdhci_pci_fixes sdhci_amd = { 852 .probe = amd_probe, 853 }; 854 855 static const struct pci_device_id pci_ids[] = { 856 { 857 .vendor = PCI_VENDOR_ID_RICOH, 858 .device = PCI_DEVICE_ID_RICOH_R5C822, 859 .subvendor = PCI_ANY_ID, 860 .subdevice = PCI_ANY_ID, 861 .driver_data = (kernel_ulong_t)&sdhci_ricoh, 862 }, 863 864 { 865 .vendor = PCI_VENDOR_ID_RICOH, 866 .device = 0x843, 867 .subvendor = PCI_ANY_ID, 868 .subdevice = PCI_ANY_ID, 869 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 870 }, 871 872 { 873 .vendor = PCI_VENDOR_ID_RICOH, 874 .device = 0xe822, 875 .subvendor = PCI_ANY_ID, 876 .subdevice = PCI_ANY_ID, 877 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 878 }, 879 880 { 881 .vendor = PCI_VENDOR_ID_RICOH, 882 .device = 0xe823, 883 .subvendor = PCI_ANY_ID, 884 .subdevice = PCI_ANY_ID, 885 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 886 }, 887 888 { 889 .vendor = PCI_VENDOR_ID_ENE, 890 .device = PCI_DEVICE_ID_ENE_CB712_SD, 891 .subvendor = PCI_ANY_ID, 892 .subdevice = PCI_ANY_ID, 893 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 894 }, 895 896 { 897 .vendor = PCI_VENDOR_ID_ENE, 898 .device = PCI_DEVICE_ID_ENE_CB712_SD_2, 899 .subvendor = PCI_ANY_ID, 900 .subdevice = PCI_ANY_ID, 901 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 902 }, 903 904 { 905 .vendor = PCI_VENDOR_ID_ENE, 906 .device = PCI_DEVICE_ID_ENE_CB714_SD, 907 .subvendor = PCI_ANY_ID, 908 .subdevice = PCI_ANY_ID, 909 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 910 }, 911 912 { 913 .vendor = PCI_VENDOR_ID_ENE, 914 .device = PCI_DEVICE_ID_ENE_CB714_SD_2, 915 .subvendor = PCI_ANY_ID, 916 .subdevice = PCI_ANY_ID, 917 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 918 }, 919 920 { 921 .vendor = PCI_VENDOR_ID_MARVELL, 922 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD, 923 .subvendor = PCI_ANY_ID, 924 .subdevice = PCI_ANY_ID, 925 .driver_data = (kernel_ulong_t)&sdhci_cafe, 926 }, 927 928 { 929 .vendor = PCI_VENDOR_ID_JMICRON, 930 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD, 931 .subvendor = PCI_ANY_ID, 932 .subdevice = PCI_ANY_ID, 933 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 934 }, 935 936 { 937 .vendor = PCI_VENDOR_ID_JMICRON, 938 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC, 939 .subvendor = PCI_ANY_ID, 940 .subdevice = PCI_ANY_ID, 941 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 942 }, 943 944 { 945 .vendor = PCI_VENDOR_ID_JMICRON, 946 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD, 947 .subvendor = PCI_ANY_ID, 948 .subdevice = PCI_ANY_ID, 949 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 950 }, 951 952 { 953 .vendor = PCI_VENDOR_ID_JMICRON, 954 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD, 955 .subvendor = PCI_ANY_ID, 956 .subdevice = PCI_ANY_ID, 957 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 958 }, 959 960 { 961 .vendor = PCI_VENDOR_ID_SYSKONNECT, 962 .device = 0x8000, 963 .subvendor = PCI_ANY_ID, 964 .subdevice = PCI_ANY_ID, 965 .driver_data = (kernel_ulong_t)&sdhci_syskt, 966 }, 967 968 { 969 .vendor = PCI_VENDOR_ID_VIA, 970 .device = 0x95d0, 971 .subvendor = PCI_ANY_ID, 972 .subdevice = PCI_ANY_ID, 973 .driver_data = (kernel_ulong_t)&sdhci_via, 974 }, 975 976 { 977 .vendor = PCI_VENDOR_ID_REALTEK, 978 .device = 0x5250, 979 .subvendor = PCI_ANY_ID, 980 .subdevice = PCI_ANY_ID, 981 .driver_data = (kernel_ulong_t)&sdhci_rtsx, 982 }, 983 984 { 985 .vendor = PCI_VENDOR_ID_INTEL, 986 .device = PCI_DEVICE_ID_INTEL_QRK_SD, 987 .subvendor = PCI_ANY_ID, 988 .subdevice = PCI_ANY_ID, 989 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk, 990 }, 991 992 { 993 .vendor = PCI_VENDOR_ID_INTEL, 994 .device = PCI_DEVICE_ID_INTEL_MRST_SD0, 995 .subvendor = PCI_ANY_ID, 996 .subdevice = PCI_ANY_ID, 997 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0, 998 }, 999 1000 { 1001 .vendor = PCI_VENDOR_ID_INTEL, 1002 .device = PCI_DEVICE_ID_INTEL_MRST_SD1, 1003 .subvendor = PCI_ANY_ID, 1004 .subdevice = PCI_ANY_ID, 1005 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 1006 }, 1007 1008 { 1009 .vendor = PCI_VENDOR_ID_INTEL, 1010 .device = PCI_DEVICE_ID_INTEL_MRST_SD2, 1011 .subvendor = PCI_ANY_ID, 1012 .subdevice = PCI_ANY_ID, 1013 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 1014 }, 1015 1016 { 1017 .vendor = PCI_VENDOR_ID_INTEL, 1018 .device = PCI_DEVICE_ID_INTEL_MFD_SD, 1019 .subvendor = PCI_ANY_ID, 1020 .subdevice = PCI_ANY_ID, 1021 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1022 }, 1023 1024 { 1025 .vendor = PCI_VENDOR_ID_INTEL, 1026 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1, 1027 .subvendor = PCI_ANY_ID, 1028 .subdevice = PCI_ANY_ID, 1029 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1030 }, 1031 1032 { 1033 .vendor = PCI_VENDOR_ID_INTEL, 1034 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2, 1035 .subvendor = PCI_ANY_ID, 1036 .subdevice = PCI_ANY_ID, 1037 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1038 }, 1039 1040 { 1041 .vendor = PCI_VENDOR_ID_INTEL, 1042 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0, 1043 .subvendor = PCI_ANY_ID, 1044 .subdevice = PCI_ANY_ID, 1045 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1046 }, 1047 1048 { 1049 .vendor = PCI_VENDOR_ID_INTEL, 1050 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1, 1051 .subvendor = PCI_ANY_ID, 1052 .subdevice = PCI_ANY_ID, 1053 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1054 }, 1055 1056 { 1057 .vendor = PCI_VENDOR_ID_INTEL, 1058 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0, 1059 .subvendor = PCI_ANY_ID, 1060 .subdevice = PCI_ANY_ID, 1061 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1062 }, 1063 1064 { 1065 .vendor = PCI_VENDOR_ID_INTEL, 1066 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1, 1067 .subvendor = PCI_ANY_ID, 1068 .subdevice = PCI_ANY_ID, 1069 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1070 }, 1071 1072 { 1073 .vendor = PCI_VENDOR_ID_INTEL, 1074 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC, 1075 .subvendor = PCI_ANY_ID, 1076 .subdevice = PCI_ANY_ID, 1077 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1078 }, 1079 1080 { 1081 .vendor = PCI_VENDOR_ID_INTEL, 1082 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, 1083 .subvendor = PCI_ANY_ID, 1084 .subdevice = PCI_ANY_ID, 1085 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1086 }, 1087 1088 { 1089 .vendor = PCI_VENDOR_ID_INTEL, 1090 .device = PCI_DEVICE_ID_INTEL_BYT_SD, 1091 .subvendor = PCI_ANY_ID, 1092 .subdevice = PCI_ANY_ID, 1093 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1094 }, 1095 1096 { 1097 .vendor = PCI_VENDOR_ID_INTEL, 1098 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2, 1099 .subvendor = PCI_ANY_ID, 1100 .subdevice = PCI_ANY_ID, 1101 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1102 }, 1103 1104 { 1105 .vendor = PCI_VENDOR_ID_INTEL, 1106 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC, 1107 .subvendor = PCI_ANY_ID, 1108 .subdevice = PCI_ANY_ID, 1109 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1110 }, 1111 1112 { 1113 .vendor = PCI_VENDOR_ID_INTEL, 1114 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO, 1115 .subvendor = PCI_ANY_ID, 1116 .subdevice = PCI_ANY_ID, 1117 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1118 }, 1119 1120 { 1121 .vendor = PCI_VENDOR_ID_INTEL, 1122 .device = PCI_DEVICE_ID_INTEL_BSW_SD, 1123 .subvendor = PCI_ANY_ID, 1124 .subdevice = PCI_ANY_ID, 1125 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1126 }, 1127 1128 { 1129 .vendor = PCI_VENDOR_ID_INTEL, 1130 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0, 1131 .subvendor = PCI_ANY_ID, 1132 .subdevice = PCI_ANY_ID, 1133 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1134 }, 1135 1136 { 1137 .vendor = PCI_VENDOR_ID_INTEL, 1138 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1, 1139 .subvendor = PCI_ANY_ID, 1140 .subdevice = PCI_ANY_ID, 1141 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1142 }, 1143 1144 { 1145 .vendor = PCI_VENDOR_ID_INTEL, 1146 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2, 1147 .subvendor = PCI_ANY_ID, 1148 .subdevice = PCI_ANY_ID, 1149 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1150 }, 1151 1152 { 1153 .vendor = PCI_VENDOR_ID_INTEL, 1154 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0, 1155 .subvendor = PCI_ANY_ID, 1156 .subdevice = PCI_ANY_ID, 1157 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1158 }, 1159 1160 { 1161 .vendor = PCI_VENDOR_ID_INTEL, 1162 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1, 1163 .subvendor = PCI_ANY_ID, 1164 .subdevice = PCI_ANY_ID, 1165 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1166 }, 1167 1168 { 1169 .vendor = PCI_VENDOR_ID_INTEL, 1170 .device = PCI_DEVICE_ID_INTEL_MRFLD_MMC, 1171 .subvendor = PCI_ANY_ID, 1172 .subdevice = PCI_ANY_ID, 1173 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfld_mmc, 1174 }, 1175 1176 { 1177 .vendor = PCI_VENDOR_ID_INTEL, 1178 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC, 1179 .subvendor = PCI_ANY_ID, 1180 .subdevice = PCI_ANY_ID, 1181 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1182 }, 1183 1184 { 1185 .vendor = PCI_VENDOR_ID_INTEL, 1186 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO, 1187 .subvendor = PCI_ANY_ID, 1188 .subdevice = PCI_ANY_ID, 1189 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1190 }, 1191 1192 { 1193 .vendor = PCI_VENDOR_ID_INTEL, 1194 .device = PCI_DEVICE_ID_INTEL_SPT_SD, 1195 .subvendor = PCI_ANY_ID, 1196 .subdevice = PCI_ANY_ID, 1197 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1198 }, 1199 1200 { 1201 .vendor = PCI_VENDOR_ID_INTEL, 1202 .device = PCI_DEVICE_ID_INTEL_DNV_EMMC, 1203 .subvendor = PCI_ANY_ID, 1204 .subdevice = PCI_ANY_ID, 1205 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1206 }, 1207 1208 { 1209 .vendor = PCI_VENDOR_ID_INTEL, 1210 .device = PCI_DEVICE_ID_INTEL_BXT_EMMC, 1211 .subvendor = PCI_ANY_ID, 1212 .subdevice = PCI_ANY_ID, 1213 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1214 }, 1215 1216 { 1217 .vendor = PCI_VENDOR_ID_INTEL, 1218 .device = PCI_DEVICE_ID_INTEL_BXT_SDIO, 1219 .subvendor = PCI_ANY_ID, 1220 .subdevice = PCI_ANY_ID, 1221 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1222 }, 1223 1224 { 1225 .vendor = PCI_VENDOR_ID_INTEL, 1226 .device = PCI_DEVICE_ID_INTEL_BXT_SD, 1227 .subvendor = PCI_ANY_ID, 1228 .subdevice = PCI_ANY_ID, 1229 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1230 }, 1231 1232 { 1233 .vendor = PCI_VENDOR_ID_INTEL, 1234 .device = PCI_DEVICE_ID_INTEL_BXTM_EMMC, 1235 .subvendor = PCI_ANY_ID, 1236 .subdevice = PCI_ANY_ID, 1237 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1238 }, 1239 1240 { 1241 .vendor = PCI_VENDOR_ID_INTEL, 1242 .device = PCI_DEVICE_ID_INTEL_BXTM_SDIO, 1243 .subvendor = PCI_ANY_ID, 1244 .subdevice = PCI_ANY_ID, 1245 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1246 }, 1247 1248 { 1249 .vendor = PCI_VENDOR_ID_INTEL, 1250 .device = PCI_DEVICE_ID_INTEL_BXTM_SD, 1251 .subvendor = PCI_ANY_ID, 1252 .subdevice = PCI_ANY_ID, 1253 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1254 }, 1255 1256 { 1257 .vendor = PCI_VENDOR_ID_INTEL, 1258 .device = PCI_DEVICE_ID_INTEL_APL_EMMC, 1259 .subvendor = PCI_ANY_ID, 1260 .subdevice = PCI_ANY_ID, 1261 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1262 }, 1263 1264 { 1265 .vendor = PCI_VENDOR_ID_INTEL, 1266 .device = PCI_DEVICE_ID_INTEL_APL_SDIO, 1267 .subvendor = PCI_ANY_ID, 1268 .subdevice = PCI_ANY_ID, 1269 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1270 }, 1271 1272 { 1273 .vendor = PCI_VENDOR_ID_INTEL, 1274 .device = PCI_DEVICE_ID_INTEL_APL_SD, 1275 .subvendor = PCI_ANY_ID, 1276 .subdevice = PCI_ANY_ID, 1277 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1278 }, 1279 1280 { 1281 .vendor = PCI_VENDOR_ID_INTEL, 1282 .device = PCI_DEVICE_ID_INTEL_GLK_EMMC, 1283 .subvendor = PCI_ANY_ID, 1284 .subdevice = PCI_ANY_ID, 1285 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1286 }, 1287 1288 { 1289 .vendor = PCI_VENDOR_ID_INTEL, 1290 .device = PCI_DEVICE_ID_INTEL_GLK_SDIO, 1291 .subvendor = PCI_ANY_ID, 1292 .subdevice = PCI_ANY_ID, 1293 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1294 }, 1295 1296 { 1297 .vendor = PCI_VENDOR_ID_INTEL, 1298 .device = PCI_DEVICE_ID_INTEL_GLK_SD, 1299 .subvendor = PCI_ANY_ID, 1300 .subdevice = PCI_ANY_ID, 1301 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1302 }, 1303 1304 { 1305 .vendor = PCI_VENDOR_ID_O2, 1306 .device = PCI_DEVICE_ID_O2_8120, 1307 .subvendor = PCI_ANY_ID, 1308 .subdevice = PCI_ANY_ID, 1309 .driver_data = (kernel_ulong_t)&sdhci_o2, 1310 }, 1311 1312 { 1313 .vendor = PCI_VENDOR_ID_O2, 1314 .device = PCI_DEVICE_ID_O2_8220, 1315 .subvendor = PCI_ANY_ID, 1316 .subdevice = PCI_ANY_ID, 1317 .driver_data = (kernel_ulong_t)&sdhci_o2, 1318 }, 1319 1320 { 1321 .vendor = PCI_VENDOR_ID_O2, 1322 .device = PCI_DEVICE_ID_O2_8221, 1323 .subvendor = PCI_ANY_ID, 1324 .subdevice = PCI_ANY_ID, 1325 .driver_data = (kernel_ulong_t)&sdhci_o2, 1326 }, 1327 1328 { 1329 .vendor = PCI_VENDOR_ID_O2, 1330 .device = PCI_DEVICE_ID_O2_8320, 1331 .subvendor = PCI_ANY_ID, 1332 .subdevice = PCI_ANY_ID, 1333 .driver_data = (kernel_ulong_t)&sdhci_o2, 1334 }, 1335 1336 { 1337 .vendor = PCI_VENDOR_ID_O2, 1338 .device = PCI_DEVICE_ID_O2_8321, 1339 .subvendor = PCI_ANY_ID, 1340 .subdevice = PCI_ANY_ID, 1341 .driver_data = (kernel_ulong_t)&sdhci_o2, 1342 }, 1343 1344 { 1345 .vendor = PCI_VENDOR_ID_O2, 1346 .device = PCI_DEVICE_ID_O2_FUJIN2, 1347 .subvendor = PCI_ANY_ID, 1348 .subdevice = PCI_ANY_ID, 1349 .driver_data = (kernel_ulong_t)&sdhci_o2, 1350 }, 1351 1352 { 1353 .vendor = PCI_VENDOR_ID_O2, 1354 .device = PCI_DEVICE_ID_O2_SDS0, 1355 .subvendor = PCI_ANY_ID, 1356 .subdevice = PCI_ANY_ID, 1357 .driver_data = (kernel_ulong_t)&sdhci_o2, 1358 }, 1359 1360 { 1361 .vendor = PCI_VENDOR_ID_O2, 1362 .device = PCI_DEVICE_ID_O2_SDS1, 1363 .subvendor = PCI_ANY_ID, 1364 .subdevice = PCI_ANY_ID, 1365 .driver_data = (kernel_ulong_t)&sdhci_o2, 1366 }, 1367 1368 { 1369 .vendor = PCI_VENDOR_ID_O2, 1370 .device = PCI_DEVICE_ID_O2_SEABIRD0, 1371 .subvendor = PCI_ANY_ID, 1372 .subdevice = PCI_ANY_ID, 1373 .driver_data = (kernel_ulong_t)&sdhci_o2, 1374 }, 1375 1376 { 1377 .vendor = PCI_VENDOR_ID_O2, 1378 .device = PCI_DEVICE_ID_O2_SEABIRD1, 1379 .subvendor = PCI_ANY_ID, 1380 .subdevice = PCI_ANY_ID, 1381 .driver_data = (kernel_ulong_t)&sdhci_o2, 1382 }, 1383 { 1384 .vendor = PCI_VENDOR_ID_AMD, 1385 .device = PCI_ANY_ID, 1386 .class = PCI_CLASS_SYSTEM_SDHCI << 8, 1387 .class_mask = 0xFFFF00, 1388 .subvendor = PCI_ANY_ID, 1389 .subdevice = PCI_ANY_ID, 1390 .driver_data = (kernel_ulong_t)&sdhci_amd, 1391 }, 1392 { /* Generic SD host controller */ 1393 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) 1394 }, 1395 1396 { /* end: all zeroes */ }, 1397 }; 1398 1399 MODULE_DEVICE_TABLE(pci, pci_ids); 1400 1401 /*****************************************************************************\ 1402 * * 1403 * SDHCI core callbacks * 1404 * * 1405 \*****************************************************************************/ 1406 1407 static int sdhci_pci_enable_dma(struct sdhci_host *host) 1408 { 1409 struct sdhci_pci_slot *slot; 1410 struct pci_dev *pdev; 1411 1412 slot = sdhci_priv(host); 1413 pdev = slot->chip->pdev; 1414 1415 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1416 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1417 (host->flags & SDHCI_USE_SDMA)) { 1418 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1419 "doesn't fully claim to support it.\n"); 1420 } 1421 1422 pci_set_master(pdev); 1423 1424 return 0; 1425 } 1426 1427 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width) 1428 { 1429 u8 ctrl; 1430 1431 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1432 1433 switch (width) { 1434 case MMC_BUS_WIDTH_8: 1435 ctrl |= SDHCI_CTRL_8BITBUS; 1436 ctrl &= ~SDHCI_CTRL_4BITBUS; 1437 break; 1438 case MMC_BUS_WIDTH_4: 1439 ctrl |= SDHCI_CTRL_4BITBUS; 1440 ctrl &= ~SDHCI_CTRL_8BITBUS; 1441 break; 1442 default: 1443 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS); 1444 break; 1445 } 1446 1447 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1448 } 1449 1450 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1451 { 1452 struct sdhci_pci_slot *slot = sdhci_priv(host); 1453 int rst_n_gpio = slot->rst_n_gpio; 1454 1455 if (!gpio_is_valid(rst_n_gpio)) 1456 return; 1457 gpio_set_value_cansleep(rst_n_gpio, 0); 1458 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1459 udelay(10); 1460 gpio_set_value_cansleep(rst_n_gpio, 1); 1461 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1462 usleep_range(300, 1000); 1463 } 1464 1465 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1466 { 1467 struct sdhci_pci_slot *slot = sdhci_priv(host); 1468 1469 if (slot->hw_reset) 1470 slot->hw_reset(host); 1471 } 1472 1473 static int sdhci_pci_select_drive_strength(struct sdhci_host *host, 1474 struct mmc_card *card, 1475 unsigned int max_dtr, int host_drv, 1476 int card_drv, int *drv_type) 1477 { 1478 struct sdhci_pci_slot *slot = sdhci_priv(host); 1479 1480 if (!slot->select_drive_strength) 1481 return 0; 1482 1483 return slot->select_drive_strength(host, card, max_dtr, host_drv, 1484 card_drv, drv_type); 1485 } 1486 1487 static const struct sdhci_ops sdhci_pci_ops = { 1488 .set_clock = sdhci_set_clock, 1489 .enable_dma = sdhci_pci_enable_dma, 1490 .set_bus_width = sdhci_pci_set_bus_width, 1491 .reset = sdhci_reset, 1492 .set_uhs_signaling = sdhci_set_uhs_signaling, 1493 .hw_reset = sdhci_pci_hw_reset, 1494 .select_drive_strength = sdhci_pci_select_drive_strength, 1495 }; 1496 1497 /*****************************************************************************\ 1498 * * 1499 * Suspend/resume * 1500 * * 1501 \*****************************************************************************/ 1502 1503 #ifdef CONFIG_PM_SLEEP 1504 static int sdhci_pci_suspend(struct device *dev) 1505 { 1506 struct pci_dev *pdev = to_pci_dev(dev); 1507 struct sdhci_pci_chip *chip; 1508 struct sdhci_pci_slot *slot; 1509 mmc_pm_flag_t slot_pm_flags; 1510 mmc_pm_flag_t pm_flags = 0; 1511 int i, ret; 1512 1513 chip = pci_get_drvdata(pdev); 1514 if (!chip) 1515 return 0; 1516 1517 for (i = 0; i < chip->num_slots; i++) { 1518 slot = chip->slots[i]; 1519 if (!slot) 1520 continue; 1521 1522 ret = sdhci_suspend_host(slot->host); 1523 1524 if (ret) 1525 goto err_pci_suspend; 1526 1527 slot_pm_flags = slot->host->mmc->pm_flags; 1528 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1529 sdhci_enable_irq_wakeups(slot->host); 1530 1531 pm_flags |= slot_pm_flags; 1532 } 1533 1534 if (chip->fixes && chip->fixes->suspend) { 1535 ret = chip->fixes->suspend(chip); 1536 if (ret) 1537 goto err_pci_suspend; 1538 } 1539 1540 if (pm_flags & MMC_PM_KEEP_POWER) { 1541 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1542 device_init_wakeup(dev, true); 1543 else 1544 device_init_wakeup(dev, false); 1545 } else 1546 device_init_wakeup(dev, false); 1547 1548 return 0; 1549 1550 err_pci_suspend: 1551 while (--i >= 0) 1552 sdhci_resume_host(chip->slots[i]->host); 1553 return ret; 1554 } 1555 1556 static int sdhci_pci_resume(struct device *dev) 1557 { 1558 struct pci_dev *pdev = to_pci_dev(dev); 1559 struct sdhci_pci_chip *chip; 1560 struct sdhci_pci_slot *slot; 1561 int i, ret; 1562 1563 chip = pci_get_drvdata(pdev); 1564 if (!chip) 1565 return 0; 1566 1567 if (chip->fixes && chip->fixes->resume) { 1568 ret = chip->fixes->resume(chip); 1569 if (ret) 1570 return ret; 1571 } 1572 1573 for (i = 0; i < chip->num_slots; i++) { 1574 slot = chip->slots[i]; 1575 if (!slot) 1576 continue; 1577 1578 ret = sdhci_resume_host(slot->host); 1579 if (ret) 1580 return ret; 1581 } 1582 1583 return 0; 1584 } 1585 #endif 1586 1587 #ifdef CONFIG_PM 1588 static int sdhci_pci_runtime_suspend(struct device *dev) 1589 { 1590 struct pci_dev *pdev = to_pci_dev(dev); 1591 struct sdhci_pci_chip *chip; 1592 struct sdhci_pci_slot *slot; 1593 int i, ret; 1594 1595 chip = pci_get_drvdata(pdev); 1596 if (!chip) 1597 return 0; 1598 1599 for (i = 0; i < chip->num_slots; i++) { 1600 slot = chip->slots[i]; 1601 if (!slot) 1602 continue; 1603 1604 ret = sdhci_runtime_suspend_host(slot->host); 1605 1606 if (ret) 1607 goto err_pci_runtime_suspend; 1608 } 1609 1610 if (chip->fixes && chip->fixes->suspend) { 1611 ret = chip->fixes->suspend(chip); 1612 if (ret) 1613 goto err_pci_runtime_suspend; 1614 } 1615 1616 return 0; 1617 1618 err_pci_runtime_suspend: 1619 while (--i >= 0) 1620 sdhci_runtime_resume_host(chip->slots[i]->host); 1621 return ret; 1622 } 1623 1624 static int sdhci_pci_runtime_resume(struct device *dev) 1625 { 1626 struct pci_dev *pdev = to_pci_dev(dev); 1627 struct sdhci_pci_chip *chip; 1628 struct sdhci_pci_slot *slot; 1629 int i, ret; 1630 1631 chip = pci_get_drvdata(pdev); 1632 if (!chip) 1633 return 0; 1634 1635 if (chip->fixes && chip->fixes->resume) { 1636 ret = chip->fixes->resume(chip); 1637 if (ret) 1638 return ret; 1639 } 1640 1641 for (i = 0; i < chip->num_slots; i++) { 1642 slot = chip->slots[i]; 1643 if (!slot) 1644 continue; 1645 1646 ret = sdhci_runtime_resume_host(slot->host); 1647 if (ret) 1648 return ret; 1649 } 1650 1651 return 0; 1652 } 1653 #endif 1654 1655 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1656 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1657 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1658 sdhci_pci_runtime_resume, NULL) 1659 }; 1660 1661 /*****************************************************************************\ 1662 * * 1663 * Device probing/removal * 1664 * * 1665 \*****************************************************************************/ 1666 1667 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1668 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1669 int slotno) 1670 { 1671 struct sdhci_pci_slot *slot; 1672 struct sdhci_host *host; 1673 int ret, bar = first_bar + slotno; 1674 1675 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1676 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1677 return ERR_PTR(-ENODEV); 1678 } 1679 1680 if (pci_resource_len(pdev, bar) < 0x100) { 1681 dev_err(&pdev->dev, "Invalid iomem size. You may " 1682 "experience problems.\n"); 1683 } 1684 1685 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1686 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1687 return ERR_PTR(-ENODEV); 1688 } 1689 1690 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1691 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1692 return ERR_PTR(-ENODEV); 1693 } 1694 1695 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot)); 1696 if (IS_ERR(host)) { 1697 dev_err(&pdev->dev, "cannot allocate host\n"); 1698 return ERR_CAST(host); 1699 } 1700 1701 slot = sdhci_priv(host); 1702 1703 slot->chip = chip; 1704 slot->host = host; 1705 slot->rst_n_gpio = -EINVAL; 1706 slot->cd_gpio = -EINVAL; 1707 slot->cd_idx = -1; 1708 1709 /* Retrieve platform data if there is any */ 1710 if (*sdhci_pci_get_data) 1711 slot->data = sdhci_pci_get_data(pdev, slotno); 1712 1713 if (slot->data) { 1714 if (slot->data->setup) { 1715 ret = slot->data->setup(slot->data); 1716 if (ret) { 1717 dev_err(&pdev->dev, "platform setup failed\n"); 1718 goto free; 1719 } 1720 } 1721 slot->rst_n_gpio = slot->data->rst_n_gpio; 1722 slot->cd_gpio = slot->data->cd_gpio; 1723 } 1724 1725 host->hw_name = "PCI"; 1726 host->ops = chip->fixes && chip->fixes->ops ? 1727 chip->fixes->ops : 1728 &sdhci_pci_ops; 1729 host->quirks = chip->quirks; 1730 host->quirks2 = chip->quirks2; 1731 1732 host->irq = pdev->irq; 1733 1734 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1735 if (ret) { 1736 dev_err(&pdev->dev, "cannot request region\n"); 1737 goto cleanup; 1738 } 1739 1740 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1741 1742 if (chip->fixes && chip->fixes->probe_slot) { 1743 ret = chip->fixes->probe_slot(slot); 1744 if (ret) 1745 goto cleanup; 1746 } 1747 1748 if (gpio_is_valid(slot->rst_n_gpio)) { 1749 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1750 gpio_direction_output(slot->rst_n_gpio, 1); 1751 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1752 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1753 } else { 1754 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1755 slot->rst_n_gpio = -EINVAL; 1756 } 1757 } 1758 1759 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; 1760 host->mmc->slotno = slotno; 1761 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1762 1763 if (slot->cd_idx >= 0) { 1764 ret = mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx, 1765 slot->cd_override_level, 0, NULL); 1766 if (ret == -EPROBE_DEFER) 1767 goto remove; 1768 1769 if (ret) { 1770 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 1771 slot->cd_idx = -1; 1772 } 1773 } 1774 1775 ret = sdhci_add_host(host); 1776 if (ret) 1777 goto remove; 1778 1779 sdhci_pci_add_own_cd(slot); 1780 1781 /* 1782 * Check if the chip needs a separate GPIO for card detect to wake up 1783 * from runtime suspend. If it is not there, don't allow runtime PM. 1784 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 1785 */ 1786 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 1787 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 1788 chip->allow_runtime_pm = false; 1789 1790 return slot; 1791 1792 remove: 1793 if (chip->fixes && chip->fixes->remove_slot) 1794 chip->fixes->remove_slot(slot, 0); 1795 1796 cleanup: 1797 if (slot->data && slot->data->cleanup) 1798 slot->data->cleanup(slot->data); 1799 1800 free: 1801 sdhci_free_host(host); 1802 1803 return ERR_PTR(ret); 1804 } 1805 1806 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 1807 { 1808 int dead; 1809 u32 scratch; 1810 1811 sdhci_pci_remove_own_cd(slot); 1812 1813 dead = 0; 1814 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 1815 if (scratch == (u32)-1) 1816 dead = 1; 1817 1818 sdhci_remove_host(slot->host, dead); 1819 1820 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 1821 slot->chip->fixes->remove_slot(slot, dead); 1822 1823 if (slot->data && slot->data->cleanup) 1824 slot->data->cleanup(slot->data); 1825 1826 sdhci_free_host(slot->host); 1827 } 1828 1829 static void sdhci_pci_runtime_pm_allow(struct device *dev) 1830 { 1831 pm_suspend_ignore_children(dev, 1); 1832 pm_runtime_set_autosuspend_delay(dev, 50); 1833 pm_runtime_use_autosuspend(dev); 1834 pm_runtime_allow(dev); 1835 /* Stay active until mmc core scans for a card */ 1836 pm_runtime_put_noidle(dev); 1837 } 1838 1839 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 1840 { 1841 pm_runtime_forbid(dev); 1842 pm_runtime_get_noresume(dev); 1843 } 1844 1845 static int sdhci_pci_probe(struct pci_dev *pdev, 1846 const struct pci_device_id *ent) 1847 { 1848 struct sdhci_pci_chip *chip; 1849 struct sdhci_pci_slot *slot; 1850 1851 u8 slots, first_bar; 1852 int ret, i; 1853 1854 BUG_ON(pdev == NULL); 1855 BUG_ON(ent == NULL); 1856 1857 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 1858 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 1859 1860 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 1861 if (ret) 1862 return ret; 1863 1864 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 1865 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 1866 if (slots == 0) 1867 return -ENODEV; 1868 1869 BUG_ON(slots > MAX_SLOTS); 1870 1871 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 1872 if (ret) 1873 return ret; 1874 1875 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 1876 1877 if (first_bar > 5) { 1878 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 1879 return -ENODEV; 1880 } 1881 1882 ret = pcim_enable_device(pdev); 1883 if (ret) 1884 return ret; 1885 1886 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 1887 if (!chip) 1888 return -ENOMEM; 1889 1890 chip->pdev = pdev; 1891 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 1892 if (chip->fixes) { 1893 chip->quirks = chip->fixes->quirks; 1894 chip->quirks2 = chip->fixes->quirks2; 1895 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 1896 } 1897 chip->num_slots = slots; 1898 1899 pci_set_drvdata(pdev, chip); 1900 1901 if (chip->fixes && chip->fixes->probe) { 1902 ret = chip->fixes->probe(chip); 1903 if (ret) 1904 return ret; 1905 } 1906 1907 slots = chip->num_slots; /* Quirk may have changed this */ 1908 1909 for (i = 0; i < slots; i++) { 1910 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 1911 if (IS_ERR(slot)) { 1912 for (i--; i >= 0; i--) 1913 sdhci_pci_remove_slot(chip->slots[i]); 1914 return PTR_ERR(slot); 1915 } 1916 1917 chip->slots[i] = slot; 1918 } 1919 1920 if (chip->allow_runtime_pm) 1921 sdhci_pci_runtime_pm_allow(&pdev->dev); 1922 1923 return 0; 1924 } 1925 1926 static void sdhci_pci_remove(struct pci_dev *pdev) 1927 { 1928 int i; 1929 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1930 1931 if (chip->allow_runtime_pm) 1932 sdhci_pci_runtime_pm_forbid(&pdev->dev); 1933 1934 for (i = 0; i < chip->num_slots; i++) 1935 sdhci_pci_remove_slot(chip->slots[i]); 1936 } 1937 1938 static struct pci_driver sdhci_driver = { 1939 .name = "sdhci-pci", 1940 .id_table = pci_ids, 1941 .probe = sdhci_pci_probe, 1942 .remove = sdhci_pci_remove, 1943 .driver = { 1944 .pm = &sdhci_pci_pm_ops 1945 }, 1946 }; 1947 1948 module_pci_driver(sdhci_driver); 1949 1950 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 1951 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 1952 MODULE_LICENSE("GPL"); 1953