1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 2 * 3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 * 10 * Thanks to the following companies for their support: 11 * 12 * - JMicron (hardware and technical support) 13 */ 14 15 #include <linux/string.h> 16 #include <linux/delay.h> 17 #include <linux/highmem.h> 18 #include <linux/module.h> 19 #include <linux/pci.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/slab.h> 22 #include <linux/device.h> 23 #include <linux/mmc/host.h> 24 #include <linux/mmc/mmc.h> 25 #include <linux/scatterlist.h> 26 #include <linux/io.h> 27 #include <linux/gpio.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/mmc/slot-gpio.h> 30 #include <linux/mmc/sdhci-pci-data.h> 31 #include <linux/acpi.h> 32 33 #include "sdhci.h" 34 #include "sdhci-pci.h" 35 #include "sdhci-pci-o2micro.h" 36 37 static int sdhci_pci_enable_dma(struct sdhci_host *host); 38 static void sdhci_pci_hw_reset(struct sdhci_host *host); 39 40 #ifdef CONFIG_PM_SLEEP 41 static int __sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 42 { 43 int i, ret; 44 45 for (i = 0; i < chip->num_slots; i++) { 46 struct sdhci_pci_slot *slot = chip->slots[i]; 47 struct sdhci_host *host; 48 49 if (!slot) 50 continue; 51 52 host = slot->host; 53 54 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 55 mmc_retune_needed(host->mmc); 56 57 ret = sdhci_suspend_host(host); 58 if (ret) 59 goto err_pci_suspend; 60 61 if (host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ) 62 sdhci_enable_irq_wakeups(host); 63 } 64 65 return 0; 66 67 err_pci_suspend: 68 while (--i >= 0) 69 sdhci_resume_host(chip->slots[i]->host); 70 return ret; 71 } 72 73 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip) 74 { 75 mmc_pm_flag_t pm_flags = 0; 76 int i; 77 78 for (i = 0; i < chip->num_slots; i++) { 79 struct sdhci_pci_slot *slot = chip->slots[i]; 80 81 if (slot) 82 pm_flags |= slot->host->mmc->pm_flags; 83 } 84 85 return device_init_wakeup(&chip->pdev->dev, 86 (pm_flags & MMC_PM_KEEP_POWER) && 87 (pm_flags & MMC_PM_WAKE_SDIO_IRQ)); 88 } 89 90 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 91 { 92 int ret; 93 94 ret = __sdhci_pci_suspend_host(chip); 95 if (ret) 96 return ret; 97 98 sdhci_pci_init_wakeup(chip); 99 100 return 0; 101 } 102 103 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip) 104 { 105 struct sdhci_pci_slot *slot; 106 int i, ret; 107 108 for (i = 0; i < chip->num_slots; i++) { 109 slot = chip->slots[i]; 110 if (!slot) 111 continue; 112 113 ret = sdhci_resume_host(slot->host); 114 if (ret) 115 return ret; 116 } 117 118 return 0; 119 } 120 #endif 121 122 #ifdef CONFIG_PM 123 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip) 124 { 125 struct sdhci_pci_slot *slot; 126 struct sdhci_host *host; 127 int i, ret; 128 129 for (i = 0; i < chip->num_slots; i++) { 130 slot = chip->slots[i]; 131 if (!slot) 132 continue; 133 134 host = slot->host; 135 136 ret = sdhci_runtime_suspend_host(host); 137 if (ret) 138 goto err_pci_runtime_suspend; 139 140 if (chip->rpm_retune && 141 host->tuning_mode != SDHCI_TUNING_MODE_3) 142 mmc_retune_needed(host->mmc); 143 } 144 145 return 0; 146 147 err_pci_runtime_suspend: 148 while (--i >= 0) 149 sdhci_runtime_resume_host(chip->slots[i]->host); 150 return ret; 151 } 152 153 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip) 154 { 155 struct sdhci_pci_slot *slot; 156 int i, ret; 157 158 for (i = 0; i < chip->num_slots; i++) { 159 slot = chip->slots[i]; 160 if (!slot) 161 continue; 162 163 ret = sdhci_runtime_resume_host(slot->host); 164 if (ret) 165 return ret; 166 } 167 168 return 0; 169 } 170 #endif 171 172 /*****************************************************************************\ 173 * * 174 * Hardware specific quirk handling * 175 * * 176 \*****************************************************************************/ 177 178 static int ricoh_probe(struct sdhci_pci_chip *chip) 179 { 180 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 181 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 182 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 183 return 0; 184 } 185 186 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 187 { 188 slot->host->caps = 189 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 190 & SDHCI_TIMEOUT_CLK_MASK) | 191 192 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 193 & SDHCI_CLOCK_BASE_MASK) | 194 195 SDHCI_TIMEOUT_CLK_UNIT | 196 SDHCI_CAN_VDD_330 | 197 SDHCI_CAN_DO_HISPD | 198 SDHCI_CAN_DO_SDMA; 199 return 0; 200 } 201 202 #ifdef CONFIG_PM_SLEEP 203 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 204 { 205 /* Apply a delay to allow controller to settle */ 206 /* Otherwise it becomes confused if card state changed 207 during suspend */ 208 msleep(500); 209 return sdhci_pci_resume_host(chip); 210 } 211 #endif 212 213 static const struct sdhci_pci_fixes sdhci_ricoh = { 214 .probe = ricoh_probe, 215 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 216 SDHCI_QUIRK_FORCE_DMA | 217 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 218 }; 219 220 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 221 .probe_slot = ricoh_mmc_probe_slot, 222 #ifdef CONFIG_PM_SLEEP 223 .resume = ricoh_mmc_resume, 224 #endif 225 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 226 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 227 SDHCI_QUIRK_NO_CARD_NO_RESET | 228 SDHCI_QUIRK_MISSING_CAPS 229 }; 230 231 static const struct sdhci_pci_fixes sdhci_ene_712 = { 232 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 233 SDHCI_QUIRK_BROKEN_DMA, 234 }; 235 236 static const struct sdhci_pci_fixes sdhci_ene_714 = { 237 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 238 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 239 SDHCI_QUIRK_BROKEN_DMA, 240 }; 241 242 static const struct sdhci_pci_fixes sdhci_cafe = { 243 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 244 SDHCI_QUIRK_NO_BUSY_IRQ | 245 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 246 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 247 }; 248 249 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 250 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 251 }; 252 253 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 254 { 255 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 256 return 0; 257 } 258 259 /* 260 * ADMA operation is disabled for Moorestown platform due to 261 * hardware bugs. 262 */ 263 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 264 { 265 /* 266 * slots number is fixed here for MRST as SDIO3/5 are never used and 267 * have hardware bugs. 268 */ 269 chip->num_slots = 1; 270 return 0; 271 } 272 273 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 274 { 275 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 276 return 0; 277 } 278 279 #ifdef CONFIG_PM 280 281 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 282 { 283 struct sdhci_pci_slot *slot = dev_id; 284 struct sdhci_host *host = slot->host; 285 286 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 287 return IRQ_HANDLED; 288 } 289 290 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 291 { 292 int err, irq, gpio = slot->cd_gpio; 293 294 slot->cd_gpio = -EINVAL; 295 slot->cd_irq = -EINVAL; 296 297 if (!gpio_is_valid(gpio)) 298 return; 299 300 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 301 if (err < 0) 302 goto out; 303 304 err = gpio_direction_input(gpio); 305 if (err < 0) 306 goto out_free; 307 308 irq = gpio_to_irq(gpio); 309 if (irq < 0) 310 goto out_free; 311 312 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 313 IRQF_TRIGGER_FALLING, "sd_cd", slot); 314 if (err) 315 goto out_free; 316 317 slot->cd_gpio = gpio; 318 slot->cd_irq = irq; 319 320 return; 321 322 out_free: 323 devm_gpio_free(&slot->chip->pdev->dev, gpio); 324 out: 325 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 326 } 327 328 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 329 { 330 if (slot->cd_irq >= 0) 331 free_irq(slot->cd_irq, slot); 332 } 333 334 #else 335 336 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 337 { 338 } 339 340 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 341 { 342 } 343 344 #endif 345 346 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 347 { 348 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 349 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC; 350 return 0; 351 } 352 353 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 354 { 355 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 356 return 0; 357 } 358 359 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 360 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 361 .probe_slot = mrst_hc_probe_slot, 362 }; 363 364 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 365 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 366 .probe = mrst_hc_probe, 367 }; 368 369 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 370 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 371 .allow_runtime_pm = true, 372 .own_cd_for_runtime_pm = true, 373 }; 374 375 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 376 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 377 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 378 .allow_runtime_pm = true, 379 .probe_slot = mfd_sdio_probe_slot, 380 }; 381 382 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 383 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 384 .allow_runtime_pm = true, 385 .probe_slot = mfd_emmc_probe_slot, 386 }; 387 388 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 389 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 390 .probe_slot = pch_hc_probe_slot, 391 }; 392 393 enum { 394 INTEL_DSM_FNS = 0, 395 INTEL_DSM_V18_SWITCH = 3, 396 INTEL_DSM_DRV_STRENGTH = 9, 397 INTEL_DSM_D3_RETUNE = 10, 398 }; 399 400 struct intel_host { 401 u32 dsm_fns; 402 int drv_strength; 403 bool d3_retune; 404 }; 405 406 static const guid_t intel_dsm_guid = 407 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F, 408 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61); 409 410 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 411 unsigned int fn, u32 *result) 412 { 413 union acpi_object *obj; 414 int err = 0; 415 size_t len; 416 417 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL); 418 if (!obj) 419 return -EOPNOTSUPP; 420 421 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { 422 err = -EINVAL; 423 goto out; 424 } 425 426 len = min_t(size_t, obj->buffer.length, 4); 427 428 *result = 0; 429 memcpy(result, obj->buffer.pointer, len); 430 out: 431 ACPI_FREE(obj); 432 433 return err; 434 } 435 436 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 437 unsigned int fn, u32 *result) 438 { 439 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 440 return -EOPNOTSUPP; 441 442 return __intel_dsm(intel_host, dev, fn, result); 443 } 444 445 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 446 struct mmc_host *mmc) 447 { 448 int err; 449 u32 val; 450 451 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 452 if (err) { 453 pr_debug("%s: DSM not supported, error %d\n", 454 mmc_hostname(mmc), err); 455 return; 456 } 457 458 pr_debug("%s: DSM function mask %#x\n", 459 mmc_hostname(mmc), intel_host->dsm_fns); 460 461 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 462 intel_host->drv_strength = err ? 0 : val; 463 464 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 465 intel_host->d3_retune = err ? true : !!val; 466 } 467 468 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 469 { 470 u8 reg; 471 472 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 473 reg |= 0x10; 474 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 475 /* For eMMC, minimum is 1us but give it 9us for good measure */ 476 udelay(9); 477 reg &= ~0x10; 478 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 479 /* For eMMC, minimum is 200us but give it 300us for good measure */ 480 usleep_range(300, 1000); 481 } 482 483 static int intel_select_drive_strength(struct mmc_card *card, 484 unsigned int max_dtr, int host_drv, 485 int card_drv, int *drv_type) 486 { 487 struct sdhci_host *host = mmc_priv(card->host); 488 struct sdhci_pci_slot *slot = sdhci_priv(host); 489 struct intel_host *intel_host = sdhci_pci_priv(slot); 490 491 return intel_host->drv_strength; 492 } 493 494 static int bxt_get_cd(struct mmc_host *mmc) 495 { 496 int gpio_cd = mmc_gpio_get_cd(mmc); 497 struct sdhci_host *host = mmc_priv(mmc); 498 unsigned long flags; 499 int ret = 0; 500 501 if (!gpio_cd) 502 return 0; 503 504 spin_lock_irqsave(&host->lock, flags); 505 506 if (host->flags & SDHCI_DEVICE_DEAD) 507 goto out; 508 509 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 510 out: 511 spin_unlock_irqrestore(&host->lock, flags); 512 513 return ret; 514 } 515 516 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 517 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 518 519 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 520 unsigned short vdd) 521 { 522 int cntr; 523 u8 reg; 524 525 sdhci_set_power(host, mode, vdd); 526 527 if (mode == MMC_POWER_OFF) 528 return; 529 530 /* 531 * Bus power might not enable after D3 -> D0 transition due to the 532 * present state not yet having propagated. Retry for up to 2ms. 533 */ 534 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 535 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 536 if (reg & SDHCI_POWER_ON) 537 break; 538 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 539 reg |= SDHCI_POWER_ON; 540 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 541 } 542 } 543 544 #define INTEL_HS400_ES_REG 0x78 545 #define INTEL_HS400_ES_BIT BIT(0) 546 547 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc, 548 struct mmc_ios *ios) 549 { 550 struct sdhci_host *host = mmc_priv(mmc); 551 u32 val; 552 553 val = sdhci_readl(host, INTEL_HS400_ES_REG); 554 if (ios->enhanced_strobe) 555 val |= INTEL_HS400_ES_BIT; 556 else 557 val &= ~INTEL_HS400_ES_BIT; 558 sdhci_writel(host, val, INTEL_HS400_ES_REG); 559 } 560 561 static void sdhci_intel_voltage_switch(struct sdhci_host *host) 562 { 563 struct sdhci_pci_slot *slot = sdhci_priv(host); 564 struct intel_host *intel_host = sdhci_pci_priv(slot); 565 struct device *dev = &slot->chip->pdev->dev; 566 u32 result = 0; 567 int err; 568 569 err = intel_dsm(intel_host, dev, INTEL_DSM_V18_SWITCH, &result); 570 pr_debug("%s: %s DSM error %d result %u\n", 571 mmc_hostname(host->mmc), __func__, err, result); 572 } 573 574 static const struct sdhci_ops sdhci_intel_byt_ops = { 575 .set_clock = sdhci_set_clock, 576 .set_power = sdhci_intel_set_power, 577 .enable_dma = sdhci_pci_enable_dma, 578 .set_bus_width = sdhci_set_bus_width, 579 .reset = sdhci_reset, 580 .set_uhs_signaling = sdhci_set_uhs_signaling, 581 .hw_reset = sdhci_pci_hw_reset, 582 .voltage_switch = sdhci_intel_voltage_switch, 583 }; 584 585 static void byt_read_dsm(struct sdhci_pci_slot *slot) 586 { 587 struct intel_host *intel_host = sdhci_pci_priv(slot); 588 struct device *dev = &slot->chip->pdev->dev; 589 struct mmc_host *mmc = slot->host->mmc; 590 591 intel_dsm_init(intel_host, dev, mmc); 592 slot->chip->rpm_retune = intel_host->d3_retune; 593 } 594 595 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 596 { 597 byt_read_dsm(slot); 598 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 599 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 600 MMC_CAP_CMD_DURING_TFR | 601 MMC_CAP_WAIT_WHILE_BUSY; 602 slot->hw_reset = sdhci_pci_int_hw_reset; 603 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 604 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 605 slot->host->mmc_host_ops.select_drive_strength = 606 intel_select_drive_strength; 607 return 0; 608 } 609 610 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot) 611 { 612 int ret = byt_emmc_probe_slot(slot); 613 614 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) { 615 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES, 616 slot->host->mmc_host_ops.hs400_enhanced_strobe = 617 intel_hs400_enhanced_strobe; 618 } 619 620 return ret; 621 } 622 623 #ifdef CONFIG_ACPI 624 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 625 { 626 acpi_status status; 627 unsigned long long max_freq; 628 629 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 630 "MXFQ", NULL, &max_freq); 631 if (ACPI_FAILURE(status)) { 632 dev_err(&slot->chip->pdev->dev, 633 "MXFQ not found in acpi table\n"); 634 return -EINVAL; 635 } 636 637 slot->host->mmc->f_max = max_freq * 1000000; 638 639 return 0; 640 } 641 #else 642 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 643 { 644 return 0; 645 } 646 #endif 647 648 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 649 { 650 int err; 651 652 byt_read_dsm(slot); 653 654 err = ni_set_max_freq(slot); 655 if (err) 656 return err; 657 658 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 659 MMC_CAP_WAIT_WHILE_BUSY; 660 return 0; 661 } 662 663 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 664 { 665 byt_read_dsm(slot); 666 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 667 MMC_CAP_WAIT_WHILE_BUSY; 668 return 0; 669 } 670 671 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 672 { 673 byt_read_dsm(slot); 674 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | 675 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE; 676 slot->cd_idx = 0; 677 slot->cd_override_level = true; 678 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 679 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 680 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 681 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) 682 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 683 684 return 0; 685 } 686 687 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 688 .allow_runtime_pm = true, 689 .probe_slot = byt_emmc_probe_slot, 690 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 691 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 692 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 693 SDHCI_QUIRK2_STOP_WITH_TC, 694 .ops = &sdhci_intel_byt_ops, 695 .priv_size = sizeof(struct intel_host), 696 }; 697 698 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = { 699 .allow_runtime_pm = true, 700 .probe_slot = glk_emmc_probe_slot, 701 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 702 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 703 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 704 SDHCI_QUIRK2_STOP_WITH_TC, 705 .ops = &sdhci_intel_byt_ops, 706 .priv_size = sizeof(struct intel_host), 707 }; 708 709 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 710 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 711 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 712 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 713 .allow_runtime_pm = true, 714 .probe_slot = ni_byt_sdio_probe_slot, 715 .ops = &sdhci_intel_byt_ops, 716 .priv_size = sizeof(struct intel_host), 717 }; 718 719 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 720 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 721 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 722 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 723 .allow_runtime_pm = true, 724 .probe_slot = byt_sdio_probe_slot, 725 .ops = &sdhci_intel_byt_ops, 726 .priv_size = sizeof(struct intel_host), 727 }; 728 729 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 730 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 731 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 732 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 733 SDHCI_QUIRK2_STOP_WITH_TC, 734 .allow_runtime_pm = true, 735 .own_cd_for_runtime_pm = true, 736 .probe_slot = byt_sd_probe_slot, 737 .ops = &sdhci_intel_byt_ops, 738 .priv_size = sizeof(struct intel_host), 739 }; 740 741 /* Define Host controllers for Intel Merrifield platform */ 742 #define INTEL_MRFLD_EMMC_0 0 743 #define INTEL_MRFLD_EMMC_1 1 744 #define INTEL_MRFLD_SD 2 745 #define INTEL_MRFLD_SDIO 3 746 747 #ifdef CONFIG_ACPI 748 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) 749 { 750 struct acpi_device *device, *child; 751 752 device = ACPI_COMPANION(&slot->chip->pdev->dev); 753 if (!device) 754 return; 755 756 acpi_device_fix_up_power(device); 757 list_for_each_entry(child, &device->children, node) 758 if (child->status.present && child->status.enabled) 759 acpi_device_fix_up_power(child); 760 } 761 #else 762 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {} 763 #endif 764 765 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 766 { 767 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 768 769 switch (func) { 770 case INTEL_MRFLD_EMMC_0: 771 case INTEL_MRFLD_EMMC_1: 772 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 773 MMC_CAP_8_BIT_DATA | 774 MMC_CAP_1_8V_DDR; 775 break; 776 case INTEL_MRFLD_SD: 777 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 778 break; 779 case INTEL_MRFLD_SDIO: 780 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 781 MMC_CAP_POWER_OFF_CARD; 782 break; 783 default: 784 return -ENODEV; 785 } 786 787 intel_mrfld_mmc_fix_up_power_slot(slot); 788 return 0; 789 } 790 791 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 792 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 793 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 794 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 795 .allow_runtime_pm = true, 796 .probe_slot = intel_mrfld_mmc_probe_slot, 797 }; 798 799 /* O2Micro extra registers */ 800 #define O2_SD_LOCK_WP 0xD3 801 #define O2_SD_MULTI_VCC3V 0xEE 802 #define O2_SD_CLKREQ 0xEC 803 #define O2_SD_CAPS 0xE0 804 #define O2_SD_ADMA1 0xE2 805 #define O2_SD_ADMA2 0xE7 806 #define O2_SD_INF_MOD 0xF1 807 808 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 809 { 810 u8 scratch; 811 int ret; 812 813 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 814 if (ret) 815 return ret; 816 817 /* 818 * Turn PMOS on [bit 0], set over current detection to 2.4 V 819 * [bit 1:2] and enable over current debouncing [bit 6]. 820 */ 821 if (on) 822 scratch |= 0x47; 823 else 824 scratch &= ~0x47; 825 826 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 827 } 828 829 static int jmicron_probe(struct sdhci_pci_chip *chip) 830 { 831 int ret; 832 u16 mmcdev = 0; 833 834 if (chip->pdev->revision == 0) { 835 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 836 SDHCI_QUIRK_32BIT_DMA_SIZE | 837 SDHCI_QUIRK_32BIT_ADMA_SIZE | 838 SDHCI_QUIRK_RESET_AFTER_REQUEST | 839 SDHCI_QUIRK_BROKEN_SMALL_PIO; 840 } 841 842 /* 843 * JMicron chips can have two interfaces to the same hardware 844 * in order to work around limitations in Microsoft's driver. 845 * We need to make sure we only bind to one of them. 846 * 847 * This code assumes two things: 848 * 849 * 1. The PCI code adds subfunctions in order. 850 * 851 * 2. The MMC interface has a lower subfunction number 852 * than the SD interface. 853 */ 854 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 855 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 856 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 857 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 858 859 if (mmcdev) { 860 struct pci_dev *sd_dev; 861 862 sd_dev = NULL; 863 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 864 mmcdev, sd_dev)) != NULL) { 865 if ((PCI_SLOT(chip->pdev->devfn) == 866 PCI_SLOT(sd_dev->devfn)) && 867 (chip->pdev->bus == sd_dev->bus)) 868 break; 869 } 870 871 if (sd_dev) { 872 pci_dev_put(sd_dev); 873 dev_info(&chip->pdev->dev, "Refusing to bind to " 874 "secondary interface.\n"); 875 return -ENODEV; 876 } 877 } 878 879 /* 880 * JMicron chips need a bit of a nudge to enable the power 881 * output pins. 882 */ 883 ret = jmicron_pmos(chip, 1); 884 if (ret) { 885 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 886 return ret; 887 } 888 889 /* quirk for unsable RO-detection on JM388 chips */ 890 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 891 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 892 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 893 894 return 0; 895 } 896 897 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 898 { 899 u8 scratch; 900 901 scratch = readb(host->ioaddr + 0xC0); 902 903 if (on) 904 scratch |= 0x01; 905 else 906 scratch &= ~0x01; 907 908 writeb(scratch, host->ioaddr + 0xC0); 909 } 910 911 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 912 { 913 if (slot->chip->pdev->revision == 0) { 914 u16 version; 915 916 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 917 version = (version & SDHCI_VENDOR_VER_MASK) >> 918 SDHCI_VENDOR_VER_SHIFT; 919 920 /* 921 * Older versions of the chip have lots of nasty glitches 922 * in the ADMA engine. It's best just to avoid it 923 * completely. 924 */ 925 if (version < 0xAC) 926 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 927 } 928 929 /* JM388 MMC doesn't support 1.8V while SD supports it */ 930 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 931 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 932 MMC_VDD_29_30 | MMC_VDD_30_31 | 933 MMC_VDD_165_195; /* allow 1.8V */ 934 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 935 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 936 } 937 938 /* 939 * The secondary interface requires a bit set to get the 940 * interrupts. 941 */ 942 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 943 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 944 jmicron_enable_mmc(slot->host, 1); 945 946 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 947 948 return 0; 949 } 950 951 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 952 { 953 if (dead) 954 return; 955 956 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 957 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 958 jmicron_enable_mmc(slot->host, 0); 959 } 960 961 #ifdef CONFIG_PM_SLEEP 962 static int jmicron_suspend(struct sdhci_pci_chip *chip) 963 { 964 int i, ret; 965 966 ret = __sdhci_pci_suspend_host(chip); 967 if (ret) 968 return ret; 969 970 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 971 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 972 for (i = 0; i < chip->num_slots; i++) 973 jmicron_enable_mmc(chip->slots[i]->host, 0); 974 } 975 976 sdhci_pci_init_wakeup(chip); 977 978 return 0; 979 } 980 981 static int jmicron_resume(struct sdhci_pci_chip *chip) 982 { 983 int ret, i; 984 985 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 986 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 987 for (i = 0; i < chip->num_slots; i++) 988 jmicron_enable_mmc(chip->slots[i]->host, 1); 989 } 990 991 ret = jmicron_pmos(chip, 1); 992 if (ret) { 993 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 994 return ret; 995 } 996 997 return sdhci_pci_resume_host(chip); 998 } 999 #endif 1000 1001 static const struct sdhci_pci_fixes sdhci_o2 = { 1002 .probe = sdhci_pci_o2_probe, 1003 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1004 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 1005 .probe_slot = sdhci_pci_o2_probe_slot, 1006 #ifdef CONFIG_PM_SLEEP 1007 .resume = sdhci_pci_o2_resume, 1008 #endif 1009 }; 1010 1011 static const struct sdhci_pci_fixes sdhci_jmicron = { 1012 .probe = jmicron_probe, 1013 1014 .probe_slot = jmicron_probe_slot, 1015 .remove_slot = jmicron_remove_slot, 1016 1017 #ifdef CONFIG_PM_SLEEP 1018 .suspend = jmicron_suspend, 1019 .resume = jmicron_resume, 1020 #endif 1021 }; 1022 1023 /* SysKonnect CardBus2SDIO extra registers */ 1024 #define SYSKT_CTRL 0x200 1025 #define SYSKT_RDFIFO_STAT 0x204 1026 #define SYSKT_WRFIFO_STAT 0x208 1027 #define SYSKT_POWER_DATA 0x20c 1028 #define SYSKT_POWER_330 0xef 1029 #define SYSKT_POWER_300 0xf8 1030 #define SYSKT_POWER_184 0xcc 1031 #define SYSKT_POWER_CMD 0x20d 1032 #define SYSKT_POWER_START (1 << 7) 1033 #define SYSKT_POWER_STATUS 0x20e 1034 #define SYSKT_POWER_STATUS_OK (1 << 0) 1035 #define SYSKT_BOARD_REV 0x210 1036 #define SYSKT_CHIP_REV 0x211 1037 #define SYSKT_CONF_DATA 0x212 1038 #define SYSKT_CONF_DATA_1V8 (1 << 2) 1039 #define SYSKT_CONF_DATA_2V5 (1 << 1) 1040 #define SYSKT_CONF_DATA_3V3 (1 << 0) 1041 1042 static int syskt_probe(struct sdhci_pci_chip *chip) 1043 { 1044 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1045 chip->pdev->class &= ~0x0000FF; 1046 chip->pdev->class |= PCI_SDHCI_IFDMA; 1047 } 1048 return 0; 1049 } 1050 1051 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 1052 { 1053 int tm, ps; 1054 1055 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 1056 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 1057 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 1058 "board rev %d.%d, chip rev %d.%d\n", 1059 board_rev >> 4, board_rev & 0xf, 1060 chip_rev >> 4, chip_rev & 0xf); 1061 if (chip_rev >= 0x20) 1062 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 1063 1064 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 1065 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 1066 udelay(50); 1067 tm = 10; /* Wait max 1 ms */ 1068 do { 1069 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 1070 if (ps & SYSKT_POWER_STATUS_OK) 1071 break; 1072 udelay(100); 1073 } while (--tm); 1074 if (!tm) { 1075 dev_err(&slot->chip->pdev->dev, 1076 "power regulator never stabilized"); 1077 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 1078 return -ENODEV; 1079 } 1080 1081 return 0; 1082 } 1083 1084 static const struct sdhci_pci_fixes sdhci_syskt = { 1085 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 1086 .probe = syskt_probe, 1087 .probe_slot = syskt_probe_slot, 1088 }; 1089 1090 static int via_probe(struct sdhci_pci_chip *chip) 1091 { 1092 if (chip->pdev->revision == 0x10) 1093 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 1094 1095 return 0; 1096 } 1097 1098 static const struct sdhci_pci_fixes sdhci_via = { 1099 .probe = via_probe, 1100 }; 1101 1102 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 1103 { 1104 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 1105 return 0; 1106 } 1107 1108 static const struct sdhci_pci_fixes sdhci_rtsx = { 1109 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1110 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 1111 SDHCI_QUIRK2_BROKEN_DDR50, 1112 .probe_slot = rtsx_probe_slot, 1113 }; 1114 1115 /*AMD chipset generation*/ 1116 enum amd_chipset_gen { 1117 AMD_CHIPSET_BEFORE_ML, 1118 AMD_CHIPSET_CZ, 1119 AMD_CHIPSET_NL, 1120 AMD_CHIPSET_UNKNOWN, 1121 }; 1122 1123 /* AMD registers */ 1124 #define AMD_SD_AUTO_PATTERN 0xB8 1125 #define AMD_MSLEEP_DURATION 4 1126 #define AMD_SD_MISC_CONTROL 0xD0 1127 #define AMD_MAX_TUNE_VALUE 0x0B 1128 #define AMD_AUTO_TUNE_SEL 0x10800 1129 #define AMD_FIFO_PTR 0x30 1130 #define AMD_BIT_MASK 0x1F 1131 1132 static void amd_tuning_reset(struct sdhci_host *host) 1133 { 1134 unsigned int val; 1135 1136 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1137 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 1138 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1139 1140 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1141 val &= ~SDHCI_CTRL_EXEC_TUNING; 1142 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1143 } 1144 1145 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 1146 { 1147 unsigned int val; 1148 1149 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 1150 val &= ~AMD_BIT_MASK; 1151 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 1152 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 1153 } 1154 1155 static void amd_enable_manual_tuning(struct pci_dev *pdev) 1156 { 1157 unsigned int val; 1158 1159 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 1160 val |= AMD_FIFO_PTR; 1161 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 1162 } 1163 1164 static int amd_execute_tuning(struct sdhci_host *host, u32 opcode) 1165 { 1166 struct sdhci_pci_slot *slot = sdhci_priv(host); 1167 struct pci_dev *pdev = slot->chip->pdev; 1168 u8 valid_win = 0; 1169 u8 valid_win_max = 0; 1170 u8 valid_win_end = 0; 1171 u8 ctrl, tune_around; 1172 1173 amd_tuning_reset(host); 1174 1175 for (tune_around = 0; tune_around < 12; tune_around++) { 1176 amd_config_tuning_phase(pdev, tune_around); 1177 1178 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1179 valid_win = 0; 1180 msleep(AMD_MSLEEP_DURATION); 1181 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 1182 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 1183 } else if (++valid_win > valid_win_max) { 1184 valid_win_max = valid_win; 1185 valid_win_end = tune_around; 1186 } 1187 } 1188 1189 if (!valid_win_max) { 1190 dev_err(&pdev->dev, "no tuning point found\n"); 1191 return -EIO; 1192 } 1193 1194 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 1195 1196 amd_enable_manual_tuning(pdev); 1197 1198 host->mmc->retune_period = 0; 1199 1200 return 0; 1201 } 1202 1203 static int amd_probe(struct sdhci_pci_chip *chip) 1204 { 1205 struct pci_dev *smbus_dev; 1206 enum amd_chipset_gen gen; 1207 1208 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1209 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 1210 if (smbus_dev) { 1211 gen = AMD_CHIPSET_BEFORE_ML; 1212 } else { 1213 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1214 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1215 if (smbus_dev) { 1216 if (smbus_dev->revision < 0x51) 1217 gen = AMD_CHIPSET_CZ; 1218 else 1219 gen = AMD_CHIPSET_NL; 1220 } else { 1221 gen = AMD_CHIPSET_UNKNOWN; 1222 } 1223 } 1224 1225 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1226 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1227 1228 return 0; 1229 } 1230 1231 static const struct sdhci_ops amd_sdhci_pci_ops = { 1232 .set_clock = sdhci_set_clock, 1233 .enable_dma = sdhci_pci_enable_dma, 1234 .set_bus_width = sdhci_set_bus_width, 1235 .reset = sdhci_reset, 1236 .set_uhs_signaling = sdhci_set_uhs_signaling, 1237 .platform_execute_tuning = amd_execute_tuning, 1238 }; 1239 1240 static const struct sdhci_pci_fixes sdhci_amd = { 1241 .probe = amd_probe, 1242 .ops = &amd_sdhci_pci_ops, 1243 }; 1244 1245 static const struct pci_device_id pci_ids[] = { 1246 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh), 1247 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc), 1248 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc), 1249 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc), 1250 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712), 1251 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712), 1252 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714), 1253 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714), 1254 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe), 1255 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron), 1256 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron), 1257 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron), 1258 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron), 1259 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt), 1260 SDHCI_PCI_DEVICE(VIA, 95D0, via), 1261 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx), 1262 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk), 1263 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0), 1264 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2), 1265 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2), 1266 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd), 1267 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio), 1268 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio), 1269 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc), 1270 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc), 1271 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio), 1272 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio), 1273 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc), 1274 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio), 1275 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio), 1276 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd), 1277 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc), 1278 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc), 1279 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio), 1280 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd), 1281 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd), 1282 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio), 1283 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio), 1284 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc), 1285 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc), 1286 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc), 1287 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc), 1288 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio), 1289 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd), 1290 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc), 1291 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc), 1292 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio), 1293 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd), 1294 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc), 1295 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio), 1296 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd), 1297 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc), 1298 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio), 1299 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd), 1300 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc), 1301 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio), 1302 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd), 1303 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc), 1304 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd), 1305 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd), 1306 SDHCI_PCI_DEVICE(O2, 8120, o2), 1307 SDHCI_PCI_DEVICE(O2, 8220, o2), 1308 SDHCI_PCI_DEVICE(O2, 8221, o2), 1309 SDHCI_PCI_DEVICE(O2, 8320, o2), 1310 SDHCI_PCI_DEVICE(O2, 8321, o2), 1311 SDHCI_PCI_DEVICE(O2, FUJIN2, o2), 1312 SDHCI_PCI_DEVICE(O2, SDS0, o2), 1313 SDHCI_PCI_DEVICE(O2, SDS1, o2), 1314 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2), 1315 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), 1316 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), 1317 /* Generic SD host controller */ 1318 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, 1319 { /* end: all zeroes */ }, 1320 }; 1321 1322 MODULE_DEVICE_TABLE(pci, pci_ids); 1323 1324 /*****************************************************************************\ 1325 * * 1326 * SDHCI core callbacks * 1327 * * 1328 \*****************************************************************************/ 1329 1330 static int sdhci_pci_enable_dma(struct sdhci_host *host) 1331 { 1332 struct sdhci_pci_slot *slot; 1333 struct pci_dev *pdev; 1334 1335 slot = sdhci_priv(host); 1336 pdev = slot->chip->pdev; 1337 1338 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1339 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1340 (host->flags & SDHCI_USE_SDMA)) { 1341 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1342 "doesn't fully claim to support it.\n"); 1343 } 1344 1345 pci_set_master(pdev); 1346 1347 return 0; 1348 } 1349 1350 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1351 { 1352 struct sdhci_pci_slot *slot = sdhci_priv(host); 1353 int rst_n_gpio = slot->rst_n_gpio; 1354 1355 if (!gpio_is_valid(rst_n_gpio)) 1356 return; 1357 gpio_set_value_cansleep(rst_n_gpio, 0); 1358 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1359 udelay(10); 1360 gpio_set_value_cansleep(rst_n_gpio, 1); 1361 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1362 usleep_range(300, 1000); 1363 } 1364 1365 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1366 { 1367 struct sdhci_pci_slot *slot = sdhci_priv(host); 1368 1369 if (slot->hw_reset) 1370 slot->hw_reset(host); 1371 } 1372 1373 static const struct sdhci_ops sdhci_pci_ops = { 1374 .set_clock = sdhci_set_clock, 1375 .enable_dma = sdhci_pci_enable_dma, 1376 .set_bus_width = sdhci_set_bus_width, 1377 .reset = sdhci_reset, 1378 .set_uhs_signaling = sdhci_set_uhs_signaling, 1379 .hw_reset = sdhci_pci_hw_reset, 1380 }; 1381 1382 /*****************************************************************************\ 1383 * * 1384 * Suspend/resume * 1385 * * 1386 \*****************************************************************************/ 1387 1388 #ifdef CONFIG_PM_SLEEP 1389 static int sdhci_pci_suspend(struct device *dev) 1390 { 1391 struct pci_dev *pdev = to_pci_dev(dev); 1392 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1393 1394 if (!chip) 1395 return 0; 1396 1397 if (chip->fixes && chip->fixes->suspend) 1398 return chip->fixes->suspend(chip); 1399 1400 return sdhci_pci_suspend_host(chip); 1401 } 1402 1403 static int sdhci_pci_resume(struct device *dev) 1404 { 1405 struct pci_dev *pdev = to_pci_dev(dev); 1406 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1407 1408 if (!chip) 1409 return 0; 1410 1411 if (chip->fixes && chip->fixes->resume) 1412 return chip->fixes->resume(chip); 1413 1414 return sdhci_pci_resume_host(chip); 1415 } 1416 #endif 1417 1418 #ifdef CONFIG_PM 1419 static int sdhci_pci_runtime_suspend(struct device *dev) 1420 { 1421 struct pci_dev *pdev = to_pci_dev(dev); 1422 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1423 1424 if (!chip) 1425 return 0; 1426 1427 if (chip->fixes && chip->fixes->runtime_suspend) 1428 return chip->fixes->runtime_suspend(chip); 1429 1430 return sdhci_pci_runtime_suspend_host(chip); 1431 } 1432 1433 static int sdhci_pci_runtime_resume(struct device *dev) 1434 { 1435 struct pci_dev *pdev = to_pci_dev(dev); 1436 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1437 1438 if (!chip) 1439 return 0; 1440 1441 if (chip->fixes && chip->fixes->runtime_resume) 1442 return chip->fixes->runtime_resume(chip); 1443 1444 return sdhci_pci_runtime_resume_host(chip); 1445 } 1446 #endif 1447 1448 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1449 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1450 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1451 sdhci_pci_runtime_resume, NULL) 1452 }; 1453 1454 /*****************************************************************************\ 1455 * * 1456 * Device probing/removal * 1457 * * 1458 \*****************************************************************************/ 1459 1460 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1461 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1462 int slotno) 1463 { 1464 struct sdhci_pci_slot *slot; 1465 struct sdhci_host *host; 1466 int ret, bar = first_bar + slotno; 1467 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 1468 1469 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1470 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1471 return ERR_PTR(-ENODEV); 1472 } 1473 1474 if (pci_resource_len(pdev, bar) < 0x100) { 1475 dev_err(&pdev->dev, "Invalid iomem size. You may " 1476 "experience problems.\n"); 1477 } 1478 1479 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1480 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1481 return ERR_PTR(-ENODEV); 1482 } 1483 1484 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1485 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1486 return ERR_PTR(-ENODEV); 1487 } 1488 1489 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 1490 if (IS_ERR(host)) { 1491 dev_err(&pdev->dev, "cannot allocate host\n"); 1492 return ERR_CAST(host); 1493 } 1494 1495 slot = sdhci_priv(host); 1496 1497 slot->chip = chip; 1498 slot->host = host; 1499 slot->rst_n_gpio = -EINVAL; 1500 slot->cd_gpio = -EINVAL; 1501 slot->cd_idx = -1; 1502 1503 /* Retrieve platform data if there is any */ 1504 if (*sdhci_pci_get_data) 1505 slot->data = sdhci_pci_get_data(pdev, slotno); 1506 1507 if (slot->data) { 1508 if (slot->data->setup) { 1509 ret = slot->data->setup(slot->data); 1510 if (ret) { 1511 dev_err(&pdev->dev, "platform setup failed\n"); 1512 goto free; 1513 } 1514 } 1515 slot->rst_n_gpio = slot->data->rst_n_gpio; 1516 slot->cd_gpio = slot->data->cd_gpio; 1517 } 1518 1519 host->hw_name = "PCI"; 1520 host->ops = chip->fixes && chip->fixes->ops ? 1521 chip->fixes->ops : 1522 &sdhci_pci_ops; 1523 host->quirks = chip->quirks; 1524 host->quirks2 = chip->quirks2; 1525 1526 host->irq = pdev->irq; 1527 1528 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1529 if (ret) { 1530 dev_err(&pdev->dev, "cannot request region\n"); 1531 goto cleanup; 1532 } 1533 1534 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1535 1536 if (chip->fixes && chip->fixes->probe_slot) { 1537 ret = chip->fixes->probe_slot(slot); 1538 if (ret) 1539 goto cleanup; 1540 } 1541 1542 if (gpio_is_valid(slot->rst_n_gpio)) { 1543 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1544 gpio_direction_output(slot->rst_n_gpio, 1); 1545 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1546 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1547 } else { 1548 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1549 slot->rst_n_gpio = -EINVAL; 1550 } 1551 } 1552 1553 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; 1554 host->mmc->slotno = slotno; 1555 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1556 1557 if (slot->cd_idx >= 0) { 1558 ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx, 1559 slot->cd_override_level, 0, NULL); 1560 if (ret == -EPROBE_DEFER) 1561 goto remove; 1562 1563 if (ret) { 1564 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 1565 slot->cd_idx = -1; 1566 } 1567 } 1568 1569 if (chip->fixes && chip->fixes->add_host) 1570 ret = chip->fixes->add_host(slot); 1571 else 1572 ret = sdhci_add_host(host); 1573 if (ret) 1574 goto remove; 1575 1576 sdhci_pci_add_own_cd(slot); 1577 1578 /* 1579 * Check if the chip needs a separate GPIO for card detect to wake up 1580 * from runtime suspend. If it is not there, don't allow runtime PM. 1581 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 1582 */ 1583 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 1584 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 1585 chip->allow_runtime_pm = false; 1586 1587 return slot; 1588 1589 remove: 1590 if (chip->fixes && chip->fixes->remove_slot) 1591 chip->fixes->remove_slot(slot, 0); 1592 1593 cleanup: 1594 if (slot->data && slot->data->cleanup) 1595 slot->data->cleanup(slot->data); 1596 1597 free: 1598 sdhci_free_host(host); 1599 1600 return ERR_PTR(ret); 1601 } 1602 1603 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 1604 { 1605 int dead; 1606 u32 scratch; 1607 1608 sdhci_pci_remove_own_cd(slot); 1609 1610 dead = 0; 1611 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 1612 if (scratch == (u32)-1) 1613 dead = 1; 1614 1615 sdhci_remove_host(slot->host, dead); 1616 1617 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 1618 slot->chip->fixes->remove_slot(slot, dead); 1619 1620 if (slot->data && slot->data->cleanup) 1621 slot->data->cleanup(slot->data); 1622 1623 sdhci_free_host(slot->host); 1624 } 1625 1626 static void sdhci_pci_runtime_pm_allow(struct device *dev) 1627 { 1628 pm_suspend_ignore_children(dev, 1); 1629 pm_runtime_set_autosuspend_delay(dev, 50); 1630 pm_runtime_use_autosuspend(dev); 1631 pm_runtime_allow(dev); 1632 /* Stay active until mmc core scans for a card */ 1633 pm_runtime_put_noidle(dev); 1634 } 1635 1636 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 1637 { 1638 pm_runtime_forbid(dev); 1639 pm_runtime_get_noresume(dev); 1640 } 1641 1642 static int sdhci_pci_probe(struct pci_dev *pdev, 1643 const struct pci_device_id *ent) 1644 { 1645 struct sdhci_pci_chip *chip; 1646 struct sdhci_pci_slot *slot; 1647 1648 u8 slots, first_bar; 1649 int ret, i; 1650 1651 BUG_ON(pdev == NULL); 1652 BUG_ON(ent == NULL); 1653 1654 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 1655 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 1656 1657 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 1658 if (ret) 1659 return ret; 1660 1661 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 1662 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 1663 if (slots == 0) 1664 return -ENODEV; 1665 1666 BUG_ON(slots > MAX_SLOTS); 1667 1668 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 1669 if (ret) 1670 return ret; 1671 1672 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 1673 1674 if (first_bar > 5) { 1675 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 1676 return -ENODEV; 1677 } 1678 1679 ret = pcim_enable_device(pdev); 1680 if (ret) 1681 return ret; 1682 1683 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 1684 if (!chip) 1685 return -ENOMEM; 1686 1687 chip->pdev = pdev; 1688 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 1689 if (chip->fixes) { 1690 chip->quirks = chip->fixes->quirks; 1691 chip->quirks2 = chip->fixes->quirks2; 1692 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 1693 } 1694 chip->num_slots = slots; 1695 chip->pm_retune = true; 1696 chip->rpm_retune = true; 1697 1698 pci_set_drvdata(pdev, chip); 1699 1700 if (chip->fixes && chip->fixes->probe) { 1701 ret = chip->fixes->probe(chip); 1702 if (ret) 1703 return ret; 1704 } 1705 1706 slots = chip->num_slots; /* Quirk may have changed this */ 1707 1708 for (i = 0; i < slots; i++) { 1709 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 1710 if (IS_ERR(slot)) { 1711 for (i--; i >= 0; i--) 1712 sdhci_pci_remove_slot(chip->slots[i]); 1713 return PTR_ERR(slot); 1714 } 1715 1716 chip->slots[i] = slot; 1717 } 1718 1719 if (chip->allow_runtime_pm) 1720 sdhci_pci_runtime_pm_allow(&pdev->dev); 1721 1722 return 0; 1723 } 1724 1725 static void sdhci_pci_remove(struct pci_dev *pdev) 1726 { 1727 int i; 1728 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1729 1730 if (chip->allow_runtime_pm) 1731 sdhci_pci_runtime_pm_forbid(&pdev->dev); 1732 1733 for (i = 0; i < chip->num_slots; i++) 1734 sdhci_pci_remove_slot(chip->slots[i]); 1735 } 1736 1737 static struct pci_driver sdhci_driver = { 1738 .name = "sdhci-pci", 1739 .id_table = pci_ids, 1740 .probe = sdhci_pci_probe, 1741 .remove = sdhci_pci_remove, 1742 .driver = { 1743 .pm = &sdhci_pci_pm_ops 1744 }, 1745 }; 1746 1747 module_pci_driver(sdhci_driver); 1748 1749 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 1750 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 1751 MODULE_LICENSE("GPL"); 1752