1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 2 * 3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 * 10 * Thanks to the following companies for their support: 11 * 12 * - JMicron (hardware and technical support) 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/highmem.h> 17 #include <linux/module.h> 18 #include <linux/pci.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/slab.h> 21 #include <linux/device.h> 22 #include <linux/mmc/host.h> 23 #include <linux/mmc/mmc.h> 24 #include <linux/scatterlist.h> 25 #include <linux/io.h> 26 #include <linux/gpio.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/mmc/slot-gpio.h> 29 #include <linux/mmc/sdhci-pci-data.h> 30 #include <linux/acpi.h> 31 32 #include "sdhci.h" 33 #include "sdhci-pci.h" 34 #include "sdhci-pci-o2micro.h" 35 36 static int sdhci_pci_enable_dma(struct sdhci_host *host); 37 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width); 38 static void sdhci_pci_hw_reset(struct sdhci_host *host); 39 static int sdhci_pci_select_drive_strength(struct sdhci_host *host, 40 struct mmc_card *card, 41 unsigned int max_dtr, int host_drv, 42 int card_drv, int *drv_type); 43 44 /*****************************************************************************\ 45 * * 46 * Hardware specific quirk handling * 47 * * 48 \*****************************************************************************/ 49 50 static int ricoh_probe(struct sdhci_pci_chip *chip) 51 { 52 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 53 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 54 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 55 return 0; 56 } 57 58 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 59 { 60 slot->host->caps = 61 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 62 & SDHCI_TIMEOUT_CLK_MASK) | 63 64 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 65 & SDHCI_CLOCK_BASE_MASK) | 66 67 SDHCI_TIMEOUT_CLK_UNIT | 68 SDHCI_CAN_VDD_330 | 69 SDHCI_CAN_DO_HISPD | 70 SDHCI_CAN_DO_SDMA; 71 return 0; 72 } 73 74 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 75 { 76 /* Apply a delay to allow controller to settle */ 77 /* Otherwise it becomes confused if card state changed 78 during suspend */ 79 msleep(500); 80 return 0; 81 } 82 83 static const struct sdhci_pci_fixes sdhci_ricoh = { 84 .probe = ricoh_probe, 85 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 86 SDHCI_QUIRK_FORCE_DMA | 87 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 88 }; 89 90 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 91 .probe_slot = ricoh_mmc_probe_slot, 92 .resume = ricoh_mmc_resume, 93 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 94 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 95 SDHCI_QUIRK_NO_CARD_NO_RESET | 96 SDHCI_QUIRK_MISSING_CAPS 97 }; 98 99 static const struct sdhci_pci_fixes sdhci_ene_712 = { 100 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 101 SDHCI_QUIRK_BROKEN_DMA, 102 }; 103 104 static const struct sdhci_pci_fixes sdhci_ene_714 = { 105 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 106 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 107 SDHCI_QUIRK_BROKEN_DMA, 108 }; 109 110 static const struct sdhci_pci_fixes sdhci_cafe = { 111 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 112 SDHCI_QUIRK_NO_BUSY_IRQ | 113 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 114 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 115 }; 116 117 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 118 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 119 }; 120 121 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 122 { 123 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 124 return 0; 125 } 126 127 /* 128 * ADMA operation is disabled for Moorestown platform due to 129 * hardware bugs. 130 */ 131 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 132 { 133 /* 134 * slots number is fixed here for MRST as SDIO3/5 are never used and 135 * have hardware bugs. 136 */ 137 chip->num_slots = 1; 138 return 0; 139 } 140 141 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 142 { 143 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 144 return 0; 145 } 146 147 #ifdef CONFIG_PM 148 149 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 150 { 151 struct sdhci_pci_slot *slot = dev_id; 152 struct sdhci_host *host = slot->host; 153 154 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 155 return IRQ_HANDLED; 156 } 157 158 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 159 { 160 int err, irq, gpio = slot->cd_gpio; 161 162 slot->cd_gpio = -EINVAL; 163 slot->cd_irq = -EINVAL; 164 165 if (!gpio_is_valid(gpio)) 166 return; 167 168 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 169 if (err < 0) 170 goto out; 171 172 err = gpio_direction_input(gpio); 173 if (err < 0) 174 goto out_free; 175 176 irq = gpio_to_irq(gpio); 177 if (irq < 0) 178 goto out_free; 179 180 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 181 IRQF_TRIGGER_FALLING, "sd_cd", slot); 182 if (err) 183 goto out_free; 184 185 slot->cd_gpio = gpio; 186 slot->cd_irq = irq; 187 188 return; 189 190 out_free: 191 devm_gpio_free(&slot->chip->pdev->dev, gpio); 192 out: 193 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 194 } 195 196 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 197 { 198 if (slot->cd_irq >= 0) 199 free_irq(slot->cd_irq, slot); 200 } 201 202 #else 203 204 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 205 { 206 } 207 208 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 209 { 210 } 211 212 #endif 213 214 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 215 { 216 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 217 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC | 218 MMC_CAP2_HC_ERASE_SZ; 219 return 0; 220 } 221 222 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 223 { 224 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 225 return 0; 226 } 227 228 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 229 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 230 .probe_slot = mrst_hc_probe_slot, 231 }; 232 233 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 234 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 235 .probe = mrst_hc_probe, 236 }; 237 238 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 239 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 240 .allow_runtime_pm = true, 241 .own_cd_for_runtime_pm = true, 242 }; 243 244 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 245 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 246 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 247 .allow_runtime_pm = true, 248 .probe_slot = mfd_sdio_probe_slot, 249 }; 250 251 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 252 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 253 .allow_runtime_pm = true, 254 .probe_slot = mfd_emmc_probe_slot, 255 }; 256 257 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 258 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 259 .probe_slot = pch_hc_probe_slot, 260 }; 261 262 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 263 { 264 u8 reg; 265 266 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 267 reg |= 0x10; 268 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 269 /* For eMMC, minimum is 1us but give it 9us for good measure */ 270 udelay(9); 271 reg &= ~0x10; 272 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 273 /* For eMMC, minimum is 200us but give it 300us for good measure */ 274 usleep_range(300, 1000); 275 } 276 277 static int spt_select_drive_strength(struct sdhci_host *host, 278 struct mmc_card *card, 279 unsigned int max_dtr, 280 int host_drv, int card_drv, int *drv_type) 281 { 282 int drive_strength; 283 284 if (sdhci_pci_spt_drive_strength > 0) 285 drive_strength = sdhci_pci_spt_drive_strength & 0xf; 286 else 287 drive_strength = 0; /* Default 50-ohm */ 288 289 if ((mmc_driver_type_mask(drive_strength) & card_drv) == 0) 290 drive_strength = 0; /* Default 50-ohm */ 291 292 return drive_strength; 293 } 294 295 /* Try to read the drive strength from the card */ 296 static void spt_read_drive_strength(struct sdhci_host *host) 297 { 298 u32 val, i, t; 299 u16 m; 300 301 if (sdhci_pci_spt_drive_strength) 302 return; 303 304 sdhci_pci_spt_drive_strength = -1; 305 306 m = sdhci_readw(host, SDHCI_HOST_CONTROL2) & 0x7; 307 if (m != 3 && m != 5) 308 return; 309 val = sdhci_readl(host, SDHCI_PRESENT_STATE); 310 if (val & 0x3) 311 return; 312 sdhci_writel(host, 0x007f0023, SDHCI_INT_ENABLE); 313 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 314 sdhci_writew(host, 0x10, SDHCI_TRANSFER_MODE); 315 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 316 sdhci_writew(host, 512, SDHCI_BLOCK_SIZE); 317 sdhci_writew(host, 1, SDHCI_BLOCK_COUNT); 318 sdhci_writel(host, 0, SDHCI_ARGUMENT); 319 sdhci_writew(host, 0x83b, SDHCI_COMMAND); 320 for (i = 0; i < 1000; i++) { 321 val = sdhci_readl(host, SDHCI_INT_STATUS); 322 if (val & 0xffff8000) 323 return; 324 if (val & 0x20) 325 break; 326 udelay(1); 327 } 328 val = sdhci_readl(host, SDHCI_PRESENT_STATE); 329 if (!(val & 0x800)) 330 return; 331 for (i = 0; i < 47; i++) 332 val = sdhci_readl(host, SDHCI_BUFFER); 333 t = val & 0xf00; 334 if (t != 0x200 && t != 0x300) 335 return; 336 337 sdhci_pci_spt_drive_strength = 0x10 | ((val >> 12) & 0xf); 338 } 339 340 static int bxt_get_cd(struct mmc_host *mmc) 341 { 342 int gpio_cd = mmc_gpio_get_cd(mmc); 343 struct sdhci_host *host = mmc_priv(mmc); 344 unsigned long flags; 345 int ret = 0; 346 347 if (!gpio_cd) 348 return 0; 349 350 spin_lock_irqsave(&host->lock, flags); 351 352 if (host->flags & SDHCI_DEVICE_DEAD) 353 goto out; 354 355 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 356 out: 357 spin_unlock_irqrestore(&host->lock, flags); 358 359 return ret; 360 } 361 362 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 363 { 364 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 365 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 366 MMC_CAP_CMD_DURING_TFR | 367 MMC_CAP_WAIT_WHILE_BUSY; 368 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ; 369 slot->hw_reset = sdhci_pci_int_hw_reset; 370 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 371 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 372 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_SPT_EMMC) { 373 spt_read_drive_strength(slot->host); 374 slot->select_drive_strength = spt_select_drive_strength; 375 } 376 return 0; 377 } 378 379 #ifdef CONFIG_ACPI 380 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 381 { 382 acpi_status status; 383 unsigned long long max_freq; 384 385 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 386 "MXFQ", NULL, &max_freq); 387 if (ACPI_FAILURE(status)) { 388 dev_err(&slot->chip->pdev->dev, 389 "MXFQ not found in acpi table\n"); 390 return -EINVAL; 391 } 392 393 slot->host->mmc->f_max = max_freq * 1000000; 394 395 return 0; 396 } 397 #else 398 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 399 { 400 return 0; 401 } 402 #endif 403 404 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 405 { 406 int err; 407 408 err = ni_set_max_freq(slot); 409 if (err) 410 return err; 411 412 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 413 MMC_CAP_WAIT_WHILE_BUSY; 414 return 0; 415 } 416 417 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 418 { 419 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 420 MMC_CAP_WAIT_WHILE_BUSY; 421 return 0; 422 } 423 424 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 425 { 426 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 427 slot->cd_con_id = NULL; 428 slot->cd_idx = 0; 429 slot->cd_override_level = true; 430 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 431 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 432 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 433 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) { 434 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 435 slot->host->mmc->caps |= MMC_CAP_AGGRESSIVE_PM; 436 } 437 438 return 0; 439 } 440 441 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 442 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 443 444 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 445 unsigned short vdd) 446 { 447 int cntr; 448 u8 reg; 449 450 sdhci_set_power(host, mode, vdd); 451 452 if (mode == MMC_POWER_OFF) 453 return; 454 455 /* 456 * Bus power might not enable after D3 -> D0 transition due to the 457 * present state not yet having propagated. Retry for up to 2ms. 458 */ 459 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 460 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 461 if (reg & SDHCI_POWER_ON) 462 break; 463 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 464 reg |= SDHCI_POWER_ON; 465 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 466 } 467 } 468 469 static const struct sdhci_ops sdhci_intel_byt_ops = { 470 .set_clock = sdhci_set_clock, 471 .set_power = sdhci_intel_set_power, 472 .enable_dma = sdhci_pci_enable_dma, 473 .set_bus_width = sdhci_pci_set_bus_width, 474 .reset = sdhci_reset, 475 .set_uhs_signaling = sdhci_set_uhs_signaling, 476 .hw_reset = sdhci_pci_hw_reset, 477 .select_drive_strength = sdhci_pci_select_drive_strength, 478 }; 479 480 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 481 .allow_runtime_pm = true, 482 .probe_slot = byt_emmc_probe_slot, 483 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 484 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 485 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 486 SDHCI_QUIRK2_STOP_WITH_TC, 487 .ops = &sdhci_intel_byt_ops, 488 }; 489 490 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 491 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 492 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 493 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 494 .allow_runtime_pm = true, 495 .probe_slot = ni_byt_sdio_probe_slot, 496 .ops = &sdhci_intel_byt_ops, 497 }; 498 499 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 500 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 501 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 502 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 503 .allow_runtime_pm = true, 504 .probe_slot = byt_sdio_probe_slot, 505 .ops = &sdhci_intel_byt_ops, 506 }; 507 508 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 509 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 510 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 511 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 512 SDHCI_QUIRK2_STOP_WITH_TC, 513 .allow_runtime_pm = true, 514 .own_cd_for_runtime_pm = true, 515 .probe_slot = byt_sd_probe_slot, 516 .ops = &sdhci_intel_byt_ops, 517 }; 518 519 /* Define Host controllers for Intel Merrifield platform */ 520 #define INTEL_MRFLD_EMMC_0 0 521 #define INTEL_MRFLD_EMMC_1 1 522 #define INTEL_MRFLD_SD 2 523 #define INTEL_MRFLD_SDIO 3 524 525 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 526 { 527 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 528 529 switch (func) { 530 case INTEL_MRFLD_EMMC_0: 531 case INTEL_MRFLD_EMMC_1: 532 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 533 MMC_CAP_8_BIT_DATA | 534 MMC_CAP_1_8V_DDR; 535 break; 536 case INTEL_MRFLD_SD: 537 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 538 break; 539 case INTEL_MRFLD_SDIO: 540 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 541 MMC_CAP_POWER_OFF_CARD; 542 break; 543 default: 544 return -ENODEV; 545 } 546 return 0; 547 } 548 549 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 550 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 551 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 552 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 553 .allow_runtime_pm = true, 554 .probe_slot = intel_mrfld_mmc_probe_slot, 555 }; 556 557 /* O2Micro extra registers */ 558 #define O2_SD_LOCK_WP 0xD3 559 #define O2_SD_MULTI_VCC3V 0xEE 560 #define O2_SD_CLKREQ 0xEC 561 #define O2_SD_CAPS 0xE0 562 #define O2_SD_ADMA1 0xE2 563 #define O2_SD_ADMA2 0xE7 564 #define O2_SD_INF_MOD 0xF1 565 566 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 567 { 568 u8 scratch; 569 int ret; 570 571 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 572 if (ret) 573 return ret; 574 575 /* 576 * Turn PMOS on [bit 0], set over current detection to 2.4 V 577 * [bit 1:2] and enable over current debouncing [bit 6]. 578 */ 579 if (on) 580 scratch |= 0x47; 581 else 582 scratch &= ~0x47; 583 584 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 585 } 586 587 static int jmicron_probe(struct sdhci_pci_chip *chip) 588 { 589 int ret; 590 u16 mmcdev = 0; 591 592 if (chip->pdev->revision == 0) { 593 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 594 SDHCI_QUIRK_32BIT_DMA_SIZE | 595 SDHCI_QUIRK_32BIT_ADMA_SIZE | 596 SDHCI_QUIRK_RESET_AFTER_REQUEST | 597 SDHCI_QUIRK_BROKEN_SMALL_PIO; 598 } 599 600 /* 601 * JMicron chips can have two interfaces to the same hardware 602 * in order to work around limitations in Microsoft's driver. 603 * We need to make sure we only bind to one of them. 604 * 605 * This code assumes two things: 606 * 607 * 1. The PCI code adds subfunctions in order. 608 * 609 * 2. The MMC interface has a lower subfunction number 610 * than the SD interface. 611 */ 612 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 613 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 614 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 615 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 616 617 if (mmcdev) { 618 struct pci_dev *sd_dev; 619 620 sd_dev = NULL; 621 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 622 mmcdev, sd_dev)) != NULL) { 623 if ((PCI_SLOT(chip->pdev->devfn) == 624 PCI_SLOT(sd_dev->devfn)) && 625 (chip->pdev->bus == sd_dev->bus)) 626 break; 627 } 628 629 if (sd_dev) { 630 pci_dev_put(sd_dev); 631 dev_info(&chip->pdev->dev, "Refusing to bind to " 632 "secondary interface.\n"); 633 return -ENODEV; 634 } 635 } 636 637 /* 638 * JMicron chips need a bit of a nudge to enable the power 639 * output pins. 640 */ 641 ret = jmicron_pmos(chip, 1); 642 if (ret) { 643 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 644 return ret; 645 } 646 647 /* quirk for unsable RO-detection on JM388 chips */ 648 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 649 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 650 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 651 652 return 0; 653 } 654 655 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 656 { 657 u8 scratch; 658 659 scratch = readb(host->ioaddr + 0xC0); 660 661 if (on) 662 scratch |= 0x01; 663 else 664 scratch &= ~0x01; 665 666 writeb(scratch, host->ioaddr + 0xC0); 667 } 668 669 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 670 { 671 if (slot->chip->pdev->revision == 0) { 672 u16 version; 673 674 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 675 version = (version & SDHCI_VENDOR_VER_MASK) >> 676 SDHCI_VENDOR_VER_SHIFT; 677 678 /* 679 * Older versions of the chip have lots of nasty glitches 680 * in the ADMA engine. It's best just to avoid it 681 * completely. 682 */ 683 if (version < 0xAC) 684 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 685 } 686 687 /* JM388 MMC doesn't support 1.8V while SD supports it */ 688 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 689 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 690 MMC_VDD_29_30 | MMC_VDD_30_31 | 691 MMC_VDD_165_195; /* allow 1.8V */ 692 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 693 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 694 } 695 696 /* 697 * The secondary interface requires a bit set to get the 698 * interrupts. 699 */ 700 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 701 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 702 jmicron_enable_mmc(slot->host, 1); 703 704 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 705 706 return 0; 707 } 708 709 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 710 { 711 if (dead) 712 return; 713 714 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 715 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 716 jmicron_enable_mmc(slot->host, 0); 717 } 718 719 static int jmicron_suspend(struct sdhci_pci_chip *chip) 720 { 721 int i; 722 723 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 724 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 725 for (i = 0; i < chip->num_slots; i++) 726 jmicron_enable_mmc(chip->slots[i]->host, 0); 727 } 728 729 return 0; 730 } 731 732 static int jmicron_resume(struct sdhci_pci_chip *chip) 733 { 734 int ret, i; 735 736 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 737 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 738 for (i = 0; i < chip->num_slots; i++) 739 jmicron_enable_mmc(chip->slots[i]->host, 1); 740 } 741 742 ret = jmicron_pmos(chip, 1); 743 if (ret) { 744 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 745 return ret; 746 } 747 748 return 0; 749 } 750 751 static const struct sdhci_pci_fixes sdhci_o2 = { 752 .probe = sdhci_pci_o2_probe, 753 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 754 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 755 .probe_slot = sdhci_pci_o2_probe_slot, 756 .resume = sdhci_pci_o2_resume, 757 }; 758 759 static const struct sdhci_pci_fixes sdhci_jmicron = { 760 .probe = jmicron_probe, 761 762 .probe_slot = jmicron_probe_slot, 763 .remove_slot = jmicron_remove_slot, 764 765 .suspend = jmicron_suspend, 766 .resume = jmicron_resume, 767 }; 768 769 /* SysKonnect CardBus2SDIO extra registers */ 770 #define SYSKT_CTRL 0x200 771 #define SYSKT_RDFIFO_STAT 0x204 772 #define SYSKT_WRFIFO_STAT 0x208 773 #define SYSKT_POWER_DATA 0x20c 774 #define SYSKT_POWER_330 0xef 775 #define SYSKT_POWER_300 0xf8 776 #define SYSKT_POWER_184 0xcc 777 #define SYSKT_POWER_CMD 0x20d 778 #define SYSKT_POWER_START (1 << 7) 779 #define SYSKT_POWER_STATUS 0x20e 780 #define SYSKT_POWER_STATUS_OK (1 << 0) 781 #define SYSKT_BOARD_REV 0x210 782 #define SYSKT_CHIP_REV 0x211 783 #define SYSKT_CONF_DATA 0x212 784 #define SYSKT_CONF_DATA_1V8 (1 << 2) 785 #define SYSKT_CONF_DATA_2V5 (1 << 1) 786 #define SYSKT_CONF_DATA_3V3 (1 << 0) 787 788 static int syskt_probe(struct sdhci_pci_chip *chip) 789 { 790 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 791 chip->pdev->class &= ~0x0000FF; 792 chip->pdev->class |= PCI_SDHCI_IFDMA; 793 } 794 return 0; 795 } 796 797 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 798 { 799 int tm, ps; 800 801 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 802 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 803 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 804 "board rev %d.%d, chip rev %d.%d\n", 805 board_rev >> 4, board_rev & 0xf, 806 chip_rev >> 4, chip_rev & 0xf); 807 if (chip_rev >= 0x20) 808 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 809 810 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 811 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 812 udelay(50); 813 tm = 10; /* Wait max 1 ms */ 814 do { 815 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 816 if (ps & SYSKT_POWER_STATUS_OK) 817 break; 818 udelay(100); 819 } while (--tm); 820 if (!tm) { 821 dev_err(&slot->chip->pdev->dev, 822 "power regulator never stabilized"); 823 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 824 return -ENODEV; 825 } 826 827 return 0; 828 } 829 830 static const struct sdhci_pci_fixes sdhci_syskt = { 831 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 832 .probe = syskt_probe, 833 .probe_slot = syskt_probe_slot, 834 }; 835 836 static int via_probe(struct sdhci_pci_chip *chip) 837 { 838 if (chip->pdev->revision == 0x10) 839 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 840 841 return 0; 842 } 843 844 static const struct sdhci_pci_fixes sdhci_via = { 845 .probe = via_probe, 846 }; 847 848 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 849 { 850 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 851 return 0; 852 } 853 854 static const struct sdhci_pci_fixes sdhci_rtsx = { 855 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 856 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 857 SDHCI_QUIRK2_BROKEN_DDR50, 858 .probe_slot = rtsx_probe_slot, 859 }; 860 861 /*AMD chipset generation*/ 862 enum amd_chipset_gen { 863 AMD_CHIPSET_BEFORE_ML, 864 AMD_CHIPSET_CZ, 865 AMD_CHIPSET_NL, 866 AMD_CHIPSET_UNKNOWN, 867 }; 868 869 static int amd_probe(struct sdhci_pci_chip *chip) 870 { 871 struct pci_dev *smbus_dev; 872 enum amd_chipset_gen gen; 873 874 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 875 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 876 if (smbus_dev) { 877 gen = AMD_CHIPSET_BEFORE_ML; 878 } else { 879 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 880 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 881 if (smbus_dev) { 882 if (smbus_dev->revision < 0x51) 883 gen = AMD_CHIPSET_CZ; 884 else 885 gen = AMD_CHIPSET_NL; 886 } else { 887 gen = AMD_CHIPSET_UNKNOWN; 888 } 889 } 890 891 if ((gen == AMD_CHIPSET_BEFORE_ML) || (gen == AMD_CHIPSET_CZ)) { 892 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 893 chip->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 894 } 895 896 return 0; 897 } 898 899 static const struct sdhci_pci_fixes sdhci_amd = { 900 .probe = amd_probe, 901 }; 902 903 static const struct pci_device_id pci_ids[] = { 904 { 905 .vendor = PCI_VENDOR_ID_RICOH, 906 .device = PCI_DEVICE_ID_RICOH_R5C822, 907 .subvendor = PCI_ANY_ID, 908 .subdevice = PCI_ANY_ID, 909 .driver_data = (kernel_ulong_t)&sdhci_ricoh, 910 }, 911 912 { 913 .vendor = PCI_VENDOR_ID_RICOH, 914 .device = 0x843, 915 .subvendor = PCI_ANY_ID, 916 .subdevice = PCI_ANY_ID, 917 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 918 }, 919 920 { 921 .vendor = PCI_VENDOR_ID_RICOH, 922 .device = 0xe822, 923 .subvendor = PCI_ANY_ID, 924 .subdevice = PCI_ANY_ID, 925 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 926 }, 927 928 { 929 .vendor = PCI_VENDOR_ID_RICOH, 930 .device = 0xe823, 931 .subvendor = PCI_ANY_ID, 932 .subdevice = PCI_ANY_ID, 933 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 934 }, 935 936 { 937 .vendor = PCI_VENDOR_ID_ENE, 938 .device = PCI_DEVICE_ID_ENE_CB712_SD, 939 .subvendor = PCI_ANY_ID, 940 .subdevice = PCI_ANY_ID, 941 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 942 }, 943 944 { 945 .vendor = PCI_VENDOR_ID_ENE, 946 .device = PCI_DEVICE_ID_ENE_CB712_SD_2, 947 .subvendor = PCI_ANY_ID, 948 .subdevice = PCI_ANY_ID, 949 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 950 }, 951 952 { 953 .vendor = PCI_VENDOR_ID_ENE, 954 .device = PCI_DEVICE_ID_ENE_CB714_SD, 955 .subvendor = PCI_ANY_ID, 956 .subdevice = PCI_ANY_ID, 957 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 958 }, 959 960 { 961 .vendor = PCI_VENDOR_ID_ENE, 962 .device = PCI_DEVICE_ID_ENE_CB714_SD_2, 963 .subvendor = PCI_ANY_ID, 964 .subdevice = PCI_ANY_ID, 965 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 966 }, 967 968 { 969 .vendor = PCI_VENDOR_ID_MARVELL, 970 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD, 971 .subvendor = PCI_ANY_ID, 972 .subdevice = PCI_ANY_ID, 973 .driver_data = (kernel_ulong_t)&sdhci_cafe, 974 }, 975 976 { 977 .vendor = PCI_VENDOR_ID_JMICRON, 978 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD, 979 .subvendor = PCI_ANY_ID, 980 .subdevice = PCI_ANY_ID, 981 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 982 }, 983 984 { 985 .vendor = PCI_VENDOR_ID_JMICRON, 986 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC, 987 .subvendor = PCI_ANY_ID, 988 .subdevice = PCI_ANY_ID, 989 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 990 }, 991 992 { 993 .vendor = PCI_VENDOR_ID_JMICRON, 994 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD, 995 .subvendor = PCI_ANY_ID, 996 .subdevice = PCI_ANY_ID, 997 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 998 }, 999 1000 { 1001 .vendor = PCI_VENDOR_ID_JMICRON, 1002 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD, 1003 .subvendor = PCI_ANY_ID, 1004 .subdevice = PCI_ANY_ID, 1005 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1006 }, 1007 1008 { 1009 .vendor = PCI_VENDOR_ID_SYSKONNECT, 1010 .device = 0x8000, 1011 .subvendor = PCI_ANY_ID, 1012 .subdevice = PCI_ANY_ID, 1013 .driver_data = (kernel_ulong_t)&sdhci_syskt, 1014 }, 1015 1016 { 1017 .vendor = PCI_VENDOR_ID_VIA, 1018 .device = 0x95d0, 1019 .subvendor = PCI_ANY_ID, 1020 .subdevice = PCI_ANY_ID, 1021 .driver_data = (kernel_ulong_t)&sdhci_via, 1022 }, 1023 1024 { 1025 .vendor = PCI_VENDOR_ID_REALTEK, 1026 .device = 0x5250, 1027 .subvendor = PCI_ANY_ID, 1028 .subdevice = PCI_ANY_ID, 1029 .driver_data = (kernel_ulong_t)&sdhci_rtsx, 1030 }, 1031 1032 { 1033 .vendor = PCI_VENDOR_ID_INTEL, 1034 .device = PCI_DEVICE_ID_INTEL_QRK_SD, 1035 .subvendor = PCI_ANY_ID, 1036 .subdevice = PCI_ANY_ID, 1037 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk, 1038 }, 1039 1040 { 1041 .vendor = PCI_VENDOR_ID_INTEL, 1042 .device = PCI_DEVICE_ID_INTEL_MRST_SD0, 1043 .subvendor = PCI_ANY_ID, 1044 .subdevice = PCI_ANY_ID, 1045 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0, 1046 }, 1047 1048 { 1049 .vendor = PCI_VENDOR_ID_INTEL, 1050 .device = PCI_DEVICE_ID_INTEL_MRST_SD1, 1051 .subvendor = PCI_ANY_ID, 1052 .subdevice = PCI_ANY_ID, 1053 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 1054 }, 1055 1056 { 1057 .vendor = PCI_VENDOR_ID_INTEL, 1058 .device = PCI_DEVICE_ID_INTEL_MRST_SD2, 1059 .subvendor = PCI_ANY_ID, 1060 .subdevice = PCI_ANY_ID, 1061 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 1062 }, 1063 1064 { 1065 .vendor = PCI_VENDOR_ID_INTEL, 1066 .device = PCI_DEVICE_ID_INTEL_MFD_SD, 1067 .subvendor = PCI_ANY_ID, 1068 .subdevice = PCI_ANY_ID, 1069 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1070 }, 1071 1072 { 1073 .vendor = PCI_VENDOR_ID_INTEL, 1074 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1, 1075 .subvendor = PCI_ANY_ID, 1076 .subdevice = PCI_ANY_ID, 1077 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1078 }, 1079 1080 { 1081 .vendor = PCI_VENDOR_ID_INTEL, 1082 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2, 1083 .subvendor = PCI_ANY_ID, 1084 .subdevice = PCI_ANY_ID, 1085 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1086 }, 1087 1088 { 1089 .vendor = PCI_VENDOR_ID_INTEL, 1090 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0, 1091 .subvendor = PCI_ANY_ID, 1092 .subdevice = PCI_ANY_ID, 1093 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1094 }, 1095 1096 { 1097 .vendor = PCI_VENDOR_ID_INTEL, 1098 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1, 1099 .subvendor = PCI_ANY_ID, 1100 .subdevice = PCI_ANY_ID, 1101 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1102 }, 1103 1104 { 1105 .vendor = PCI_VENDOR_ID_INTEL, 1106 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0, 1107 .subvendor = PCI_ANY_ID, 1108 .subdevice = PCI_ANY_ID, 1109 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1110 }, 1111 1112 { 1113 .vendor = PCI_VENDOR_ID_INTEL, 1114 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1, 1115 .subvendor = PCI_ANY_ID, 1116 .subdevice = PCI_ANY_ID, 1117 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1118 }, 1119 1120 { 1121 .vendor = PCI_VENDOR_ID_INTEL, 1122 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC, 1123 .subvendor = PCI_ANY_ID, 1124 .subdevice = PCI_ANY_ID, 1125 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1126 }, 1127 1128 { 1129 .vendor = PCI_VENDOR_ID_INTEL, 1130 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, 1131 .subvendor = PCI_VENDOR_ID_NI, 1132 .subdevice = 0x7884, 1133 .driver_data = (kernel_ulong_t)&sdhci_ni_byt_sdio, 1134 }, 1135 1136 { 1137 .vendor = PCI_VENDOR_ID_INTEL, 1138 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, 1139 .subvendor = PCI_ANY_ID, 1140 .subdevice = PCI_ANY_ID, 1141 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1142 }, 1143 1144 { 1145 .vendor = PCI_VENDOR_ID_INTEL, 1146 .device = PCI_DEVICE_ID_INTEL_BYT_SD, 1147 .subvendor = PCI_ANY_ID, 1148 .subdevice = PCI_ANY_ID, 1149 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1150 }, 1151 1152 { 1153 .vendor = PCI_VENDOR_ID_INTEL, 1154 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2, 1155 .subvendor = PCI_ANY_ID, 1156 .subdevice = PCI_ANY_ID, 1157 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1158 }, 1159 1160 { 1161 .vendor = PCI_VENDOR_ID_INTEL, 1162 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC, 1163 .subvendor = PCI_ANY_ID, 1164 .subdevice = PCI_ANY_ID, 1165 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1166 }, 1167 1168 { 1169 .vendor = PCI_VENDOR_ID_INTEL, 1170 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO, 1171 .subvendor = PCI_ANY_ID, 1172 .subdevice = PCI_ANY_ID, 1173 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1174 }, 1175 1176 { 1177 .vendor = PCI_VENDOR_ID_INTEL, 1178 .device = PCI_DEVICE_ID_INTEL_BSW_SD, 1179 .subvendor = PCI_ANY_ID, 1180 .subdevice = PCI_ANY_ID, 1181 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1182 }, 1183 1184 { 1185 .vendor = PCI_VENDOR_ID_INTEL, 1186 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0, 1187 .subvendor = PCI_ANY_ID, 1188 .subdevice = PCI_ANY_ID, 1189 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1190 }, 1191 1192 { 1193 .vendor = PCI_VENDOR_ID_INTEL, 1194 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1, 1195 .subvendor = PCI_ANY_ID, 1196 .subdevice = PCI_ANY_ID, 1197 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1198 }, 1199 1200 { 1201 .vendor = PCI_VENDOR_ID_INTEL, 1202 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2, 1203 .subvendor = PCI_ANY_ID, 1204 .subdevice = PCI_ANY_ID, 1205 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1206 }, 1207 1208 { 1209 .vendor = PCI_VENDOR_ID_INTEL, 1210 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0, 1211 .subvendor = PCI_ANY_ID, 1212 .subdevice = PCI_ANY_ID, 1213 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1214 }, 1215 1216 { 1217 .vendor = PCI_VENDOR_ID_INTEL, 1218 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1, 1219 .subvendor = PCI_ANY_ID, 1220 .subdevice = PCI_ANY_ID, 1221 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1222 }, 1223 1224 { 1225 .vendor = PCI_VENDOR_ID_INTEL, 1226 .device = PCI_DEVICE_ID_INTEL_MRFLD_MMC, 1227 .subvendor = PCI_ANY_ID, 1228 .subdevice = PCI_ANY_ID, 1229 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfld_mmc, 1230 }, 1231 1232 { 1233 .vendor = PCI_VENDOR_ID_INTEL, 1234 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC, 1235 .subvendor = PCI_ANY_ID, 1236 .subdevice = PCI_ANY_ID, 1237 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1238 }, 1239 1240 { 1241 .vendor = PCI_VENDOR_ID_INTEL, 1242 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO, 1243 .subvendor = PCI_ANY_ID, 1244 .subdevice = PCI_ANY_ID, 1245 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1246 }, 1247 1248 { 1249 .vendor = PCI_VENDOR_ID_INTEL, 1250 .device = PCI_DEVICE_ID_INTEL_SPT_SD, 1251 .subvendor = PCI_ANY_ID, 1252 .subdevice = PCI_ANY_ID, 1253 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1254 }, 1255 1256 { 1257 .vendor = PCI_VENDOR_ID_INTEL, 1258 .device = PCI_DEVICE_ID_INTEL_DNV_EMMC, 1259 .subvendor = PCI_ANY_ID, 1260 .subdevice = PCI_ANY_ID, 1261 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1262 }, 1263 1264 { 1265 .vendor = PCI_VENDOR_ID_INTEL, 1266 .device = PCI_DEVICE_ID_INTEL_BXT_EMMC, 1267 .subvendor = PCI_ANY_ID, 1268 .subdevice = PCI_ANY_ID, 1269 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1270 }, 1271 1272 { 1273 .vendor = PCI_VENDOR_ID_INTEL, 1274 .device = PCI_DEVICE_ID_INTEL_BXT_SDIO, 1275 .subvendor = PCI_ANY_ID, 1276 .subdevice = PCI_ANY_ID, 1277 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1278 }, 1279 1280 { 1281 .vendor = PCI_VENDOR_ID_INTEL, 1282 .device = PCI_DEVICE_ID_INTEL_BXT_SD, 1283 .subvendor = PCI_ANY_ID, 1284 .subdevice = PCI_ANY_ID, 1285 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1286 }, 1287 1288 { 1289 .vendor = PCI_VENDOR_ID_INTEL, 1290 .device = PCI_DEVICE_ID_INTEL_BXTM_EMMC, 1291 .subvendor = PCI_ANY_ID, 1292 .subdevice = PCI_ANY_ID, 1293 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1294 }, 1295 1296 { 1297 .vendor = PCI_VENDOR_ID_INTEL, 1298 .device = PCI_DEVICE_ID_INTEL_BXTM_SDIO, 1299 .subvendor = PCI_ANY_ID, 1300 .subdevice = PCI_ANY_ID, 1301 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1302 }, 1303 1304 { 1305 .vendor = PCI_VENDOR_ID_INTEL, 1306 .device = PCI_DEVICE_ID_INTEL_BXTM_SD, 1307 .subvendor = PCI_ANY_ID, 1308 .subdevice = PCI_ANY_ID, 1309 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1310 }, 1311 1312 { 1313 .vendor = PCI_VENDOR_ID_INTEL, 1314 .device = PCI_DEVICE_ID_INTEL_APL_EMMC, 1315 .subvendor = PCI_ANY_ID, 1316 .subdevice = PCI_ANY_ID, 1317 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1318 }, 1319 1320 { 1321 .vendor = PCI_VENDOR_ID_INTEL, 1322 .device = PCI_DEVICE_ID_INTEL_APL_SDIO, 1323 .subvendor = PCI_ANY_ID, 1324 .subdevice = PCI_ANY_ID, 1325 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1326 }, 1327 1328 { 1329 .vendor = PCI_VENDOR_ID_INTEL, 1330 .device = PCI_DEVICE_ID_INTEL_APL_SD, 1331 .subvendor = PCI_ANY_ID, 1332 .subdevice = PCI_ANY_ID, 1333 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1334 }, 1335 1336 { 1337 .vendor = PCI_VENDOR_ID_INTEL, 1338 .device = PCI_DEVICE_ID_INTEL_GLK_EMMC, 1339 .subvendor = PCI_ANY_ID, 1340 .subdevice = PCI_ANY_ID, 1341 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1342 }, 1343 1344 { 1345 .vendor = PCI_VENDOR_ID_INTEL, 1346 .device = PCI_DEVICE_ID_INTEL_GLK_SDIO, 1347 .subvendor = PCI_ANY_ID, 1348 .subdevice = PCI_ANY_ID, 1349 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1350 }, 1351 1352 { 1353 .vendor = PCI_VENDOR_ID_INTEL, 1354 .device = PCI_DEVICE_ID_INTEL_GLK_SD, 1355 .subvendor = PCI_ANY_ID, 1356 .subdevice = PCI_ANY_ID, 1357 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1358 }, 1359 1360 { 1361 .vendor = PCI_VENDOR_ID_O2, 1362 .device = PCI_DEVICE_ID_O2_8120, 1363 .subvendor = PCI_ANY_ID, 1364 .subdevice = PCI_ANY_ID, 1365 .driver_data = (kernel_ulong_t)&sdhci_o2, 1366 }, 1367 1368 { 1369 .vendor = PCI_VENDOR_ID_O2, 1370 .device = PCI_DEVICE_ID_O2_8220, 1371 .subvendor = PCI_ANY_ID, 1372 .subdevice = PCI_ANY_ID, 1373 .driver_data = (kernel_ulong_t)&sdhci_o2, 1374 }, 1375 1376 { 1377 .vendor = PCI_VENDOR_ID_O2, 1378 .device = PCI_DEVICE_ID_O2_8221, 1379 .subvendor = PCI_ANY_ID, 1380 .subdevice = PCI_ANY_ID, 1381 .driver_data = (kernel_ulong_t)&sdhci_o2, 1382 }, 1383 1384 { 1385 .vendor = PCI_VENDOR_ID_O2, 1386 .device = PCI_DEVICE_ID_O2_8320, 1387 .subvendor = PCI_ANY_ID, 1388 .subdevice = PCI_ANY_ID, 1389 .driver_data = (kernel_ulong_t)&sdhci_o2, 1390 }, 1391 1392 { 1393 .vendor = PCI_VENDOR_ID_O2, 1394 .device = PCI_DEVICE_ID_O2_8321, 1395 .subvendor = PCI_ANY_ID, 1396 .subdevice = PCI_ANY_ID, 1397 .driver_data = (kernel_ulong_t)&sdhci_o2, 1398 }, 1399 1400 { 1401 .vendor = PCI_VENDOR_ID_O2, 1402 .device = PCI_DEVICE_ID_O2_FUJIN2, 1403 .subvendor = PCI_ANY_ID, 1404 .subdevice = PCI_ANY_ID, 1405 .driver_data = (kernel_ulong_t)&sdhci_o2, 1406 }, 1407 1408 { 1409 .vendor = PCI_VENDOR_ID_O2, 1410 .device = PCI_DEVICE_ID_O2_SDS0, 1411 .subvendor = PCI_ANY_ID, 1412 .subdevice = PCI_ANY_ID, 1413 .driver_data = (kernel_ulong_t)&sdhci_o2, 1414 }, 1415 1416 { 1417 .vendor = PCI_VENDOR_ID_O2, 1418 .device = PCI_DEVICE_ID_O2_SDS1, 1419 .subvendor = PCI_ANY_ID, 1420 .subdevice = PCI_ANY_ID, 1421 .driver_data = (kernel_ulong_t)&sdhci_o2, 1422 }, 1423 1424 { 1425 .vendor = PCI_VENDOR_ID_O2, 1426 .device = PCI_DEVICE_ID_O2_SEABIRD0, 1427 .subvendor = PCI_ANY_ID, 1428 .subdevice = PCI_ANY_ID, 1429 .driver_data = (kernel_ulong_t)&sdhci_o2, 1430 }, 1431 1432 { 1433 .vendor = PCI_VENDOR_ID_O2, 1434 .device = PCI_DEVICE_ID_O2_SEABIRD1, 1435 .subvendor = PCI_ANY_ID, 1436 .subdevice = PCI_ANY_ID, 1437 .driver_data = (kernel_ulong_t)&sdhci_o2, 1438 }, 1439 { 1440 .vendor = PCI_VENDOR_ID_AMD, 1441 .device = PCI_ANY_ID, 1442 .class = PCI_CLASS_SYSTEM_SDHCI << 8, 1443 .class_mask = 0xFFFF00, 1444 .subvendor = PCI_ANY_ID, 1445 .subdevice = PCI_ANY_ID, 1446 .driver_data = (kernel_ulong_t)&sdhci_amd, 1447 }, 1448 { /* Generic SD host controller */ 1449 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) 1450 }, 1451 1452 { /* end: all zeroes */ }, 1453 }; 1454 1455 MODULE_DEVICE_TABLE(pci, pci_ids); 1456 1457 /*****************************************************************************\ 1458 * * 1459 * SDHCI core callbacks * 1460 * * 1461 \*****************************************************************************/ 1462 1463 static int sdhci_pci_enable_dma(struct sdhci_host *host) 1464 { 1465 struct sdhci_pci_slot *slot; 1466 struct pci_dev *pdev; 1467 1468 slot = sdhci_priv(host); 1469 pdev = slot->chip->pdev; 1470 1471 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1472 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1473 (host->flags & SDHCI_USE_SDMA)) { 1474 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1475 "doesn't fully claim to support it.\n"); 1476 } 1477 1478 pci_set_master(pdev); 1479 1480 return 0; 1481 } 1482 1483 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width) 1484 { 1485 u8 ctrl; 1486 1487 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1488 1489 switch (width) { 1490 case MMC_BUS_WIDTH_8: 1491 ctrl |= SDHCI_CTRL_8BITBUS; 1492 ctrl &= ~SDHCI_CTRL_4BITBUS; 1493 break; 1494 case MMC_BUS_WIDTH_4: 1495 ctrl |= SDHCI_CTRL_4BITBUS; 1496 ctrl &= ~SDHCI_CTRL_8BITBUS; 1497 break; 1498 default: 1499 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS); 1500 break; 1501 } 1502 1503 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1504 } 1505 1506 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1507 { 1508 struct sdhci_pci_slot *slot = sdhci_priv(host); 1509 int rst_n_gpio = slot->rst_n_gpio; 1510 1511 if (!gpio_is_valid(rst_n_gpio)) 1512 return; 1513 gpio_set_value_cansleep(rst_n_gpio, 0); 1514 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1515 udelay(10); 1516 gpio_set_value_cansleep(rst_n_gpio, 1); 1517 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1518 usleep_range(300, 1000); 1519 } 1520 1521 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1522 { 1523 struct sdhci_pci_slot *slot = sdhci_priv(host); 1524 1525 if (slot->hw_reset) 1526 slot->hw_reset(host); 1527 } 1528 1529 static int sdhci_pci_select_drive_strength(struct sdhci_host *host, 1530 struct mmc_card *card, 1531 unsigned int max_dtr, int host_drv, 1532 int card_drv, int *drv_type) 1533 { 1534 struct sdhci_pci_slot *slot = sdhci_priv(host); 1535 1536 if (!slot->select_drive_strength) 1537 return 0; 1538 1539 return slot->select_drive_strength(host, card, max_dtr, host_drv, 1540 card_drv, drv_type); 1541 } 1542 1543 static const struct sdhci_ops sdhci_pci_ops = { 1544 .set_clock = sdhci_set_clock, 1545 .enable_dma = sdhci_pci_enable_dma, 1546 .set_bus_width = sdhci_pci_set_bus_width, 1547 .reset = sdhci_reset, 1548 .set_uhs_signaling = sdhci_set_uhs_signaling, 1549 .hw_reset = sdhci_pci_hw_reset, 1550 .select_drive_strength = sdhci_pci_select_drive_strength, 1551 }; 1552 1553 /*****************************************************************************\ 1554 * * 1555 * Suspend/resume * 1556 * * 1557 \*****************************************************************************/ 1558 1559 #ifdef CONFIG_PM_SLEEP 1560 static int sdhci_pci_suspend(struct device *dev) 1561 { 1562 struct pci_dev *pdev = to_pci_dev(dev); 1563 struct sdhci_pci_chip *chip; 1564 struct sdhci_pci_slot *slot; 1565 mmc_pm_flag_t slot_pm_flags; 1566 mmc_pm_flag_t pm_flags = 0; 1567 int i, ret; 1568 1569 chip = pci_get_drvdata(pdev); 1570 if (!chip) 1571 return 0; 1572 1573 for (i = 0; i < chip->num_slots; i++) { 1574 slot = chip->slots[i]; 1575 if (!slot) 1576 continue; 1577 1578 ret = sdhci_suspend_host(slot->host); 1579 1580 if (ret) 1581 goto err_pci_suspend; 1582 1583 slot_pm_flags = slot->host->mmc->pm_flags; 1584 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1585 sdhci_enable_irq_wakeups(slot->host); 1586 1587 pm_flags |= slot_pm_flags; 1588 } 1589 1590 if (chip->fixes && chip->fixes->suspend) { 1591 ret = chip->fixes->suspend(chip); 1592 if (ret) 1593 goto err_pci_suspend; 1594 } 1595 1596 if (pm_flags & MMC_PM_KEEP_POWER) { 1597 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1598 device_init_wakeup(dev, true); 1599 else 1600 device_init_wakeup(dev, false); 1601 } else 1602 device_init_wakeup(dev, false); 1603 1604 return 0; 1605 1606 err_pci_suspend: 1607 while (--i >= 0) 1608 sdhci_resume_host(chip->slots[i]->host); 1609 return ret; 1610 } 1611 1612 static int sdhci_pci_resume(struct device *dev) 1613 { 1614 struct pci_dev *pdev = to_pci_dev(dev); 1615 struct sdhci_pci_chip *chip; 1616 struct sdhci_pci_slot *slot; 1617 int i, ret; 1618 1619 chip = pci_get_drvdata(pdev); 1620 if (!chip) 1621 return 0; 1622 1623 if (chip->fixes && chip->fixes->resume) { 1624 ret = chip->fixes->resume(chip); 1625 if (ret) 1626 return ret; 1627 } 1628 1629 for (i = 0; i < chip->num_slots; i++) { 1630 slot = chip->slots[i]; 1631 if (!slot) 1632 continue; 1633 1634 ret = sdhci_resume_host(slot->host); 1635 if (ret) 1636 return ret; 1637 } 1638 1639 return 0; 1640 } 1641 #endif 1642 1643 #ifdef CONFIG_PM 1644 static int sdhci_pci_runtime_suspend(struct device *dev) 1645 { 1646 struct pci_dev *pdev = to_pci_dev(dev); 1647 struct sdhci_pci_chip *chip; 1648 struct sdhci_pci_slot *slot; 1649 int i, ret; 1650 1651 chip = pci_get_drvdata(pdev); 1652 if (!chip) 1653 return 0; 1654 1655 for (i = 0; i < chip->num_slots; i++) { 1656 slot = chip->slots[i]; 1657 if (!slot) 1658 continue; 1659 1660 ret = sdhci_runtime_suspend_host(slot->host); 1661 1662 if (ret) 1663 goto err_pci_runtime_suspend; 1664 } 1665 1666 if (chip->fixes && chip->fixes->suspend) { 1667 ret = chip->fixes->suspend(chip); 1668 if (ret) 1669 goto err_pci_runtime_suspend; 1670 } 1671 1672 return 0; 1673 1674 err_pci_runtime_suspend: 1675 while (--i >= 0) 1676 sdhci_runtime_resume_host(chip->slots[i]->host); 1677 return ret; 1678 } 1679 1680 static int sdhci_pci_runtime_resume(struct device *dev) 1681 { 1682 struct pci_dev *pdev = to_pci_dev(dev); 1683 struct sdhci_pci_chip *chip; 1684 struct sdhci_pci_slot *slot; 1685 int i, ret; 1686 1687 chip = pci_get_drvdata(pdev); 1688 if (!chip) 1689 return 0; 1690 1691 if (chip->fixes && chip->fixes->resume) { 1692 ret = chip->fixes->resume(chip); 1693 if (ret) 1694 return ret; 1695 } 1696 1697 for (i = 0; i < chip->num_slots; i++) { 1698 slot = chip->slots[i]; 1699 if (!slot) 1700 continue; 1701 1702 ret = sdhci_runtime_resume_host(slot->host); 1703 if (ret) 1704 return ret; 1705 } 1706 1707 return 0; 1708 } 1709 #endif 1710 1711 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1712 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1713 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1714 sdhci_pci_runtime_resume, NULL) 1715 }; 1716 1717 /*****************************************************************************\ 1718 * * 1719 * Device probing/removal * 1720 * * 1721 \*****************************************************************************/ 1722 1723 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1724 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1725 int slotno) 1726 { 1727 struct sdhci_pci_slot *slot; 1728 struct sdhci_host *host; 1729 int ret, bar = first_bar + slotno; 1730 1731 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1732 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1733 return ERR_PTR(-ENODEV); 1734 } 1735 1736 if (pci_resource_len(pdev, bar) < 0x100) { 1737 dev_err(&pdev->dev, "Invalid iomem size. You may " 1738 "experience problems.\n"); 1739 } 1740 1741 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1742 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1743 return ERR_PTR(-ENODEV); 1744 } 1745 1746 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1747 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1748 return ERR_PTR(-ENODEV); 1749 } 1750 1751 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot)); 1752 if (IS_ERR(host)) { 1753 dev_err(&pdev->dev, "cannot allocate host\n"); 1754 return ERR_CAST(host); 1755 } 1756 1757 slot = sdhci_priv(host); 1758 1759 slot->chip = chip; 1760 slot->host = host; 1761 slot->rst_n_gpio = -EINVAL; 1762 slot->cd_gpio = -EINVAL; 1763 slot->cd_idx = -1; 1764 1765 /* Retrieve platform data if there is any */ 1766 if (*sdhci_pci_get_data) 1767 slot->data = sdhci_pci_get_data(pdev, slotno); 1768 1769 if (slot->data) { 1770 if (slot->data->setup) { 1771 ret = slot->data->setup(slot->data); 1772 if (ret) { 1773 dev_err(&pdev->dev, "platform setup failed\n"); 1774 goto free; 1775 } 1776 } 1777 slot->rst_n_gpio = slot->data->rst_n_gpio; 1778 slot->cd_gpio = slot->data->cd_gpio; 1779 } 1780 1781 host->hw_name = "PCI"; 1782 host->ops = chip->fixes && chip->fixes->ops ? 1783 chip->fixes->ops : 1784 &sdhci_pci_ops; 1785 host->quirks = chip->quirks; 1786 host->quirks2 = chip->quirks2; 1787 1788 host->irq = pdev->irq; 1789 1790 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1791 if (ret) { 1792 dev_err(&pdev->dev, "cannot request region\n"); 1793 goto cleanup; 1794 } 1795 1796 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1797 1798 if (chip->fixes && chip->fixes->probe_slot) { 1799 ret = chip->fixes->probe_slot(slot); 1800 if (ret) 1801 goto cleanup; 1802 } 1803 1804 if (gpio_is_valid(slot->rst_n_gpio)) { 1805 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1806 gpio_direction_output(slot->rst_n_gpio, 1); 1807 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1808 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1809 } else { 1810 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1811 slot->rst_n_gpio = -EINVAL; 1812 } 1813 } 1814 1815 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; 1816 host->mmc->slotno = slotno; 1817 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1818 1819 if (slot->cd_idx >= 0) { 1820 ret = mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx, 1821 slot->cd_override_level, 0, NULL); 1822 if (ret == -EPROBE_DEFER) 1823 goto remove; 1824 1825 if (ret) { 1826 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 1827 slot->cd_idx = -1; 1828 } 1829 } 1830 1831 ret = sdhci_add_host(host); 1832 if (ret) 1833 goto remove; 1834 1835 sdhci_pci_add_own_cd(slot); 1836 1837 /* 1838 * Check if the chip needs a separate GPIO for card detect to wake up 1839 * from runtime suspend. If it is not there, don't allow runtime PM. 1840 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 1841 */ 1842 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 1843 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 1844 chip->allow_runtime_pm = false; 1845 1846 return slot; 1847 1848 remove: 1849 if (chip->fixes && chip->fixes->remove_slot) 1850 chip->fixes->remove_slot(slot, 0); 1851 1852 cleanup: 1853 if (slot->data && slot->data->cleanup) 1854 slot->data->cleanup(slot->data); 1855 1856 free: 1857 sdhci_free_host(host); 1858 1859 return ERR_PTR(ret); 1860 } 1861 1862 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 1863 { 1864 int dead; 1865 u32 scratch; 1866 1867 sdhci_pci_remove_own_cd(slot); 1868 1869 dead = 0; 1870 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 1871 if (scratch == (u32)-1) 1872 dead = 1; 1873 1874 sdhci_remove_host(slot->host, dead); 1875 1876 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 1877 slot->chip->fixes->remove_slot(slot, dead); 1878 1879 if (slot->data && slot->data->cleanup) 1880 slot->data->cleanup(slot->data); 1881 1882 sdhci_free_host(slot->host); 1883 } 1884 1885 static void sdhci_pci_runtime_pm_allow(struct device *dev) 1886 { 1887 pm_suspend_ignore_children(dev, 1); 1888 pm_runtime_set_autosuspend_delay(dev, 50); 1889 pm_runtime_use_autosuspend(dev); 1890 pm_runtime_allow(dev); 1891 /* Stay active until mmc core scans for a card */ 1892 pm_runtime_put_noidle(dev); 1893 } 1894 1895 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 1896 { 1897 pm_runtime_forbid(dev); 1898 pm_runtime_get_noresume(dev); 1899 } 1900 1901 static int sdhci_pci_probe(struct pci_dev *pdev, 1902 const struct pci_device_id *ent) 1903 { 1904 struct sdhci_pci_chip *chip; 1905 struct sdhci_pci_slot *slot; 1906 1907 u8 slots, first_bar; 1908 int ret, i; 1909 1910 BUG_ON(pdev == NULL); 1911 BUG_ON(ent == NULL); 1912 1913 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 1914 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 1915 1916 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 1917 if (ret) 1918 return ret; 1919 1920 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 1921 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 1922 if (slots == 0) 1923 return -ENODEV; 1924 1925 BUG_ON(slots > MAX_SLOTS); 1926 1927 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 1928 if (ret) 1929 return ret; 1930 1931 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 1932 1933 if (first_bar > 5) { 1934 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 1935 return -ENODEV; 1936 } 1937 1938 ret = pcim_enable_device(pdev); 1939 if (ret) 1940 return ret; 1941 1942 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 1943 if (!chip) 1944 return -ENOMEM; 1945 1946 chip->pdev = pdev; 1947 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 1948 if (chip->fixes) { 1949 chip->quirks = chip->fixes->quirks; 1950 chip->quirks2 = chip->fixes->quirks2; 1951 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 1952 } 1953 chip->num_slots = slots; 1954 1955 pci_set_drvdata(pdev, chip); 1956 1957 if (chip->fixes && chip->fixes->probe) { 1958 ret = chip->fixes->probe(chip); 1959 if (ret) 1960 return ret; 1961 } 1962 1963 slots = chip->num_slots; /* Quirk may have changed this */ 1964 1965 for (i = 0; i < slots; i++) { 1966 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 1967 if (IS_ERR(slot)) { 1968 for (i--; i >= 0; i--) 1969 sdhci_pci_remove_slot(chip->slots[i]); 1970 return PTR_ERR(slot); 1971 } 1972 1973 chip->slots[i] = slot; 1974 } 1975 1976 if (chip->allow_runtime_pm) 1977 sdhci_pci_runtime_pm_allow(&pdev->dev); 1978 1979 return 0; 1980 } 1981 1982 static void sdhci_pci_remove(struct pci_dev *pdev) 1983 { 1984 int i; 1985 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1986 1987 if (chip->allow_runtime_pm) 1988 sdhci_pci_runtime_pm_forbid(&pdev->dev); 1989 1990 for (i = 0; i < chip->num_slots; i++) 1991 sdhci_pci_remove_slot(chip->slots[i]); 1992 } 1993 1994 static struct pci_driver sdhci_driver = { 1995 .name = "sdhci-pci", 1996 .id_table = pci_ids, 1997 .probe = sdhci_pci_probe, 1998 .remove = sdhci_pci_remove, 1999 .driver = { 2000 .pm = &sdhci_pci_pm_ops 2001 }, 2002 }; 2003 2004 module_pci_driver(sdhci_driver); 2005 2006 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 2007 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 2008 MODULE_LICENSE("GPL"); 2009