1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 3 * 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 5 * 6 * Thanks to the following companies for their support: 7 * 8 * - JMicron (hardware and technical support) 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/string.h> 13 #include <linux/delay.h> 14 #include <linux/highmem.h> 15 #include <linux/module.h> 16 #include <linux/pci.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/slab.h> 19 #include <linux/device.h> 20 #include <linux/scatterlist.h> 21 #include <linux/io.h> 22 #include <linux/iopoll.h> 23 #include <linux/gpio.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/pm_qos.h> 26 #include <linux/debugfs.h> 27 #include <linux/acpi.h> 28 #include <linux/dmi.h> 29 30 #include <linux/mmc/host.h> 31 #include <linux/mmc/mmc.h> 32 #include <linux/mmc/slot-gpio.h> 33 34 #ifdef CONFIG_X86 35 #include <asm/iosf_mbi.h> 36 #endif 37 38 #include "cqhci.h" 39 40 #include "sdhci.h" 41 #include "sdhci-pci.h" 42 43 static void sdhci_pci_hw_reset(struct sdhci_host *host); 44 45 #ifdef CONFIG_PM_SLEEP 46 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip) 47 { 48 mmc_pm_flag_t pm_flags = 0; 49 bool cap_cd_wake = false; 50 int i; 51 52 for (i = 0; i < chip->num_slots; i++) { 53 struct sdhci_pci_slot *slot = chip->slots[i]; 54 55 if (slot) { 56 pm_flags |= slot->host->mmc->pm_flags; 57 if (slot->host->mmc->caps & MMC_CAP_CD_WAKE) 58 cap_cd_wake = true; 59 } 60 } 61 62 if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ)) 63 return device_wakeup_enable(&chip->pdev->dev); 64 else if (!cap_cd_wake) 65 return device_wakeup_disable(&chip->pdev->dev); 66 67 return 0; 68 } 69 70 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 71 { 72 int i, ret; 73 74 sdhci_pci_init_wakeup(chip); 75 76 for (i = 0; i < chip->num_slots; i++) { 77 struct sdhci_pci_slot *slot = chip->slots[i]; 78 struct sdhci_host *host; 79 80 if (!slot) 81 continue; 82 83 host = slot->host; 84 85 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 86 mmc_retune_needed(host->mmc); 87 88 ret = sdhci_suspend_host(host); 89 if (ret) 90 goto err_pci_suspend; 91 92 if (device_may_wakeup(&chip->pdev->dev)) 93 mmc_gpio_set_cd_wake(host->mmc, true); 94 } 95 96 return 0; 97 98 err_pci_suspend: 99 while (--i >= 0) 100 sdhci_resume_host(chip->slots[i]->host); 101 return ret; 102 } 103 104 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip) 105 { 106 struct sdhci_pci_slot *slot; 107 int i, ret; 108 109 for (i = 0; i < chip->num_slots; i++) { 110 slot = chip->slots[i]; 111 if (!slot) 112 continue; 113 114 ret = sdhci_resume_host(slot->host); 115 if (ret) 116 return ret; 117 118 mmc_gpio_set_cd_wake(slot->host->mmc, false); 119 } 120 121 return 0; 122 } 123 124 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip) 125 { 126 int ret; 127 128 ret = cqhci_suspend(chip->slots[0]->host->mmc); 129 if (ret) 130 return ret; 131 132 return sdhci_pci_suspend_host(chip); 133 } 134 135 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip) 136 { 137 int ret; 138 139 ret = sdhci_pci_resume_host(chip); 140 if (ret) 141 return ret; 142 143 return cqhci_resume(chip->slots[0]->host->mmc); 144 } 145 #endif 146 147 #ifdef CONFIG_PM 148 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip) 149 { 150 struct sdhci_pci_slot *slot; 151 struct sdhci_host *host; 152 int i, ret; 153 154 for (i = 0; i < chip->num_slots; i++) { 155 slot = chip->slots[i]; 156 if (!slot) 157 continue; 158 159 host = slot->host; 160 161 ret = sdhci_runtime_suspend_host(host); 162 if (ret) 163 goto err_pci_runtime_suspend; 164 165 if (chip->rpm_retune && 166 host->tuning_mode != SDHCI_TUNING_MODE_3) 167 mmc_retune_needed(host->mmc); 168 } 169 170 return 0; 171 172 err_pci_runtime_suspend: 173 while (--i >= 0) 174 sdhci_runtime_resume_host(chip->slots[i]->host, 0); 175 return ret; 176 } 177 178 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip) 179 { 180 struct sdhci_pci_slot *slot; 181 int i, ret; 182 183 for (i = 0; i < chip->num_slots; i++) { 184 slot = chip->slots[i]; 185 if (!slot) 186 continue; 187 188 ret = sdhci_runtime_resume_host(slot->host, 0); 189 if (ret) 190 return ret; 191 } 192 193 return 0; 194 } 195 196 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip) 197 { 198 int ret; 199 200 ret = cqhci_suspend(chip->slots[0]->host->mmc); 201 if (ret) 202 return ret; 203 204 return sdhci_pci_runtime_suspend_host(chip); 205 } 206 207 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip) 208 { 209 int ret; 210 211 ret = sdhci_pci_runtime_resume_host(chip); 212 if (ret) 213 return ret; 214 215 return cqhci_resume(chip->slots[0]->host->mmc); 216 } 217 #endif 218 219 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask) 220 { 221 int cmd_error = 0; 222 int data_error = 0; 223 224 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 225 return intmask; 226 227 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 228 229 return 0; 230 } 231 232 static void sdhci_pci_dumpregs(struct mmc_host *mmc) 233 { 234 sdhci_dumpregs(mmc_priv(mmc)); 235 } 236 237 static void sdhci_cqhci_reset(struct sdhci_host *host, u8 mask) 238 { 239 if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) && 240 host->mmc->cqe_private) 241 cqhci_deactivate(host->mmc); 242 sdhci_reset(host, mask); 243 } 244 245 /*****************************************************************************\ 246 * * 247 * Hardware specific quirk handling * 248 * * 249 \*****************************************************************************/ 250 251 static int ricoh_probe(struct sdhci_pci_chip *chip) 252 { 253 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 254 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 255 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 256 return 0; 257 } 258 259 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 260 { 261 slot->host->caps = 262 FIELD_PREP(SDHCI_TIMEOUT_CLK_MASK, 0x21) | 263 FIELD_PREP(SDHCI_CLOCK_BASE_MASK, 0x21) | 264 SDHCI_TIMEOUT_CLK_UNIT | 265 SDHCI_CAN_VDD_330 | 266 SDHCI_CAN_DO_HISPD | 267 SDHCI_CAN_DO_SDMA; 268 return 0; 269 } 270 271 #ifdef CONFIG_PM_SLEEP 272 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 273 { 274 /* Apply a delay to allow controller to settle */ 275 /* Otherwise it becomes confused if card state changed 276 during suspend */ 277 msleep(500); 278 return sdhci_pci_resume_host(chip); 279 } 280 #endif 281 282 static const struct sdhci_pci_fixes sdhci_ricoh = { 283 .probe = ricoh_probe, 284 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 285 SDHCI_QUIRK_FORCE_DMA | 286 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 287 }; 288 289 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 290 .probe_slot = ricoh_mmc_probe_slot, 291 #ifdef CONFIG_PM_SLEEP 292 .resume = ricoh_mmc_resume, 293 #endif 294 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 295 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 296 SDHCI_QUIRK_NO_CARD_NO_RESET | 297 SDHCI_QUIRK_MISSING_CAPS 298 }; 299 300 static void ene_714_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 301 { 302 struct sdhci_host *host = mmc_priv(mmc); 303 304 sdhci_set_ios(mmc, ios); 305 306 /* 307 * Some (ENE) controllers misbehave on some ios operations, 308 * signalling timeout and CRC errors even on CMD0. Resetting 309 * it on each ios seems to solve the problem. 310 */ 311 if (!(host->flags & SDHCI_DEVICE_DEAD)) 312 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 313 } 314 315 static int ene_714_probe_slot(struct sdhci_pci_slot *slot) 316 { 317 slot->host->mmc_host_ops.set_ios = ene_714_set_ios; 318 return 0; 319 } 320 321 static const struct sdhci_pci_fixes sdhci_ene_712 = { 322 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 323 SDHCI_QUIRK_BROKEN_DMA, 324 }; 325 326 static const struct sdhci_pci_fixes sdhci_ene_714 = { 327 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 328 SDHCI_QUIRK_BROKEN_DMA, 329 .probe_slot = ene_714_probe_slot, 330 }; 331 332 static const struct sdhci_pci_fixes sdhci_cafe = { 333 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 334 SDHCI_QUIRK_NO_BUSY_IRQ | 335 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 336 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 337 }; 338 339 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 340 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 341 }; 342 343 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 344 { 345 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 346 return 0; 347 } 348 349 /* 350 * ADMA operation is disabled for Moorestown platform due to 351 * hardware bugs. 352 */ 353 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 354 { 355 /* 356 * slots number is fixed here for MRST as SDIO3/5 are never used and 357 * have hardware bugs. 358 */ 359 chip->num_slots = 1; 360 return 0; 361 } 362 363 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 364 { 365 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 366 return 0; 367 } 368 369 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 370 { 371 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 372 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC; 373 return 0; 374 } 375 376 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 377 { 378 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 379 return 0; 380 } 381 382 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 383 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 384 .probe_slot = mrst_hc_probe_slot, 385 }; 386 387 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 388 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 389 .probe = mrst_hc_probe, 390 }; 391 392 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 393 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 394 .allow_runtime_pm = true, 395 .own_cd_for_runtime_pm = true, 396 }; 397 398 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 399 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 400 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 401 .allow_runtime_pm = true, 402 .probe_slot = mfd_sdio_probe_slot, 403 }; 404 405 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 406 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 407 .allow_runtime_pm = true, 408 .probe_slot = mfd_emmc_probe_slot, 409 }; 410 411 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 412 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 413 .probe_slot = pch_hc_probe_slot, 414 }; 415 416 #ifdef CONFIG_X86 417 418 #define BYT_IOSF_SCCEP 0x63 419 #define BYT_IOSF_OCP_NETCTRL0 0x1078 420 #define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8) 421 422 static void byt_ocp_setting(struct pci_dev *pdev) 423 { 424 u32 val = 0; 425 426 if (pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC && 427 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SDIO && 428 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SD && 429 pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC2) 430 return; 431 432 if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0, 433 &val)) { 434 dev_err(&pdev->dev, "%s read error\n", __func__); 435 return; 436 } 437 438 if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE)) 439 return; 440 441 val &= ~BYT_IOSF_OCP_TIMEOUT_BASE; 442 443 if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0, 444 val)) { 445 dev_err(&pdev->dev, "%s write error\n", __func__); 446 return; 447 } 448 449 dev_dbg(&pdev->dev, "%s completed\n", __func__); 450 } 451 452 #else 453 454 static inline void byt_ocp_setting(struct pci_dev *pdev) 455 { 456 } 457 458 #endif 459 460 enum { 461 INTEL_DSM_FNS = 0, 462 INTEL_DSM_V18_SWITCH = 3, 463 INTEL_DSM_V33_SWITCH = 4, 464 INTEL_DSM_DRV_STRENGTH = 9, 465 INTEL_DSM_D3_RETUNE = 10, 466 }; 467 468 struct intel_host { 469 u32 dsm_fns; 470 int drv_strength; 471 bool d3_retune; 472 bool rpm_retune_ok; 473 bool needs_pwr_off; 474 u32 glk_rx_ctrl1; 475 u32 glk_tun_val; 476 u32 active_ltr; 477 u32 idle_ltr; 478 }; 479 480 static const guid_t intel_dsm_guid = 481 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F, 482 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61); 483 484 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 485 unsigned int fn, u32 *result) 486 { 487 union acpi_object *obj; 488 int err = 0; 489 size_t len; 490 491 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL); 492 if (!obj) 493 return -EOPNOTSUPP; 494 495 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { 496 err = -EINVAL; 497 goto out; 498 } 499 500 len = min_t(size_t, obj->buffer.length, 4); 501 502 *result = 0; 503 memcpy(result, obj->buffer.pointer, len); 504 out: 505 ACPI_FREE(obj); 506 507 return err; 508 } 509 510 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 511 unsigned int fn, u32 *result) 512 { 513 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 514 return -EOPNOTSUPP; 515 516 return __intel_dsm(intel_host, dev, fn, result); 517 } 518 519 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 520 struct mmc_host *mmc) 521 { 522 int err; 523 u32 val; 524 525 intel_host->d3_retune = true; 526 527 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 528 if (err) { 529 pr_debug("%s: DSM not supported, error %d\n", 530 mmc_hostname(mmc), err); 531 return; 532 } 533 534 pr_debug("%s: DSM function mask %#x\n", 535 mmc_hostname(mmc), intel_host->dsm_fns); 536 537 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 538 intel_host->drv_strength = err ? 0 : val; 539 540 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 541 intel_host->d3_retune = err ? true : !!val; 542 } 543 544 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 545 { 546 u8 reg; 547 548 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 549 reg |= 0x10; 550 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 551 /* For eMMC, minimum is 1us but give it 9us for good measure */ 552 udelay(9); 553 reg &= ~0x10; 554 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 555 /* For eMMC, minimum is 200us but give it 300us for good measure */ 556 usleep_range(300, 1000); 557 } 558 559 static int intel_select_drive_strength(struct mmc_card *card, 560 unsigned int max_dtr, int host_drv, 561 int card_drv, int *drv_type) 562 { 563 struct sdhci_host *host = mmc_priv(card->host); 564 struct sdhci_pci_slot *slot = sdhci_priv(host); 565 struct intel_host *intel_host = sdhci_pci_priv(slot); 566 567 if (!(mmc_driver_type_mask(intel_host->drv_strength) & card_drv)) 568 return 0; 569 570 return intel_host->drv_strength; 571 } 572 573 static int bxt_get_cd(struct mmc_host *mmc) 574 { 575 int gpio_cd = mmc_gpio_get_cd(mmc); 576 577 if (!gpio_cd) 578 return 0; 579 580 return sdhci_get_cd_nogpio(mmc); 581 } 582 583 static int mrfld_get_cd(struct mmc_host *mmc) 584 { 585 return sdhci_get_cd_nogpio(mmc); 586 } 587 588 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 589 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 590 591 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 592 unsigned short vdd) 593 { 594 struct sdhci_pci_slot *slot = sdhci_priv(host); 595 struct intel_host *intel_host = sdhci_pci_priv(slot); 596 int cntr; 597 u8 reg; 598 599 /* 600 * Bus power may control card power, but a full reset still may not 601 * reset the power, whereas a direct write to SDHCI_POWER_CONTROL can. 602 * That might be needed to initialize correctly, if the card was left 603 * powered on previously. 604 */ 605 if (intel_host->needs_pwr_off) { 606 intel_host->needs_pwr_off = false; 607 if (mode != MMC_POWER_OFF) { 608 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 609 usleep_range(10000, 12500); 610 } 611 } 612 613 sdhci_set_power(host, mode, vdd); 614 615 if (mode == MMC_POWER_OFF) 616 return; 617 618 /* 619 * Bus power might not enable after D3 -> D0 transition due to the 620 * present state not yet having propagated. Retry for up to 2ms. 621 */ 622 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 623 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 624 if (reg & SDHCI_POWER_ON) 625 break; 626 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 627 reg |= SDHCI_POWER_ON; 628 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 629 } 630 } 631 632 static void sdhci_intel_set_uhs_signaling(struct sdhci_host *host, 633 unsigned int timing) 634 { 635 /* Set UHS timing to SDR25 for High Speed mode */ 636 if (timing == MMC_TIMING_MMC_HS || timing == MMC_TIMING_SD_HS) 637 timing = MMC_TIMING_UHS_SDR25; 638 sdhci_set_uhs_signaling(host, timing); 639 } 640 641 #define INTEL_HS400_ES_REG 0x78 642 #define INTEL_HS400_ES_BIT BIT(0) 643 644 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc, 645 struct mmc_ios *ios) 646 { 647 struct sdhci_host *host = mmc_priv(mmc); 648 u32 val; 649 650 val = sdhci_readl(host, INTEL_HS400_ES_REG); 651 if (ios->enhanced_strobe) 652 val |= INTEL_HS400_ES_BIT; 653 else 654 val &= ~INTEL_HS400_ES_BIT; 655 sdhci_writel(host, val, INTEL_HS400_ES_REG); 656 } 657 658 static int intel_start_signal_voltage_switch(struct mmc_host *mmc, 659 struct mmc_ios *ios) 660 { 661 struct device *dev = mmc_dev(mmc); 662 struct sdhci_host *host = mmc_priv(mmc); 663 struct sdhci_pci_slot *slot = sdhci_priv(host); 664 struct intel_host *intel_host = sdhci_pci_priv(slot); 665 unsigned int fn; 666 u32 result = 0; 667 int err; 668 669 err = sdhci_start_signal_voltage_switch(mmc, ios); 670 if (err) 671 return err; 672 673 switch (ios->signal_voltage) { 674 case MMC_SIGNAL_VOLTAGE_330: 675 fn = INTEL_DSM_V33_SWITCH; 676 break; 677 case MMC_SIGNAL_VOLTAGE_180: 678 fn = INTEL_DSM_V18_SWITCH; 679 break; 680 default: 681 return 0; 682 } 683 684 err = intel_dsm(intel_host, dev, fn, &result); 685 pr_debug("%s: %s DSM fn %u error %d result %u\n", 686 mmc_hostname(mmc), __func__, fn, err, result); 687 688 return 0; 689 } 690 691 static const struct sdhci_ops sdhci_intel_byt_ops = { 692 .set_clock = sdhci_set_clock, 693 .set_power = sdhci_intel_set_power, 694 .enable_dma = sdhci_pci_enable_dma, 695 .set_bus_width = sdhci_set_bus_width, 696 .reset = sdhci_reset, 697 .set_uhs_signaling = sdhci_intel_set_uhs_signaling, 698 .hw_reset = sdhci_pci_hw_reset, 699 }; 700 701 static const struct sdhci_ops sdhci_intel_glk_ops = { 702 .set_clock = sdhci_set_clock, 703 .set_power = sdhci_intel_set_power, 704 .enable_dma = sdhci_pci_enable_dma, 705 .set_bus_width = sdhci_set_bus_width, 706 .reset = sdhci_cqhci_reset, 707 .set_uhs_signaling = sdhci_intel_set_uhs_signaling, 708 .hw_reset = sdhci_pci_hw_reset, 709 .irq = sdhci_cqhci_irq, 710 }; 711 712 static void byt_read_dsm(struct sdhci_pci_slot *slot) 713 { 714 struct intel_host *intel_host = sdhci_pci_priv(slot); 715 struct device *dev = &slot->chip->pdev->dev; 716 struct mmc_host *mmc = slot->host->mmc; 717 718 intel_dsm_init(intel_host, dev, mmc); 719 slot->chip->rpm_retune = intel_host->d3_retune; 720 } 721 722 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode) 723 { 724 int err = sdhci_execute_tuning(mmc, opcode); 725 struct sdhci_host *host = mmc_priv(mmc); 726 727 if (err) 728 return err; 729 730 /* 731 * Tuning can leave the IP in an active state (Buffer Read Enable bit 732 * set) which prevents the entry to low power states (i.e. S0i3). Data 733 * reset will clear it. 734 */ 735 sdhci_reset(host, SDHCI_RESET_DATA); 736 737 return 0; 738 } 739 740 #define INTEL_ACTIVELTR 0x804 741 #define INTEL_IDLELTR 0x808 742 743 #define INTEL_LTR_REQ BIT(15) 744 #define INTEL_LTR_SCALE_MASK GENMASK(11, 10) 745 #define INTEL_LTR_SCALE_1US (2 << 10) 746 #define INTEL_LTR_SCALE_32US (3 << 10) 747 #define INTEL_LTR_VALUE_MASK GENMASK(9, 0) 748 749 static void intel_cache_ltr(struct sdhci_pci_slot *slot) 750 { 751 struct intel_host *intel_host = sdhci_pci_priv(slot); 752 struct sdhci_host *host = slot->host; 753 754 intel_host->active_ltr = readl(host->ioaddr + INTEL_ACTIVELTR); 755 intel_host->idle_ltr = readl(host->ioaddr + INTEL_IDLELTR); 756 } 757 758 static void intel_ltr_set(struct device *dev, s32 val) 759 { 760 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 761 struct sdhci_pci_slot *slot = chip->slots[0]; 762 struct intel_host *intel_host = sdhci_pci_priv(slot); 763 struct sdhci_host *host = slot->host; 764 u32 ltr; 765 766 pm_runtime_get_sync(dev); 767 768 /* 769 * Program latency tolerance (LTR) accordingly what has been asked 770 * by the PM QoS layer or disable it in case we were passed 771 * negative value or PM_QOS_LATENCY_ANY. 772 */ 773 ltr = readl(host->ioaddr + INTEL_ACTIVELTR); 774 775 if (val == PM_QOS_LATENCY_ANY || val < 0) { 776 ltr &= ~INTEL_LTR_REQ; 777 } else { 778 ltr |= INTEL_LTR_REQ; 779 ltr &= ~INTEL_LTR_SCALE_MASK; 780 ltr &= ~INTEL_LTR_VALUE_MASK; 781 782 if (val > INTEL_LTR_VALUE_MASK) { 783 val >>= 5; 784 if (val > INTEL_LTR_VALUE_MASK) 785 val = INTEL_LTR_VALUE_MASK; 786 ltr |= INTEL_LTR_SCALE_32US | val; 787 } else { 788 ltr |= INTEL_LTR_SCALE_1US | val; 789 } 790 } 791 792 if (ltr == intel_host->active_ltr) 793 goto out; 794 795 writel(ltr, host->ioaddr + INTEL_ACTIVELTR); 796 writel(ltr, host->ioaddr + INTEL_IDLELTR); 797 798 /* Cache the values into lpss structure */ 799 intel_cache_ltr(slot); 800 out: 801 pm_runtime_put_autosuspend(dev); 802 } 803 804 static bool intel_use_ltr(struct sdhci_pci_chip *chip) 805 { 806 switch (chip->pdev->device) { 807 case PCI_DEVICE_ID_INTEL_BYT_EMMC: 808 case PCI_DEVICE_ID_INTEL_BYT_EMMC2: 809 case PCI_DEVICE_ID_INTEL_BYT_SDIO: 810 case PCI_DEVICE_ID_INTEL_BYT_SD: 811 case PCI_DEVICE_ID_INTEL_BSW_EMMC: 812 case PCI_DEVICE_ID_INTEL_BSW_SDIO: 813 case PCI_DEVICE_ID_INTEL_BSW_SD: 814 return false; 815 default: 816 return true; 817 } 818 } 819 820 static void intel_ltr_expose(struct sdhci_pci_chip *chip) 821 { 822 struct device *dev = &chip->pdev->dev; 823 824 if (!intel_use_ltr(chip)) 825 return; 826 827 dev->power.set_latency_tolerance = intel_ltr_set; 828 dev_pm_qos_expose_latency_tolerance(dev); 829 } 830 831 static void intel_ltr_hide(struct sdhci_pci_chip *chip) 832 { 833 struct device *dev = &chip->pdev->dev; 834 835 if (!intel_use_ltr(chip)) 836 return; 837 838 dev_pm_qos_hide_latency_tolerance(dev); 839 dev->power.set_latency_tolerance = NULL; 840 } 841 842 static void byt_probe_slot(struct sdhci_pci_slot *slot) 843 { 844 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 845 struct device *dev = &slot->chip->pdev->dev; 846 struct mmc_host *mmc = slot->host->mmc; 847 848 byt_read_dsm(slot); 849 850 byt_ocp_setting(slot->chip->pdev); 851 852 ops->execute_tuning = intel_execute_tuning; 853 ops->start_signal_voltage_switch = intel_start_signal_voltage_switch; 854 855 device_property_read_u32(dev, "max-frequency", &mmc->f_max); 856 857 if (!mmc->slotno) { 858 slot->chip->slots[mmc->slotno] = slot; 859 intel_ltr_expose(slot->chip); 860 } 861 } 862 863 static void byt_add_debugfs(struct sdhci_pci_slot *slot) 864 { 865 struct intel_host *intel_host = sdhci_pci_priv(slot); 866 struct mmc_host *mmc = slot->host->mmc; 867 struct dentry *dir = mmc->debugfs_root; 868 869 if (!intel_use_ltr(slot->chip)) 870 return; 871 872 debugfs_create_x32("active_ltr", 0444, dir, &intel_host->active_ltr); 873 debugfs_create_x32("idle_ltr", 0444, dir, &intel_host->idle_ltr); 874 875 intel_cache_ltr(slot); 876 } 877 878 static int byt_add_host(struct sdhci_pci_slot *slot) 879 { 880 int ret = sdhci_add_host(slot->host); 881 882 if (!ret) 883 byt_add_debugfs(slot); 884 return ret; 885 } 886 887 static void byt_remove_slot(struct sdhci_pci_slot *slot, int dead) 888 { 889 struct mmc_host *mmc = slot->host->mmc; 890 891 if (!mmc->slotno) 892 intel_ltr_hide(slot->chip); 893 } 894 895 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 896 { 897 byt_probe_slot(slot); 898 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 899 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 900 MMC_CAP_CMD_DURING_TFR | 901 MMC_CAP_WAIT_WHILE_BUSY; 902 slot->hw_reset = sdhci_pci_int_hw_reset; 903 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 904 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 905 slot->host->mmc_host_ops.select_drive_strength = 906 intel_select_drive_strength; 907 return 0; 908 } 909 910 static bool glk_broken_cqhci(struct sdhci_pci_slot *slot) 911 { 912 return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 913 (dmi_match(DMI_BIOS_VENDOR, "LENOVO") || 914 dmi_match(DMI_SYS_VENDOR, "IRBIS")); 915 } 916 917 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot) 918 { 919 int ret = byt_emmc_probe_slot(slot); 920 921 if (!glk_broken_cqhci(slot)) 922 slot->host->mmc->caps2 |= MMC_CAP2_CQE; 923 924 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) { 925 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES; 926 slot->host->mmc_host_ops.hs400_enhanced_strobe = 927 intel_hs400_enhanced_strobe; 928 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; 929 } 930 931 return ret; 932 } 933 934 static const struct cqhci_host_ops glk_cqhci_ops = { 935 .enable = sdhci_cqe_enable, 936 .disable = sdhci_cqe_disable, 937 .dumpregs = sdhci_pci_dumpregs, 938 }; 939 940 static int glk_emmc_add_host(struct sdhci_pci_slot *slot) 941 { 942 struct device *dev = &slot->chip->pdev->dev; 943 struct sdhci_host *host = slot->host; 944 struct cqhci_host *cq_host; 945 bool dma64; 946 int ret; 947 948 ret = sdhci_setup_host(host); 949 if (ret) 950 return ret; 951 952 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); 953 if (!cq_host) { 954 ret = -ENOMEM; 955 goto cleanup; 956 } 957 958 cq_host->mmio = host->ioaddr + 0x200; 959 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 960 cq_host->ops = &glk_cqhci_ops; 961 962 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 963 if (dma64) 964 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 965 966 ret = cqhci_init(cq_host, host->mmc, dma64); 967 if (ret) 968 goto cleanup; 969 970 ret = __sdhci_add_host(host); 971 if (ret) 972 goto cleanup; 973 974 byt_add_debugfs(slot); 975 976 return 0; 977 978 cleanup: 979 sdhci_cleanup_host(host); 980 return ret; 981 } 982 983 #ifdef CONFIG_PM 984 #define GLK_RX_CTRL1 0x834 985 #define GLK_TUN_VAL 0x840 986 #define GLK_PATH_PLL GENMASK(13, 8) 987 #define GLK_DLY GENMASK(6, 0) 988 /* Workaround firmware failing to restore the tuning value */ 989 static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp) 990 { 991 struct sdhci_pci_slot *slot = chip->slots[0]; 992 struct intel_host *intel_host = sdhci_pci_priv(slot); 993 struct sdhci_host *host = slot->host; 994 u32 glk_rx_ctrl1; 995 u32 glk_tun_val; 996 u32 dly; 997 998 if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc)) 999 return; 1000 1001 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1); 1002 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL); 1003 1004 if (susp) { 1005 intel_host->glk_rx_ctrl1 = glk_rx_ctrl1; 1006 intel_host->glk_tun_val = glk_tun_val; 1007 return; 1008 } 1009 1010 if (!intel_host->glk_tun_val) 1011 return; 1012 1013 if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) { 1014 intel_host->rpm_retune_ok = true; 1015 return; 1016 } 1017 1018 dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) + 1019 (intel_host->glk_tun_val << 1)); 1020 if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1)) 1021 return; 1022 1023 glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly; 1024 sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1); 1025 1026 intel_host->rpm_retune_ok = true; 1027 chip->rpm_retune = true; 1028 mmc_retune_needed(host->mmc); 1029 pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc)); 1030 } 1031 1032 static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp) 1033 { 1034 if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 1035 !chip->rpm_retune) 1036 glk_rpm_retune_wa(chip, susp); 1037 } 1038 1039 static int glk_runtime_suspend(struct sdhci_pci_chip *chip) 1040 { 1041 glk_rpm_retune_chk(chip, true); 1042 1043 return sdhci_cqhci_runtime_suspend(chip); 1044 } 1045 1046 static int glk_runtime_resume(struct sdhci_pci_chip *chip) 1047 { 1048 glk_rpm_retune_chk(chip, false); 1049 1050 return sdhci_cqhci_runtime_resume(chip); 1051 } 1052 #endif 1053 1054 #ifdef CONFIG_ACPI 1055 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 1056 { 1057 acpi_status status; 1058 unsigned long long max_freq; 1059 1060 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 1061 "MXFQ", NULL, &max_freq); 1062 if (ACPI_FAILURE(status)) { 1063 dev_err(&slot->chip->pdev->dev, 1064 "MXFQ not found in acpi table\n"); 1065 return -EINVAL; 1066 } 1067 1068 slot->host->mmc->f_max = max_freq * 1000000; 1069 1070 return 0; 1071 } 1072 #else 1073 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 1074 { 1075 return 0; 1076 } 1077 #endif 1078 1079 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 1080 { 1081 int err; 1082 1083 byt_probe_slot(slot); 1084 1085 err = ni_set_max_freq(slot); 1086 if (err) 1087 return err; 1088 1089 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 1090 MMC_CAP_WAIT_WHILE_BUSY; 1091 return 0; 1092 } 1093 1094 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 1095 { 1096 byt_probe_slot(slot); 1097 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 1098 MMC_CAP_WAIT_WHILE_BUSY; 1099 return 0; 1100 } 1101 1102 static void byt_needs_pwr_off(struct sdhci_pci_slot *slot) 1103 { 1104 struct intel_host *intel_host = sdhci_pci_priv(slot); 1105 u8 reg = sdhci_readb(slot->host, SDHCI_POWER_CONTROL); 1106 1107 intel_host->needs_pwr_off = reg & SDHCI_POWER_ON; 1108 } 1109 1110 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 1111 { 1112 byt_probe_slot(slot); 1113 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | 1114 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE; 1115 slot->cd_idx = 0; 1116 slot->cd_override_level = true; 1117 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 1118 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 1119 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 1120 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) 1121 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 1122 1123 if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI && 1124 slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3) 1125 slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V; 1126 1127 byt_needs_pwr_off(slot); 1128 1129 return 0; 1130 } 1131 1132 #ifdef CONFIG_PM_SLEEP 1133 1134 static int byt_resume(struct sdhci_pci_chip *chip) 1135 { 1136 byt_ocp_setting(chip->pdev); 1137 1138 return sdhci_pci_resume_host(chip); 1139 } 1140 1141 #endif 1142 1143 #ifdef CONFIG_PM 1144 1145 static int byt_runtime_resume(struct sdhci_pci_chip *chip) 1146 { 1147 byt_ocp_setting(chip->pdev); 1148 1149 return sdhci_pci_runtime_resume_host(chip); 1150 } 1151 1152 #endif 1153 1154 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 1155 #ifdef CONFIG_PM_SLEEP 1156 .resume = byt_resume, 1157 #endif 1158 #ifdef CONFIG_PM 1159 .runtime_resume = byt_runtime_resume, 1160 #endif 1161 .allow_runtime_pm = true, 1162 .probe_slot = byt_emmc_probe_slot, 1163 .add_host = byt_add_host, 1164 .remove_slot = byt_remove_slot, 1165 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1166 SDHCI_QUIRK_NO_LED, 1167 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1168 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1169 SDHCI_QUIRK2_STOP_WITH_TC, 1170 .ops = &sdhci_intel_byt_ops, 1171 .priv_size = sizeof(struct intel_host), 1172 }; 1173 1174 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = { 1175 .allow_runtime_pm = true, 1176 .probe_slot = glk_emmc_probe_slot, 1177 .add_host = glk_emmc_add_host, 1178 .remove_slot = byt_remove_slot, 1179 #ifdef CONFIG_PM_SLEEP 1180 .suspend = sdhci_cqhci_suspend, 1181 .resume = sdhci_cqhci_resume, 1182 #endif 1183 #ifdef CONFIG_PM 1184 .runtime_suspend = glk_runtime_suspend, 1185 .runtime_resume = glk_runtime_resume, 1186 #endif 1187 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1188 SDHCI_QUIRK_NO_LED, 1189 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1190 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1191 SDHCI_QUIRK2_STOP_WITH_TC, 1192 .ops = &sdhci_intel_glk_ops, 1193 .priv_size = sizeof(struct intel_host), 1194 }; 1195 1196 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 1197 #ifdef CONFIG_PM_SLEEP 1198 .resume = byt_resume, 1199 #endif 1200 #ifdef CONFIG_PM 1201 .runtime_resume = byt_runtime_resume, 1202 #endif 1203 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1204 SDHCI_QUIRK_NO_LED, 1205 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1206 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1207 .allow_runtime_pm = true, 1208 .probe_slot = ni_byt_sdio_probe_slot, 1209 .add_host = byt_add_host, 1210 .remove_slot = byt_remove_slot, 1211 .ops = &sdhci_intel_byt_ops, 1212 .priv_size = sizeof(struct intel_host), 1213 }; 1214 1215 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 1216 #ifdef CONFIG_PM_SLEEP 1217 .resume = byt_resume, 1218 #endif 1219 #ifdef CONFIG_PM 1220 .runtime_resume = byt_runtime_resume, 1221 #endif 1222 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1223 SDHCI_QUIRK_NO_LED, 1224 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1225 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1226 .allow_runtime_pm = true, 1227 .probe_slot = byt_sdio_probe_slot, 1228 .add_host = byt_add_host, 1229 .remove_slot = byt_remove_slot, 1230 .ops = &sdhci_intel_byt_ops, 1231 .priv_size = sizeof(struct intel_host), 1232 }; 1233 1234 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 1235 #ifdef CONFIG_PM_SLEEP 1236 .resume = byt_resume, 1237 #endif 1238 #ifdef CONFIG_PM 1239 .runtime_resume = byt_runtime_resume, 1240 #endif 1241 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1242 SDHCI_QUIRK_NO_LED, 1243 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 1244 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1245 SDHCI_QUIRK2_STOP_WITH_TC, 1246 .allow_runtime_pm = true, 1247 .own_cd_for_runtime_pm = true, 1248 .probe_slot = byt_sd_probe_slot, 1249 .add_host = byt_add_host, 1250 .remove_slot = byt_remove_slot, 1251 .ops = &sdhci_intel_byt_ops, 1252 .priv_size = sizeof(struct intel_host), 1253 }; 1254 1255 /* Define Host controllers for Intel Merrifield platform */ 1256 #define INTEL_MRFLD_EMMC_0 0 1257 #define INTEL_MRFLD_EMMC_1 1 1258 #define INTEL_MRFLD_SD 2 1259 #define INTEL_MRFLD_SDIO 3 1260 1261 #ifdef CONFIG_ACPI 1262 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) 1263 { 1264 struct acpi_device *device; 1265 1266 device = ACPI_COMPANION(&slot->chip->pdev->dev); 1267 if (device) 1268 acpi_device_fix_up_power_extended(device); 1269 } 1270 #else 1271 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {} 1272 #endif 1273 1274 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 1275 { 1276 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 1277 1278 switch (func) { 1279 case INTEL_MRFLD_EMMC_0: 1280 case INTEL_MRFLD_EMMC_1: 1281 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1282 MMC_CAP_8_BIT_DATA | 1283 MMC_CAP_1_8V_DDR; 1284 break; 1285 case INTEL_MRFLD_SD: 1286 slot->cd_idx = 0; 1287 slot->cd_override_level = true; 1288 /* 1289 * There are two PCB designs of SD card slot with the opposite 1290 * card detection sense. Quirk this out by ignoring GPIO state 1291 * completely in the custom ->get_cd() callback. 1292 */ 1293 slot->host->mmc_host_ops.get_cd = mrfld_get_cd; 1294 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1295 break; 1296 case INTEL_MRFLD_SDIO: 1297 /* Advertise 2.0v for compatibility with the SDIO card's OCR */ 1298 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195; 1299 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1300 MMC_CAP_POWER_OFF_CARD; 1301 break; 1302 default: 1303 return -ENODEV; 1304 } 1305 1306 intel_mrfld_mmc_fix_up_power_slot(slot); 1307 return 0; 1308 } 1309 1310 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 1311 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1312 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 1313 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1314 .allow_runtime_pm = true, 1315 .probe_slot = intel_mrfld_mmc_probe_slot, 1316 }; 1317 1318 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 1319 { 1320 u8 scratch; 1321 int ret; 1322 1323 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 1324 if (ret) 1325 return ret; 1326 1327 /* 1328 * Turn PMOS on [bit 0], set over current detection to 2.4 V 1329 * [bit 1:2] and enable over current debouncing [bit 6]. 1330 */ 1331 if (on) 1332 scratch |= 0x47; 1333 else 1334 scratch &= ~0x47; 1335 1336 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 1337 } 1338 1339 static int jmicron_probe(struct sdhci_pci_chip *chip) 1340 { 1341 int ret; 1342 u16 mmcdev = 0; 1343 1344 if (chip->pdev->revision == 0) { 1345 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 1346 SDHCI_QUIRK_32BIT_DMA_SIZE | 1347 SDHCI_QUIRK_32BIT_ADMA_SIZE | 1348 SDHCI_QUIRK_RESET_AFTER_REQUEST | 1349 SDHCI_QUIRK_BROKEN_SMALL_PIO; 1350 } 1351 1352 /* 1353 * JMicron chips can have two interfaces to the same hardware 1354 * in order to work around limitations in Microsoft's driver. 1355 * We need to make sure we only bind to one of them. 1356 * 1357 * This code assumes two things: 1358 * 1359 * 1. The PCI code adds subfunctions in order. 1360 * 1361 * 2. The MMC interface has a lower subfunction number 1362 * than the SD interface. 1363 */ 1364 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 1365 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 1366 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 1367 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 1368 1369 if (mmcdev) { 1370 struct pci_dev *sd_dev; 1371 1372 sd_dev = NULL; 1373 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 1374 mmcdev, sd_dev)) != NULL) { 1375 if ((PCI_SLOT(chip->pdev->devfn) == 1376 PCI_SLOT(sd_dev->devfn)) && 1377 (chip->pdev->bus == sd_dev->bus)) 1378 break; 1379 } 1380 1381 if (sd_dev) { 1382 pci_dev_put(sd_dev); 1383 dev_info(&chip->pdev->dev, "Refusing to bind to " 1384 "secondary interface.\n"); 1385 return -ENODEV; 1386 } 1387 } 1388 1389 /* 1390 * JMicron chips need a bit of a nudge to enable the power 1391 * output pins. 1392 */ 1393 ret = jmicron_pmos(chip, 1); 1394 if (ret) { 1395 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1396 return ret; 1397 } 1398 1399 /* quirk for unsable RO-detection on JM388 chips */ 1400 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 1401 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1402 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 1403 1404 return 0; 1405 } 1406 1407 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 1408 { 1409 u8 scratch; 1410 1411 scratch = readb(host->ioaddr + 0xC0); 1412 1413 if (on) 1414 scratch |= 0x01; 1415 else 1416 scratch &= ~0x01; 1417 1418 writeb(scratch, host->ioaddr + 0xC0); 1419 } 1420 1421 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 1422 { 1423 if (slot->chip->pdev->revision == 0) { 1424 u16 version; 1425 1426 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 1427 version = (version & SDHCI_VENDOR_VER_MASK) >> 1428 SDHCI_VENDOR_VER_SHIFT; 1429 1430 /* 1431 * Older versions of the chip have lots of nasty glitches 1432 * in the ADMA engine. It's best just to avoid it 1433 * completely. 1434 */ 1435 if (version < 0xAC) 1436 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 1437 } 1438 1439 /* JM388 MMC doesn't support 1.8V while SD supports it */ 1440 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1441 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 1442 MMC_VDD_29_30 | MMC_VDD_30_31 | 1443 MMC_VDD_165_195; /* allow 1.8V */ 1444 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 1445 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 1446 } 1447 1448 /* 1449 * The secondary interface requires a bit set to get the 1450 * interrupts. 1451 */ 1452 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1453 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1454 jmicron_enable_mmc(slot->host, 1); 1455 1456 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 1457 1458 return 0; 1459 } 1460 1461 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 1462 { 1463 if (dead) 1464 return; 1465 1466 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1467 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1468 jmicron_enable_mmc(slot->host, 0); 1469 } 1470 1471 #ifdef CONFIG_PM_SLEEP 1472 static int jmicron_suspend(struct sdhci_pci_chip *chip) 1473 { 1474 int i, ret; 1475 1476 ret = sdhci_pci_suspend_host(chip); 1477 if (ret) 1478 return ret; 1479 1480 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1481 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1482 for (i = 0; i < chip->num_slots; i++) 1483 jmicron_enable_mmc(chip->slots[i]->host, 0); 1484 } 1485 1486 return 0; 1487 } 1488 1489 static int jmicron_resume(struct sdhci_pci_chip *chip) 1490 { 1491 int ret, i; 1492 1493 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1494 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1495 for (i = 0; i < chip->num_slots; i++) 1496 jmicron_enable_mmc(chip->slots[i]->host, 1); 1497 } 1498 1499 ret = jmicron_pmos(chip, 1); 1500 if (ret) { 1501 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1502 return ret; 1503 } 1504 1505 return sdhci_pci_resume_host(chip); 1506 } 1507 #endif 1508 1509 static const struct sdhci_pci_fixes sdhci_jmicron = { 1510 .probe = jmicron_probe, 1511 1512 .probe_slot = jmicron_probe_slot, 1513 .remove_slot = jmicron_remove_slot, 1514 1515 #ifdef CONFIG_PM_SLEEP 1516 .suspend = jmicron_suspend, 1517 .resume = jmicron_resume, 1518 #endif 1519 }; 1520 1521 /* SysKonnect CardBus2SDIO extra registers */ 1522 #define SYSKT_CTRL 0x200 1523 #define SYSKT_RDFIFO_STAT 0x204 1524 #define SYSKT_WRFIFO_STAT 0x208 1525 #define SYSKT_POWER_DATA 0x20c 1526 #define SYSKT_POWER_330 0xef 1527 #define SYSKT_POWER_300 0xf8 1528 #define SYSKT_POWER_184 0xcc 1529 #define SYSKT_POWER_CMD 0x20d 1530 #define SYSKT_POWER_START (1 << 7) 1531 #define SYSKT_POWER_STATUS 0x20e 1532 #define SYSKT_POWER_STATUS_OK (1 << 0) 1533 #define SYSKT_BOARD_REV 0x210 1534 #define SYSKT_CHIP_REV 0x211 1535 #define SYSKT_CONF_DATA 0x212 1536 #define SYSKT_CONF_DATA_1V8 (1 << 2) 1537 #define SYSKT_CONF_DATA_2V5 (1 << 1) 1538 #define SYSKT_CONF_DATA_3V3 (1 << 0) 1539 1540 static int syskt_probe(struct sdhci_pci_chip *chip) 1541 { 1542 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1543 chip->pdev->class &= ~0x0000FF; 1544 chip->pdev->class |= PCI_SDHCI_IFDMA; 1545 } 1546 return 0; 1547 } 1548 1549 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 1550 { 1551 int tm, ps; 1552 1553 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 1554 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 1555 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 1556 "board rev %d.%d, chip rev %d.%d\n", 1557 board_rev >> 4, board_rev & 0xf, 1558 chip_rev >> 4, chip_rev & 0xf); 1559 if (chip_rev >= 0x20) 1560 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 1561 1562 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 1563 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 1564 udelay(50); 1565 tm = 10; /* Wait max 1 ms */ 1566 do { 1567 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 1568 if (ps & SYSKT_POWER_STATUS_OK) 1569 break; 1570 udelay(100); 1571 } while (--tm); 1572 if (!tm) { 1573 dev_err(&slot->chip->pdev->dev, 1574 "power regulator never stabilized"); 1575 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 1576 return -ENODEV; 1577 } 1578 1579 return 0; 1580 } 1581 1582 static const struct sdhci_pci_fixes sdhci_syskt = { 1583 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 1584 .probe = syskt_probe, 1585 .probe_slot = syskt_probe_slot, 1586 }; 1587 1588 static int via_probe(struct sdhci_pci_chip *chip) 1589 { 1590 if (chip->pdev->revision == 0x10) 1591 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 1592 1593 return 0; 1594 } 1595 1596 static const struct sdhci_pci_fixes sdhci_via = { 1597 .probe = via_probe, 1598 }; 1599 1600 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 1601 { 1602 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 1603 return 0; 1604 } 1605 1606 static const struct sdhci_pci_fixes sdhci_rtsx = { 1607 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1608 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 1609 SDHCI_QUIRK2_BROKEN_DDR50, 1610 .probe_slot = rtsx_probe_slot, 1611 }; 1612 1613 /*AMD chipset generation*/ 1614 enum amd_chipset_gen { 1615 AMD_CHIPSET_BEFORE_ML, 1616 AMD_CHIPSET_CZ, 1617 AMD_CHIPSET_NL, 1618 AMD_CHIPSET_UNKNOWN, 1619 }; 1620 1621 /* AMD registers */ 1622 #define AMD_SD_AUTO_PATTERN 0xB8 1623 #define AMD_MSLEEP_DURATION 4 1624 #define AMD_SD_MISC_CONTROL 0xD0 1625 #define AMD_MAX_TUNE_VALUE 0x0B 1626 #define AMD_AUTO_TUNE_SEL 0x10800 1627 #define AMD_FIFO_PTR 0x30 1628 #define AMD_BIT_MASK 0x1F 1629 1630 static void amd_tuning_reset(struct sdhci_host *host) 1631 { 1632 unsigned int val; 1633 1634 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1635 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 1636 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1637 1638 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1639 val &= ~SDHCI_CTRL_EXEC_TUNING; 1640 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1641 } 1642 1643 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 1644 { 1645 unsigned int val; 1646 1647 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 1648 val &= ~AMD_BIT_MASK; 1649 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 1650 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 1651 } 1652 1653 static void amd_enable_manual_tuning(struct pci_dev *pdev) 1654 { 1655 unsigned int val; 1656 1657 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 1658 val |= AMD_FIFO_PTR; 1659 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 1660 } 1661 1662 static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode) 1663 { 1664 struct sdhci_pci_slot *slot = sdhci_priv(host); 1665 struct pci_dev *pdev = slot->chip->pdev; 1666 u8 valid_win = 0; 1667 u8 valid_win_max = 0; 1668 u8 valid_win_end = 0; 1669 u8 ctrl, tune_around; 1670 1671 amd_tuning_reset(host); 1672 1673 for (tune_around = 0; tune_around < 12; tune_around++) { 1674 amd_config_tuning_phase(pdev, tune_around); 1675 1676 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1677 valid_win = 0; 1678 msleep(AMD_MSLEEP_DURATION); 1679 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 1680 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 1681 } else if (++valid_win > valid_win_max) { 1682 valid_win_max = valid_win; 1683 valid_win_end = tune_around; 1684 } 1685 } 1686 1687 if (!valid_win_max) { 1688 dev_err(&pdev->dev, "no tuning point found\n"); 1689 return -EIO; 1690 } 1691 1692 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 1693 1694 amd_enable_manual_tuning(pdev); 1695 1696 host->mmc->retune_period = 0; 1697 1698 return 0; 1699 } 1700 1701 static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode) 1702 { 1703 struct sdhci_host *host = mmc_priv(mmc); 1704 1705 /* AMD requires custom HS200 tuning */ 1706 if (host->timing == MMC_TIMING_MMC_HS200) 1707 return amd_execute_tuning_hs200(host, opcode); 1708 1709 /* Otherwise perform standard SDHCI tuning */ 1710 return sdhci_execute_tuning(mmc, opcode); 1711 } 1712 1713 static int amd_probe_slot(struct sdhci_pci_slot *slot) 1714 { 1715 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 1716 1717 ops->execute_tuning = amd_execute_tuning; 1718 1719 return 0; 1720 } 1721 1722 static int amd_probe(struct sdhci_pci_chip *chip) 1723 { 1724 struct pci_dev *smbus_dev; 1725 enum amd_chipset_gen gen; 1726 1727 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1728 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 1729 if (smbus_dev) { 1730 gen = AMD_CHIPSET_BEFORE_ML; 1731 } else { 1732 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1733 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1734 if (smbus_dev) { 1735 if (smbus_dev->revision < 0x51) 1736 gen = AMD_CHIPSET_CZ; 1737 else 1738 gen = AMD_CHIPSET_NL; 1739 } else { 1740 gen = AMD_CHIPSET_UNKNOWN; 1741 } 1742 } 1743 1744 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1745 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1746 1747 return 0; 1748 } 1749 1750 static u32 sdhci_read_present_state(struct sdhci_host *host) 1751 { 1752 return sdhci_readl(host, SDHCI_PRESENT_STATE); 1753 } 1754 1755 static void amd_sdhci_reset(struct sdhci_host *host, u8 mask) 1756 { 1757 struct sdhci_pci_slot *slot = sdhci_priv(host); 1758 struct pci_dev *pdev = slot->chip->pdev; 1759 u32 present_state; 1760 1761 /* 1762 * SDHC 0x7906 requires a hard reset to clear all internal state. 1763 * Otherwise it can get into a bad state where the DATA lines are always 1764 * read as zeros. 1765 */ 1766 if (pdev->device == 0x7906 && (mask & SDHCI_RESET_ALL)) { 1767 pci_clear_master(pdev); 1768 1769 pci_save_state(pdev); 1770 1771 pci_set_power_state(pdev, PCI_D3cold); 1772 pr_debug("%s: power_state=%u\n", mmc_hostname(host->mmc), 1773 pdev->current_state); 1774 pci_set_power_state(pdev, PCI_D0); 1775 1776 pci_restore_state(pdev); 1777 1778 /* 1779 * SDHCI_RESET_ALL says the card detect logic should not be 1780 * reset, but since we need to reset the entire controller 1781 * we should wait until the card detect logic has stabilized. 1782 * 1783 * This normally takes about 40ms. 1784 */ 1785 readx_poll_timeout( 1786 sdhci_read_present_state, 1787 host, 1788 present_state, 1789 present_state & SDHCI_CD_STABLE, 1790 10000, 1791 100000 1792 ); 1793 } 1794 1795 return sdhci_reset(host, mask); 1796 } 1797 1798 static const struct sdhci_ops amd_sdhci_pci_ops = { 1799 .set_clock = sdhci_set_clock, 1800 .enable_dma = sdhci_pci_enable_dma, 1801 .set_bus_width = sdhci_set_bus_width, 1802 .reset = amd_sdhci_reset, 1803 .set_uhs_signaling = sdhci_set_uhs_signaling, 1804 }; 1805 1806 static const struct sdhci_pci_fixes sdhci_amd = { 1807 .probe = amd_probe, 1808 .ops = &amd_sdhci_pci_ops, 1809 .probe_slot = amd_probe_slot, 1810 }; 1811 1812 static const struct pci_device_id pci_ids[] = { 1813 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh), 1814 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc), 1815 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc), 1816 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc), 1817 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712), 1818 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712), 1819 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714), 1820 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714), 1821 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe), 1822 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron), 1823 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron), 1824 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron), 1825 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron), 1826 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt), 1827 SDHCI_PCI_DEVICE(VIA, 95D0, via), 1828 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx), 1829 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk), 1830 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0), 1831 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2), 1832 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2), 1833 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd), 1834 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio), 1835 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio), 1836 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc), 1837 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc), 1838 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio), 1839 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio), 1840 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc), 1841 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio), 1842 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio), 1843 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd), 1844 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc), 1845 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc), 1846 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio), 1847 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd), 1848 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd), 1849 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio), 1850 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio), 1851 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc), 1852 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc), 1853 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc), 1854 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc), 1855 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio), 1856 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd), 1857 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc), 1858 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc), 1859 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc), 1860 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio), 1861 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd), 1862 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc), 1863 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio), 1864 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd), 1865 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc), 1866 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio), 1867 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd), 1868 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc), 1869 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio), 1870 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd), 1871 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc), 1872 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd), 1873 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd), 1874 SDHCI_PCI_DEVICE(INTEL, ICP_EMMC, intel_glk_emmc), 1875 SDHCI_PCI_DEVICE(INTEL, ICP_SD, intel_byt_sd), 1876 SDHCI_PCI_DEVICE(INTEL, EHL_EMMC, intel_glk_emmc), 1877 SDHCI_PCI_DEVICE(INTEL, EHL_SD, intel_byt_sd), 1878 SDHCI_PCI_DEVICE(INTEL, CML_EMMC, intel_glk_emmc), 1879 SDHCI_PCI_DEVICE(INTEL, CML_SD, intel_byt_sd), 1880 SDHCI_PCI_DEVICE(INTEL, CMLH_SD, intel_byt_sd), 1881 SDHCI_PCI_DEVICE(INTEL, JSL_EMMC, intel_glk_emmc), 1882 SDHCI_PCI_DEVICE(INTEL, JSL_SD, intel_byt_sd), 1883 SDHCI_PCI_DEVICE(INTEL, LKF_EMMC, intel_glk_emmc), 1884 SDHCI_PCI_DEVICE(INTEL, LKF_SD, intel_byt_sd), 1885 SDHCI_PCI_DEVICE(INTEL, ADL_EMMC, intel_glk_emmc), 1886 SDHCI_PCI_DEVICE(O2, 8120, o2), 1887 SDHCI_PCI_DEVICE(O2, 8220, o2), 1888 SDHCI_PCI_DEVICE(O2, 8221, o2), 1889 SDHCI_PCI_DEVICE(O2, 8320, o2), 1890 SDHCI_PCI_DEVICE(O2, 8321, o2), 1891 SDHCI_PCI_DEVICE(O2, FUJIN2, o2), 1892 SDHCI_PCI_DEVICE(O2, SDS0, o2), 1893 SDHCI_PCI_DEVICE(O2, SDS1, o2), 1894 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2), 1895 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), 1896 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan), 1897 SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps), 1898 SDHCI_PCI_DEVICE(GLI, 9750, gl9750), 1899 SDHCI_PCI_DEVICE(GLI, 9755, gl9755), 1900 SDHCI_PCI_DEVICE(GLI, 9763E, gl9763e), 1901 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), 1902 /* Generic SD host controller */ 1903 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, 1904 { /* end: all zeroes */ }, 1905 }; 1906 1907 MODULE_DEVICE_TABLE(pci, pci_ids); 1908 1909 /*****************************************************************************\ 1910 * * 1911 * SDHCI core callbacks * 1912 * * 1913 \*****************************************************************************/ 1914 1915 int sdhci_pci_enable_dma(struct sdhci_host *host) 1916 { 1917 struct sdhci_pci_slot *slot; 1918 struct pci_dev *pdev; 1919 1920 slot = sdhci_priv(host); 1921 pdev = slot->chip->pdev; 1922 1923 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1924 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1925 (host->flags & SDHCI_USE_SDMA)) { 1926 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1927 "doesn't fully claim to support it.\n"); 1928 } 1929 1930 pci_set_master(pdev); 1931 1932 return 0; 1933 } 1934 1935 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1936 { 1937 struct sdhci_pci_slot *slot = sdhci_priv(host); 1938 1939 if (slot->hw_reset) 1940 slot->hw_reset(host); 1941 } 1942 1943 static const struct sdhci_ops sdhci_pci_ops = { 1944 .set_clock = sdhci_set_clock, 1945 .enable_dma = sdhci_pci_enable_dma, 1946 .set_bus_width = sdhci_set_bus_width, 1947 .reset = sdhci_reset, 1948 .set_uhs_signaling = sdhci_set_uhs_signaling, 1949 .hw_reset = sdhci_pci_hw_reset, 1950 }; 1951 1952 /*****************************************************************************\ 1953 * * 1954 * Suspend/resume * 1955 * * 1956 \*****************************************************************************/ 1957 1958 #ifdef CONFIG_PM_SLEEP 1959 static int sdhci_pci_suspend(struct device *dev) 1960 { 1961 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 1962 1963 if (!chip) 1964 return 0; 1965 1966 if (chip->fixes && chip->fixes->suspend) 1967 return chip->fixes->suspend(chip); 1968 1969 return sdhci_pci_suspend_host(chip); 1970 } 1971 1972 static int sdhci_pci_resume(struct device *dev) 1973 { 1974 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 1975 1976 if (!chip) 1977 return 0; 1978 1979 if (chip->fixes && chip->fixes->resume) 1980 return chip->fixes->resume(chip); 1981 1982 return sdhci_pci_resume_host(chip); 1983 } 1984 #endif 1985 1986 #ifdef CONFIG_PM 1987 static int sdhci_pci_runtime_suspend(struct device *dev) 1988 { 1989 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 1990 1991 if (!chip) 1992 return 0; 1993 1994 if (chip->fixes && chip->fixes->runtime_suspend) 1995 return chip->fixes->runtime_suspend(chip); 1996 1997 return sdhci_pci_runtime_suspend_host(chip); 1998 } 1999 2000 static int sdhci_pci_runtime_resume(struct device *dev) 2001 { 2002 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2003 2004 if (!chip) 2005 return 0; 2006 2007 if (chip->fixes && chip->fixes->runtime_resume) 2008 return chip->fixes->runtime_resume(chip); 2009 2010 return sdhci_pci_runtime_resume_host(chip); 2011 } 2012 #endif 2013 2014 static const struct dev_pm_ops sdhci_pci_pm_ops = { 2015 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 2016 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 2017 sdhci_pci_runtime_resume, NULL) 2018 }; 2019 2020 /*****************************************************************************\ 2021 * * 2022 * Device probing/removal * 2023 * * 2024 \*****************************************************************************/ 2025 2026 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 2027 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 2028 int slotno) 2029 { 2030 struct sdhci_pci_slot *slot; 2031 struct sdhci_host *host; 2032 int ret, bar = first_bar + slotno; 2033 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 2034 2035 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 2036 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 2037 return ERR_PTR(-ENODEV); 2038 } 2039 2040 if (pci_resource_len(pdev, bar) < 0x100) { 2041 dev_err(&pdev->dev, "Invalid iomem size. You may " 2042 "experience problems.\n"); 2043 } 2044 2045 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 2046 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 2047 return ERR_PTR(-ENODEV); 2048 } 2049 2050 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 2051 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 2052 return ERR_PTR(-ENODEV); 2053 } 2054 2055 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 2056 if (IS_ERR(host)) { 2057 dev_err(&pdev->dev, "cannot allocate host\n"); 2058 return ERR_CAST(host); 2059 } 2060 2061 slot = sdhci_priv(host); 2062 2063 slot->chip = chip; 2064 slot->host = host; 2065 slot->cd_idx = -1; 2066 2067 host->hw_name = "PCI"; 2068 host->ops = chip->fixes && chip->fixes->ops ? 2069 chip->fixes->ops : 2070 &sdhci_pci_ops; 2071 host->quirks = chip->quirks; 2072 host->quirks2 = chip->quirks2; 2073 2074 host->irq = pdev->irq; 2075 2076 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 2077 if (ret) { 2078 dev_err(&pdev->dev, "cannot request region\n"); 2079 goto cleanup; 2080 } 2081 2082 host->ioaddr = pcim_iomap_table(pdev)[bar]; 2083 2084 if (chip->fixes && chip->fixes->probe_slot) { 2085 ret = chip->fixes->probe_slot(slot); 2086 if (ret) 2087 goto cleanup; 2088 } 2089 2090 host->mmc->pm_caps = MMC_PM_KEEP_POWER; 2091 host->mmc->slotno = slotno; 2092 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 2093 2094 if (device_can_wakeup(&pdev->dev)) 2095 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ; 2096 2097 if (host->mmc->caps & MMC_CAP_CD_WAKE) 2098 device_init_wakeup(&pdev->dev, true); 2099 2100 if (slot->cd_idx >= 0) { 2101 ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx, 2102 slot->cd_override_level, 0); 2103 if (ret && ret != -EPROBE_DEFER) 2104 ret = mmc_gpiod_request_cd(host->mmc, NULL, 2105 slot->cd_idx, 2106 slot->cd_override_level, 2107 0); 2108 if (ret == -EPROBE_DEFER) 2109 goto remove; 2110 2111 if (ret) { 2112 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 2113 slot->cd_idx = -1; 2114 } 2115 } 2116 2117 if (chip->fixes && chip->fixes->add_host) 2118 ret = chip->fixes->add_host(slot); 2119 else 2120 ret = sdhci_add_host(host); 2121 if (ret) 2122 goto remove; 2123 2124 /* 2125 * Check if the chip needs a separate GPIO for card detect to wake up 2126 * from runtime suspend. If it is not there, don't allow runtime PM. 2127 */ 2128 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && slot->cd_idx < 0) 2129 chip->allow_runtime_pm = false; 2130 2131 return slot; 2132 2133 remove: 2134 if (chip->fixes && chip->fixes->remove_slot) 2135 chip->fixes->remove_slot(slot, 0); 2136 2137 cleanup: 2138 sdhci_free_host(host); 2139 2140 return ERR_PTR(ret); 2141 } 2142 2143 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 2144 { 2145 int dead; 2146 u32 scratch; 2147 2148 dead = 0; 2149 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 2150 if (scratch == (u32)-1) 2151 dead = 1; 2152 2153 sdhci_remove_host(slot->host, dead); 2154 2155 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 2156 slot->chip->fixes->remove_slot(slot, dead); 2157 2158 sdhci_free_host(slot->host); 2159 } 2160 2161 static void sdhci_pci_runtime_pm_allow(struct device *dev) 2162 { 2163 pm_suspend_ignore_children(dev, 1); 2164 pm_runtime_set_autosuspend_delay(dev, 50); 2165 pm_runtime_use_autosuspend(dev); 2166 pm_runtime_allow(dev); 2167 /* Stay active until mmc core scans for a card */ 2168 pm_runtime_put_noidle(dev); 2169 } 2170 2171 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 2172 { 2173 pm_runtime_forbid(dev); 2174 pm_runtime_get_noresume(dev); 2175 } 2176 2177 static int sdhci_pci_probe(struct pci_dev *pdev, 2178 const struct pci_device_id *ent) 2179 { 2180 struct sdhci_pci_chip *chip; 2181 struct sdhci_pci_slot *slot; 2182 2183 u8 slots, first_bar; 2184 int ret, i; 2185 2186 BUG_ON(pdev == NULL); 2187 BUG_ON(ent == NULL); 2188 2189 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 2190 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 2191 2192 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 2193 if (ret) 2194 return ret; 2195 2196 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 2197 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 2198 2199 BUG_ON(slots > MAX_SLOTS); 2200 2201 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 2202 if (ret) 2203 return ret; 2204 2205 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 2206 2207 if (first_bar > 5) { 2208 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 2209 return -ENODEV; 2210 } 2211 2212 ret = pcim_enable_device(pdev); 2213 if (ret) 2214 return ret; 2215 2216 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 2217 if (!chip) 2218 return -ENOMEM; 2219 2220 chip->pdev = pdev; 2221 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 2222 if (chip->fixes) { 2223 chip->quirks = chip->fixes->quirks; 2224 chip->quirks2 = chip->fixes->quirks2; 2225 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 2226 } 2227 chip->num_slots = slots; 2228 chip->pm_retune = true; 2229 chip->rpm_retune = true; 2230 2231 pci_set_drvdata(pdev, chip); 2232 2233 if (chip->fixes && chip->fixes->probe) { 2234 ret = chip->fixes->probe(chip); 2235 if (ret) 2236 return ret; 2237 } 2238 2239 slots = chip->num_slots; /* Quirk may have changed this */ 2240 2241 for (i = 0; i < slots; i++) { 2242 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 2243 if (IS_ERR(slot)) { 2244 for (i--; i >= 0; i--) 2245 sdhci_pci_remove_slot(chip->slots[i]); 2246 return PTR_ERR(slot); 2247 } 2248 2249 chip->slots[i] = slot; 2250 } 2251 2252 if (chip->allow_runtime_pm) 2253 sdhci_pci_runtime_pm_allow(&pdev->dev); 2254 2255 return 0; 2256 } 2257 2258 static void sdhci_pci_remove(struct pci_dev *pdev) 2259 { 2260 int i; 2261 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 2262 2263 if (chip->allow_runtime_pm) 2264 sdhci_pci_runtime_pm_forbid(&pdev->dev); 2265 2266 for (i = 0; i < chip->num_slots; i++) 2267 sdhci_pci_remove_slot(chip->slots[i]); 2268 } 2269 2270 static struct pci_driver sdhci_driver = { 2271 .name = "sdhci-pci", 2272 .id_table = pci_ids, 2273 .probe = sdhci_pci_probe, 2274 .remove = sdhci_pci_remove, 2275 .driver = { 2276 .pm = &sdhci_pci_pm_ops 2277 }, 2278 }; 2279 2280 module_pci_driver(sdhci_driver); 2281 2282 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 2283 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 2284 MODULE_LICENSE("GPL"); 2285