1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 2 * 3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 * 10 * Thanks to the following companies for their support: 11 * 12 * - JMicron (hardware and technical support) 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/highmem.h> 17 #include <linux/module.h> 18 #include <linux/pci.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/slab.h> 21 #include <linux/device.h> 22 #include <linux/mmc/host.h> 23 #include <linux/mmc/mmc.h> 24 #include <linux/scatterlist.h> 25 #include <linux/io.h> 26 #include <linux/gpio.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/mmc/slot-gpio.h> 29 #include <linux/mmc/sdhci-pci-data.h> 30 31 #include "sdhci.h" 32 #include "sdhci-pci.h" 33 #include "sdhci-pci-o2micro.h" 34 35 static int sdhci_pci_enable_dma(struct sdhci_host *host); 36 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width); 37 static void sdhci_pci_hw_reset(struct sdhci_host *host); 38 static int sdhci_pci_select_drive_strength(struct sdhci_host *host, 39 struct mmc_card *card, 40 unsigned int max_dtr, int host_drv, 41 int card_drv, int *drv_type); 42 43 /*****************************************************************************\ 44 * * 45 * Hardware specific quirk handling * 46 * * 47 \*****************************************************************************/ 48 49 static int ricoh_probe(struct sdhci_pci_chip *chip) 50 { 51 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 52 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 53 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 54 return 0; 55 } 56 57 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 58 { 59 slot->host->caps = 60 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 61 & SDHCI_TIMEOUT_CLK_MASK) | 62 63 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 64 & SDHCI_CLOCK_BASE_MASK) | 65 66 SDHCI_TIMEOUT_CLK_UNIT | 67 SDHCI_CAN_VDD_330 | 68 SDHCI_CAN_DO_HISPD | 69 SDHCI_CAN_DO_SDMA; 70 return 0; 71 } 72 73 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 74 { 75 /* Apply a delay to allow controller to settle */ 76 /* Otherwise it becomes confused if card state changed 77 during suspend */ 78 msleep(500); 79 return 0; 80 } 81 82 static const struct sdhci_pci_fixes sdhci_ricoh = { 83 .probe = ricoh_probe, 84 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 85 SDHCI_QUIRK_FORCE_DMA | 86 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 87 }; 88 89 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 90 .probe_slot = ricoh_mmc_probe_slot, 91 .resume = ricoh_mmc_resume, 92 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 93 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 94 SDHCI_QUIRK_NO_CARD_NO_RESET | 95 SDHCI_QUIRK_MISSING_CAPS 96 }; 97 98 static const struct sdhci_pci_fixes sdhci_ene_712 = { 99 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 100 SDHCI_QUIRK_BROKEN_DMA, 101 }; 102 103 static const struct sdhci_pci_fixes sdhci_ene_714 = { 104 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 105 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 106 SDHCI_QUIRK_BROKEN_DMA, 107 }; 108 109 static const struct sdhci_pci_fixes sdhci_cafe = { 110 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 111 SDHCI_QUIRK_NO_BUSY_IRQ | 112 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 113 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 114 }; 115 116 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 117 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 118 }; 119 120 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 121 { 122 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 123 return 0; 124 } 125 126 /* 127 * ADMA operation is disabled for Moorestown platform due to 128 * hardware bugs. 129 */ 130 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 131 { 132 /* 133 * slots number is fixed here for MRST as SDIO3/5 are never used and 134 * have hardware bugs. 135 */ 136 chip->num_slots = 1; 137 return 0; 138 } 139 140 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 141 { 142 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 143 return 0; 144 } 145 146 #ifdef CONFIG_PM 147 148 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 149 { 150 struct sdhci_pci_slot *slot = dev_id; 151 struct sdhci_host *host = slot->host; 152 153 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 154 return IRQ_HANDLED; 155 } 156 157 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 158 { 159 int err, irq, gpio = slot->cd_gpio; 160 161 slot->cd_gpio = -EINVAL; 162 slot->cd_irq = -EINVAL; 163 164 if (!gpio_is_valid(gpio)) 165 return; 166 167 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 168 if (err < 0) 169 goto out; 170 171 err = gpio_direction_input(gpio); 172 if (err < 0) 173 goto out_free; 174 175 irq = gpio_to_irq(gpio); 176 if (irq < 0) 177 goto out_free; 178 179 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 180 IRQF_TRIGGER_FALLING, "sd_cd", slot); 181 if (err) 182 goto out_free; 183 184 slot->cd_gpio = gpio; 185 slot->cd_irq = irq; 186 187 return; 188 189 out_free: 190 devm_gpio_free(&slot->chip->pdev->dev, gpio); 191 out: 192 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 193 } 194 195 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 196 { 197 if (slot->cd_irq >= 0) 198 free_irq(slot->cd_irq, slot); 199 } 200 201 #else 202 203 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 204 { 205 } 206 207 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 208 { 209 } 210 211 #endif 212 213 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 214 { 215 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 216 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC | 217 MMC_CAP2_HC_ERASE_SZ; 218 return 0; 219 } 220 221 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 222 { 223 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 224 return 0; 225 } 226 227 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 228 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 229 .probe_slot = mrst_hc_probe_slot, 230 }; 231 232 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 233 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 234 .probe = mrst_hc_probe, 235 }; 236 237 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 238 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 239 .allow_runtime_pm = true, 240 .own_cd_for_runtime_pm = true, 241 }; 242 243 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 244 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 245 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 246 .allow_runtime_pm = true, 247 .probe_slot = mfd_sdio_probe_slot, 248 }; 249 250 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 251 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 252 .allow_runtime_pm = true, 253 .probe_slot = mfd_emmc_probe_slot, 254 }; 255 256 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 257 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 258 .probe_slot = pch_hc_probe_slot, 259 }; 260 261 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 262 { 263 u8 reg; 264 265 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 266 reg |= 0x10; 267 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 268 /* For eMMC, minimum is 1us but give it 9us for good measure */ 269 udelay(9); 270 reg &= ~0x10; 271 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 272 /* For eMMC, minimum is 200us but give it 300us for good measure */ 273 usleep_range(300, 1000); 274 } 275 276 static int spt_select_drive_strength(struct sdhci_host *host, 277 struct mmc_card *card, 278 unsigned int max_dtr, 279 int host_drv, int card_drv, int *drv_type) 280 { 281 int drive_strength; 282 283 if (sdhci_pci_spt_drive_strength > 0) 284 drive_strength = sdhci_pci_spt_drive_strength & 0xf; 285 else 286 drive_strength = 0; /* Default 50-ohm */ 287 288 if ((mmc_driver_type_mask(drive_strength) & card_drv) == 0) 289 drive_strength = 0; /* Default 50-ohm */ 290 291 return drive_strength; 292 } 293 294 /* Try to read the drive strength from the card */ 295 static void spt_read_drive_strength(struct sdhci_host *host) 296 { 297 u32 val, i, t; 298 u16 m; 299 300 if (sdhci_pci_spt_drive_strength) 301 return; 302 303 sdhci_pci_spt_drive_strength = -1; 304 305 m = sdhci_readw(host, SDHCI_HOST_CONTROL2) & 0x7; 306 if (m != 3 && m != 5) 307 return; 308 val = sdhci_readl(host, SDHCI_PRESENT_STATE); 309 if (val & 0x3) 310 return; 311 sdhci_writel(host, 0x007f0023, SDHCI_INT_ENABLE); 312 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 313 sdhci_writew(host, 0x10, SDHCI_TRANSFER_MODE); 314 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 315 sdhci_writew(host, 512, SDHCI_BLOCK_SIZE); 316 sdhci_writew(host, 1, SDHCI_BLOCK_COUNT); 317 sdhci_writel(host, 0, SDHCI_ARGUMENT); 318 sdhci_writew(host, 0x83b, SDHCI_COMMAND); 319 for (i = 0; i < 1000; i++) { 320 val = sdhci_readl(host, SDHCI_INT_STATUS); 321 if (val & 0xffff8000) 322 return; 323 if (val & 0x20) 324 break; 325 udelay(1); 326 } 327 val = sdhci_readl(host, SDHCI_PRESENT_STATE); 328 if (!(val & 0x800)) 329 return; 330 for (i = 0; i < 47; i++) 331 val = sdhci_readl(host, SDHCI_BUFFER); 332 t = val & 0xf00; 333 if (t != 0x200 && t != 0x300) 334 return; 335 336 sdhci_pci_spt_drive_strength = 0x10 | ((val >> 12) & 0xf); 337 } 338 339 static int bxt_get_cd(struct mmc_host *mmc) 340 { 341 int gpio_cd = mmc_gpio_get_cd(mmc); 342 struct sdhci_host *host = mmc_priv(mmc); 343 unsigned long flags; 344 int ret = 0; 345 346 if (!gpio_cd) 347 return 0; 348 349 spin_lock_irqsave(&host->lock, flags); 350 351 if (host->flags & SDHCI_DEVICE_DEAD) 352 goto out; 353 354 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 355 out: 356 spin_unlock_irqrestore(&host->lock, flags); 357 358 return ret; 359 } 360 361 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 362 { 363 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 364 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 365 MMC_CAP_CMD_DURING_TFR | 366 MMC_CAP_WAIT_WHILE_BUSY; 367 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ; 368 slot->hw_reset = sdhci_pci_int_hw_reset; 369 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 370 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 371 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_SPT_EMMC) { 372 spt_read_drive_strength(slot->host); 373 slot->select_drive_strength = spt_select_drive_strength; 374 } 375 return 0; 376 } 377 378 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 379 { 380 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 381 MMC_CAP_WAIT_WHILE_BUSY; 382 return 0; 383 } 384 385 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 386 { 387 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 388 slot->cd_con_id = NULL; 389 slot->cd_idx = 0; 390 slot->cd_override_level = true; 391 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 392 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 393 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD) { 394 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 395 slot->host->mmc->caps |= MMC_CAP_AGGRESSIVE_PM; 396 } 397 398 return 0; 399 } 400 401 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 402 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 403 404 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 405 unsigned short vdd) 406 { 407 int cntr; 408 u8 reg; 409 410 sdhci_set_power(host, mode, vdd); 411 412 if (mode == MMC_POWER_OFF) 413 return; 414 415 /* 416 * Bus power might not enable after D3 -> D0 transition due to the 417 * present state not yet having propagated. Retry for up to 2ms. 418 */ 419 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 420 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 421 if (reg & SDHCI_POWER_ON) 422 break; 423 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 424 reg |= SDHCI_POWER_ON; 425 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 426 } 427 } 428 429 static const struct sdhci_ops sdhci_intel_byt_ops = { 430 .set_clock = sdhci_set_clock, 431 .set_power = sdhci_intel_set_power, 432 .enable_dma = sdhci_pci_enable_dma, 433 .set_bus_width = sdhci_pci_set_bus_width, 434 .reset = sdhci_reset, 435 .set_uhs_signaling = sdhci_set_uhs_signaling, 436 .hw_reset = sdhci_pci_hw_reset, 437 .select_drive_strength = sdhci_pci_select_drive_strength, 438 }; 439 440 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 441 .allow_runtime_pm = true, 442 .probe_slot = byt_emmc_probe_slot, 443 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 444 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 445 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 446 SDHCI_QUIRK2_STOP_WITH_TC, 447 .ops = &sdhci_intel_byt_ops, 448 }; 449 450 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 451 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 452 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 453 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 454 .allow_runtime_pm = true, 455 .probe_slot = byt_sdio_probe_slot, 456 .ops = &sdhci_intel_byt_ops, 457 }; 458 459 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 460 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 461 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 462 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 463 SDHCI_QUIRK2_STOP_WITH_TC, 464 .allow_runtime_pm = true, 465 .own_cd_for_runtime_pm = true, 466 .probe_slot = byt_sd_probe_slot, 467 .ops = &sdhci_intel_byt_ops, 468 }; 469 470 /* Define Host controllers for Intel Merrifield platform */ 471 #define INTEL_MRFLD_EMMC_0 0 472 #define INTEL_MRFLD_EMMC_1 1 473 #define INTEL_MRFLD_SD 2 474 #define INTEL_MRFLD_SDIO 3 475 476 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 477 { 478 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 479 480 switch (func) { 481 case INTEL_MRFLD_EMMC_0: 482 case INTEL_MRFLD_EMMC_1: 483 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 484 MMC_CAP_8_BIT_DATA | 485 MMC_CAP_1_8V_DDR; 486 break; 487 case INTEL_MRFLD_SD: 488 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 489 break; 490 case INTEL_MRFLD_SDIO: 491 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 492 MMC_CAP_POWER_OFF_CARD; 493 break; 494 default: 495 return -ENODEV; 496 } 497 return 0; 498 } 499 500 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 501 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 502 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 503 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 504 .allow_runtime_pm = true, 505 .probe_slot = intel_mrfld_mmc_probe_slot, 506 }; 507 508 /* O2Micro extra registers */ 509 #define O2_SD_LOCK_WP 0xD3 510 #define O2_SD_MULTI_VCC3V 0xEE 511 #define O2_SD_CLKREQ 0xEC 512 #define O2_SD_CAPS 0xE0 513 #define O2_SD_ADMA1 0xE2 514 #define O2_SD_ADMA2 0xE7 515 #define O2_SD_INF_MOD 0xF1 516 517 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 518 { 519 u8 scratch; 520 int ret; 521 522 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 523 if (ret) 524 return ret; 525 526 /* 527 * Turn PMOS on [bit 0], set over current detection to 2.4 V 528 * [bit 1:2] and enable over current debouncing [bit 6]. 529 */ 530 if (on) 531 scratch |= 0x47; 532 else 533 scratch &= ~0x47; 534 535 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 536 } 537 538 static int jmicron_probe(struct sdhci_pci_chip *chip) 539 { 540 int ret; 541 u16 mmcdev = 0; 542 543 if (chip->pdev->revision == 0) { 544 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 545 SDHCI_QUIRK_32BIT_DMA_SIZE | 546 SDHCI_QUIRK_32BIT_ADMA_SIZE | 547 SDHCI_QUIRK_RESET_AFTER_REQUEST | 548 SDHCI_QUIRK_BROKEN_SMALL_PIO; 549 } 550 551 /* 552 * JMicron chips can have two interfaces to the same hardware 553 * in order to work around limitations in Microsoft's driver. 554 * We need to make sure we only bind to one of them. 555 * 556 * This code assumes two things: 557 * 558 * 1. The PCI code adds subfunctions in order. 559 * 560 * 2. The MMC interface has a lower subfunction number 561 * than the SD interface. 562 */ 563 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 564 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 565 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 566 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 567 568 if (mmcdev) { 569 struct pci_dev *sd_dev; 570 571 sd_dev = NULL; 572 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 573 mmcdev, sd_dev)) != NULL) { 574 if ((PCI_SLOT(chip->pdev->devfn) == 575 PCI_SLOT(sd_dev->devfn)) && 576 (chip->pdev->bus == sd_dev->bus)) 577 break; 578 } 579 580 if (sd_dev) { 581 pci_dev_put(sd_dev); 582 dev_info(&chip->pdev->dev, "Refusing to bind to " 583 "secondary interface.\n"); 584 return -ENODEV; 585 } 586 } 587 588 /* 589 * JMicron chips need a bit of a nudge to enable the power 590 * output pins. 591 */ 592 ret = jmicron_pmos(chip, 1); 593 if (ret) { 594 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 595 return ret; 596 } 597 598 /* quirk for unsable RO-detection on JM388 chips */ 599 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 600 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 601 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 602 603 return 0; 604 } 605 606 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 607 { 608 u8 scratch; 609 610 scratch = readb(host->ioaddr + 0xC0); 611 612 if (on) 613 scratch |= 0x01; 614 else 615 scratch &= ~0x01; 616 617 writeb(scratch, host->ioaddr + 0xC0); 618 } 619 620 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 621 { 622 if (slot->chip->pdev->revision == 0) { 623 u16 version; 624 625 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 626 version = (version & SDHCI_VENDOR_VER_MASK) >> 627 SDHCI_VENDOR_VER_SHIFT; 628 629 /* 630 * Older versions of the chip have lots of nasty glitches 631 * in the ADMA engine. It's best just to avoid it 632 * completely. 633 */ 634 if (version < 0xAC) 635 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 636 } 637 638 /* JM388 MMC doesn't support 1.8V while SD supports it */ 639 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 640 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 641 MMC_VDD_29_30 | MMC_VDD_30_31 | 642 MMC_VDD_165_195; /* allow 1.8V */ 643 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 644 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 645 } 646 647 /* 648 * The secondary interface requires a bit set to get the 649 * interrupts. 650 */ 651 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 652 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 653 jmicron_enable_mmc(slot->host, 1); 654 655 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 656 657 return 0; 658 } 659 660 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 661 { 662 if (dead) 663 return; 664 665 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 666 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 667 jmicron_enable_mmc(slot->host, 0); 668 } 669 670 static int jmicron_suspend(struct sdhci_pci_chip *chip) 671 { 672 int i; 673 674 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 675 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 676 for (i = 0; i < chip->num_slots; i++) 677 jmicron_enable_mmc(chip->slots[i]->host, 0); 678 } 679 680 return 0; 681 } 682 683 static int jmicron_resume(struct sdhci_pci_chip *chip) 684 { 685 int ret, i; 686 687 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 688 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 689 for (i = 0; i < chip->num_slots; i++) 690 jmicron_enable_mmc(chip->slots[i]->host, 1); 691 } 692 693 ret = jmicron_pmos(chip, 1); 694 if (ret) { 695 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 696 return ret; 697 } 698 699 return 0; 700 } 701 702 static const struct sdhci_pci_fixes sdhci_o2 = { 703 .probe = sdhci_pci_o2_probe, 704 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 705 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 706 .probe_slot = sdhci_pci_o2_probe_slot, 707 .resume = sdhci_pci_o2_resume, 708 }; 709 710 static const struct sdhci_pci_fixes sdhci_jmicron = { 711 .probe = jmicron_probe, 712 713 .probe_slot = jmicron_probe_slot, 714 .remove_slot = jmicron_remove_slot, 715 716 .suspend = jmicron_suspend, 717 .resume = jmicron_resume, 718 }; 719 720 /* SysKonnect CardBus2SDIO extra registers */ 721 #define SYSKT_CTRL 0x200 722 #define SYSKT_RDFIFO_STAT 0x204 723 #define SYSKT_WRFIFO_STAT 0x208 724 #define SYSKT_POWER_DATA 0x20c 725 #define SYSKT_POWER_330 0xef 726 #define SYSKT_POWER_300 0xf8 727 #define SYSKT_POWER_184 0xcc 728 #define SYSKT_POWER_CMD 0x20d 729 #define SYSKT_POWER_START (1 << 7) 730 #define SYSKT_POWER_STATUS 0x20e 731 #define SYSKT_POWER_STATUS_OK (1 << 0) 732 #define SYSKT_BOARD_REV 0x210 733 #define SYSKT_CHIP_REV 0x211 734 #define SYSKT_CONF_DATA 0x212 735 #define SYSKT_CONF_DATA_1V8 (1 << 2) 736 #define SYSKT_CONF_DATA_2V5 (1 << 1) 737 #define SYSKT_CONF_DATA_3V3 (1 << 0) 738 739 static int syskt_probe(struct sdhci_pci_chip *chip) 740 { 741 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 742 chip->pdev->class &= ~0x0000FF; 743 chip->pdev->class |= PCI_SDHCI_IFDMA; 744 } 745 return 0; 746 } 747 748 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 749 { 750 int tm, ps; 751 752 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 753 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 754 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 755 "board rev %d.%d, chip rev %d.%d\n", 756 board_rev >> 4, board_rev & 0xf, 757 chip_rev >> 4, chip_rev & 0xf); 758 if (chip_rev >= 0x20) 759 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 760 761 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 762 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 763 udelay(50); 764 tm = 10; /* Wait max 1 ms */ 765 do { 766 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 767 if (ps & SYSKT_POWER_STATUS_OK) 768 break; 769 udelay(100); 770 } while (--tm); 771 if (!tm) { 772 dev_err(&slot->chip->pdev->dev, 773 "power regulator never stabilized"); 774 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 775 return -ENODEV; 776 } 777 778 return 0; 779 } 780 781 static const struct sdhci_pci_fixes sdhci_syskt = { 782 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 783 .probe = syskt_probe, 784 .probe_slot = syskt_probe_slot, 785 }; 786 787 static int via_probe(struct sdhci_pci_chip *chip) 788 { 789 if (chip->pdev->revision == 0x10) 790 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 791 792 return 0; 793 } 794 795 static const struct sdhci_pci_fixes sdhci_via = { 796 .probe = via_probe, 797 }; 798 799 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 800 { 801 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 802 return 0; 803 } 804 805 static const struct sdhci_pci_fixes sdhci_rtsx = { 806 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 807 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 808 SDHCI_QUIRK2_BROKEN_DDR50, 809 .probe_slot = rtsx_probe_slot, 810 }; 811 812 /*AMD chipset generation*/ 813 enum amd_chipset_gen { 814 AMD_CHIPSET_BEFORE_ML, 815 AMD_CHIPSET_CZ, 816 AMD_CHIPSET_NL, 817 AMD_CHIPSET_UNKNOWN, 818 }; 819 820 static int amd_probe(struct sdhci_pci_chip *chip) 821 { 822 struct pci_dev *smbus_dev; 823 enum amd_chipset_gen gen; 824 825 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 826 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 827 if (smbus_dev) { 828 gen = AMD_CHIPSET_BEFORE_ML; 829 } else { 830 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 831 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 832 if (smbus_dev) { 833 if (smbus_dev->revision < 0x51) 834 gen = AMD_CHIPSET_CZ; 835 else 836 gen = AMD_CHIPSET_NL; 837 } else { 838 gen = AMD_CHIPSET_UNKNOWN; 839 } 840 } 841 842 if ((gen == AMD_CHIPSET_BEFORE_ML) || (gen == AMD_CHIPSET_CZ)) { 843 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 844 chip->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 845 } 846 847 return 0; 848 } 849 850 static const struct sdhci_pci_fixes sdhci_amd = { 851 .probe = amd_probe, 852 }; 853 854 static const struct pci_device_id pci_ids[] = { 855 { 856 .vendor = PCI_VENDOR_ID_RICOH, 857 .device = PCI_DEVICE_ID_RICOH_R5C822, 858 .subvendor = PCI_ANY_ID, 859 .subdevice = PCI_ANY_ID, 860 .driver_data = (kernel_ulong_t)&sdhci_ricoh, 861 }, 862 863 { 864 .vendor = PCI_VENDOR_ID_RICOH, 865 .device = 0x843, 866 .subvendor = PCI_ANY_ID, 867 .subdevice = PCI_ANY_ID, 868 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 869 }, 870 871 { 872 .vendor = PCI_VENDOR_ID_RICOH, 873 .device = 0xe822, 874 .subvendor = PCI_ANY_ID, 875 .subdevice = PCI_ANY_ID, 876 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 877 }, 878 879 { 880 .vendor = PCI_VENDOR_ID_RICOH, 881 .device = 0xe823, 882 .subvendor = PCI_ANY_ID, 883 .subdevice = PCI_ANY_ID, 884 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 885 }, 886 887 { 888 .vendor = PCI_VENDOR_ID_ENE, 889 .device = PCI_DEVICE_ID_ENE_CB712_SD, 890 .subvendor = PCI_ANY_ID, 891 .subdevice = PCI_ANY_ID, 892 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 893 }, 894 895 { 896 .vendor = PCI_VENDOR_ID_ENE, 897 .device = PCI_DEVICE_ID_ENE_CB712_SD_2, 898 .subvendor = PCI_ANY_ID, 899 .subdevice = PCI_ANY_ID, 900 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 901 }, 902 903 { 904 .vendor = PCI_VENDOR_ID_ENE, 905 .device = PCI_DEVICE_ID_ENE_CB714_SD, 906 .subvendor = PCI_ANY_ID, 907 .subdevice = PCI_ANY_ID, 908 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 909 }, 910 911 { 912 .vendor = PCI_VENDOR_ID_ENE, 913 .device = PCI_DEVICE_ID_ENE_CB714_SD_2, 914 .subvendor = PCI_ANY_ID, 915 .subdevice = PCI_ANY_ID, 916 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 917 }, 918 919 { 920 .vendor = PCI_VENDOR_ID_MARVELL, 921 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD, 922 .subvendor = PCI_ANY_ID, 923 .subdevice = PCI_ANY_ID, 924 .driver_data = (kernel_ulong_t)&sdhci_cafe, 925 }, 926 927 { 928 .vendor = PCI_VENDOR_ID_JMICRON, 929 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD, 930 .subvendor = PCI_ANY_ID, 931 .subdevice = PCI_ANY_ID, 932 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 933 }, 934 935 { 936 .vendor = PCI_VENDOR_ID_JMICRON, 937 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC, 938 .subvendor = PCI_ANY_ID, 939 .subdevice = PCI_ANY_ID, 940 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 941 }, 942 943 { 944 .vendor = PCI_VENDOR_ID_JMICRON, 945 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD, 946 .subvendor = PCI_ANY_ID, 947 .subdevice = PCI_ANY_ID, 948 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 949 }, 950 951 { 952 .vendor = PCI_VENDOR_ID_JMICRON, 953 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD, 954 .subvendor = PCI_ANY_ID, 955 .subdevice = PCI_ANY_ID, 956 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 957 }, 958 959 { 960 .vendor = PCI_VENDOR_ID_SYSKONNECT, 961 .device = 0x8000, 962 .subvendor = PCI_ANY_ID, 963 .subdevice = PCI_ANY_ID, 964 .driver_data = (kernel_ulong_t)&sdhci_syskt, 965 }, 966 967 { 968 .vendor = PCI_VENDOR_ID_VIA, 969 .device = 0x95d0, 970 .subvendor = PCI_ANY_ID, 971 .subdevice = PCI_ANY_ID, 972 .driver_data = (kernel_ulong_t)&sdhci_via, 973 }, 974 975 { 976 .vendor = PCI_VENDOR_ID_REALTEK, 977 .device = 0x5250, 978 .subvendor = PCI_ANY_ID, 979 .subdevice = PCI_ANY_ID, 980 .driver_data = (kernel_ulong_t)&sdhci_rtsx, 981 }, 982 983 { 984 .vendor = PCI_VENDOR_ID_INTEL, 985 .device = PCI_DEVICE_ID_INTEL_QRK_SD, 986 .subvendor = PCI_ANY_ID, 987 .subdevice = PCI_ANY_ID, 988 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk, 989 }, 990 991 { 992 .vendor = PCI_VENDOR_ID_INTEL, 993 .device = PCI_DEVICE_ID_INTEL_MRST_SD0, 994 .subvendor = PCI_ANY_ID, 995 .subdevice = PCI_ANY_ID, 996 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0, 997 }, 998 999 { 1000 .vendor = PCI_VENDOR_ID_INTEL, 1001 .device = PCI_DEVICE_ID_INTEL_MRST_SD1, 1002 .subvendor = PCI_ANY_ID, 1003 .subdevice = PCI_ANY_ID, 1004 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 1005 }, 1006 1007 { 1008 .vendor = PCI_VENDOR_ID_INTEL, 1009 .device = PCI_DEVICE_ID_INTEL_MRST_SD2, 1010 .subvendor = PCI_ANY_ID, 1011 .subdevice = PCI_ANY_ID, 1012 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 1013 }, 1014 1015 { 1016 .vendor = PCI_VENDOR_ID_INTEL, 1017 .device = PCI_DEVICE_ID_INTEL_MFD_SD, 1018 .subvendor = PCI_ANY_ID, 1019 .subdevice = PCI_ANY_ID, 1020 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1021 }, 1022 1023 { 1024 .vendor = PCI_VENDOR_ID_INTEL, 1025 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1, 1026 .subvendor = PCI_ANY_ID, 1027 .subdevice = PCI_ANY_ID, 1028 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1029 }, 1030 1031 { 1032 .vendor = PCI_VENDOR_ID_INTEL, 1033 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2, 1034 .subvendor = PCI_ANY_ID, 1035 .subdevice = PCI_ANY_ID, 1036 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1037 }, 1038 1039 { 1040 .vendor = PCI_VENDOR_ID_INTEL, 1041 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0, 1042 .subvendor = PCI_ANY_ID, 1043 .subdevice = PCI_ANY_ID, 1044 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1045 }, 1046 1047 { 1048 .vendor = PCI_VENDOR_ID_INTEL, 1049 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1, 1050 .subvendor = PCI_ANY_ID, 1051 .subdevice = PCI_ANY_ID, 1052 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1053 }, 1054 1055 { 1056 .vendor = PCI_VENDOR_ID_INTEL, 1057 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0, 1058 .subvendor = PCI_ANY_ID, 1059 .subdevice = PCI_ANY_ID, 1060 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1061 }, 1062 1063 { 1064 .vendor = PCI_VENDOR_ID_INTEL, 1065 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1, 1066 .subvendor = PCI_ANY_ID, 1067 .subdevice = PCI_ANY_ID, 1068 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1069 }, 1070 1071 { 1072 .vendor = PCI_VENDOR_ID_INTEL, 1073 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC, 1074 .subvendor = PCI_ANY_ID, 1075 .subdevice = PCI_ANY_ID, 1076 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1077 }, 1078 1079 { 1080 .vendor = PCI_VENDOR_ID_INTEL, 1081 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, 1082 .subvendor = PCI_ANY_ID, 1083 .subdevice = PCI_ANY_ID, 1084 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1085 }, 1086 1087 { 1088 .vendor = PCI_VENDOR_ID_INTEL, 1089 .device = PCI_DEVICE_ID_INTEL_BYT_SD, 1090 .subvendor = PCI_ANY_ID, 1091 .subdevice = PCI_ANY_ID, 1092 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1093 }, 1094 1095 { 1096 .vendor = PCI_VENDOR_ID_INTEL, 1097 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2, 1098 .subvendor = PCI_ANY_ID, 1099 .subdevice = PCI_ANY_ID, 1100 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1101 }, 1102 1103 { 1104 .vendor = PCI_VENDOR_ID_INTEL, 1105 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC, 1106 .subvendor = PCI_ANY_ID, 1107 .subdevice = PCI_ANY_ID, 1108 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1109 }, 1110 1111 { 1112 .vendor = PCI_VENDOR_ID_INTEL, 1113 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO, 1114 .subvendor = PCI_ANY_ID, 1115 .subdevice = PCI_ANY_ID, 1116 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1117 }, 1118 1119 { 1120 .vendor = PCI_VENDOR_ID_INTEL, 1121 .device = PCI_DEVICE_ID_INTEL_BSW_SD, 1122 .subvendor = PCI_ANY_ID, 1123 .subdevice = PCI_ANY_ID, 1124 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1125 }, 1126 1127 { 1128 .vendor = PCI_VENDOR_ID_INTEL, 1129 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0, 1130 .subvendor = PCI_ANY_ID, 1131 .subdevice = PCI_ANY_ID, 1132 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1133 }, 1134 1135 { 1136 .vendor = PCI_VENDOR_ID_INTEL, 1137 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1, 1138 .subvendor = PCI_ANY_ID, 1139 .subdevice = PCI_ANY_ID, 1140 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1141 }, 1142 1143 { 1144 .vendor = PCI_VENDOR_ID_INTEL, 1145 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2, 1146 .subvendor = PCI_ANY_ID, 1147 .subdevice = PCI_ANY_ID, 1148 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1149 }, 1150 1151 { 1152 .vendor = PCI_VENDOR_ID_INTEL, 1153 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0, 1154 .subvendor = PCI_ANY_ID, 1155 .subdevice = PCI_ANY_ID, 1156 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1157 }, 1158 1159 { 1160 .vendor = PCI_VENDOR_ID_INTEL, 1161 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1, 1162 .subvendor = PCI_ANY_ID, 1163 .subdevice = PCI_ANY_ID, 1164 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1165 }, 1166 1167 { 1168 .vendor = PCI_VENDOR_ID_INTEL, 1169 .device = PCI_DEVICE_ID_INTEL_MRFLD_MMC, 1170 .subvendor = PCI_ANY_ID, 1171 .subdevice = PCI_ANY_ID, 1172 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfld_mmc, 1173 }, 1174 1175 { 1176 .vendor = PCI_VENDOR_ID_INTEL, 1177 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC, 1178 .subvendor = PCI_ANY_ID, 1179 .subdevice = PCI_ANY_ID, 1180 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1181 }, 1182 1183 { 1184 .vendor = PCI_VENDOR_ID_INTEL, 1185 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO, 1186 .subvendor = PCI_ANY_ID, 1187 .subdevice = PCI_ANY_ID, 1188 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1189 }, 1190 1191 { 1192 .vendor = PCI_VENDOR_ID_INTEL, 1193 .device = PCI_DEVICE_ID_INTEL_SPT_SD, 1194 .subvendor = PCI_ANY_ID, 1195 .subdevice = PCI_ANY_ID, 1196 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1197 }, 1198 1199 { 1200 .vendor = PCI_VENDOR_ID_INTEL, 1201 .device = PCI_DEVICE_ID_INTEL_DNV_EMMC, 1202 .subvendor = PCI_ANY_ID, 1203 .subdevice = PCI_ANY_ID, 1204 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1205 }, 1206 1207 { 1208 .vendor = PCI_VENDOR_ID_INTEL, 1209 .device = PCI_DEVICE_ID_INTEL_BXT_EMMC, 1210 .subvendor = PCI_ANY_ID, 1211 .subdevice = PCI_ANY_ID, 1212 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1213 }, 1214 1215 { 1216 .vendor = PCI_VENDOR_ID_INTEL, 1217 .device = PCI_DEVICE_ID_INTEL_BXT_SDIO, 1218 .subvendor = PCI_ANY_ID, 1219 .subdevice = PCI_ANY_ID, 1220 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1221 }, 1222 1223 { 1224 .vendor = PCI_VENDOR_ID_INTEL, 1225 .device = PCI_DEVICE_ID_INTEL_BXT_SD, 1226 .subvendor = PCI_ANY_ID, 1227 .subdevice = PCI_ANY_ID, 1228 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1229 }, 1230 1231 { 1232 .vendor = PCI_VENDOR_ID_INTEL, 1233 .device = PCI_DEVICE_ID_INTEL_BXTM_EMMC, 1234 .subvendor = PCI_ANY_ID, 1235 .subdevice = PCI_ANY_ID, 1236 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1237 }, 1238 1239 { 1240 .vendor = PCI_VENDOR_ID_INTEL, 1241 .device = PCI_DEVICE_ID_INTEL_BXTM_SDIO, 1242 .subvendor = PCI_ANY_ID, 1243 .subdevice = PCI_ANY_ID, 1244 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1245 }, 1246 1247 { 1248 .vendor = PCI_VENDOR_ID_INTEL, 1249 .device = PCI_DEVICE_ID_INTEL_BXTM_SD, 1250 .subvendor = PCI_ANY_ID, 1251 .subdevice = PCI_ANY_ID, 1252 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1253 }, 1254 1255 { 1256 .vendor = PCI_VENDOR_ID_INTEL, 1257 .device = PCI_DEVICE_ID_INTEL_APL_EMMC, 1258 .subvendor = PCI_ANY_ID, 1259 .subdevice = PCI_ANY_ID, 1260 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1261 }, 1262 1263 { 1264 .vendor = PCI_VENDOR_ID_INTEL, 1265 .device = PCI_DEVICE_ID_INTEL_APL_SDIO, 1266 .subvendor = PCI_ANY_ID, 1267 .subdevice = PCI_ANY_ID, 1268 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1269 }, 1270 1271 { 1272 .vendor = PCI_VENDOR_ID_INTEL, 1273 .device = PCI_DEVICE_ID_INTEL_APL_SD, 1274 .subvendor = PCI_ANY_ID, 1275 .subdevice = PCI_ANY_ID, 1276 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1277 }, 1278 1279 { 1280 .vendor = PCI_VENDOR_ID_O2, 1281 .device = PCI_DEVICE_ID_O2_8120, 1282 .subvendor = PCI_ANY_ID, 1283 .subdevice = PCI_ANY_ID, 1284 .driver_data = (kernel_ulong_t)&sdhci_o2, 1285 }, 1286 1287 { 1288 .vendor = PCI_VENDOR_ID_O2, 1289 .device = PCI_DEVICE_ID_O2_8220, 1290 .subvendor = PCI_ANY_ID, 1291 .subdevice = PCI_ANY_ID, 1292 .driver_data = (kernel_ulong_t)&sdhci_o2, 1293 }, 1294 1295 { 1296 .vendor = PCI_VENDOR_ID_O2, 1297 .device = PCI_DEVICE_ID_O2_8221, 1298 .subvendor = PCI_ANY_ID, 1299 .subdevice = PCI_ANY_ID, 1300 .driver_data = (kernel_ulong_t)&sdhci_o2, 1301 }, 1302 1303 { 1304 .vendor = PCI_VENDOR_ID_O2, 1305 .device = PCI_DEVICE_ID_O2_8320, 1306 .subvendor = PCI_ANY_ID, 1307 .subdevice = PCI_ANY_ID, 1308 .driver_data = (kernel_ulong_t)&sdhci_o2, 1309 }, 1310 1311 { 1312 .vendor = PCI_VENDOR_ID_O2, 1313 .device = PCI_DEVICE_ID_O2_8321, 1314 .subvendor = PCI_ANY_ID, 1315 .subdevice = PCI_ANY_ID, 1316 .driver_data = (kernel_ulong_t)&sdhci_o2, 1317 }, 1318 1319 { 1320 .vendor = PCI_VENDOR_ID_O2, 1321 .device = PCI_DEVICE_ID_O2_FUJIN2, 1322 .subvendor = PCI_ANY_ID, 1323 .subdevice = PCI_ANY_ID, 1324 .driver_data = (kernel_ulong_t)&sdhci_o2, 1325 }, 1326 1327 { 1328 .vendor = PCI_VENDOR_ID_O2, 1329 .device = PCI_DEVICE_ID_O2_SDS0, 1330 .subvendor = PCI_ANY_ID, 1331 .subdevice = PCI_ANY_ID, 1332 .driver_data = (kernel_ulong_t)&sdhci_o2, 1333 }, 1334 1335 { 1336 .vendor = PCI_VENDOR_ID_O2, 1337 .device = PCI_DEVICE_ID_O2_SDS1, 1338 .subvendor = PCI_ANY_ID, 1339 .subdevice = PCI_ANY_ID, 1340 .driver_data = (kernel_ulong_t)&sdhci_o2, 1341 }, 1342 1343 { 1344 .vendor = PCI_VENDOR_ID_O2, 1345 .device = PCI_DEVICE_ID_O2_SEABIRD0, 1346 .subvendor = PCI_ANY_ID, 1347 .subdevice = PCI_ANY_ID, 1348 .driver_data = (kernel_ulong_t)&sdhci_o2, 1349 }, 1350 1351 { 1352 .vendor = PCI_VENDOR_ID_O2, 1353 .device = PCI_DEVICE_ID_O2_SEABIRD1, 1354 .subvendor = PCI_ANY_ID, 1355 .subdevice = PCI_ANY_ID, 1356 .driver_data = (kernel_ulong_t)&sdhci_o2, 1357 }, 1358 { 1359 .vendor = PCI_VENDOR_ID_AMD, 1360 .device = PCI_ANY_ID, 1361 .class = PCI_CLASS_SYSTEM_SDHCI << 8, 1362 .class_mask = 0xFFFF00, 1363 .subvendor = PCI_ANY_ID, 1364 .subdevice = PCI_ANY_ID, 1365 .driver_data = (kernel_ulong_t)&sdhci_amd, 1366 }, 1367 { /* Generic SD host controller */ 1368 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) 1369 }, 1370 1371 { /* end: all zeroes */ }, 1372 }; 1373 1374 MODULE_DEVICE_TABLE(pci, pci_ids); 1375 1376 /*****************************************************************************\ 1377 * * 1378 * SDHCI core callbacks * 1379 * * 1380 \*****************************************************************************/ 1381 1382 static int sdhci_pci_enable_dma(struct sdhci_host *host) 1383 { 1384 struct sdhci_pci_slot *slot; 1385 struct pci_dev *pdev; 1386 1387 slot = sdhci_priv(host); 1388 pdev = slot->chip->pdev; 1389 1390 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1391 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1392 (host->flags & SDHCI_USE_SDMA)) { 1393 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1394 "doesn't fully claim to support it.\n"); 1395 } 1396 1397 pci_set_master(pdev); 1398 1399 return 0; 1400 } 1401 1402 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width) 1403 { 1404 u8 ctrl; 1405 1406 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1407 1408 switch (width) { 1409 case MMC_BUS_WIDTH_8: 1410 ctrl |= SDHCI_CTRL_8BITBUS; 1411 ctrl &= ~SDHCI_CTRL_4BITBUS; 1412 break; 1413 case MMC_BUS_WIDTH_4: 1414 ctrl |= SDHCI_CTRL_4BITBUS; 1415 ctrl &= ~SDHCI_CTRL_8BITBUS; 1416 break; 1417 default: 1418 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS); 1419 break; 1420 } 1421 1422 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1423 } 1424 1425 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1426 { 1427 struct sdhci_pci_slot *slot = sdhci_priv(host); 1428 int rst_n_gpio = slot->rst_n_gpio; 1429 1430 if (!gpio_is_valid(rst_n_gpio)) 1431 return; 1432 gpio_set_value_cansleep(rst_n_gpio, 0); 1433 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1434 udelay(10); 1435 gpio_set_value_cansleep(rst_n_gpio, 1); 1436 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1437 usleep_range(300, 1000); 1438 } 1439 1440 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1441 { 1442 struct sdhci_pci_slot *slot = sdhci_priv(host); 1443 1444 if (slot->hw_reset) 1445 slot->hw_reset(host); 1446 } 1447 1448 static int sdhci_pci_select_drive_strength(struct sdhci_host *host, 1449 struct mmc_card *card, 1450 unsigned int max_dtr, int host_drv, 1451 int card_drv, int *drv_type) 1452 { 1453 struct sdhci_pci_slot *slot = sdhci_priv(host); 1454 1455 if (!slot->select_drive_strength) 1456 return 0; 1457 1458 return slot->select_drive_strength(host, card, max_dtr, host_drv, 1459 card_drv, drv_type); 1460 } 1461 1462 static const struct sdhci_ops sdhci_pci_ops = { 1463 .set_clock = sdhci_set_clock, 1464 .enable_dma = sdhci_pci_enable_dma, 1465 .set_bus_width = sdhci_pci_set_bus_width, 1466 .reset = sdhci_reset, 1467 .set_uhs_signaling = sdhci_set_uhs_signaling, 1468 .hw_reset = sdhci_pci_hw_reset, 1469 .select_drive_strength = sdhci_pci_select_drive_strength, 1470 }; 1471 1472 /*****************************************************************************\ 1473 * * 1474 * Suspend/resume * 1475 * * 1476 \*****************************************************************************/ 1477 1478 #ifdef CONFIG_PM_SLEEP 1479 static int sdhci_pci_suspend(struct device *dev) 1480 { 1481 struct pci_dev *pdev = to_pci_dev(dev); 1482 struct sdhci_pci_chip *chip; 1483 struct sdhci_pci_slot *slot; 1484 mmc_pm_flag_t slot_pm_flags; 1485 mmc_pm_flag_t pm_flags = 0; 1486 int i, ret; 1487 1488 chip = pci_get_drvdata(pdev); 1489 if (!chip) 1490 return 0; 1491 1492 for (i = 0; i < chip->num_slots; i++) { 1493 slot = chip->slots[i]; 1494 if (!slot) 1495 continue; 1496 1497 ret = sdhci_suspend_host(slot->host); 1498 1499 if (ret) 1500 goto err_pci_suspend; 1501 1502 slot_pm_flags = slot->host->mmc->pm_flags; 1503 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1504 sdhci_enable_irq_wakeups(slot->host); 1505 1506 pm_flags |= slot_pm_flags; 1507 } 1508 1509 if (chip->fixes && chip->fixes->suspend) { 1510 ret = chip->fixes->suspend(chip); 1511 if (ret) 1512 goto err_pci_suspend; 1513 } 1514 1515 if (pm_flags & MMC_PM_KEEP_POWER) { 1516 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1517 device_init_wakeup(dev, true); 1518 else 1519 device_init_wakeup(dev, false); 1520 } else 1521 device_init_wakeup(dev, false); 1522 1523 return 0; 1524 1525 err_pci_suspend: 1526 while (--i >= 0) 1527 sdhci_resume_host(chip->slots[i]->host); 1528 return ret; 1529 } 1530 1531 static int sdhci_pci_resume(struct device *dev) 1532 { 1533 struct pci_dev *pdev = to_pci_dev(dev); 1534 struct sdhci_pci_chip *chip; 1535 struct sdhci_pci_slot *slot; 1536 int i, ret; 1537 1538 chip = pci_get_drvdata(pdev); 1539 if (!chip) 1540 return 0; 1541 1542 if (chip->fixes && chip->fixes->resume) { 1543 ret = chip->fixes->resume(chip); 1544 if (ret) 1545 return ret; 1546 } 1547 1548 for (i = 0; i < chip->num_slots; i++) { 1549 slot = chip->slots[i]; 1550 if (!slot) 1551 continue; 1552 1553 ret = sdhci_resume_host(slot->host); 1554 if (ret) 1555 return ret; 1556 } 1557 1558 return 0; 1559 } 1560 #endif 1561 1562 #ifdef CONFIG_PM 1563 static int sdhci_pci_runtime_suspend(struct device *dev) 1564 { 1565 struct pci_dev *pdev = to_pci_dev(dev); 1566 struct sdhci_pci_chip *chip; 1567 struct sdhci_pci_slot *slot; 1568 int i, ret; 1569 1570 chip = pci_get_drvdata(pdev); 1571 if (!chip) 1572 return 0; 1573 1574 for (i = 0; i < chip->num_slots; i++) { 1575 slot = chip->slots[i]; 1576 if (!slot) 1577 continue; 1578 1579 ret = sdhci_runtime_suspend_host(slot->host); 1580 1581 if (ret) 1582 goto err_pci_runtime_suspend; 1583 } 1584 1585 if (chip->fixes && chip->fixes->suspend) { 1586 ret = chip->fixes->suspend(chip); 1587 if (ret) 1588 goto err_pci_runtime_suspend; 1589 } 1590 1591 return 0; 1592 1593 err_pci_runtime_suspend: 1594 while (--i >= 0) 1595 sdhci_runtime_resume_host(chip->slots[i]->host); 1596 return ret; 1597 } 1598 1599 static int sdhci_pci_runtime_resume(struct device *dev) 1600 { 1601 struct pci_dev *pdev = to_pci_dev(dev); 1602 struct sdhci_pci_chip *chip; 1603 struct sdhci_pci_slot *slot; 1604 int i, ret; 1605 1606 chip = pci_get_drvdata(pdev); 1607 if (!chip) 1608 return 0; 1609 1610 if (chip->fixes && chip->fixes->resume) { 1611 ret = chip->fixes->resume(chip); 1612 if (ret) 1613 return ret; 1614 } 1615 1616 for (i = 0; i < chip->num_slots; i++) { 1617 slot = chip->slots[i]; 1618 if (!slot) 1619 continue; 1620 1621 ret = sdhci_runtime_resume_host(slot->host); 1622 if (ret) 1623 return ret; 1624 } 1625 1626 return 0; 1627 } 1628 #endif 1629 1630 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1631 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1632 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1633 sdhci_pci_runtime_resume, NULL) 1634 }; 1635 1636 /*****************************************************************************\ 1637 * * 1638 * Device probing/removal * 1639 * * 1640 \*****************************************************************************/ 1641 1642 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1643 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1644 int slotno) 1645 { 1646 struct sdhci_pci_slot *slot; 1647 struct sdhci_host *host; 1648 int ret, bar = first_bar + slotno; 1649 1650 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1651 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1652 return ERR_PTR(-ENODEV); 1653 } 1654 1655 if (pci_resource_len(pdev, bar) < 0x100) { 1656 dev_err(&pdev->dev, "Invalid iomem size. You may " 1657 "experience problems.\n"); 1658 } 1659 1660 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1661 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1662 return ERR_PTR(-ENODEV); 1663 } 1664 1665 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1666 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1667 return ERR_PTR(-ENODEV); 1668 } 1669 1670 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot)); 1671 if (IS_ERR(host)) { 1672 dev_err(&pdev->dev, "cannot allocate host\n"); 1673 return ERR_CAST(host); 1674 } 1675 1676 slot = sdhci_priv(host); 1677 1678 slot->chip = chip; 1679 slot->host = host; 1680 slot->rst_n_gpio = -EINVAL; 1681 slot->cd_gpio = -EINVAL; 1682 slot->cd_idx = -1; 1683 1684 /* Retrieve platform data if there is any */ 1685 if (*sdhci_pci_get_data) 1686 slot->data = sdhci_pci_get_data(pdev, slotno); 1687 1688 if (slot->data) { 1689 if (slot->data->setup) { 1690 ret = slot->data->setup(slot->data); 1691 if (ret) { 1692 dev_err(&pdev->dev, "platform setup failed\n"); 1693 goto free; 1694 } 1695 } 1696 slot->rst_n_gpio = slot->data->rst_n_gpio; 1697 slot->cd_gpio = slot->data->cd_gpio; 1698 } 1699 1700 host->hw_name = "PCI"; 1701 host->ops = chip->fixes && chip->fixes->ops ? 1702 chip->fixes->ops : 1703 &sdhci_pci_ops; 1704 host->quirks = chip->quirks; 1705 host->quirks2 = chip->quirks2; 1706 1707 host->irq = pdev->irq; 1708 1709 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1710 if (ret) { 1711 dev_err(&pdev->dev, "cannot request region\n"); 1712 goto cleanup; 1713 } 1714 1715 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1716 1717 if (chip->fixes && chip->fixes->probe_slot) { 1718 ret = chip->fixes->probe_slot(slot); 1719 if (ret) 1720 goto cleanup; 1721 } 1722 1723 if (gpio_is_valid(slot->rst_n_gpio)) { 1724 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1725 gpio_direction_output(slot->rst_n_gpio, 1); 1726 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1727 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1728 } else { 1729 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1730 slot->rst_n_gpio = -EINVAL; 1731 } 1732 } 1733 1734 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; 1735 host->mmc->slotno = slotno; 1736 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1737 1738 if (slot->cd_idx >= 0 && 1739 mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx, 1740 slot->cd_override_level, 0, NULL)) { 1741 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 1742 slot->cd_idx = -1; 1743 } 1744 1745 ret = sdhci_add_host(host); 1746 if (ret) 1747 goto remove; 1748 1749 sdhci_pci_add_own_cd(slot); 1750 1751 /* 1752 * Check if the chip needs a separate GPIO for card detect to wake up 1753 * from runtime suspend. If it is not there, don't allow runtime PM. 1754 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 1755 */ 1756 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 1757 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 1758 chip->allow_runtime_pm = false; 1759 1760 return slot; 1761 1762 remove: 1763 if (chip->fixes && chip->fixes->remove_slot) 1764 chip->fixes->remove_slot(slot, 0); 1765 1766 cleanup: 1767 if (slot->data && slot->data->cleanup) 1768 slot->data->cleanup(slot->data); 1769 1770 free: 1771 sdhci_free_host(host); 1772 1773 return ERR_PTR(ret); 1774 } 1775 1776 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 1777 { 1778 int dead; 1779 u32 scratch; 1780 1781 sdhci_pci_remove_own_cd(slot); 1782 1783 dead = 0; 1784 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 1785 if (scratch == (u32)-1) 1786 dead = 1; 1787 1788 sdhci_remove_host(slot->host, dead); 1789 1790 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 1791 slot->chip->fixes->remove_slot(slot, dead); 1792 1793 if (slot->data && slot->data->cleanup) 1794 slot->data->cleanup(slot->data); 1795 1796 sdhci_free_host(slot->host); 1797 } 1798 1799 static void sdhci_pci_runtime_pm_allow(struct device *dev) 1800 { 1801 pm_suspend_ignore_children(dev, 1); 1802 pm_runtime_set_autosuspend_delay(dev, 50); 1803 pm_runtime_use_autosuspend(dev); 1804 pm_runtime_allow(dev); 1805 /* Stay active until mmc core scans for a card */ 1806 pm_runtime_put_noidle(dev); 1807 } 1808 1809 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 1810 { 1811 pm_runtime_forbid(dev); 1812 pm_runtime_get_noresume(dev); 1813 } 1814 1815 static int sdhci_pci_probe(struct pci_dev *pdev, 1816 const struct pci_device_id *ent) 1817 { 1818 struct sdhci_pci_chip *chip; 1819 struct sdhci_pci_slot *slot; 1820 1821 u8 slots, first_bar; 1822 int ret, i; 1823 1824 BUG_ON(pdev == NULL); 1825 BUG_ON(ent == NULL); 1826 1827 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 1828 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 1829 1830 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 1831 if (ret) 1832 return ret; 1833 1834 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 1835 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 1836 if (slots == 0) 1837 return -ENODEV; 1838 1839 BUG_ON(slots > MAX_SLOTS); 1840 1841 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 1842 if (ret) 1843 return ret; 1844 1845 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 1846 1847 if (first_bar > 5) { 1848 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 1849 return -ENODEV; 1850 } 1851 1852 ret = pcim_enable_device(pdev); 1853 if (ret) 1854 return ret; 1855 1856 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 1857 if (!chip) 1858 return -ENOMEM; 1859 1860 chip->pdev = pdev; 1861 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 1862 if (chip->fixes) { 1863 chip->quirks = chip->fixes->quirks; 1864 chip->quirks2 = chip->fixes->quirks2; 1865 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 1866 } 1867 chip->num_slots = slots; 1868 1869 pci_set_drvdata(pdev, chip); 1870 1871 if (chip->fixes && chip->fixes->probe) { 1872 ret = chip->fixes->probe(chip); 1873 if (ret) 1874 return ret; 1875 } 1876 1877 slots = chip->num_slots; /* Quirk may have changed this */ 1878 1879 for (i = 0; i < slots; i++) { 1880 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 1881 if (IS_ERR(slot)) { 1882 for (i--; i >= 0; i--) 1883 sdhci_pci_remove_slot(chip->slots[i]); 1884 return PTR_ERR(slot); 1885 } 1886 1887 chip->slots[i] = slot; 1888 } 1889 1890 if (chip->allow_runtime_pm) 1891 sdhci_pci_runtime_pm_allow(&pdev->dev); 1892 1893 return 0; 1894 } 1895 1896 static void sdhci_pci_remove(struct pci_dev *pdev) 1897 { 1898 int i; 1899 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1900 1901 if (chip->allow_runtime_pm) 1902 sdhci_pci_runtime_pm_forbid(&pdev->dev); 1903 1904 for (i = 0; i < chip->num_slots; i++) 1905 sdhci_pci_remove_slot(chip->slots[i]); 1906 } 1907 1908 static struct pci_driver sdhci_driver = { 1909 .name = "sdhci-pci", 1910 .id_table = pci_ids, 1911 .probe = sdhci_pci_probe, 1912 .remove = sdhci_pci_remove, 1913 .driver = { 1914 .pm = &sdhci_pci_pm_ops 1915 }, 1916 }; 1917 1918 module_pci_driver(sdhci_driver); 1919 1920 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 1921 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 1922 MODULE_LICENSE("GPL"); 1923