1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 2 * 3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 * 10 * Thanks to the following companies for their support: 11 * 12 * - JMicron (hardware and technical support) 13 */ 14 15 #include <linux/string.h> 16 #include <linux/delay.h> 17 #include <linux/highmem.h> 18 #include <linux/module.h> 19 #include <linux/pci.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/slab.h> 22 #include <linux/device.h> 23 #include <linux/mmc/host.h> 24 #include <linux/mmc/mmc.h> 25 #include <linux/scatterlist.h> 26 #include <linux/io.h> 27 #include <linux/gpio.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/mmc/slot-gpio.h> 30 #include <linux/mmc/sdhci-pci-data.h> 31 #include <linux/acpi.h> 32 33 #include "cqhci.h" 34 35 #include "sdhci.h" 36 #include "sdhci-pci.h" 37 38 static void sdhci_pci_hw_reset(struct sdhci_host *host); 39 40 #ifdef CONFIG_PM_SLEEP 41 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip) 42 { 43 mmc_pm_flag_t pm_flags = 0; 44 int i; 45 46 for (i = 0; i < chip->num_slots; i++) { 47 struct sdhci_pci_slot *slot = chip->slots[i]; 48 49 if (slot) 50 pm_flags |= slot->host->mmc->pm_flags; 51 } 52 53 return device_set_wakeup_enable(&chip->pdev->dev, 54 (pm_flags & MMC_PM_KEEP_POWER) && 55 (pm_flags & MMC_PM_WAKE_SDIO_IRQ)); 56 } 57 58 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 59 { 60 int i, ret; 61 62 sdhci_pci_init_wakeup(chip); 63 64 for (i = 0; i < chip->num_slots; i++) { 65 struct sdhci_pci_slot *slot = chip->slots[i]; 66 struct sdhci_host *host; 67 68 if (!slot) 69 continue; 70 71 host = slot->host; 72 73 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 74 mmc_retune_needed(host->mmc); 75 76 ret = sdhci_suspend_host(host); 77 if (ret) 78 goto err_pci_suspend; 79 } 80 81 return 0; 82 83 err_pci_suspend: 84 while (--i >= 0) 85 sdhci_resume_host(chip->slots[i]->host); 86 return ret; 87 } 88 89 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip) 90 { 91 struct sdhci_pci_slot *slot; 92 int i, ret; 93 94 for (i = 0; i < chip->num_slots; i++) { 95 slot = chip->slots[i]; 96 if (!slot) 97 continue; 98 99 ret = sdhci_resume_host(slot->host); 100 if (ret) 101 return ret; 102 } 103 104 return 0; 105 } 106 107 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip) 108 { 109 int ret; 110 111 ret = cqhci_suspend(chip->slots[0]->host->mmc); 112 if (ret) 113 return ret; 114 115 return sdhci_pci_suspend_host(chip); 116 } 117 118 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip) 119 { 120 int ret; 121 122 ret = sdhci_pci_resume_host(chip); 123 if (ret) 124 return ret; 125 126 return cqhci_resume(chip->slots[0]->host->mmc); 127 } 128 #endif 129 130 #ifdef CONFIG_PM 131 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip) 132 { 133 struct sdhci_pci_slot *slot; 134 struct sdhci_host *host; 135 int i, ret; 136 137 for (i = 0; i < chip->num_slots; i++) { 138 slot = chip->slots[i]; 139 if (!slot) 140 continue; 141 142 host = slot->host; 143 144 ret = sdhci_runtime_suspend_host(host); 145 if (ret) 146 goto err_pci_runtime_suspend; 147 148 if (chip->rpm_retune && 149 host->tuning_mode != SDHCI_TUNING_MODE_3) 150 mmc_retune_needed(host->mmc); 151 } 152 153 return 0; 154 155 err_pci_runtime_suspend: 156 while (--i >= 0) 157 sdhci_runtime_resume_host(chip->slots[i]->host); 158 return ret; 159 } 160 161 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip) 162 { 163 struct sdhci_pci_slot *slot; 164 int i, ret; 165 166 for (i = 0; i < chip->num_slots; i++) { 167 slot = chip->slots[i]; 168 if (!slot) 169 continue; 170 171 ret = sdhci_runtime_resume_host(slot->host); 172 if (ret) 173 return ret; 174 } 175 176 return 0; 177 } 178 179 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip) 180 { 181 int ret; 182 183 ret = cqhci_suspend(chip->slots[0]->host->mmc); 184 if (ret) 185 return ret; 186 187 return sdhci_pci_runtime_suspend_host(chip); 188 } 189 190 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip) 191 { 192 int ret; 193 194 ret = sdhci_pci_runtime_resume_host(chip); 195 if (ret) 196 return ret; 197 198 return cqhci_resume(chip->slots[0]->host->mmc); 199 } 200 #endif 201 202 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask) 203 { 204 int cmd_error = 0; 205 int data_error = 0; 206 207 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 208 return intmask; 209 210 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 211 212 return 0; 213 } 214 215 static void sdhci_pci_dumpregs(struct mmc_host *mmc) 216 { 217 sdhci_dumpregs(mmc_priv(mmc)); 218 } 219 220 /*****************************************************************************\ 221 * * 222 * Hardware specific quirk handling * 223 * * 224 \*****************************************************************************/ 225 226 static int ricoh_probe(struct sdhci_pci_chip *chip) 227 { 228 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 229 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 230 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 231 return 0; 232 } 233 234 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 235 { 236 slot->host->caps = 237 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 238 & SDHCI_TIMEOUT_CLK_MASK) | 239 240 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 241 & SDHCI_CLOCK_BASE_MASK) | 242 243 SDHCI_TIMEOUT_CLK_UNIT | 244 SDHCI_CAN_VDD_330 | 245 SDHCI_CAN_DO_HISPD | 246 SDHCI_CAN_DO_SDMA; 247 return 0; 248 } 249 250 #ifdef CONFIG_PM_SLEEP 251 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 252 { 253 /* Apply a delay to allow controller to settle */ 254 /* Otherwise it becomes confused if card state changed 255 during suspend */ 256 msleep(500); 257 return sdhci_pci_resume_host(chip); 258 } 259 #endif 260 261 static const struct sdhci_pci_fixes sdhci_ricoh = { 262 .probe = ricoh_probe, 263 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 264 SDHCI_QUIRK_FORCE_DMA | 265 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 266 }; 267 268 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 269 .probe_slot = ricoh_mmc_probe_slot, 270 #ifdef CONFIG_PM_SLEEP 271 .resume = ricoh_mmc_resume, 272 #endif 273 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 274 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 275 SDHCI_QUIRK_NO_CARD_NO_RESET | 276 SDHCI_QUIRK_MISSING_CAPS 277 }; 278 279 static const struct sdhci_pci_fixes sdhci_ene_712 = { 280 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 281 SDHCI_QUIRK_BROKEN_DMA, 282 }; 283 284 static const struct sdhci_pci_fixes sdhci_ene_714 = { 285 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 286 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 287 SDHCI_QUIRK_BROKEN_DMA, 288 }; 289 290 static const struct sdhci_pci_fixes sdhci_cafe = { 291 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 292 SDHCI_QUIRK_NO_BUSY_IRQ | 293 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 294 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 295 }; 296 297 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 298 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 299 }; 300 301 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 302 { 303 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 304 return 0; 305 } 306 307 /* 308 * ADMA operation is disabled for Moorestown platform due to 309 * hardware bugs. 310 */ 311 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 312 { 313 /* 314 * slots number is fixed here for MRST as SDIO3/5 are never used and 315 * have hardware bugs. 316 */ 317 chip->num_slots = 1; 318 return 0; 319 } 320 321 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 322 { 323 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 324 return 0; 325 } 326 327 #ifdef CONFIG_PM 328 329 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 330 { 331 struct sdhci_pci_slot *slot = dev_id; 332 struct sdhci_host *host = slot->host; 333 334 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 335 return IRQ_HANDLED; 336 } 337 338 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 339 { 340 int err, irq, gpio = slot->cd_gpio; 341 342 slot->cd_gpio = -EINVAL; 343 slot->cd_irq = -EINVAL; 344 345 if (!gpio_is_valid(gpio)) 346 return; 347 348 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 349 if (err < 0) 350 goto out; 351 352 err = gpio_direction_input(gpio); 353 if (err < 0) 354 goto out_free; 355 356 irq = gpio_to_irq(gpio); 357 if (irq < 0) 358 goto out_free; 359 360 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 361 IRQF_TRIGGER_FALLING, "sd_cd", slot); 362 if (err) 363 goto out_free; 364 365 slot->cd_gpio = gpio; 366 slot->cd_irq = irq; 367 368 return; 369 370 out_free: 371 devm_gpio_free(&slot->chip->pdev->dev, gpio); 372 out: 373 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 374 } 375 376 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 377 { 378 if (slot->cd_irq >= 0) 379 free_irq(slot->cd_irq, slot); 380 } 381 382 #else 383 384 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 385 { 386 } 387 388 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 389 { 390 } 391 392 #endif 393 394 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 395 { 396 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 397 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC; 398 return 0; 399 } 400 401 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 402 { 403 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 404 return 0; 405 } 406 407 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 408 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 409 .probe_slot = mrst_hc_probe_slot, 410 }; 411 412 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 413 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 414 .probe = mrst_hc_probe, 415 }; 416 417 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 418 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 419 .allow_runtime_pm = true, 420 .own_cd_for_runtime_pm = true, 421 }; 422 423 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 424 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 425 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 426 .allow_runtime_pm = true, 427 .probe_slot = mfd_sdio_probe_slot, 428 }; 429 430 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 431 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 432 .allow_runtime_pm = true, 433 .probe_slot = mfd_emmc_probe_slot, 434 }; 435 436 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 437 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 438 .probe_slot = pch_hc_probe_slot, 439 }; 440 441 enum { 442 INTEL_DSM_FNS = 0, 443 INTEL_DSM_V18_SWITCH = 3, 444 INTEL_DSM_DRV_STRENGTH = 9, 445 INTEL_DSM_D3_RETUNE = 10, 446 }; 447 448 struct intel_host { 449 u32 dsm_fns; 450 int drv_strength; 451 bool d3_retune; 452 }; 453 454 static const guid_t intel_dsm_guid = 455 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F, 456 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61); 457 458 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 459 unsigned int fn, u32 *result) 460 { 461 union acpi_object *obj; 462 int err = 0; 463 size_t len; 464 465 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL); 466 if (!obj) 467 return -EOPNOTSUPP; 468 469 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { 470 err = -EINVAL; 471 goto out; 472 } 473 474 len = min_t(size_t, obj->buffer.length, 4); 475 476 *result = 0; 477 memcpy(result, obj->buffer.pointer, len); 478 out: 479 ACPI_FREE(obj); 480 481 return err; 482 } 483 484 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 485 unsigned int fn, u32 *result) 486 { 487 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 488 return -EOPNOTSUPP; 489 490 return __intel_dsm(intel_host, dev, fn, result); 491 } 492 493 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 494 struct mmc_host *mmc) 495 { 496 int err; 497 u32 val; 498 499 intel_host->d3_retune = true; 500 501 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 502 if (err) { 503 pr_debug("%s: DSM not supported, error %d\n", 504 mmc_hostname(mmc), err); 505 return; 506 } 507 508 pr_debug("%s: DSM function mask %#x\n", 509 mmc_hostname(mmc), intel_host->dsm_fns); 510 511 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 512 intel_host->drv_strength = err ? 0 : val; 513 514 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 515 intel_host->d3_retune = err ? true : !!val; 516 } 517 518 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 519 { 520 u8 reg; 521 522 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 523 reg |= 0x10; 524 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 525 /* For eMMC, minimum is 1us but give it 9us for good measure */ 526 udelay(9); 527 reg &= ~0x10; 528 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 529 /* For eMMC, minimum is 200us but give it 300us for good measure */ 530 usleep_range(300, 1000); 531 } 532 533 static int intel_select_drive_strength(struct mmc_card *card, 534 unsigned int max_dtr, int host_drv, 535 int card_drv, int *drv_type) 536 { 537 struct sdhci_host *host = mmc_priv(card->host); 538 struct sdhci_pci_slot *slot = sdhci_priv(host); 539 struct intel_host *intel_host = sdhci_pci_priv(slot); 540 541 return intel_host->drv_strength; 542 } 543 544 static int bxt_get_cd(struct mmc_host *mmc) 545 { 546 int gpio_cd = mmc_gpio_get_cd(mmc); 547 struct sdhci_host *host = mmc_priv(mmc); 548 unsigned long flags; 549 int ret = 0; 550 551 if (!gpio_cd) 552 return 0; 553 554 spin_lock_irqsave(&host->lock, flags); 555 556 if (host->flags & SDHCI_DEVICE_DEAD) 557 goto out; 558 559 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 560 out: 561 spin_unlock_irqrestore(&host->lock, flags); 562 563 return ret; 564 } 565 566 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 567 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 568 569 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 570 unsigned short vdd) 571 { 572 int cntr; 573 u8 reg; 574 575 sdhci_set_power(host, mode, vdd); 576 577 if (mode == MMC_POWER_OFF) 578 return; 579 580 /* 581 * Bus power might not enable after D3 -> D0 transition due to the 582 * present state not yet having propagated. Retry for up to 2ms. 583 */ 584 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 585 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 586 if (reg & SDHCI_POWER_ON) 587 break; 588 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 589 reg |= SDHCI_POWER_ON; 590 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 591 } 592 } 593 594 #define INTEL_HS400_ES_REG 0x78 595 #define INTEL_HS400_ES_BIT BIT(0) 596 597 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc, 598 struct mmc_ios *ios) 599 { 600 struct sdhci_host *host = mmc_priv(mmc); 601 u32 val; 602 603 val = sdhci_readl(host, INTEL_HS400_ES_REG); 604 if (ios->enhanced_strobe) 605 val |= INTEL_HS400_ES_BIT; 606 else 607 val &= ~INTEL_HS400_ES_BIT; 608 sdhci_writel(host, val, INTEL_HS400_ES_REG); 609 } 610 611 static void sdhci_intel_voltage_switch(struct sdhci_host *host) 612 { 613 struct sdhci_pci_slot *slot = sdhci_priv(host); 614 struct intel_host *intel_host = sdhci_pci_priv(slot); 615 struct device *dev = &slot->chip->pdev->dev; 616 u32 result = 0; 617 int err; 618 619 err = intel_dsm(intel_host, dev, INTEL_DSM_V18_SWITCH, &result); 620 pr_debug("%s: %s DSM error %d result %u\n", 621 mmc_hostname(host->mmc), __func__, err, result); 622 } 623 624 static const struct sdhci_ops sdhci_intel_byt_ops = { 625 .set_clock = sdhci_set_clock, 626 .set_power = sdhci_intel_set_power, 627 .enable_dma = sdhci_pci_enable_dma, 628 .set_bus_width = sdhci_set_bus_width, 629 .reset = sdhci_reset, 630 .set_uhs_signaling = sdhci_set_uhs_signaling, 631 .hw_reset = sdhci_pci_hw_reset, 632 .voltage_switch = sdhci_intel_voltage_switch, 633 }; 634 635 static const struct sdhci_ops sdhci_intel_glk_ops = { 636 .set_clock = sdhci_set_clock, 637 .set_power = sdhci_intel_set_power, 638 .enable_dma = sdhci_pci_enable_dma, 639 .set_bus_width = sdhci_set_bus_width, 640 .reset = sdhci_reset, 641 .set_uhs_signaling = sdhci_set_uhs_signaling, 642 .hw_reset = sdhci_pci_hw_reset, 643 .voltage_switch = sdhci_intel_voltage_switch, 644 .irq = sdhci_cqhci_irq, 645 }; 646 647 static void byt_read_dsm(struct sdhci_pci_slot *slot) 648 { 649 struct intel_host *intel_host = sdhci_pci_priv(slot); 650 struct device *dev = &slot->chip->pdev->dev; 651 struct mmc_host *mmc = slot->host->mmc; 652 653 intel_dsm_init(intel_host, dev, mmc); 654 slot->chip->rpm_retune = intel_host->d3_retune; 655 } 656 657 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode) 658 { 659 int err = sdhci_execute_tuning(mmc, opcode); 660 struct sdhci_host *host = mmc_priv(mmc); 661 662 if (err) 663 return err; 664 665 /* 666 * Tuning can leave the IP in an active state (Buffer Read Enable bit 667 * set) which prevents the entry to low power states (i.e. S0i3). Data 668 * reset will clear it. 669 */ 670 sdhci_reset(host, SDHCI_RESET_DATA); 671 672 return 0; 673 } 674 675 static void byt_probe_slot(struct sdhci_pci_slot *slot) 676 { 677 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 678 679 byt_read_dsm(slot); 680 681 ops->execute_tuning = intel_execute_tuning; 682 } 683 684 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 685 { 686 byt_probe_slot(slot); 687 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 688 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 689 MMC_CAP_CMD_DURING_TFR | 690 MMC_CAP_WAIT_WHILE_BUSY; 691 slot->hw_reset = sdhci_pci_int_hw_reset; 692 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 693 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 694 slot->host->mmc_host_ops.select_drive_strength = 695 intel_select_drive_strength; 696 return 0; 697 } 698 699 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot) 700 { 701 int ret = byt_emmc_probe_slot(slot); 702 703 slot->host->mmc->caps2 |= MMC_CAP2_CQE; 704 705 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) { 706 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES, 707 slot->host->mmc_host_ops.hs400_enhanced_strobe = 708 intel_hs400_enhanced_strobe; 709 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; 710 } 711 712 return ret; 713 } 714 715 static const struct cqhci_host_ops glk_cqhci_ops = { 716 .enable = sdhci_cqe_enable, 717 .disable = sdhci_cqe_disable, 718 .dumpregs = sdhci_pci_dumpregs, 719 }; 720 721 static int glk_emmc_add_host(struct sdhci_pci_slot *slot) 722 { 723 struct device *dev = &slot->chip->pdev->dev; 724 struct sdhci_host *host = slot->host; 725 struct cqhci_host *cq_host; 726 bool dma64; 727 int ret; 728 729 ret = sdhci_setup_host(host); 730 if (ret) 731 return ret; 732 733 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); 734 if (!cq_host) { 735 ret = -ENOMEM; 736 goto cleanup; 737 } 738 739 cq_host->mmio = host->ioaddr + 0x200; 740 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 741 cq_host->ops = &glk_cqhci_ops; 742 743 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 744 if (dma64) 745 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 746 747 ret = cqhci_init(cq_host, host->mmc, dma64); 748 if (ret) 749 goto cleanup; 750 751 ret = __sdhci_add_host(host); 752 if (ret) 753 goto cleanup; 754 755 return 0; 756 757 cleanup: 758 sdhci_cleanup_host(host); 759 return ret; 760 } 761 762 #ifdef CONFIG_ACPI 763 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 764 { 765 acpi_status status; 766 unsigned long long max_freq; 767 768 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 769 "MXFQ", NULL, &max_freq); 770 if (ACPI_FAILURE(status)) { 771 dev_err(&slot->chip->pdev->dev, 772 "MXFQ not found in acpi table\n"); 773 return -EINVAL; 774 } 775 776 slot->host->mmc->f_max = max_freq * 1000000; 777 778 return 0; 779 } 780 #else 781 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 782 { 783 return 0; 784 } 785 #endif 786 787 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 788 { 789 int err; 790 791 byt_probe_slot(slot); 792 793 err = ni_set_max_freq(slot); 794 if (err) 795 return err; 796 797 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 798 MMC_CAP_WAIT_WHILE_BUSY; 799 return 0; 800 } 801 802 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 803 { 804 byt_probe_slot(slot); 805 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 806 MMC_CAP_WAIT_WHILE_BUSY; 807 return 0; 808 } 809 810 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 811 { 812 byt_probe_slot(slot); 813 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | 814 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE; 815 slot->cd_idx = 0; 816 slot->cd_override_level = true; 817 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 818 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 819 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 820 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) 821 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 822 823 return 0; 824 } 825 826 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 827 .allow_runtime_pm = true, 828 .probe_slot = byt_emmc_probe_slot, 829 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 830 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 831 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 832 SDHCI_QUIRK2_STOP_WITH_TC, 833 .ops = &sdhci_intel_byt_ops, 834 .priv_size = sizeof(struct intel_host), 835 }; 836 837 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = { 838 .allow_runtime_pm = true, 839 .probe_slot = glk_emmc_probe_slot, 840 .add_host = glk_emmc_add_host, 841 #ifdef CONFIG_PM_SLEEP 842 .suspend = sdhci_cqhci_suspend, 843 .resume = sdhci_cqhci_resume, 844 #endif 845 #ifdef CONFIG_PM 846 .runtime_suspend = sdhci_cqhci_runtime_suspend, 847 .runtime_resume = sdhci_cqhci_runtime_resume, 848 #endif 849 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 850 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 851 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 852 SDHCI_QUIRK2_STOP_WITH_TC, 853 .ops = &sdhci_intel_glk_ops, 854 .priv_size = sizeof(struct intel_host), 855 }; 856 857 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 858 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 859 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 860 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 861 .allow_runtime_pm = true, 862 .probe_slot = ni_byt_sdio_probe_slot, 863 .ops = &sdhci_intel_byt_ops, 864 .priv_size = sizeof(struct intel_host), 865 }; 866 867 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 868 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 869 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 870 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 871 .allow_runtime_pm = true, 872 .probe_slot = byt_sdio_probe_slot, 873 .ops = &sdhci_intel_byt_ops, 874 .priv_size = sizeof(struct intel_host), 875 }; 876 877 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 878 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 879 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 880 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 881 SDHCI_QUIRK2_STOP_WITH_TC, 882 .allow_runtime_pm = true, 883 .own_cd_for_runtime_pm = true, 884 .probe_slot = byt_sd_probe_slot, 885 .ops = &sdhci_intel_byt_ops, 886 .priv_size = sizeof(struct intel_host), 887 }; 888 889 /* Define Host controllers for Intel Merrifield platform */ 890 #define INTEL_MRFLD_EMMC_0 0 891 #define INTEL_MRFLD_EMMC_1 1 892 #define INTEL_MRFLD_SD 2 893 #define INTEL_MRFLD_SDIO 3 894 895 #ifdef CONFIG_ACPI 896 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) 897 { 898 struct acpi_device *device, *child; 899 900 device = ACPI_COMPANION(&slot->chip->pdev->dev); 901 if (!device) 902 return; 903 904 acpi_device_fix_up_power(device); 905 list_for_each_entry(child, &device->children, node) 906 if (child->status.present && child->status.enabled) 907 acpi_device_fix_up_power(child); 908 } 909 #else 910 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {} 911 #endif 912 913 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 914 { 915 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 916 917 switch (func) { 918 case INTEL_MRFLD_EMMC_0: 919 case INTEL_MRFLD_EMMC_1: 920 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 921 MMC_CAP_8_BIT_DATA | 922 MMC_CAP_1_8V_DDR; 923 break; 924 case INTEL_MRFLD_SD: 925 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 926 break; 927 case INTEL_MRFLD_SDIO: 928 /* Advertise 2.0v for compatibility with the SDIO card's OCR */ 929 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195; 930 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 931 MMC_CAP_POWER_OFF_CARD; 932 break; 933 default: 934 return -ENODEV; 935 } 936 937 intel_mrfld_mmc_fix_up_power_slot(slot); 938 return 0; 939 } 940 941 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 942 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 943 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 944 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 945 .allow_runtime_pm = true, 946 .probe_slot = intel_mrfld_mmc_probe_slot, 947 }; 948 949 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 950 { 951 u8 scratch; 952 int ret; 953 954 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 955 if (ret) 956 return ret; 957 958 /* 959 * Turn PMOS on [bit 0], set over current detection to 2.4 V 960 * [bit 1:2] and enable over current debouncing [bit 6]. 961 */ 962 if (on) 963 scratch |= 0x47; 964 else 965 scratch &= ~0x47; 966 967 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 968 } 969 970 static int jmicron_probe(struct sdhci_pci_chip *chip) 971 { 972 int ret; 973 u16 mmcdev = 0; 974 975 if (chip->pdev->revision == 0) { 976 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 977 SDHCI_QUIRK_32BIT_DMA_SIZE | 978 SDHCI_QUIRK_32BIT_ADMA_SIZE | 979 SDHCI_QUIRK_RESET_AFTER_REQUEST | 980 SDHCI_QUIRK_BROKEN_SMALL_PIO; 981 } 982 983 /* 984 * JMicron chips can have two interfaces to the same hardware 985 * in order to work around limitations in Microsoft's driver. 986 * We need to make sure we only bind to one of them. 987 * 988 * This code assumes two things: 989 * 990 * 1. The PCI code adds subfunctions in order. 991 * 992 * 2. The MMC interface has a lower subfunction number 993 * than the SD interface. 994 */ 995 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 996 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 997 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 998 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 999 1000 if (mmcdev) { 1001 struct pci_dev *sd_dev; 1002 1003 sd_dev = NULL; 1004 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 1005 mmcdev, sd_dev)) != NULL) { 1006 if ((PCI_SLOT(chip->pdev->devfn) == 1007 PCI_SLOT(sd_dev->devfn)) && 1008 (chip->pdev->bus == sd_dev->bus)) 1009 break; 1010 } 1011 1012 if (sd_dev) { 1013 pci_dev_put(sd_dev); 1014 dev_info(&chip->pdev->dev, "Refusing to bind to " 1015 "secondary interface.\n"); 1016 return -ENODEV; 1017 } 1018 } 1019 1020 /* 1021 * JMicron chips need a bit of a nudge to enable the power 1022 * output pins. 1023 */ 1024 ret = jmicron_pmos(chip, 1); 1025 if (ret) { 1026 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1027 return ret; 1028 } 1029 1030 /* quirk for unsable RO-detection on JM388 chips */ 1031 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 1032 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1033 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 1034 1035 return 0; 1036 } 1037 1038 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 1039 { 1040 u8 scratch; 1041 1042 scratch = readb(host->ioaddr + 0xC0); 1043 1044 if (on) 1045 scratch |= 0x01; 1046 else 1047 scratch &= ~0x01; 1048 1049 writeb(scratch, host->ioaddr + 0xC0); 1050 } 1051 1052 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 1053 { 1054 if (slot->chip->pdev->revision == 0) { 1055 u16 version; 1056 1057 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 1058 version = (version & SDHCI_VENDOR_VER_MASK) >> 1059 SDHCI_VENDOR_VER_SHIFT; 1060 1061 /* 1062 * Older versions of the chip have lots of nasty glitches 1063 * in the ADMA engine. It's best just to avoid it 1064 * completely. 1065 */ 1066 if (version < 0xAC) 1067 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 1068 } 1069 1070 /* JM388 MMC doesn't support 1.8V while SD supports it */ 1071 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1072 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 1073 MMC_VDD_29_30 | MMC_VDD_30_31 | 1074 MMC_VDD_165_195; /* allow 1.8V */ 1075 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 1076 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 1077 } 1078 1079 /* 1080 * The secondary interface requires a bit set to get the 1081 * interrupts. 1082 */ 1083 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1084 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1085 jmicron_enable_mmc(slot->host, 1); 1086 1087 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 1088 1089 return 0; 1090 } 1091 1092 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 1093 { 1094 if (dead) 1095 return; 1096 1097 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1098 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1099 jmicron_enable_mmc(slot->host, 0); 1100 } 1101 1102 #ifdef CONFIG_PM_SLEEP 1103 static int jmicron_suspend(struct sdhci_pci_chip *chip) 1104 { 1105 int i, ret; 1106 1107 ret = sdhci_pci_suspend_host(chip); 1108 if (ret) 1109 return ret; 1110 1111 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1112 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1113 for (i = 0; i < chip->num_slots; i++) 1114 jmicron_enable_mmc(chip->slots[i]->host, 0); 1115 } 1116 1117 return 0; 1118 } 1119 1120 static int jmicron_resume(struct sdhci_pci_chip *chip) 1121 { 1122 int ret, i; 1123 1124 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1125 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1126 for (i = 0; i < chip->num_slots; i++) 1127 jmicron_enable_mmc(chip->slots[i]->host, 1); 1128 } 1129 1130 ret = jmicron_pmos(chip, 1); 1131 if (ret) { 1132 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1133 return ret; 1134 } 1135 1136 return sdhci_pci_resume_host(chip); 1137 } 1138 #endif 1139 1140 static const struct sdhci_pci_fixes sdhci_o2 = { 1141 .probe = sdhci_pci_o2_probe, 1142 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1143 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 1144 .probe_slot = sdhci_pci_o2_probe_slot, 1145 #ifdef CONFIG_PM_SLEEP 1146 .resume = sdhci_pci_o2_resume, 1147 #endif 1148 }; 1149 1150 static const struct sdhci_pci_fixes sdhci_jmicron = { 1151 .probe = jmicron_probe, 1152 1153 .probe_slot = jmicron_probe_slot, 1154 .remove_slot = jmicron_remove_slot, 1155 1156 #ifdef CONFIG_PM_SLEEP 1157 .suspend = jmicron_suspend, 1158 .resume = jmicron_resume, 1159 #endif 1160 }; 1161 1162 /* SysKonnect CardBus2SDIO extra registers */ 1163 #define SYSKT_CTRL 0x200 1164 #define SYSKT_RDFIFO_STAT 0x204 1165 #define SYSKT_WRFIFO_STAT 0x208 1166 #define SYSKT_POWER_DATA 0x20c 1167 #define SYSKT_POWER_330 0xef 1168 #define SYSKT_POWER_300 0xf8 1169 #define SYSKT_POWER_184 0xcc 1170 #define SYSKT_POWER_CMD 0x20d 1171 #define SYSKT_POWER_START (1 << 7) 1172 #define SYSKT_POWER_STATUS 0x20e 1173 #define SYSKT_POWER_STATUS_OK (1 << 0) 1174 #define SYSKT_BOARD_REV 0x210 1175 #define SYSKT_CHIP_REV 0x211 1176 #define SYSKT_CONF_DATA 0x212 1177 #define SYSKT_CONF_DATA_1V8 (1 << 2) 1178 #define SYSKT_CONF_DATA_2V5 (1 << 1) 1179 #define SYSKT_CONF_DATA_3V3 (1 << 0) 1180 1181 static int syskt_probe(struct sdhci_pci_chip *chip) 1182 { 1183 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1184 chip->pdev->class &= ~0x0000FF; 1185 chip->pdev->class |= PCI_SDHCI_IFDMA; 1186 } 1187 return 0; 1188 } 1189 1190 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 1191 { 1192 int tm, ps; 1193 1194 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 1195 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 1196 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 1197 "board rev %d.%d, chip rev %d.%d\n", 1198 board_rev >> 4, board_rev & 0xf, 1199 chip_rev >> 4, chip_rev & 0xf); 1200 if (chip_rev >= 0x20) 1201 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 1202 1203 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 1204 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 1205 udelay(50); 1206 tm = 10; /* Wait max 1 ms */ 1207 do { 1208 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 1209 if (ps & SYSKT_POWER_STATUS_OK) 1210 break; 1211 udelay(100); 1212 } while (--tm); 1213 if (!tm) { 1214 dev_err(&slot->chip->pdev->dev, 1215 "power regulator never stabilized"); 1216 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 1217 return -ENODEV; 1218 } 1219 1220 return 0; 1221 } 1222 1223 static const struct sdhci_pci_fixes sdhci_syskt = { 1224 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 1225 .probe = syskt_probe, 1226 .probe_slot = syskt_probe_slot, 1227 }; 1228 1229 static int via_probe(struct sdhci_pci_chip *chip) 1230 { 1231 if (chip->pdev->revision == 0x10) 1232 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 1233 1234 return 0; 1235 } 1236 1237 static const struct sdhci_pci_fixes sdhci_via = { 1238 .probe = via_probe, 1239 }; 1240 1241 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 1242 { 1243 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 1244 return 0; 1245 } 1246 1247 static const struct sdhci_pci_fixes sdhci_rtsx = { 1248 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1249 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 1250 SDHCI_QUIRK2_BROKEN_DDR50, 1251 .probe_slot = rtsx_probe_slot, 1252 }; 1253 1254 /*AMD chipset generation*/ 1255 enum amd_chipset_gen { 1256 AMD_CHIPSET_BEFORE_ML, 1257 AMD_CHIPSET_CZ, 1258 AMD_CHIPSET_NL, 1259 AMD_CHIPSET_UNKNOWN, 1260 }; 1261 1262 /* AMD registers */ 1263 #define AMD_SD_AUTO_PATTERN 0xB8 1264 #define AMD_MSLEEP_DURATION 4 1265 #define AMD_SD_MISC_CONTROL 0xD0 1266 #define AMD_MAX_TUNE_VALUE 0x0B 1267 #define AMD_AUTO_TUNE_SEL 0x10800 1268 #define AMD_FIFO_PTR 0x30 1269 #define AMD_BIT_MASK 0x1F 1270 1271 static void amd_tuning_reset(struct sdhci_host *host) 1272 { 1273 unsigned int val; 1274 1275 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1276 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 1277 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1278 1279 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1280 val &= ~SDHCI_CTRL_EXEC_TUNING; 1281 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1282 } 1283 1284 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 1285 { 1286 unsigned int val; 1287 1288 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 1289 val &= ~AMD_BIT_MASK; 1290 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 1291 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 1292 } 1293 1294 static void amd_enable_manual_tuning(struct pci_dev *pdev) 1295 { 1296 unsigned int val; 1297 1298 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 1299 val |= AMD_FIFO_PTR; 1300 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 1301 } 1302 1303 static int amd_execute_tuning(struct sdhci_host *host, u32 opcode) 1304 { 1305 struct sdhci_pci_slot *slot = sdhci_priv(host); 1306 struct pci_dev *pdev = slot->chip->pdev; 1307 u8 valid_win = 0; 1308 u8 valid_win_max = 0; 1309 u8 valid_win_end = 0; 1310 u8 ctrl, tune_around; 1311 1312 amd_tuning_reset(host); 1313 1314 for (tune_around = 0; tune_around < 12; tune_around++) { 1315 amd_config_tuning_phase(pdev, tune_around); 1316 1317 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1318 valid_win = 0; 1319 msleep(AMD_MSLEEP_DURATION); 1320 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 1321 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 1322 } else if (++valid_win > valid_win_max) { 1323 valid_win_max = valid_win; 1324 valid_win_end = tune_around; 1325 } 1326 } 1327 1328 if (!valid_win_max) { 1329 dev_err(&pdev->dev, "no tuning point found\n"); 1330 return -EIO; 1331 } 1332 1333 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 1334 1335 amd_enable_manual_tuning(pdev); 1336 1337 host->mmc->retune_period = 0; 1338 1339 return 0; 1340 } 1341 1342 static int amd_probe(struct sdhci_pci_chip *chip) 1343 { 1344 struct pci_dev *smbus_dev; 1345 enum amd_chipset_gen gen; 1346 1347 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1348 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 1349 if (smbus_dev) { 1350 gen = AMD_CHIPSET_BEFORE_ML; 1351 } else { 1352 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1353 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1354 if (smbus_dev) { 1355 if (smbus_dev->revision < 0x51) 1356 gen = AMD_CHIPSET_CZ; 1357 else 1358 gen = AMD_CHIPSET_NL; 1359 } else { 1360 gen = AMD_CHIPSET_UNKNOWN; 1361 } 1362 } 1363 1364 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1365 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1366 1367 return 0; 1368 } 1369 1370 static const struct sdhci_ops amd_sdhci_pci_ops = { 1371 .set_clock = sdhci_set_clock, 1372 .enable_dma = sdhci_pci_enable_dma, 1373 .set_bus_width = sdhci_set_bus_width, 1374 .reset = sdhci_reset, 1375 .set_uhs_signaling = sdhci_set_uhs_signaling, 1376 .platform_execute_tuning = amd_execute_tuning, 1377 }; 1378 1379 static const struct sdhci_pci_fixes sdhci_amd = { 1380 .probe = amd_probe, 1381 .ops = &amd_sdhci_pci_ops, 1382 }; 1383 1384 static const struct pci_device_id pci_ids[] = { 1385 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh), 1386 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc), 1387 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc), 1388 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc), 1389 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712), 1390 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712), 1391 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714), 1392 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714), 1393 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe), 1394 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron), 1395 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron), 1396 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron), 1397 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron), 1398 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt), 1399 SDHCI_PCI_DEVICE(VIA, 95D0, via), 1400 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx), 1401 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk), 1402 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0), 1403 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2), 1404 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2), 1405 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd), 1406 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio), 1407 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio), 1408 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc), 1409 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc), 1410 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio), 1411 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio), 1412 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc), 1413 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio), 1414 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio), 1415 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd), 1416 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc), 1417 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc), 1418 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio), 1419 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd), 1420 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd), 1421 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio), 1422 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio), 1423 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc), 1424 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc), 1425 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc), 1426 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc), 1427 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio), 1428 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd), 1429 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc), 1430 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc), 1431 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc), 1432 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio), 1433 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd), 1434 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc), 1435 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio), 1436 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd), 1437 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc), 1438 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio), 1439 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd), 1440 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc), 1441 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio), 1442 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd), 1443 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc), 1444 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd), 1445 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd), 1446 SDHCI_PCI_DEVICE(O2, 8120, o2), 1447 SDHCI_PCI_DEVICE(O2, 8220, o2), 1448 SDHCI_PCI_DEVICE(O2, 8221, o2), 1449 SDHCI_PCI_DEVICE(O2, 8320, o2), 1450 SDHCI_PCI_DEVICE(O2, 8321, o2), 1451 SDHCI_PCI_DEVICE(O2, FUJIN2, o2), 1452 SDHCI_PCI_DEVICE(O2, SDS0, o2), 1453 SDHCI_PCI_DEVICE(O2, SDS1, o2), 1454 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2), 1455 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), 1456 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan), 1457 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), 1458 /* Generic SD host controller */ 1459 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, 1460 { /* end: all zeroes */ }, 1461 }; 1462 1463 MODULE_DEVICE_TABLE(pci, pci_ids); 1464 1465 /*****************************************************************************\ 1466 * * 1467 * SDHCI core callbacks * 1468 * * 1469 \*****************************************************************************/ 1470 1471 int sdhci_pci_enable_dma(struct sdhci_host *host) 1472 { 1473 struct sdhci_pci_slot *slot; 1474 struct pci_dev *pdev; 1475 1476 slot = sdhci_priv(host); 1477 pdev = slot->chip->pdev; 1478 1479 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1480 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1481 (host->flags & SDHCI_USE_SDMA)) { 1482 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1483 "doesn't fully claim to support it.\n"); 1484 } 1485 1486 pci_set_master(pdev); 1487 1488 return 0; 1489 } 1490 1491 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1492 { 1493 struct sdhci_pci_slot *slot = sdhci_priv(host); 1494 int rst_n_gpio = slot->rst_n_gpio; 1495 1496 if (!gpio_is_valid(rst_n_gpio)) 1497 return; 1498 gpio_set_value_cansleep(rst_n_gpio, 0); 1499 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1500 udelay(10); 1501 gpio_set_value_cansleep(rst_n_gpio, 1); 1502 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1503 usleep_range(300, 1000); 1504 } 1505 1506 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1507 { 1508 struct sdhci_pci_slot *slot = sdhci_priv(host); 1509 1510 if (slot->hw_reset) 1511 slot->hw_reset(host); 1512 } 1513 1514 static const struct sdhci_ops sdhci_pci_ops = { 1515 .set_clock = sdhci_set_clock, 1516 .enable_dma = sdhci_pci_enable_dma, 1517 .set_bus_width = sdhci_set_bus_width, 1518 .reset = sdhci_reset, 1519 .set_uhs_signaling = sdhci_set_uhs_signaling, 1520 .hw_reset = sdhci_pci_hw_reset, 1521 }; 1522 1523 /*****************************************************************************\ 1524 * * 1525 * Suspend/resume * 1526 * * 1527 \*****************************************************************************/ 1528 1529 #ifdef CONFIG_PM_SLEEP 1530 static int sdhci_pci_suspend(struct device *dev) 1531 { 1532 struct pci_dev *pdev = to_pci_dev(dev); 1533 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1534 1535 if (!chip) 1536 return 0; 1537 1538 if (chip->fixes && chip->fixes->suspend) 1539 return chip->fixes->suspend(chip); 1540 1541 return sdhci_pci_suspend_host(chip); 1542 } 1543 1544 static int sdhci_pci_resume(struct device *dev) 1545 { 1546 struct pci_dev *pdev = to_pci_dev(dev); 1547 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1548 1549 if (!chip) 1550 return 0; 1551 1552 if (chip->fixes && chip->fixes->resume) 1553 return chip->fixes->resume(chip); 1554 1555 return sdhci_pci_resume_host(chip); 1556 } 1557 #endif 1558 1559 #ifdef CONFIG_PM 1560 static int sdhci_pci_runtime_suspend(struct device *dev) 1561 { 1562 struct pci_dev *pdev = to_pci_dev(dev); 1563 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1564 1565 if (!chip) 1566 return 0; 1567 1568 if (chip->fixes && chip->fixes->runtime_suspend) 1569 return chip->fixes->runtime_suspend(chip); 1570 1571 return sdhci_pci_runtime_suspend_host(chip); 1572 } 1573 1574 static int sdhci_pci_runtime_resume(struct device *dev) 1575 { 1576 struct pci_dev *pdev = to_pci_dev(dev); 1577 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1578 1579 if (!chip) 1580 return 0; 1581 1582 if (chip->fixes && chip->fixes->runtime_resume) 1583 return chip->fixes->runtime_resume(chip); 1584 1585 return sdhci_pci_runtime_resume_host(chip); 1586 } 1587 #endif 1588 1589 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1590 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1591 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1592 sdhci_pci_runtime_resume, NULL) 1593 }; 1594 1595 /*****************************************************************************\ 1596 * * 1597 * Device probing/removal * 1598 * * 1599 \*****************************************************************************/ 1600 1601 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1602 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1603 int slotno) 1604 { 1605 struct sdhci_pci_slot *slot; 1606 struct sdhci_host *host; 1607 int ret, bar = first_bar + slotno; 1608 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 1609 1610 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1611 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1612 return ERR_PTR(-ENODEV); 1613 } 1614 1615 if (pci_resource_len(pdev, bar) < 0x100) { 1616 dev_err(&pdev->dev, "Invalid iomem size. You may " 1617 "experience problems.\n"); 1618 } 1619 1620 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1621 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1622 return ERR_PTR(-ENODEV); 1623 } 1624 1625 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1626 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1627 return ERR_PTR(-ENODEV); 1628 } 1629 1630 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 1631 if (IS_ERR(host)) { 1632 dev_err(&pdev->dev, "cannot allocate host\n"); 1633 return ERR_CAST(host); 1634 } 1635 1636 slot = sdhci_priv(host); 1637 1638 slot->chip = chip; 1639 slot->host = host; 1640 slot->rst_n_gpio = -EINVAL; 1641 slot->cd_gpio = -EINVAL; 1642 slot->cd_idx = -1; 1643 1644 /* Retrieve platform data if there is any */ 1645 if (*sdhci_pci_get_data) 1646 slot->data = sdhci_pci_get_data(pdev, slotno); 1647 1648 if (slot->data) { 1649 if (slot->data->setup) { 1650 ret = slot->data->setup(slot->data); 1651 if (ret) { 1652 dev_err(&pdev->dev, "platform setup failed\n"); 1653 goto free; 1654 } 1655 } 1656 slot->rst_n_gpio = slot->data->rst_n_gpio; 1657 slot->cd_gpio = slot->data->cd_gpio; 1658 } 1659 1660 host->hw_name = "PCI"; 1661 host->ops = chip->fixes && chip->fixes->ops ? 1662 chip->fixes->ops : 1663 &sdhci_pci_ops; 1664 host->quirks = chip->quirks; 1665 host->quirks2 = chip->quirks2; 1666 1667 host->irq = pdev->irq; 1668 1669 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1670 if (ret) { 1671 dev_err(&pdev->dev, "cannot request region\n"); 1672 goto cleanup; 1673 } 1674 1675 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1676 1677 if (chip->fixes && chip->fixes->probe_slot) { 1678 ret = chip->fixes->probe_slot(slot); 1679 if (ret) 1680 goto cleanup; 1681 } 1682 1683 if (gpio_is_valid(slot->rst_n_gpio)) { 1684 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1685 gpio_direction_output(slot->rst_n_gpio, 1); 1686 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1687 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1688 } else { 1689 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1690 slot->rst_n_gpio = -EINVAL; 1691 } 1692 } 1693 1694 host->mmc->pm_caps = MMC_PM_KEEP_POWER; 1695 host->mmc->slotno = slotno; 1696 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1697 1698 if (device_can_wakeup(&pdev->dev)) 1699 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ; 1700 1701 if (slot->cd_idx >= 0) { 1702 ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx, 1703 slot->cd_override_level, 0, NULL); 1704 if (ret == -EPROBE_DEFER) 1705 goto remove; 1706 1707 if (ret) { 1708 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 1709 slot->cd_idx = -1; 1710 } 1711 } 1712 1713 if (chip->fixes && chip->fixes->add_host) 1714 ret = chip->fixes->add_host(slot); 1715 else 1716 ret = sdhci_add_host(host); 1717 if (ret) 1718 goto remove; 1719 1720 sdhci_pci_add_own_cd(slot); 1721 1722 /* 1723 * Check if the chip needs a separate GPIO for card detect to wake up 1724 * from runtime suspend. If it is not there, don't allow runtime PM. 1725 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 1726 */ 1727 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 1728 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 1729 chip->allow_runtime_pm = false; 1730 1731 return slot; 1732 1733 remove: 1734 if (chip->fixes && chip->fixes->remove_slot) 1735 chip->fixes->remove_slot(slot, 0); 1736 1737 cleanup: 1738 if (slot->data && slot->data->cleanup) 1739 slot->data->cleanup(slot->data); 1740 1741 free: 1742 sdhci_free_host(host); 1743 1744 return ERR_PTR(ret); 1745 } 1746 1747 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 1748 { 1749 int dead; 1750 u32 scratch; 1751 1752 sdhci_pci_remove_own_cd(slot); 1753 1754 dead = 0; 1755 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 1756 if (scratch == (u32)-1) 1757 dead = 1; 1758 1759 sdhci_remove_host(slot->host, dead); 1760 1761 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 1762 slot->chip->fixes->remove_slot(slot, dead); 1763 1764 if (slot->data && slot->data->cleanup) 1765 slot->data->cleanup(slot->data); 1766 1767 sdhci_free_host(slot->host); 1768 } 1769 1770 static void sdhci_pci_runtime_pm_allow(struct device *dev) 1771 { 1772 pm_suspend_ignore_children(dev, 1); 1773 pm_runtime_set_autosuspend_delay(dev, 50); 1774 pm_runtime_use_autosuspend(dev); 1775 pm_runtime_allow(dev); 1776 /* Stay active until mmc core scans for a card */ 1777 pm_runtime_put_noidle(dev); 1778 } 1779 1780 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 1781 { 1782 pm_runtime_forbid(dev); 1783 pm_runtime_get_noresume(dev); 1784 } 1785 1786 static int sdhci_pci_probe(struct pci_dev *pdev, 1787 const struct pci_device_id *ent) 1788 { 1789 struct sdhci_pci_chip *chip; 1790 struct sdhci_pci_slot *slot; 1791 1792 u8 slots, first_bar; 1793 int ret, i; 1794 1795 BUG_ON(pdev == NULL); 1796 BUG_ON(ent == NULL); 1797 1798 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 1799 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 1800 1801 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 1802 if (ret) 1803 return ret; 1804 1805 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 1806 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 1807 if (slots == 0) 1808 return -ENODEV; 1809 1810 BUG_ON(slots > MAX_SLOTS); 1811 1812 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 1813 if (ret) 1814 return ret; 1815 1816 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 1817 1818 if (first_bar > 5) { 1819 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 1820 return -ENODEV; 1821 } 1822 1823 ret = pcim_enable_device(pdev); 1824 if (ret) 1825 return ret; 1826 1827 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 1828 if (!chip) 1829 return -ENOMEM; 1830 1831 chip->pdev = pdev; 1832 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 1833 if (chip->fixes) { 1834 chip->quirks = chip->fixes->quirks; 1835 chip->quirks2 = chip->fixes->quirks2; 1836 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 1837 } 1838 chip->num_slots = slots; 1839 chip->pm_retune = true; 1840 chip->rpm_retune = true; 1841 1842 pci_set_drvdata(pdev, chip); 1843 1844 if (chip->fixes && chip->fixes->probe) { 1845 ret = chip->fixes->probe(chip); 1846 if (ret) 1847 return ret; 1848 } 1849 1850 slots = chip->num_slots; /* Quirk may have changed this */ 1851 1852 for (i = 0; i < slots; i++) { 1853 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 1854 if (IS_ERR(slot)) { 1855 for (i--; i >= 0; i--) 1856 sdhci_pci_remove_slot(chip->slots[i]); 1857 return PTR_ERR(slot); 1858 } 1859 1860 chip->slots[i] = slot; 1861 } 1862 1863 if (chip->allow_runtime_pm) 1864 sdhci_pci_runtime_pm_allow(&pdev->dev); 1865 1866 return 0; 1867 } 1868 1869 static void sdhci_pci_remove(struct pci_dev *pdev) 1870 { 1871 int i; 1872 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1873 1874 if (chip->allow_runtime_pm) 1875 sdhci_pci_runtime_pm_forbid(&pdev->dev); 1876 1877 for (i = 0; i < chip->num_slots; i++) 1878 sdhci_pci_remove_slot(chip->slots[i]); 1879 } 1880 1881 static struct pci_driver sdhci_driver = { 1882 .name = "sdhci-pci", 1883 .id_table = pci_ids, 1884 .probe = sdhci_pci_probe, 1885 .remove = sdhci_pci_remove, 1886 .driver = { 1887 .pm = &sdhci_pci_pm_ops 1888 }, 1889 }; 1890 1891 module_pci_driver(sdhci_driver); 1892 1893 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 1894 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 1895 MODULE_LICENSE("GPL"); 1896