1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 3 * 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 5 * 6 * Thanks to the following companies for their support: 7 * 8 * - JMicron (hardware and technical support) 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/string.h> 13 #include <linux/delay.h> 14 #include <linux/highmem.h> 15 #include <linux/module.h> 16 #include <linux/pci.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/slab.h> 19 #include <linux/device.h> 20 #include <linux/mmc/host.h> 21 #include <linux/mmc/mmc.h> 22 #include <linux/scatterlist.h> 23 #include <linux/io.h> 24 #include <linux/iopoll.h> 25 #include <linux/gpio.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/mmc/slot-gpio.h> 28 #include <linux/mmc/sdhci-pci-data.h> 29 #include <linux/acpi.h> 30 31 #ifdef CONFIG_X86 32 #include <asm/iosf_mbi.h> 33 #endif 34 35 #include "cqhci.h" 36 37 #include "sdhci.h" 38 #include "sdhci-pci.h" 39 40 static void sdhci_pci_hw_reset(struct sdhci_host *host); 41 42 #ifdef CONFIG_PM_SLEEP 43 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip) 44 { 45 mmc_pm_flag_t pm_flags = 0; 46 bool cap_cd_wake = false; 47 int i; 48 49 for (i = 0; i < chip->num_slots; i++) { 50 struct sdhci_pci_slot *slot = chip->slots[i]; 51 52 if (slot) { 53 pm_flags |= slot->host->mmc->pm_flags; 54 if (slot->host->mmc->caps & MMC_CAP_CD_WAKE) 55 cap_cd_wake = true; 56 } 57 } 58 59 if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ)) 60 return device_wakeup_enable(&chip->pdev->dev); 61 else if (!cap_cd_wake) 62 return device_wakeup_disable(&chip->pdev->dev); 63 64 return 0; 65 } 66 67 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 68 { 69 int i, ret; 70 71 sdhci_pci_init_wakeup(chip); 72 73 for (i = 0; i < chip->num_slots; i++) { 74 struct sdhci_pci_slot *slot = chip->slots[i]; 75 struct sdhci_host *host; 76 77 if (!slot) 78 continue; 79 80 host = slot->host; 81 82 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 83 mmc_retune_needed(host->mmc); 84 85 ret = sdhci_suspend_host(host); 86 if (ret) 87 goto err_pci_suspend; 88 89 if (device_may_wakeup(&chip->pdev->dev)) 90 mmc_gpio_set_cd_wake(host->mmc, true); 91 } 92 93 return 0; 94 95 err_pci_suspend: 96 while (--i >= 0) 97 sdhci_resume_host(chip->slots[i]->host); 98 return ret; 99 } 100 101 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip) 102 { 103 struct sdhci_pci_slot *slot; 104 int i, ret; 105 106 for (i = 0; i < chip->num_slots; i++) { 107 slot = chip->slots[i]; 108 if (!slot) 109 continue; 110 111 ret = sdhci_resume_host(slot->host); 112 if (ret) 113 return ret; 114 115 mmc_gpio_set_cd_wake(slot->host->mmc, false); 116 } 117 118 return 0; 119 } 120 121 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip) 122 { 123 int ret; 124 125 ret = cqhci_suspend(chip->slots[0]->host->mmc); 126 if (ret) 127 return ret; 128 129 return sdhci_pci_suspend_host(chip); 130 } 131 132 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip) 133 { 134 int ret; 135 136 ret = sdhci_pci_resume_host(chip); 137 if (ret) 138 return ret; 139 140 return cqhci_resume(chip->slots[0]->host->mmc); 141 } 142 #endif 143 144 #ifdef CONFIG_PM 145 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip) 146 { 147 struct sdhci_pci_slot *slot; 148 struct sdhci_host *host; 149 int i, ret; 150 151 for (i = 0; i < chip->num_slots; i++) { 152 slot = chip->slots[i]; 153 if (!slot) 154 continue; 155 156 host = slot->host; 157 158 ret = sdhci_runtime_suspend_host(host); 159 if (ret) 160 goto err_pci_runtime_suspend; 161 162 if (chip->rpm_retune && 163 host->tuning_mode != SDHCI_TUNING_MODE_3) 164 mmc_retune_needed(host->mmc); 165 } 166 167 return 0; 168 169 err_pci_runtime_suspend: 170 while (--i >= 0) 171 sdhci_runtime_resume_host(chip->slots[i]->host, 0); 172 return ret; 173 } 174 175 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip) 176 { 177 struct sdhci_pci_slot *slot; 178 int i, ret; 179 180 for (i = 0; i < chip->num_slots; i++) { 181 slot = chip->slots[i]; 182 if (!slot) 183 continue; 184 185 ret = sdhci_runtime_resume_host(slot->host, 0); 186 if (ret) 187 return ret; 188 } 189 190 return 0; 191 } 192 193 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip) 194 { 195 int ret; 196 197 ret = cqhci_suspend(chip->slots[0]->host->mmc); 198 if (ret) 199 return ret; 200 201 return sdhci_pci_runtime_suspend_host(chip); 202 } 203 204 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip) 205 { 206 int ret; 207 208 ret = sdhci_pci_runtime_resume_host(chip); 209 if (ret) 210 return ret; 211 212 return cqhci_resume(chip->slots[0]->host->mmc); 213 } 214 #endif 215 216 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask) 217 { 218 int cmd_error = 0; 219 int data_error = 0; 220 221 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 222 return intmask; 223 224 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 225 226 return 0; 227 } 228 229 static void sdhci_pci_dumpregs(struct mmc_host *mmc) 230 { 231 sdhci_dumpregs(mmc_priv(mmc)); 232 } 233 234 /*****************************************************************************\ 235 * * 236 * Hardware specific quirk handling * 237 * * 238 \*****************************************************************************/ 239 240 static int ricoh_probe(struct sdhci_pci_chip *chip) 241 { 242 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 243 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 244 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 245 return 0; 246 } 247 248 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 249 { 250 slot->host->caps = 251 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 252 & SDHCI_TIMEOUT_CLK_MASK) | 253 254 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 255 & SDHCI_CLOCK_BASE_MASK) | 256 257 SDHCI_TIMEOUT_CLK_UNIT | 258 SDHCI_CAN_VDD_330 | 259 SDHCI_CAN_DO_HISPD | 260 SDHCI_CAN_DO_SDMA; 261 return 0; 262 } 263 264 #ifdef CONFIG_PM_SLEEP 265 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 266 { 267 /* Apply a delay to allow controller to settle */ 268 /* Otherwise it becomes confused if card state changed 269 during suspend */ 270 msleep(500); 271 return sdhci_pci_resume_host(chip); 272 } 273 #endif 274 275 static const struct sdhci_pci_fixes sdhci_ricoh = { 276 .probe = ricoh_probe, 277 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 278 SDHCI_QUIRK_FORCE_DMA | 279 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 280 }; 281 282 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 283 .probe_slot = ricoh_mmc_probe_slot, 284 #ifdef CONFIG_PM_SLEEP 285 .resume = ricoh_mmc_resume, 286 #endif 287 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 288 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 289 SDHCI_QUIRK_NO_CARD_NO_RESET | 290 SDHCI_QUIRK_MISSING_CAPS 291 }; 292 293 static const struct sdhci_pci_fixes sdhci_ene_712 = { 294 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 295 SDHCI_QUIRK_BROKEN_DMA, 296 }; 297 298 static const struct sdhci_pci_fixes sdhci_ene_714 = { 299 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 300 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 301 SDHCI_QUIRK_BROKEN_DMA, 302 }; 303 304 static const struct sdhci_pci_fixes sdhci_cafe = { 305 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 306 SDHCI_QUIRK_NO_BUSY_IRQ | 307 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 308 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 309 }; 310 311 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 312 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 313 }; 314 315 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 316 { 317 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 318 return 0; 319 } 320 321 /* 322 * ADMA operation is disabled for Moorestown platform due to 323 * hardware bugs. 324 */ 325 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 326 { 327 /* 328 * slots number is fixed here for MRST as SDIO3/5 are never used and 329 * have hardware bugs. 330 */ 331 chip->num_slots = 1; 332 return 0; 333 } 334 335 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 336 { 337 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 338 return 0; 339 } 340 341 #ifdef CONFIG_PM 342 343 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 344 { 345 struct sdhci_pci_slot *slot = dev_id; 346 struct sdhci_host *host = slot->host; 347 348 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 349 return IRQ_HANDLED; 350 } 351 352 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 353 { 354 int err, irq, gpio = slot->cd_gpio; 355 356 slot->cd_gpio = -EINVAL; 357 slot->cd_irq = -EINVAL; 358 359 if (!gpio_is_valid(gpio)) 360 return; 361 362 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 363 if (err < 0) 364 goto out; 365 366 err = gpio_direction_input(gpio); 367 if (err < 0) 368 goto out_free; 369 370 irq = gpio_to_irq(gpio); 371 if (irq < 0) 372 goto out_free; 373 374 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 375 IRQF_TRIGGER_FALLING, "sd_cd", slot); 376 if (err) 377 goto out_free; 378 379 slot->cd_gpio = gpio; 380 slot->cd_irq = irq; 381 382 return; 383 384 out_free: 385 devm_gpio_free(&slot->chip->pdev->dev, gpio); 386 out: 387 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 388 } 389 390 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 391 { 392 if (slot->cd_irq >= 0) 393 free_irq(slot->cd_irq, slot); 394 } 395 396 #else 397 398 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 399 { 400 } 401 402 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 403 { 404 } 405 406 #endif 407 408 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 409 { 410 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 411 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC; 412 return 0; 413 } 414 415 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 416 { 417 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 418 return 0; 419 } 420 421 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 422 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 423 .probe_slot = mrst_hc_probe_slot, 424 }; 425 426 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 427 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 428 .probe = mrst_hc_probe, 429 }; 430 431 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 432 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 433 .allow_runtime_pm = true, 434 .own_cd_for_runtime_pm = true, 435 }; 436 437 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 438 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 439 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 440 .allow_runtime_pm = true, 441 .probe_slot = mfd_sdio_probe_slot, 442 }; 443 444 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 445 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 446 .allow_runtime_pm = true, 447 .probe_slot = mfd_emmc_probe_slot, 448 }; 449 450 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 451 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 452 .probe_slot = pch_hc_probe_slot, 453 }; 454 455 #ifdef CONFIG_X86 456 457 #define BYT_IOSF_SCCEP 0x63 458 #define BYT_IOSF_OCP_NETCTRL0 0x1078 459 #define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8) 460 461 static void byt_ocp_setting(struct pci_dev *pdev) 462 { 463 u32 val = 0; 464 465 if (pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC && 466 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SDIO && 467 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SD && 468 pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC2) 469 return; 470 471 if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0, 472 &val)) { 473 dev_err(&pdev->dev, "%s read error\n", __func__); 474 return; 475 } 476 477 if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE)) 478 return; 479 480 val &= ~BYT_IOSF_OCP_TIMEOUT_BASE; 481 482 if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0, 483 val)) { 484 dev_err(&pdev->dev, "%s write error\n", __func__); 485 return; 486 } 487 488 dev_dbg(&pdev->dev, "%s completed\n", __func__); 489 } 490 491 #else 492 493 static inline void byt_ocp_setting(struct pci_dev *pdev) 494 { 495 } 496 497 #endif 498 499 enum { 500 INTEL_DSM_FNS = 0, 501 INTEL_DSM_V18_SWITCH = 3, 502 INTEL_DSM_V33_SWITCH = 4, 503 INTEL_DSM_DRV_STRENGTH = 9, 504 INTEL_DSM_D3_RETUNE = 10, 505 }; 506 507 struct intel_host { 508 u32 dsm_fns; 509 int drv_strength; 510 bool d3_retune; 511 bool rpm_retune_ok; 512 u32 glk_rx_ctrl1; 513 u32 glk_tun_val; 514 }; 515 516 static const guid_t intel_dsm_guid = 517 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F, 518 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61); 519 520 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 521 unsigned int fn, u32 *result) 522 { 523 union acpi_object *obj; 524 int err = 0; 525 size_t len; 526 527 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL); 528 if (!obj) 529 return -EOPNOTSUPP; 530 531 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { 532 err = -EINVAL; 533 goto out; 534 } 535 536 len = min_t(size_t, obj->buffer.length, 4); 537 538 *result = 0; 539 memcpy(result, obj->buffer.pointer, len); 540 out: 541 ACPI_FREE(obj); 542 543 return err; 544 } 545 546 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 547 unsigned int fn, u32 *result) 548 { 549 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 550 return -EOPNOTSUPP; 551 552 return __intel_dsm(intel_host, dev, fn, result); 553 } 554 555 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 556 struct mmc_host *mmc) 557 { 558 int err; 559 u32 val; 560 561 intel_host->d3_retune = true; 562 563 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 564 if (err) { 565 pr_debug("%s: DSM not supported, error %d\n", 566 mmc_hostname(mmc), err); 567 return; 568 } 569 570 pr_debug("%s: DSM function mask %#x\n", 571 mmc_hostname(mmc), intel_host->dsm_fns); 572 573 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 574 intel_host->drv_strength = err ? 0 : val; 575 576 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 577 intel_host->d3_retune = err ? true : !!val; 578 } 579 580 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 581 { 582 u8 reg; 583 584 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 585 reg |= 0x10; 586 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 587 /* For eMMC, minimum is 1us but give it 9us for good measure */ 588 udelay(9); 589 reg &= ~0x10; 590 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 591 /* For eMMC, minimum is 200us but give it 300us for good measure */ 592 usleep_range(300, 1000); 593 } 594 595 static int intel_select_drive_strength(struct mmc_card *card, 596 unsigned int max_dtr, int host_drv, 597 int card_drv, int *drv_type) 598 { 599 struct sdhci_host *host = mmc_priv(card->host); 600 struct sdhci_pci_slot *slot = sdhci_priv(host); 601 struct intel_host *intel_host = sdhci_pci_priv(slot); 602 603 return intel_host->drv_strength; 604 } 605 606 static int bxt_get_cd(struct mmc_host *mmc) 607 { 608 int gpio_cd = mmc_gpio_get_cd(mmc); 609 struct sdhci_host *host = mmc_priv(mmc); 610 unsigned long flags; 611 int ret = 0; 612 613 if (!gpio_cd) 614 return 0; 615 616 spin_lock_irqsave(&host->lock, flags); 617 618 if (host->flags & SDHCI_DEVICE_DEAD) 619 goto out; 620 621 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 622 out: 623 spin_unlock_irqrestore(&host->lock, flags); 624 625 return ret; 626 } 627 628 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 629 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 630 631 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 632 unsigned short vdd) 633 { 634 int cntr; 635 u8 reg; 636 637 sdhci_set_power(host, mode, vdd); 638 639 if (mode == MMC_POWER_OFF) 640 return; 641 642 /* 643 * Bus power might not enable after D3 -> D0 transition due to the 644 * present state not yet having propagated. Retry for up to 2ms. 645 */ 646 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 647 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 648 if (reg & SDHCI_POWER_ON) 649 break; 650 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 651 reg |= SDHCI_POWER_ON; 652 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 653 } 654 } 655 656 #define INTEL_HS400_ES_REG 0x78 657 #define INTEL_HS400_ES_BIT BIT(0) 658 659 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc, 660 struct mmc_ios *ios) 661 { 662 struct sdhci_host *host = mmc_priv(mmc); 663 u32 val; 664 665 val = sdhci_readl(host, INTEL_HS400_ES_REG); 666 if (ios->enhanced_strobe) 667 val |= INTEL_HS400_ES_BIT; 668 else 669 val &= ~INTEL_HS400_ES_BIT; 670 sdhci_writel(host, val, INTEL_HS400_ES_REG); 671 } 672 673 static int intel_start_signal_voltage_switch(struct mmc_host *mmc, 674 struct mmc_ios *ios) 675 { 676 struct device *dev = mmc_dev(mmc); 677 struct sdhci_host *host = mmc_priv(mmc); 678 struct sdhci_pci_slot *slot = sdhci_priv(host); 679 struct intel_host *intel_host = sdhci_pci_priv(slot); 680 unsigned int fn; 681 u32 result = 0; 682 int err; 683 684 err = sdhci_start_signal_voltage_switch(mmc, ios); 685 if (err) 686 return err; 687 688 switch (ios->signal_voltage) { 689 case MMC_SIGNAL_VOLTAGE_330: 690 fn = INTEL_DSM_V33_SWITCH; 691 break; 692 case MMC_SIGNAL_VOLTAGE_180: 693 fn = INTEL_DSM_V18_SWITCH; 694 break; 695 default: 696 return 0; 697 } 698 699 err = intel_dsm(intel_host, dev, fn, &result); 700 pr_debug("%s: %s DSM fn %u error %d result %u\n", 701 mmc_hostname(mmc), __func__, fn, err, result); 702 703 return 0; 704 } 705 706 static const struct sdhci_ops sdhci_intel_byt_ops = { 707 .set_clock = sdhci_set_clock, 708 .set_power = sdhci_intel_set_power, 709 .enable_dma = sdhci_pci_enable_dma, 710 .set_bus_width = sdhci_set_bus_width, 711 .reset = sdhci_reset, 712 .set_uhs_signaling = sdhci_set_uhs_signaling, 713 .hw_reset = sdhci_pci_hw_reset, 714 }; 715 716 static const struct sdhci_ops sdhci_intel_glk_ops = { 717 .set_clock = sdhci_set_clock, 718 .set_power = sdhci_intel_set_power, 719 .enable_dma = sdhci_pci_enable_dma, 720 .set_bus_width = sdhci_set_bus_width, 721 .reset = sdhci_reset, 722 .set_uhs_signaling = sdhci_set_uhs_signaling, 723 .hw_reset = sdhci_pci_hw_reset, 724 .irq = sdhci_cqhci_irq, 725 }; 726 727 static void byt_read_dsm(struct sdhci_pci_slot *slot) 728 { 729 struct intel_host *intel_host = sdhci_pci_priv(slot); 730 struct device *dev = &slot->chip->pdev->dev; 731 struct mmc_host *mmc = slot->host->mmc; 732 733 intel_dsm_init(intel_host, dev, mmc); 734 slot->chip->rpm_retune = intel_host->d3_retune; 735 } 736 737 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode) 738 { 739 int err = sdhci_execute_tuning(mmc, opcode); 740 struct sdhci_host *host = mmc_priv(mmc); 741 742 if (err) 743 return err; 744 745 /* 746 * Tuning can leave the IP in an active state (Buffer Read Enable bit 747 * set) which prevents the entry to low power states (i.e. S0i3). Data 748 * reset will clear it. 749 */ 750 sdhci_reset(host, SDHCI_RESET_DATA); 751 752 return 0; 753 } 754 755 static void byt_probe_slot(struct sdhci_pci_slot *slot) 756 { 757 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 758 struct device *dev = &slot->chip->pdev->dev; 759 struct mmc_host *mmc = slot->host->mmc; 760 761 byt_read_dsm(slot); 762 763 byt_ocp_setting(slot->chip->pdev); 764 765 ops->execute_tuning = intel_execute_tuning; 766 ops->start_signal_voltage_switch = intel_start_signal_voltage_switch; 767 768 device_property_read_u32(dev, "max-frequency", &mmc->f_max); 769 } 770 771 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 772 { 773 byt_probe_slot(slot); 774 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 775 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 776 MMC_CAP_CMD_DURING_TFR | 777 MMC_CAP_WAIT_WHILE_BUSY; 778 slot->hw_reset = sdhci_pci_int_hw_reset; 779 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 780 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 781 slot->host->mmc_host_ops.select_drive_strength = 782 intel_select_drive_strength; 783 return 0; 784 } 785 786 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot) 787 { 788 int ret = byt_emmc_probe_slot(slot); 789 790 slot->host->mmc->caps2 |= MMC_CAP2_CQE; 791 792 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) { 793 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES, 794 slot->host->mmc_host_ops.hs400_enhanced_strobe = 795 intel_hs400_enhanced_strobe; 796 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; 797 } 798 799 return ret; 800 } 801 802 static const struct cqhci_host_ops glk_cqhci_ops = { 803 .enable = sdhci_cqe_enable, 804 .disable = sdhci_cqe_disable, 805 .dumpregs = sdhci_pci_dumpregs, 806 }; 807 808 static int glk_emmc_add_host(struct sdhci_pci_slot *slot) 809 { 810 struct device *dev = &slot->chip->pdev->dev; 811 struct sdhci_host *host = slot->host; 812 struct cqhci_host *cq_host; 813 bool dma64; 814 int ret; 815 816 ret = sdhci_setup_host(host); 817 if (ret) 818 return ret; 819 820 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); 821 if (!cq_host) { 822 ret = -ENOMEM; 823 goto cleanup; 824 } 825 826 cq_host->mmio = host->ioaddr + 0x200; 827 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 828 cq_host->ops = &glk_cqhci_ops; 829 830 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 831 if (dma64) 832 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 833 834 ret = cqhci_init(cq_host, host->mmc, dma64); 835 if (ret) 836 goto cleanup; 837 838 ret = __sdhci_add_host(host); 839 if (ret) 840 goto cleanup; 841 842 return 0; 843 844 cleanup: 845 sdhci_cleanup_host(host); 846 return ret; 847 } 848 849 #ifdef CONFIG_PM 850 #define GLK_RX_CTRL1 0x834 851 #define GLK_TUN_VAL 0x840 852 #define GLK_PATH_PLL GENMASK(13, 8) 853 #define GLK_DLY GENMASK(6, 0) 854 /* Workaround firmware failing to restore the tuning value */ 855 static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp) 856 { 857 struct sdhci_pci_slot *slot = chip->slots[0]; 858 struct intel_host *intel_host = sdhci_pci_priv(slot); 859 struct sdhci_host *host = slot->host; 860 u32 glk_rx_ctrl1; 861 u32 glk_tun_val; 862 u32 dly; 863 864 if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc)) 865 return; 866 867 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1); 868 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL); 869 870 if (susp) { 871 intel_host->glk_rx_ctrl1 = glk_rx_ctrl1; 872 intel_host->glk_tun_val = glk_tun_val; 873 return; 874 } 875 876 if (!intel_host->glk_tun_val) 877 return; 878 879 if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) { 880 intel_host->rpm_retune_ok = true; 881 return; 882 } 883 884 dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) + 885 (intel_host->glk_tun_val << 1)); 886 if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1)) 887 return; 888 889 glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly; 890 sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1); 891 892 intel_host->rpm_retune_ok = true; 893 chip->rpm_retune = true; 894 mmc_retune_needed(host->mmc); 895 pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc)); 896 } 897 898 static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp) 899 { 900 if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 901 !chip->rpm_retune) 902 glk_rpm_retune_wa(chip, susp); 903 } 904 905 static int glk_runtime_suspend(struct sdhci_pci_chip *chip) 906 { 907 glk_rpm_retune_chk(chip, true); 908 909 return sdhci_cqhci_runtime_suspend(chip); 910 } 911 912 static int glk_runtime_resume(struct sdhci_pci_chip *chip) 913 { 914 glk_rpm_retune_chk(chip, false); 915 916 return sdhci_cqhci_runtime_resume(chip); 917 } 918 #endif 919 920 #ifdef CONFIG_ACPI 921 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 922 { 923 acpi_status status; 924 unsigned long long max_freq; 925 926 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 927 "MXFQ", NULL, &max_freq); 928 if (ACPI_FAILURE(status)) { 929 dev_err(&slot->chip->pdev->dev, 930 "MXFQ not found in acpi table\n"); 931 return -EINVAL; 932 } 933 934 slot->host->mmc->f_max = max_freq * 1000000; 935 936 return 0; 937 } 938 #else 939 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 940 { 941 return 0; 942 } 943 #endif 944 945 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 946 { 947 int err; 948 949 byt_probe_slot(slot); 950 951 err = ni_set_max_freq(slot); 952 if (err) 953 return err; 954 955 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 956 MMC_CAP_WAIT_WHILE_BUSY; 957 return 0; 958 } 959 960 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 961 { 962 byt_probe_slot(slot); 963 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 964 MMC_CAP_WAIT_WHILE_BUSY; 965 return 0; 966 } 967 968 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 969 { 970 byt_probe_slot(slot); 971 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | 972 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE; 973 slot->cd_idx = 0; 974 slot->cd_override_level = true; 975 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 976 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 977 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 978 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) 979 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 980 981 if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI && 982 slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3) 983 slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V; 984 985 return 0; 986 } 987 988 #ifdef CONFIG_PM_SLEEP 989 990 static int byt_resume(struct sdhci_pci_chip *chip) 991 { 992 byt_ocp_setting(chip->pdev); 993 994 return sdhci_pci_resume_host(chip); 995 } 996 997 #endif 998 999 #ifdef CONFIG_PM 1000 1001 static int byt_runtime_resume(struct sdhci_pci_chip *chip) 1002 { 1003 byt_ocp_setting(chip->pdev); 1004 1005 return sdhci_pci_runtime_resume_host(chip); 1006 } 1007 1008 #endif 1009 1010 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 1011 #ifdef CONFIG_PM_SLEEP 1012 .resume = byt_resume, 1013 #endif 1014 #ifdef CONFIG_PM 1015 .runtime_resume = byt_runtime_resume, 1016 #endif 1017 .allow_runtime_pm = true, 1018 .probe_slot = byt_emmc_probe_slot, 1019 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1020 SDHCI_QUIRK_NO_LED, 1021 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1022 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1023 SDHCI_QUIRK2_STOP_WITH_TC, 1024 .ops = &sdhci_intel_byt_ops, 1025 .priv_size = sizeof(struct intel_host), 1026 }; 1027 1028 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = { 1029 .allow_runtime_pm = true, 1030 .probe_slot = glk_emmc_probe_slot, 1031 .add_host = glk_emmc_add_host, 1032 #ifdef CONFIG_PM_SLEEP 1033 .suspend = sdhci_cqhci_suspend, 1034 .resume = sdhci_cqhci_resume, 1035 #endif 1036 #ifdef CONFIG_PM 1037 .runtime_suspend = glk_runtime_suspend, 1038 .runtime_resume = glk_runtime_resume, 1039 #endif 1040 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1041 SDHCI_QUIRK_NO_LED, 1042 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1043 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1044 SDHCI_QUIRK2_STOP_WITH_TC, 1045 .ops = &sdhci_intel_glk_ops, 1046 .priv_size = sizeof(struct intel_host), 1047 }; 1048 1049 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 1050 #ifdef CONFIG_PM_SLEEP 1051 .resume = byt_resume, 1052 #endif 1053 #ifdef CONFIG_PM 1054 .runtime_resume = byt_runtime_resume, 1055 #endif 1056 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1057 SDHCI_QUIRK_NO_LED, 1058 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1059 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1060 .allow_runtime_pm = true, 1061 .probe_slot = ni_byt_sdio_probe_slot, 1062 .ops = &sdhci_intel_byt_ops, 1063 .priv_size = sizeof(struct intel_host), 1064 }; 1065 1066 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 1067 #ifdef CONFIG_PM_SLEEP 1068 .resume = byt_resume, 1069 #endif 1070 #ifdef CONFIG_PM 1071 .runtime_resume = byt_runtime_resume, 1072 #endif 1073 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1074 SDHCI_QUIRK_NO_LED, 1075 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1076 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1077 .allow_runtime_pm = true, 1078 .probe_slot = byt_sdio_probe_slot, 1079 .ops = &sdhci_intel_byt_ops, 1080 .priv_size = sizeof(struct intel_host), 1081 }; 1082 1083 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 1084 #ifdef CONFIG_PM_SLEEP 1085 .resume = byt_resume, 1086 #endif 1087 #ifdef CONFIG_PM 1088 .runtime_resume = byt_runtime_resume, 1089 #endif 1090 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1091 SDHCI_QUIRK_NO_LED, 1092 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 1093 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1094 SDHCI_QUIRK2_STOP_WITH_TC, 1095 .allow_runtime_pm = true, 1096 .own_cd_for_runtime_pm = true, 1097 .probe_slot = byt_sd_probe_slot, 1098 .ops = &sdhci_intel_byt_ops, 1099 .priv_size = sizeof(struct intel_host), 1100 }; 1101 1102 /* Define Host controllers for Intel Merrifield platform */ 1103 #define INTEL_MRFLD_EMMC_0 0 1104 #define INTEL_MRFLD_EMMC_1 1 1105 #define INTEL_MRFLD_SD 2 1106 #define INTEL_MRFLD_SDIO 3 1107 1108 #ifdef CONFIG_ACPI 1109 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) 1110 { 1111 struct acpi_device *device, *child; 1112 1113 device = ACPI_COMPANION(&slot->chip->pdev->dev); 1114 if (!device) 1115 return; 1116 1117 acpi_device_fix_up_power(device); 1118 list_for_each_entry(child, &device->children, node) 1119 if (child->status.present && child->status.enabled) 1120 acpi_device_fix_up_power(child); 1121 } 1122 #else 1123 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {} 1124 #endif 1125 1126 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 1127 { 1128 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 1129 1130 switch (func) { 1131 case INTEL_MRFLD_EMMC_0: 1132 case INTEL_MRFLD_EMMC_1: 1133 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1134 MMC_CAP_8_BIT_DATA | 1135 MMC_CAP_1_8V_DDR; 1136 break; 1137 case INTEL_MRFLD_SD: 1138 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1139 break; 1140 case INTEL_MRFLD_SDIO: 1141 /* Advertise 2.0v for compatibility with the SDIO card's OCR */ 1142 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195; 1143 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1144 MMC_CAP_POWER_OFF_CARD; 1145 break; 1146 default: 1147 return -ENODEV; 1148 } 1149 1150 intel_mrfld_mmc_fix_up_power_slot(slot); 1151 return 0; 1152 } 1153 1154 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 1155 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1156 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 1157 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1158 .allow_runtime_pm = true, 1159 .probe_slot = intel_mrfld_mmc_probe_slot, 1160 }; 1161 1162 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 1163 { 1164 u8 scratch; 1165 int ret; 1166 1167 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 1168 if (ret) 1169 return ret; 1170 1171 /* 1172 * Turn PMOS on [bit 0], set over current detection to 2.4 V 1173 * [bit 1:2] and enable over current debouncing [bit 6]. 1174 */ 1175 if (on) 1176 scratch |= 0x47; 1177 else 1178 scratch &= ~0x47; 1179 1180 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 1181 } 1182 1183 static int jmicron_probe(struct sdhci_pci_chip *chip) 1184 { 1185 int ret; 1186 u16 mmcdev = 0; 1187 1188 if (chip->pdev->revision == 0) { 1189 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 1190 SDHCI_QUIRK_32BIT_DMA_SIZE | 1191 SDHCI_QUIRK_32BIT_ADMA_SIZE | 1192 SDHCI_QUIRK_RESET_AFTER_REQUEST | 1193 SDHCI_QUIRK_BROKEN_SMALL_PIO; 1194 } 1195 1196 /* 1197 * JMicron chips can have two interfaces to the same hardware 1198 * in order to work around limitations in Microsoft's driver. 1199 * We need to make sure we only bind to one of them. 1200 * 1201 * This code assumes two things: 1202 * 1203 * 1. The PCI code adds subfunctions in order. 1204 * 1205 * 2. The MMC interface has a lower subfunction number 1206 * than the SD interface. 1207 */ 1208 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 1209 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 1210 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 1211 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 1212 1213 if (mmcdev) { 1214 struct pci_dev *sd_dev; 1215 1216 sd_dev = NULL; 1217 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 1218 mmcdev, sd_dev)) != NULL) { 1219 if ((PCI_SLOT(chip->pdev->devfn) == 1220 PCI_SLOT(sd_dev->devfn)) && 1221 (chip->pdev->bus == sd_dev->bus)) 1222 break; 1223 } 1224 1225 if (sd_dev) { 1226 pci_dev_put(sd_dev); 1227 dev_info(&chip->pdev->dev, "Refusing to bind to " 1228 "secondary interface.\n"); 1229 return -ENODEV; 1230 } 1231 } 1232 1233 /* 1234 * JMicron chips need a bit of a nudge to enable the power 1235 * output pins. 1236 */ 1237 ret = jmicron_pmos(chip, 1); 1238 if (ret) { 1239 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1240 return ret; 1241 } 1242 1243 /* quirk for unsable RO-detection on JM388 chips */ 1244 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 1245 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1246 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 1247 1248 return 0; 1249 } 1250 1251 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 1252 { 1253 u8 scratch; 1254 1255 scratch = readb(host->ioaddr + 0xC0); 1256 1257 if (on) 1258 scratch |= 0x01; 1259 else 1260 scratch &= ~0x01; 1261 1262 writeb(scratch, host->ioaddr + 0xC0); 1263 } 1264 1265 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 1266 { 1267 if (slot->chip->pdev->revision == 0) { 1268 u16 version; 1269 1270 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 1271 version = (version & SDHCI_VENDOR_VER_MASK) >> 1272 SDHCI_VENDOR_VER_SHIFT; 1273 1274 /* 1275 * Older versions of the chip have lots of nasty glitches 1276 * in the ADMA engine. It's best just to avoid it 1277 * completely. 1278 */ 1279 if (version < 0xAC) 1280 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 1281 } 1282 1283 /* JM388 MMC doesn't support 1.8V while SD supports it */ 1284 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1285 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 1286 MMC_VDD_29_30 | MMC_VDD_30_31 | 1287 MMC_VDD_165_195; /* allow 1.8V */ 1288 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 1289 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 1290 } 1291 1292 /* 1293 * The secondary interface requires a bit set to get the 1294 * interrupts. 1295 */ 1296 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1297 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1298 jmicron_enable_mmc(slot->host, 1); 1299 1300 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 1301 1302 return 0; 1303 } 1304 1305 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 1306 { 1307 if (dead) 1308 return; 1309 1310 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1311 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1312 jmicron_enable_mmc(slot->host, 0); 1313 } 1314 1315 #ifdef CONFIG_PM_SLEEP 1316 static int jmicron_suspend(struct sdhci_pci_chip *chip) 1317 { 1318 int i, ret; 1319 1320 ret = sdhci_pci_suspend_host(chip); 1321 if (ret) 1322 return ret; 1323 1324 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1325 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1326 for (i = 0; i < chip->num_slots; i++) 1327 jmicron_enable_mmc(chip->slots[i]->host, 0); 1328 } 1329 1330 return 0; 1331 } 1332 1333 static int jmicron_resume(struct sdhci_pci_chip *chip) 1334 { 1335 int ret, i; 1336 1337 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1338 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1339 for (i = 0; i < chip->num_slots; i++) 1340 jmicron_enable_mmc(chip->slots[i]->host, 1); 1341 } 1342 1343 ret = jmicron_pmos(chip, 1); 1344 if (ret) { 1345 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1346 return ret; 1347 } 1348 1349 return sdhci_pci_resume_host(chip); 1350 } 1351 #endif 1352 1353 static const struct sdhci_pci_fixes sdhci_jmicron = { 1354 .probe = jmicron_probe, 1355 1356 .probe_slot = jmicron_probe_slot, 1357 .remove_slot = jmicron_remove_slot, 1358 1359 #ifdef CONFIG_PM_SLEEP 1360 .suspend = jmicron_suspend, 1361 .resume = jmicron_resume, 1362 #endif 1363 }; 1364 1365 /* SysKonnect CardBus2SDIO extra registers */ 1366 #define SYSKT_CTRL 0x200 1367 #define SYSKT_RDFIFO_STAT 0x204 1368 #define SYSKT_WRFIFO_STAT 0x208 1369 #define SYSKT_POWER_DATA 0x20c 1370 #define SYSKT_POWER_330 0xef 1371 #define SYSKT_POWER_300 0xf8 1372 #define SYSKT_POWER_184 0xcc 1373 #define SYSKT_POWER_CMD 0x20d 1374 #define SYSKT_POWER_START (1 << 7) 1375 #define SYSKT_POWER_STATUS 0x20e 1376 #define SYSKT_POWER_STATUS_OK (1 << 0) 1377 #define SYSKT_BOARD_REV 0x210 1378 #define SYSKT_CHIP_REV 0x211 1379 #define SYSKT_CONF_DATA 0x212 1380 #define SYSKT_CONF_DATA_1V8 (1 << 2) 1381 #define SYSKT_CONF_DATA_2V5 (1 << 1) 1382 #define SYSKT_CONF_DATA_3V3 (1 << 0) 1383 1384 static int syskt_probe(struct sdhci_pci_chip *chip) 1385 { 1386 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1387 chip->pdev->class &= ~0x0000FF; 1388 chip->pdev->class |= PCI_SDHCI_IFDMA; 1389 } 1390 return 0; 1391 } 1392 1393 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 1394 { 1395 int tm, ps; 1396 1397 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 1398 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 1399 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 1400 "board rev %d.%d, chip rev %d.%d\n", 1401 board_rev >> 4, board_rev & 0xf, 1402 chip_rev >> 4, chip_rev & 0xf); 1403 if (chip_rev >= 0x20) 1404 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 1405 1406 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 1407 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 1408 udelay(50); 1409 tm = 10; /* Wait max 1 ms */ 1410 do { 1411 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 1412 if (ps & SYSKT_POWER_STATUS_OK) 1413 break; 1414 udelay(100); 1415 } while (--tm); 1416 if (!tm) { 1417 dev_err(&slot->chip->pdev->dev, 1418 "power regulator never stabilized"); 1419 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 1420 return -ENODEV; 1421 } 1422 1423 return 0; 1424 } 1425 1426 static const struct sdhci_pci_fixes sdhci_syskt = { 1427 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 1428 .probe = syskt_probe, 1429 .probe_slot = syskt_probe_slot, 1430 }; 1431 1432 static int via_probe(struct sdhci_pci_chip *chip) 1433 { 1434 if (chip->pdev->revision == 0x10) 1435 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 1436 1437 return 0; 1438 } 1439 1440 static const struct sdhci_pci_fixes sdhci_via = { 1441 .probe = via_probe, 1442 }; 1443 1444 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 1445 { 1446 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 1447 return 0; 1448 } 1449 1450 static const struct sdhci_pci_fixes sdhci_rtsx = { 1451 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1452 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 1453 SDHCI_QUIRK2_BROKEN_DDR50, 1454 .probe_slot = rtsx_probe_slot, 1455 }; 1456 1457 /*AMD chipset generation*/ 1458 enum amd_chipset_gen { 1459 AMD_CHIPSET_BEFORE_ML, 1460 AMD_CHIPSET_CZ, 1461 AMD_CHIPSET_NL, 1462 AMD_CHIPSET_UNKNOWN, 1463 }; 1464 1465 /* AMD registers */ 1466 #define AMD_SD_AUTO_PATTERN 0xB8 1467 #define AMD_MSLEEP_DURATION 4 1468 #define AMD_SD_MISC_CONTROL 0xD0 1469 #define AMD_MAX_TUNE_VALUE 0x0B 1470 #define AMD_AUTO_TUNE_SEL 0x10800 1471 #define AMD_FIFO_PTR 0x30 1472 #define AMD_BIT_MASK 0x1F 1473 1474 static void amd_tuning_reset(struct sdhci_host *host) 1475 { 1476 unsigned int val; 1477 1478 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1479 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 1480 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1481 1482 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1483 val &= ~SDHCI_CTRL_EXEC_TUNING; 1484 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1485 } 1486 1487 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 1488 { 1489 unsigned int val; 1490 1491 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 1492 val &= ~AMD_BIT_MASK; 1493 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 1494 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 1495 } 1496 1497 static void amd_enable_manual_tuning(struct pci_dev *pdev) 1498 { 1499 unsigned int val; 1500 1501 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 1502 val |= AMD_FIFO_PTR; 1503 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 1504 } 1505 1506 static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode) 1507 { 1508 struct sdhci_pci_slot *slot = sdhci_priv(host); 1509 struct pci_dev *pdev = slot->chip->pdev; 1510 u8 valid_win = 0; 1511 u8 valid_win_max = 0; 1512 u8 valid_win_end = 0; 1513 u8 ctrl, tune_around; 1514 1515 amd_tuning_reset(host); 1516 1517 for (tune_around = 0; tune_around < 12; tune_around++) { 1518 amd_config_tuning_phase(pdev, tune_around); 1519 1520 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1521 valid_win = 0; 1522 msleep(AMD_MSLEEP_DURATION); 1523 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 1524 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 1525 } else if (++valid_win > valid_win_max) { 1526 valid_win_max = valid_win; 1527 valid_win_end = tune_around; 1528 } 1529 } 1530 1531 if (!valid_win_max) { 1532 dev_err(&pdev->dev, "no tuning point found\n"); 1533 return -EIO; 1534 } 1535 1536 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 1537 1538 amd_enable_manual_tuning(pdev); 1539 1540 host->mmc->retune_period = 0; 1541 1542 return 0; 1543 } 1544 1545 static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode) 1546 { 1547 struct sdhci_host *host = mmc_priv(mmc); 1548 1549 /* AMD requires custom HS200 tuning */ 1550 if (host->timing == MMC_TIMING_MMC_HS200) 1551 return amd_execute_tuning_hs200(host, opcode); 1552 1553 /* Otherwise perform standard SDHCI tuning */ 1554 return sdhci_execute_tuning(mmc, opcode); 1555 } 1556 1557 static int amd_probe_slot(struct sdhci_pci_slot *slot) 1558 { 1559 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 1560 1561 ops->execute_tuning = amd_execute_tuning; 1562 1563 return 0; 1564 } 1565 1566 static int amd_probe(struct sdhci_pci_chip *chip) 1567 { 1568 struct pci_dev *smbus_dev; 1569 enum amd_chipset_gen gen; 1570 1571 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1572 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 1573 if (smbus_dev) { 1574 gen = AMD_CHIPSET_BEFORE_ML; 1575 } else { 1576 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1577 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1578 if (smbus_dev) { 1579 if (smbus_dev->revision < 0x51) 1580 gen = AMD_CHIPSET_CZ; 1581 else 1582 gen = AMD_CHIPSET_NL; 1583 } else { 1584 gen = AMD_CHIPSET_UNKNOWN; 1585 } 1586 } 1587 1588 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1589 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1590 1591 return 0; 1592 } 1593 1594 static u32 sdhci_read_present_state(struct sdhci_host *host) 1595 { 1596 return sdhci_readl(host, SDHCI_PRESENT_STATE); 1597 } 1598 1599 void amd_sdhci_reset(struct sdhci_host *host, u8 mask) 1600 { 1601 struct sdhci_pci_slot *slot = sdhci_priv(host); 1602 struct pci_dev *pdev = slot->chip->pdev; 1603 u32 present_state; 1604 1605 /* 1606 * SDHC 0x7906 requires a hard reset to clear all internal state. 1607 * Otherwise it can get into a bad state where the DATA lines are always 1608 * read as zeros. 1609 */ 1610 if (pdev->device == 0x7906 && (mask & SDHCI_RESET_ALL)) { 1611 pci_clear_master(pdev); 1612 1613 pci_save_state(pdev); 1614 1615 pci_set_power_state(pdev, PCI_D3cold); 1616 pr_debug("%s: power_state=%u\n", mmc_hostname(host->mmc), 1617 pdev->current_state); 1618 pci_set_power_state(pdev, PCI_D0); 1619 1620 pci_restore_state(pdev); 1621 1622 /* 1623 * SDHCI_RESET_ALL says the card detect logic should not be 1624 * reset, but since we need to reset the entire controller 1625 * we should wait until the card detect logic has stabilized. 1626 * 1627 * This normally takes about 40ms. 1628 */ 1629 readx_poll_timeout( 1630 sdhci_read_present_state, 1631 host, 1632 present_state, 1633 present_state & SDHCI_CD_STABLE, 1634 10000, 1635 100000 1636 ); 1637 } 1638 1639 return sdhci_reset(host, mask); 1640 } 1641 1642 static const struct sdhci_ops amd_sdhci_pci_ops = { 1643 .set_clock = sdhci_set_clock, 1644 .enable_dma = sdhci_pci_enable_dma, 1645 .set_bus_width = sdhci_set_bus_width, 1646 .reset = amd_sdhci_reset, 1647 .set_uhs_signaling = sdhci_set_uhs_signaling, 1648 }; 1649 1650 static const struct sdhci_pci_fixes sdhci_amd = { 1651 .probe = amd_probe, 1652 .ops = &amd_sdhci_pci_ops, 1653 .probe_slot = amd_probe_slot, 1654 }; 1655 1656 static const struct pci_device_id pci_ids[] = { 1657 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh), 1658 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc), 1659 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc), 1660 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc), 1661 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712), 1662 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712), 1663 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714), 1664 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714), 1665 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe), 1666 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron), 1667 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron), 1668 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron), 1669 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron), 1670 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt), 1671 SDHCI_PCI_DEVICE(VIA, 95D0, via), 1672 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx), 1673 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk), 1674 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0), 1675 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2), 1676 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2), 1677 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd), 1678 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio), 1679 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio), 1680 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc), 1681 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc), 1682 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio), 1683 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio), 1684 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc), 1685 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio), 1686 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio), 1687 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd), 1688 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc), 1689 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc), 1690 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio), 1691 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd), 1692 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd), 1693 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio), 1694 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio), 1695 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc), 1696 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc), 1697 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc), 1698 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc), 1699 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio), 1700 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd), 1701 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc), 1702 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc), 1703 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc), 1704 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio), 1705 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd), 1706 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc), 1707 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio), 1708 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd), 1709 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc), 1710 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio), 1711 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd), 1712 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc), 1713 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio), 1714 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd), 1715 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc), 1716 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd), 1717 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd), 1718 SDHCI_PCI_DEVICE(INTEL, ICP_EMMC, intel_glk_emmc), 1719 SDHCI_PCI_DEVICE(INTEL, ICP_SD, intel_byt_sd), 1720 SDHCI_PCI_DEVICE(INTEL, EHL_EMMC, intel_glk_emmc), 1721 SDHCI_PCI_DEVICE(INTEL, EHL_SD, intel_byt_sd), 1722 SDHCI_PCI_DEVICE(INTEL, CML_EMMC, intel_glk_emmc), 1723 SDHCI_PCI_DEVICE(INTEL, CML_SD, intel_byt_sd), 1724 SDHCI_PCI_DEVICE(INTEL, CMLH_SD, intel_byt_sd), 1725 SDHCI_PCI_DEVICE(O2, 8120, o2), 1726 SDHCI_PCI_DEVICE(O2, 8220, o2), 1727 SDHCI_PCI_DEVICE(O2, 8221, o2), 1728 SDHCI_PCI_DEVICE(O2, 8320, o2), 1729 SDHCI_PCI_DEVICE(O2, 8321, o2), 1730 SDHCI_PCI_DEVICE(O2, FUJIN2, o2), 1731 SDHCI_PCI_DEVICE(O2, SDS0, o2), 1732 SDHCI_PCI_DEVICE(O2, SDS1, o2), 1733 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2), 1734 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), 1735 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan), 1736 SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps), 1737 SDHCI_PCI_DEVICE(GLI, 9750, gl9750), 1738 SDHCI_PCI_DEVICE(GLI, 9755, gl9755), 1739 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), 1740 /* Generic SD host controller */ 1741 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, 1742 { /* end: all zeroes */ }, 1743 }; 1744 1745 MODULE_DEVICE_TABLE(pci, pci_ids); 1746 1747 /*****************************************************************************\ 1748 * * 1749 * SDHCI core callbacks * 1750 * * 1751 \*****************************************************************************/ 1752 1753 int sdhci_pci_enable_dma(struct sdhci_host *host) 1754 { 1755 struct sdhci_pci_slot *slot; 1756 struct pci_dev *pdev; 1757 1758 slot = sdhci_priv(host); 1759 pdev = slot->chip->pdev; 1760 1761 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1762 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1763 (host->flags & SDHCI_USE_SDMA)) { 1764 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1765 "doesn't fully claim to support it.\n"); 1766 } 1767 1768 pci_set_master(pdev); 1769 1770 return 0; 1771 } 1772 1773 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1774 { 1775 struct sdhci_pci_slot *slot = sdhci_priv(host); 1776 int rst_n_gpio = slot->rst_n_gpio; 1777 1778 if (!gpio_is_valid(rst_n_gpio)) 1779 return; 1780 gpio_set_value_cansleep(rst_n_gpio, 0); 1781 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1782 udelay(10); 1783 gpio_set_value_cansleep(rst_n_gpio, 1); 1784 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1785 usleep_range(300, 1000); 1786 } 1787 1788 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1789 { 1790 struct sdhci_pci_slot *slot = sdhci_priv(host); 1791 1792 if (slot->hw_reset) 1793 slot->hw_reset(host); 1794 } 1795 1796 static const struct sdhci_ops sdhci_pci_ops = { 1797 .set_clock = sdhci_set_clock, 1798 .enable_dma = sdhci_pci_enable_dma, 1799 .set_bus_width = sdhci_set_bus_width, 1800 .reset = sdhci_reset, 1801 .set_uhs_signaling = sdhci_set_uhs_signaling, 1802 .hw_reset = sdhci_pci_hw_reset, 1803 }; 1804 1805 /*****************************************************************************\ 1806 * * 1807 * Suspend/resume * 1808 * * 1809 \*****************************************************************************/ 1810 1811 #ifdef CONFIG_PM_SLEEP 1812 static int sdhci_pci_suspend(struct device *dev) 1813 { 1814 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 1815 1816 if (!chip) 1817 return 0; 1818 1819 if (chip->fixes && chip->fixes->suspend) 1820 return chip->fixes->suspend(chip); 1821 1822 return sdhci_pci_suspend_host(chip); 1823 } 1824 1825 static int sdhci_pci_resume(struct device *dev) 1826 { 1827 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 1828 1829 if (!chip) 1830 return 0; 1831 1832 if (chip->fixes && chip->fixes->resume) 1833 return chip->fixes->resume(chip); 1834 1835 return sdhci_pci_resume_host(chip); 1836 } 1837 #endif 1838 1839 #ifdef CONFIG_PM 1840 static int sdhci_pci_runtime_suspend(struct device *dev) 1841 { 1842 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 1843 1844 if (!chip) 1845 return 0; 1846 1847 if (chip->fixes && chip->fixes->runtime_suspend) 1848 return chip->fixes->runtime_suspend(chip); 1849 1850 return sdhci_pci_runtime_suspend_host(chip); 1851 } 1852 1853 static int sdhci_pci_runtime_resume(struct device *dev) 1854 { 1855 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 1856 1857 if (!chip) 1858 return 0; 1859 1860 if (chip->fixes && chip->fixes->runtime_resume) 1861 return chip->fixes->runtime_resume(chip); 1862 1863 return sdhci_pci_runtime_resume_host(chip); 1864 } 1865 #endif 1866 1867 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1868 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1869 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1870 sdhci_pci_runtime_resume, NULL) 1871 }; 1872 1873 /*****************************************************************************\ 1874 * * 1875 * Device probing/removal * 1876 * * 1877 \*****************************************************************************/ 1878 1879 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1880 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1881 int slotno) 1882 { 1883 struct sdhci_pci_slot *slot; 1884 struct sdhci_host *host; 1885 int ret, bar = first_bar + slotno; 1886 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 1887 1888 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1889 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1890 return ERR_PTR(-ENODEV); 1891 } 1892 1893 if (pci_resource_len(pdev, bar) < 0x100) { 1894 dev_err(&pdev->dev, "Invalid iomem size. You may " 1895 "experience problems.\n"); 1896 } 1897 1898 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1899 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1900 return ERR_PTR(-ENODEV); 1901 } 1902 1903 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1904 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1905 return ERR_PTR(-ENODEV); 1906 } 1907 1908 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 1909 if (IS_ERR(host)) { 1910 dev_err(&pdev->dev, "cannot allocate host\n"); 1911 return ERR_CAST(host); 1912 } 1913 1914 slot = sdhci_priv(host); 1915 1916 slot->chip = chip; 1917 slot->host = host; 1918 slot->rst_n_gpio = -EINVAL; 1919 slot->cd_gpio = -EINVAL; 1920 slot->cd_idx = -1; 1921 1922 /* Retrieve platform data if there is any */ 1923 if (*sdhci_pci_get_data) 1924 slot->data = sdhci_pci_get_data(pdev, slotno); 1925 1926 if (slot->data) { 1927 if (slot->data->setup) { 1928 ret = slot->data->setup(slot->data); 1929 if (ret) { 1930 dev_err(&pdev->dev, "platform setup failed\n"); 1931 goto free; 1932 } 1933 } 1934 slot->rst_n_gpio = slot->data->rst_n_gpio; 1935 slot->cd_gpio = slot->data->cd_gpio; 1936 } 1937 1938 host->hw_name = "PCI"; 1939 host->ops = chip->fixes && chip->fixes->ops ? 1940 chip->fixes->ops : 1941 &sdhci_pci_ops; 1942 host->quirks = chip->quirks; 1943 host->quirks2 = chip->quirks2; 1944 1945 host->irq = pdev->irq; 1946 1947 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1948 if (ret) { 1949 dev_err(&pdev->dev, "cannot request region\n"); 1950 goto cleanup; 1951 } 1952 1953 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1954 1955 if (chip->fixes && chip->fixes->probe_slot) { 1956 ret = chip->fixes->probe_slot(slot); 1957 if (ret) 1958 goto cleanup; 1959 } 1960 1961 if (gpio_is_valid(slot->rst_n_gpio)) { 1962 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1963 gpio_direction_output(slot->rst_n_gpio, 1); 1964 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1965 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1966 } else { 1967 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1968 slot->rst_n_gpio = -EINVAL; 1969 } 1970 } 1971 1972 host->mmc->pm_caps = MMC_PM_KEEP_POWER; 1973 host->mmc->slotno = slotno; 1974 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1975 1976 if (device_can_wakeup(&pdev->dev)) 1977 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ; 1978 1979 if (host->mmc->caps & MMC_CAP_CD_WAKE) 1980 device_init_wakeup(&pdev->dev, true); 1981 1982 if (slot->cd_idx >= 0) { 1983 ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx, 1984 slot->cd_override_level, 0, NULL); 1985 if (ret && ret != -EPROBE_DEFER) 1986 ret = mmc_gpiod_request_cd(host->mmc, NULL, 1987 slot->cd_idx, 1988 slot->cd_override_level, 1989 0, NULL); 1990 if (ret == -EPROBE_DEFER) 1991 goto remove; 1992 1993 if (ret) { 1994 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 1995 slot->cd_idx = -1; 1996 } 1997 } 1998 1999 if (chip->fixes && chip->fixes->add_host) 2000 ret = chip->fixes->add_host(slot); 2001 else 2002 ret = sdhci_add_host(host); 2003 if (ret) 2004 goto remove; 2005 2006 sdhci_pci_add_own_cd(slot); 2007 2008 /* 2009 * Check if the chip needs a separate GPIO for card detect to wake up 2010 * from runtime suspend. If it is not there, don't allow runtime PM. 2011 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 2012 */ 2013 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 2014 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 2015 chip->allow_runtime_pm = false; 2016 2017 return slot; 2018 2019 remove: 2020 if (chip->fixes && chip->fixes->remove_slot) 2021 chip->fixes->remove_slot(slot, 0); 2022 2023 cleanup: 2024 if (slot->data && slot->data->cleanup) 2025 slot->data->cleanup(slot->data); 2026 2027 free: 2028 sdhci_free_host(host); 2029 2030 return ERR_PTR(ret); 2031 } 2032 2033 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 2034 { 2035 int dead; 2036 u32 scratch; 2037 2038 sdhci_pci_remove_own_cd(slot); 2039 2040 dead = 0; 2041 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 2042 if (scratch == (u32)-1) 2043 dead = 1; 2044 2045 sdhci_remove_host(slot->host, dead); 2046 2047 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 2048 slot->chip->fixes->remove_slot(slot, dead); 2049 2050 if (slot->data && slot->data->cleanup) 2051 slot->data->cleanup(slot->data); 2052 2053 sdhci_free_host(slot->host); 2054 } 2055 2056 static void sdhci_pci_runtime_pm_allow(struct device *dev) 2057 { 2058 pm_suspend_ignore_children(dev, 1); 2059 pm_runtime_set_autosuspend_delay(dev, 50); 2060 pm_runtime_use_autosuspend(dev); 2061 pm_runtime_allow(dev); 2062 /* Stay active until mmc core scans for a card */ 2063 pm_runtime_put_noidle(dev); 2064 } 2065 2066 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 2067 { 2068 pm_runtime_forbid(dev); 2069 pm_runtime_get_noresume(dev); 2070 } 2071 2072 static int sdhci_pci_probe(struct pci_dev *pdev, 2073 const struct pci_device_id *ent) 2074 { 2075 struct sdhci_pci_chip *chip; 2076 struct sdhci_pci_slot *slot; 2077 2078 u8 slots, first_bar; 2079 int ret, i; 2080 2081 BUG_ON(pdev == NULL); 2082 BUG_ON(ent == NULL); 2083 2084 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 2085 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 2086 2087 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 2088 if (ret) 2089 return ret; 2090 2091 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 2092 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 2093 2094 BUG_ON(slots > MAX_SLOTS); 2095 2096 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 2097 if (ret) 2098 return ret; 2099 2100 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 2101 2102 if (first_bar > 5) { 2103 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 2104 return -ENODEV; 2105 } 2106 2107 ret = pcim_enable_device(pdev); 2108 if (ret) 2109 return ret; 2110 2111 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 2112 if (!chip) 2113 return -ENOMEM; 2114 2115 chip->pdev = pdev; 2116 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 2117 if (chip->fixes) { 2118 chip->quirks = chip->fixes->quirks; 2119 chip->quirks2 = chip->fixes->quirks2; 2120 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 2121 } 2122 chip->num_slots = slots; 2123 chip->pm_retune = true; 2124 chip->rpm_retune = true; 2125 2126 pci_set_drvdata(pdev, chip); 2127 2128 if (chip->fixes && chip->fixes->probe) { 2129 ret = chip->fixes->probe(chip); 2130 if (ret) 2131 return ret; 2132 } 2133 2134 slots = chip->num_slots; /* Quirk may have changed this */ 2135 2136 for (i = 0; i < slots; i++) { 2137 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 2138 if (IS_ERR(slot)) { 2139 for (i--; i >= 0; i--) 2140 sdhci_pci_remove_slot(chip->slots[i]); 2141 return PTR_ERR(slot); 2142 } 2143 2144 chip->slots[i] = slot; 2145 } 2146 2147 if (chip->allow_runtime_pm) 2148 sdhci_pci_runtime_pm_allow(&pdev->dev); 2149 2150 return 0; 2151 } 2152 2153 static void sdhci_pci_remove(struct pci_dev *pdev) 2154 { 2155 int i; 2156 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 2157 2158 if (chip->allow_runtime_pm) 2159 sdhci_pci_runtime_pm_forbid(&pdev->dev); 2160 2161 for (i = 0; i < chip->num_slots; i++) 2162 sdhci_pci_remove_slot(chip->slots[i]); 2163 } 2164 2165 static struct pci_driver sdhci_driver = { 2166 .name = "sdhci-pci", 2167 .id_table = pci_ids, 2168 .probe = sdhci_pci_probe, 2169 .remove = sdhci_pci_remove, 2170 .driver = { 2171 .pm = &sdhci_pci_pm_ops 2172 }, 2173 }; 2174 2175 module_pci_driver(sdhci_driver); 2176 2177 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 2178 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 2179 MODULE_LICENSE("GPL"); 2180