1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 2 * 3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 * 10 * Thanks to the following companies for their support: 11 * 12 * - JMicron (hardware and technical support) 13 */ 14 15 #include <linux/bitfield.h> 16 #include <linux/string.h> 17 #include <linux/delay.h> 18 #include <linux/highmem.h> 19 #include <linux/module.h> 20 #include <linux/pci.h> 21 #include <linux/dma-mapping.h> 22 #include <linux/slab.h> 23 #include <linux/device.h> 24 #include <linux/mmc/host.h> 25 #include <linux/mmc/mmc.h> 26 #include <linux/scatterlist.h> 27 #include <linux/io.h> 28 #include <linux/gpio.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/mmc/slot-gpio.h> 31 #include <linux/mmc/sdhci-pci-data.h> 32 #include <linux/acpi.h> 33 34 #ifdef CONFIG_X86 35 #include <asm/iosf_mbi.h> 36 #endif 37 38 #include "cqhci.h" 39 40 #include "sdhci.h" 41 #include "sdhci-pci.h" 42 43 static void sdhci_pci_hw_reset(struct sdhci_host *host); 44 45 #ifdef CONFIG_PM_SLEEP 46 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip) 47 { 48 mmc_pm_flag_t pm_flags = 0; 49 bool cap_cd_wake = false; 50 int i; 51 52 for (i = 0; i < chip->num_slots; i++) { 53 struct sdhci_pci_slot *slot = chip->slots[i]; 54 55 if (slot) { 56 pm_flags |= slot->host->mmc->pm_flags; 57 if (slot->host->mmc->caps & MMC_CAP_CD_WAKE) 58 cap_cd_wake = true; 59 } 60 } 61 62 if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ)) 63 return device_wakeup_enable(&chip->pdev->dev); 64 else if (!cap_cd_wake) 65 return device_wakeup_disable(&chip->pdev->dev); 66 67 return 0; 68 } 69 70 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 71 { 72 int i, ret; 73 74 sdhci_pci_init_wakeup(chip); 75 76 for (i = 0; i < chip->num_slots; i++) { 77 struct sdhci_pci_slot *slot = chip->slots[i]; 78 struct sdhci_host *host; 79 80 if (!slot) 81 continue; 82 83 host = slot->host; 84 85 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 86 mmc_retune_needed(host->mmc); 87 88 ret = sdhci_suspend_host(host); 89 if (ret) 90 goto err_pci_suspend; 91 92 if (device_may_wakeup(&chip->pdev->dev)) 93 mmc_gpio_set_cd_wake(host->mmc, true); 94 } 95 96 return 0; 97 98 err_pci_suspend: 99 while (--i >= 0) 100 sdhci_resume_host(chip->slots[i]->host); 101 return ret; 102 } 103 104 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip) 105 { 106 struct sdhci_pci_slot *slot; 107 int i, ret; 108 109 for (i = 0; i < chip->num_slots; i++) { 110 slot = chip->slots[i]; 111 if (!slot) 112 continue; 113 114 ret = sdhci_resume_host(slot->host); 115 if (ret) 116 return ret; 117 118 mmc_gpio_set_cd_wake(slot->host->mmc, false); 119 } 120 121 return 0; 122 } 123 124 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip) 125 { 126 int ret; 127 128 ret = cqhci_suspend(chip->slots[0]->host->mmc); 129 if (ret) 130 return ret; 131 132 return sdhci_pci_suspend_host(chip); 133 } 134 135 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip) 136 { 137 int ret; 138 139 ret = sdhci_pci_resume_host(chip); 140 if (ret) 141 return ret; 142 143 return cqhci_resume(chip->slots[0]->host->mmc); 144 } 145 #endif 146 147 #ifdef CONFIG_PM 148 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip) 149 { 150 struct sdhci_pci_slot *slot; 151 struct sdhci_host *host; 152 int i, ret; 153 154 for (i = 0; i < chip->num_slots; i++) { 155 slot = chip->slots[i]; 156 if (!slot) 157 continue; 158 159 host = slot->host; 160 161 ret = sdhci_runtime_suspend_host(host); 162 if (ret) 163 goto err_pci_runtime_suspend; 164 165 if (chip->rpm_retune && 166 host->tuning_mode != SDHCI_TUNING_MODE_3) 167 mmc_retune_needed(host->mmc); 168 } 169 170 return 0; 171 172 err_pci_runtime_suspend: 173 while (--i >= 0) 174 sdhci_runtime_resume_host(chip->slots[i]->host); 175 return ret; 176 } 177 178 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip) 179 { 180 struct sdhci_pci_slot *slot; 181 int i, ret; 182 183 for (i = 0; i < chip->num_slots; i++) { 184 slot = chip->slots[i]; 185 if (!slot) 186 continue; 187 188 ret = sdhci_runtime_resume_host(slot->host); 189 if (ret) 190 return ret; 191 } 192 193 return 0; 194 } 195 196 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip) 197 { 198 int ret; 199 200 ret = cqhci_suspend(chip->slots[0]->host->mmc); 201 if (ret) 202 return ret; 203 204 return sdhci_pci_runtime_suspend_host(chip); 205 } 206 207 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip) 208 { 209 int ret; 210 211 ret = sdhci_pci_runtime_resume_host(chip); 212 if (ret) 213 return ret; 214 215 return cqhci_resume(chip->slots[0]->host->mmc); 216 } 217 #endif 218 219 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask) 220 { 221 int cmd_error = 0; 222 int data_error = 0; 223 224 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 225 return intmask; 226 227 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 228 229 return 0; 230 } 231 232 static void sdhci_pci_dumpregs(struct mmc_host *mmc) 233 { 234 sdhci_dumpregs(mmc_priv(mmc)); 235 } 236 237 /*****************************************************************************\ 238 * * 239 * Hardware specific quirk handling * 240 * * 241 \*****************************************************************************/ 242 243 static int ricoh_probe(struct sdhci_pci_chip *chip) 244 { 245 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 246 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 247 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 248 return 0; 249 } 250 251 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 252 { 253 slot->host->caps = 254 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 255 & SDHCI_TIMEOUT_CLK_MASK) | 256 257 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 258 & SDHCI_CLOCK_BASE_MASK) | 259 260 SDHCI_TIMEOUT_CLK_UNIT | 261 SDHCI_CAN_VDD_330 | 262 SDHCI_CAN_DO_HISPD | 263 SDHCI_CAN_DO_SDMA; 264 return 0; 265 } 266 267 #ifdef CONFIG_PM_SLEEP 268 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 269 { 270 /* Apply a delay to allow controller to settle */ 271 /* Otherwise it becomes confused if card state changed 272 during suspend */ 273 msleep(500); 274 return sdhci_pci_resume_host(chip); 275 } 276 #endif 277 278 static const struct sdhci_pci_fixes sdhci_ricoh = { 279 .probe = ricoh_probe, 280 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 281 SDHCI_QUIRK_FORCE_DMA | 282 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 283 }; 284 285 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 286 .probe_slot = ricoh_mmc_probe_slot, 287 #ifdef CONFIG_PM_SLEEP 288 .resume = ricoh_mmc_resume, 289 #endif 290 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 291 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 292 SDHCI_QUIRK_NO_CARD_NO_RESET | 293 SDHCI_QUIRK_MISSING_CAPS 294 }; 295 296 static const struct sdhci_pci_fixes sdhci_ene_712 = { 297 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 298 SDHCI_QUIRK_BROKEN_DMA, 299 }; 300 301 static const struct sdhci_pci_fixes sdhci_ene_714 = { 302 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 303 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 304 SDHCI_QUIRK_BROKEN_DMA, 305 }; 306 307 static const struct sdhci_pci_fixes sdhci_cafe = { 308 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 309 SDHCI_QUIRK_NO_BUSY_IRQ | 310 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 311 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 312 }; 313 314 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 315 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 316 }; 317 318 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 319 { 320 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 321 return 0; 322 } 323 324 /* 325 * ADMA operation is disabled for Moorestown platform due to 326 * hardware bugs. 327 */ 328 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 329 { 330 /* 331 * slots number is fixed here for MRST as SDIO3/5 are never used and 332 * have hardware bugs. 333 */ 334 chip->num_slots = 1; 335 return 0; 336 } 337 338 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 339 { 340 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 341 return 0; 342 } 343 344 #ifdef CONFIG_PM 345 346 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 347 { 348 struct sdhci_pci_slot *slot = dev_id; 349 struct sdhci_host *host = slot->host; 350 351 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 352 return IRQ_HANDLED; 353 } 354 355 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 356 { 357 int err, irq, gpio = slot->cd_gpio; 358 359 slot->cd_gpio = -EINVAL; 360 slot->cd_irq = -EINVAL; 361 362 if (!gpio_is_valid(gpio)) 363 return; 364 365 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 366 if (err < 0) 367 goto out; 368 369 err = gpio_direction_input(gpio); 370 if (err < 0) 371 goto out_free; 372 373 irq = gpio_to_irq(gpio); 374 if (irq < 0) 375 goto out_free; 376 377 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 378 IRQF_TRIGGER_FALLING, "sd_cd", slot); 379 if (err) 380 goto out_free; 381 382 slot->cd_gpio = gpio; 383 slot->cd_irq = irq; 384 385 return; 386 387 out_free: 388 devm_gpio_free(&slot->chip->pdev->dev, gpio); 389 out: 390 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 391 } 392 393 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 394 { 395 if (slot->cd_irq >= 0) 396 free_irq(slot->cd_irq, slot); 397 } 398 399 #else 400 401 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 402 { 403 } 404 405 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 406 { 407 } 408 409 #endif 410 411 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 412 { 413 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 414 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC; 415 return 0; 416 } 417 418 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 419 { 420 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 421 return 0; 422 } 423 424 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 425 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 426 .probe_slot = mrst_hc_probe_slot, 427 }; 428 429 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 430 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 431 .probe = mrst_hc_probe, 432 }; 433 434 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 435 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 436 .allow_runtime_pm = true, 437 .own_cd_for_runtime_pm = true, 438 }; 439 440 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 441 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 442 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 443 .allow_runtime_pm = true, 444 .probe_slot = mfd_sdio_probe_slot, 445 }; 446 447 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 448 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 449 .allow_runtime_pm = true, 450 .probe_slot = mfd_emmc_probe_slot, 451 }; 452 453 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 454 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 455 .probe_slot = pch_hc_probe_slot, 456 }; 457 458 #ifdef CONFIG_X86 459 460 #define BYT_IOSF_SCCEP 0x63 461 #define BYT_IOSF_OCP_NETCTRL0 0x1078 462 #define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8) 463 464 static void byt_ocp_setting(struct pci_dev *pdev) 465 { 466 u32 val = 0; 467 468 if (pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC && 469 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SDIO && 470 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SD && 471 pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC2) 472 return; 473 474 if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0, 475 &val)) { 476 dev_err(&pdev->dev, "%s read error\n", __func__); 477 return; 478 } 479 480 if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE)) 481 return; 482 483 val &= ~BYT_IOSF_OCP_TIMEOUT_BASE; 484 485 if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0, 486 val)) { 487 dev_err(&pdev->dev, "%s write error\n", __func__); 488 return; 489 } 490 491 dev_dbg(&pdev->dev, "%s completed\n", __func__); 492 } 493 494 #else 495 496 static inline void byt_ocp_setting(struct pci_dev *pdev) 497 { 498 } 499 500 #endif 501 502 enum { 503 INTEL_DSM_FNS = 0, 504 INTEL_DSM_V18_SWITCH = 3, 505 INTEL_DSM_V33_SWITCH = 4, 506 INTEL_DSM_DRV_STRENGTH = 9, 507 INTEL_DSM_D3_RETUNE = 10, 508 }; 509 510 struct intel_host { 511 u32 dsm_fns; 512 int drv_strength; 513 bool d3_retune; 514 bool rpm_retune_ok; 515 u32 glk_rx_ctrl1; 516 u32 glk_tun_val; 517 }; 518 519 static const guid_t intel_dsm_guid = 520 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F, 521 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61); 522 523 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 524 unsigned int fn, u32 *result) 525 { 526 union acpi_object *obj; 527 int err = 0; 528 size_t len; 529 530 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL); 531 if (!obj) 532 return -EOPNOTSUPP; 533 534 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { 535 err = -EINVAL; 536 goto out; 537 } 538 539 len = min_t(size_t, obj->buffer.length, 4); 540 541 *result = 0; 542 memcpy(result, obj->buffer.pointer, len); 543 out: 544 ACPI_FREE(obj); 545 546 return err; 547 } 548 549 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 550 unsigned int fn, u32 *result) 551 { 552 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 553 return -EOPNOTSUPP; 554 555 return __intel_dsm(intel_host, dev, fn, result); 556 } 557 558 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 559 struct mmc_host *mmc) 560 { 561 int err; 562 u32 val; 563 564 intel_host->d3_retune = true; 565 566 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 567 if (err) { 568 pr_debug("%s: DSM not supported, error %d\n", 569 mmc_hostname(mmc), err); 570 return; 571 } 572 573 pr_debug("%s: DSM function mask %#x\n", 574 mmc_hostname(mmc), intel_host->dsm_fns); 575 576 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 577 intel_host->drv_strength = err ? 0 : val; 578 579 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 580 intel_host->d3_retune = err ? true : !!val; 581 } 582 583 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 584 { 585 u8 reg; 586 587 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 588 reg |= 0x10; 589 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 590 /* For eMMC, minimum is 1us but give it 9us for good measure */ 591 udelay(9); 592 reg &= ~0x10; 593 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 594 /* For eMMC, minimum is 200us but give it 300us for good measure */ 595 usleep_range(300, 1000); 596 } 597 598 static int intel_select_drive_strength(struct mmc_card *card, 599 unsigned int max_dtr, int host_drv, 600 int card_drv, int *drv_type) 601 { 602 struct sdhci_host *host = mmc_priv(card->host); 603 struct sdhci_pci_slot *slot = sdhci_priv(host); 604 struct intel_host *intel_host = sdhci_pci_priv(slot); 605 606 return intel_host->drv_strength; 607 } 608 609 static int bxt_get_cd(struct mmc_host *mmc) 610 { 611 int gpio_cd = mmc_gpio_get_cd(mmc); 612 struct sdhci_host *host = mmc_priv(mmc); 613 unsigned long flags; 614 int ret = 0; 615 616 if (!gpio_cd) 617 return 0; 618 619 spin_lock_irqsave(&host->lock, flags); 620 621 if (host->flags & SDHCI_DEVICE_DEAD) 622 goto out; 623 624 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 625 out: 626 spin_unlock_irqrestore(&host->lock, flags); 627 628 return ret; 629 } 630 631 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 632 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 633 634 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 635 unsigned short vdd) 636 { 637 int cntr; 638 u8 reg; 639 640 sdhci_set_power(host, mode, vdd); 641 642 if (mode == MMC_POWER_OFF) 643 return; 644 645 /* 646 * Bus power might not enable after D3 -> D0 transition due to the 647 * present state not yet having propagated. Retry for up to 2ms. 648 */ 649 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 650 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 651 if (reg & SDHCI_POWER_ON) 652 break; 653 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 654 reg |= SDHCI_POWER_ON; 655 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 656 } 657 } 658 659 #define INTEL_HS400_ES_REG 0x78 660 #define INTEL_HS400_ES_BIT BIT(0) 661 662 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc, 663 struct mmc_ios *ios) 664 { 665 struct sdhci_host *host = mmc_priv(mmc); 666 u32 val; 667 668 val = sdhci_readl(host, INTEL_HS400_ES_REG); 669 if (ios->enhanced_strobe) 670 val |= INTEL_HS400_ES_BIT; 671 else 672 val &= ~INTEL_HS400_ES_BIT; 673 sdhci_writel(host, val, INTEL_HS400_ES_REG); 674 } 675 676 static int intel_start_signal_voltage_switch(struct mmc_host *mmc, 677 struct mmc_ios *ios) 678 { 679 struct device *dev = mmc_dev(mmc); 680 struct sdhci_host *host = mmc_priv(mmc); 681 struct sdhci_pci_slot *slot = sdhci_priv(host); 682 struct intel_host *intel_host = sdhci_pci_priv(slot); 683 unsigned int fn; 684 u32 result = 0; 685 int err; 686 687 err = sdhci_start_signal_voltage_switch(mmc, ios); 688 if (err) 689 return err; 690 691 switch (ios->signal_voltage) { 692 case MMC_SIGNAL_VOLTAGE_330: 693 fn = INTEL_DSM_V33_SWITCH; 694 break; 695 case MMC_SIGNAL_VOLTAGE_180: 696 fn = INTEL_DSM_V18_SWITCH; 697 break; 698 default: 699 return 0; 700 } 701 702 err = intel_dsm(intel_host, dev, fn, &result); 703 pr_debug("%s: %s DSM fn %u error %d result %u\n", 704 mmc_hostname(mmc), __func__, fn, err, result); 705 706 return 0; 707 } 708 709 static const struct sdhci_ops sdhci_intel_byt_ops = { 710 .set_clock = sdhci_set_clock, 711 .set_power = sdhci_intel_set_power, 712 .enable_dma = sdhci_pci_enable_dma, 713 .set_bus_width = sdhci_set_bus_width, 714 .reset = sdhci_reset, 715 .set_uhs_signaling = sdhci_set_uhs_signaling, 716 .hw_reset = sdhci_pci_hw_reset, 717 }; 718 719 static const struct sdhci_ops sdhci_intel_glk_ops = { 720 .set_clock = sdhci_set_clock, 721 .set_power = sdhci_intel_set_power, 722 .enable_dma = sdhci_pci_enable_dma, 723 .set_bus_width = sdhci_set_bus_width, 724 .reset = sdhci_reset, 725 .set_uhs_signaling = sdhci_set_uhs_signaling, 726 .hw_reset = sdhci_pci_hw_reset, 727 .irq = sdhci_cqhci_irq, 728 }; 729 730 static void byt_read_dsm(struct sdhci_pci_slot *slot) 731 { 732 struct intel_host *intel_host = sdhci_pci_priv(slot); 733 struct device *dev = &slot->chip->pdev->dev; 734 struct mmc_host *mmc = slot->host->mmc; 735 736 intel_dsm_init(intel_host, dev, mmc); 737 slot->chip->rpm_retune = intel_host->d3_retune; 738 } 739 740 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode) 741 { 742 int err = sdhci_execute_tuning(mmc, opcode); 743 struct sdhci_host *host = mmc_priv(mmc); 744 745 if (err) 746 return err; 747 748 /* 749 * Tuning can leave the IP in an active state (Buffer Read Enable bit 750 * set) which prevents the entry to low power states (i.e. S0i3). Data 751 * reset will clear it. 752 */ 753 sdhci_reset(host, SDHCI_RESET_DATA); 754 755 return 0; 756 } 757 758 static void byt_probe_slot(struct sdhci_pci_slot *slot) 759 { 760 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 761 struct device *dev = &slot->chip->pdev->dev; 762 struct mmc_host *mmc = slot->host->mmc; 763 764 byt_read_dsm(slot); 765 766 byt_ocp_setting(slot->chip->pdev); 767 768 ops->execute_tuning = intel_execute_tuning; 769 ops->start_signal_voltage_switch = intel_start_signal_voltage_switch; 770 771 device_property_read_u32(dev, "max-frequency", &mmc->f_max); 772 } 773 774 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 775 { 776 byt_probe_slot(slot); 777 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 778 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 779 MMC_CAP_CMD_DURING_TFR | 780 MMC_CAP_WAIT_WHILE_BUSY; 781 slot->hw_reset = sdhci_pci_int_hw_reset; 782 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 783 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 784 slot->host->mmc_host_ops.select_drive_strength = 785 intel_select_drive_strength; 786 return 0; 787 } 788 789 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot) 790 { 791 int ret = byt_emmc_probe_slot(slot); 792 793 slot->host->mmc->caps2 |= MMC_CAP2_CQE; 794 795 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) { 796 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES, 797 slot->host->mmc_host_ops.hs400_enhanced_strobe = 798 intel_hs400_enhanced_strobe; 799 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; 800 } 801 802 return ret; 803 } 804 805 static const struct cqhci_host_ops glk_cqhci_ops = { 806 .enable = sdhci_cqe_enable, 807 .disable = sdhci_cqe_disable, 808 .dumpregs = sdhci_pci_dumpregs, 809 }; 810 811 static int glk_emmc_add_host(struct sdhci_pci_slot *slot) 812 { 813 struct device *dev = &slot->chip->pdev->dev; 814 struct sdhci_host *host = slot->host; 815 struct cqhci_host *cq_host; 816 bool dma64; 817 int ret; 818 819 ret = sdhci_setup_host(host); 820 if (ret) 821 return ret; 822 823 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); 824 if (!cq_host) { 825 ret = -ENOMEM; 826 goto cleanup; 827 } 828 829 cq_host->mmio = host->ioaddr + 0x200; 830 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 831 cq_host->ops = &glk_cqhci_ops; 832 833 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 834 if (dma64) 835 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 836 837 ret = cqhci_init(cq_host, host->mmc, dma64); 838 if (ret) 839 goto cleanup; 840 841 ret = __sdhci_add_host(host); 842 if (ret) 843 goto cleanup; 844 845 return 0; 846 847 cleanup: 848 sdhci_cleanup_host(host); 849 return ret; 850 } 851 852 #ifdef CONFIG_PM 853 #define GLK_RX_CTRL1 0x834 854 #define GLK_TUN_VAL 0x840 855 #define GLK_PATH_PLL GENMASK(13, 8) 856 #define GLK_DLY GENMASK(6, 0) 857 /* Workaround firmware failing to restore the tuning value */ 858 static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp) 859 { 860 struct sdhci_pci_slot *slot = chip->slots[0]; 861 struct intel_host *intel_host = sdhci_pci_priv(slot); 862 struct sdhci_host *host = slot->host; 863 u32 glk_rx_ctrl1; 864 u32 glk_tun_val; 865 u32 dly; 866 867 if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc)) 868 return; 869 870 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1); 871 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL); 872 873 if (susp) { 874 intel_host->glk_rx_ctrl1 = glk_rx_ctrl1; 875 intel_host->glk_tun_val = glk_tun_val; 876 return; 877 } 878 879 if (!intel_host->glk_tun_val) 880 return; 881 882 if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) { 883 intel_host->rpm_retune_ok = true; 884 return; 885 } 886 887 dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) + 888 (intel_host->glk_tun_val << 1)); 889 if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1)) 890 return; 891 892 glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly; 893 sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1); 894 895 intel_host->rpm_retune_ok = true; 896 chip->rpm_retune = true; 897 mmc_retune_needed(host->mmc); 898 pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc)); 899 } 900 901 static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp) 902 { 903 if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 904 !chip->rpm_retune) 905 glk_rpm_retune_wa(chip, susp); 906 } 907 908 static int glk_runtime_suspend(struct sdhci_pci_chip *chip) 909 { 910 glk_rpm_retune_chk(chip, true); 911 912 return sdhci_cqhci_runtime_suspend(chip); 913 } 914 915 static int glk_runtime_resume(struct sdhci_pci_chip *chip) 916 { 917 glk_rpm_retune_chk(chip, false); 918 919 return sdhci_cqhci_runtime_resume(chip); 920 } 921 #endif 922 923 #ifdef CONFIG_ACPI 924 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 925 { 926 acpi_status status; 927 unsigned long long max_freq; 928 929 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 930 "MXFQ", NULL, &max_freq); 931 if (ACPI_FAILURE(status)) { 932 dev_err(&slot->chip->pdev->dev, 933 "MXFQ not found in acpi table\n"); 934 return -EINVAL; 935 } 936 937 slot->host->mmc->f_max = max_freq * 1000000; 938 939 return 0; 940 } 941 #else 942 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 943 { 944 return 0; 945 } 946 #endif 947 948 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 949 { 950 int err; 951 952 byt_probe_slot(slot); 953 954 err = ni_set_max_freq(slot); 955 if (err) 956 return err; 957 958 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 959 MMC_CAP_WAIT_WHILE_BUSY; 960 return 0; 961 } 962 963 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 964 { 965 byt_probe_slot(slot); 966 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 967 MMC_CAP_WAIT_WHILE_BUSY; 968 return 0; 969 } 970 971 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 972 { 973 byt_probe_slot(slot); 974 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | 975 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE; 976 slot->cd_idx = 0; 977 slot->cd_override_level = true; 978 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 979 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 980 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 981 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) 982 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 983 984 if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI && 985 slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3) 986 slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V; 987 988 return 0; 989 } 990 991 #ifdef CONFIG_PM_SLEEP 992 993 static int byt_resume(struct sdhci_pci_chip *chip) 994 { 995 byt_ocp_setting(chip->pdev); 996 997 return sdhci_pci_resume_host(chip); 998 } 999 1000 #endif 1001 1002 #ifdef CONFIG_PM 1003 1004 static int byt_runtime_resume(struct sdhci_pci_chip *chip) 1005 { 1006 byt_ocp_setting(chip->pdev); 1007 1008 return sdhci_pci_runtime_resume_host(chip); 1009 } 1010 1011 #endif 1012 1013 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 1014 #ifdef CONFIG_PM_SLEEP 1015 .resume = byt_resume, 1016 #endif 1017 #ifdef CONFIG_PM 1018 .runtime_resume = byt_runtime_resume, 1019 #endif 1020 .allow_runtime_pm = true, 1021 .probe_slot = byt_emmc_probe_slot, 1022 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1023 SDHCI_QUIRK_NO_LED, 1024 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1025 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1026 SDHCI_QUIRK2_STOP_WITH_TC, 1027 .ops = &sdhci_intel_byt_ops, 1028 .priv_size = sizeof(struct intel_host), 1029 }; 1030 1031 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = { 1032 .allow_runtime_pm = true, 1033 .probe_slot = glk_emmc_probe_slot, 1034 .add_host = glk_emmc_add_host, 1035 #ifdef CONFIG_PM_SLEEP 1036 .suspend = sdhci_cqhci_suspend, 1037 .resume = sdhci_cqhci_resume, 1038 #endif 1039 #ifdef CONFIG_PM 1040 .runtime_suspend = glk_runtime_suspend, 1041 .runtime_resume = glk_runtime_resume, 1042 #endif 1043 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1044 SDHCI_QUIRK_NO_LED, 1045 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1046 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1047 SDHCI_QUIRK2_STOP_WITH_TC, 1048 .ops = &sdhci_intel_glk_ops, 1049 .priv_size = sizeof(struct intel_host), 1050 }; 1051 1052 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 1053 #ifdef CONFIG_PM_SLEEP 1054 .resume = byt_resume, 1055 #endif 1056 #ifdef CONFIG_PM 1057 .runtime_resume = byt_runtime_resume, 1058 #endif 1059 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1060 SDHCI_QUIRK_NO_LED, 1061 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1062 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1063 .allow_runtime_pm = true, 1064 .probe_slot = ni_byt_sdio_probe_slot, 1065 .ops = &sdhci_intel_byt_ops, 1066 .priv_size = sizeof(struct intel_host), 1067 }; 1068 1069 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 1070 #ifdef CONFIG_PM_SLEEP 1071 .resume = byt_resume, 1072 #endif 1073 #ifdef CONFIG_PM 1074 .runtime_resume = byt_runtime_resume, 1075 #endif 1076 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1077 SDHCI_QUIRK_NO_LED, 1078 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1079 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1080 .allow_runtime_pm = true, 1081 .probe_slot = byt_sdio_probe_slot, 1082 .ops = &sdhci_intel_byt_ops, 1083 .priv_size = sizeof(struct intel_host), 1084 }; 1085 1086 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 1087 #ifdef CONFIG_PM_SLEEP 1088 .resume = byt_resume, 1089 #endif 1090 #ifdef CONFIG_PM 1091 .runtime_resume = byt_runtime_resume, 1092 #endif 1093 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1094 SDHCI_QUIRK_NO_LED, 1095 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 1096 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1097 SDHCI_QUIRK2_STOP_WITH_TC, 1098 .allow_runtime_pm = true, 1099 .own_cd_for_runtime_pm = true, 1100 .probe_slot = byt_sd_probe_slot, 1101 .ops = &sdhci_intel_byt_ops, 1102 .priv_size = sizeof(struct intel_host), 1103 }; 1104 1105 /* Define Host controllers for Intel Merrifield platform */ 1106 #define INTEL_MRFLD_EMMC_0 0 1107 #define INTEL_MRFLD_EMMC_1 1 1108 #define INTEL_MRFLD_SD 2 1109 #define INTEL_MRFLD_SDIO 3 1110 1111 #ifdef CONFIG_ACPI 1112 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) 1113 { 1114 struct acpi_device *device, *child; 1115 1116 device = ACPI_COMPANION(&slot->chip->pdev->dev); 1117 if (!device) 1118 return; 1119 1120 acpi_device_fix_up_power(device); 1121 list_for_each_entry(child, &device->children, node) 1122 if (child->status.present && child->status.enabled) 1123 acpi_device_fix_up_power(child); 1124 } 1125 #else 1126 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {} 1127 #endif 1128 1129 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 1130 { 1131 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 1132 1133 switch (func) { 1134 case INTEL_MRFLD_EMMC_0: 1135 case INTEL_MRFLD_EMMC_1: 1136 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1137 MMC_CAP_8_BIT_DATA | 1138 MMC_CAP_1_8V_DDR; 1139 break; 1140 case INTEL_MRFLD_SD: 1141 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1142 break; 1143 case INTEL_MRFLD_SDIO: 1144 /* Advertise 2.0v for compatibility with the SDIO card's OCR */ 1145 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195; 1146 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1147 MMC_CAP_POWER_OFF_CARD; 1148 break; 1149 default: 1150 return -ENODEV; 1151 } 1152 1153 intel_mrfld_mmc_fix_up_power_slot(slot); 1154 return 0; 1155 } 1156 1157 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 1158 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1159 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 1160 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1161 .allow_runtime_pm = true, 1162 .probe_slot = intel_mrfld_mmc_probe_slot, 1163 }; 1164 1165 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 1166 { 1167 u8 scratch; 1168 int ret; 1169 1170 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 1171 if (ret) 1172 return ret; 1173 1174 /* 1175 * Turn PMOS on [bit 0], set over current detection to 2.4 V 1176 * [bit 1:2] and enable over current debouncing [bit 6]. 1177 */ 1178 if (on) 1179 scratch |= 0x47; 1180 else 1181 scratch &= ~0x47; 1182 1183 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 1184 } 1185 1186 static int jmicron_probe(struct sdhci_pci_chip *chip) 1187 { 1188 int ret; 1189 u16 mmcdev = 0; 1190 1191 if (chip->pdev->revision == 0) { 1192 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 1193 SDHCI_QUIRK_32BIT_DMA_SIZE | 1194 SDHCI_QUIRK_32BIT_ADMA_SIZE | 1195 SDHCI_QUIRK_RESET_AFTER_REQUEST | 1196 SDHCI_QUIRK_BROKEN_SMALL_PIO; 1197 } 1198 1199 /* 1200 * JMicron chips can have two interfaces to the same hardware 1201 * in order to work around limitations in Microsoft's driver. 1202 * We need to make sure we only bind to one of them. 1203 * 1204 * This code assumes two things: 1205 * 1206 * 1. The PCI code adds subfunctions in order. 1207 * 1208 * 2. The MMC interface has a lower subfunction number 1209 * than the SD interface. 1210 */ 1211 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 1212 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 1213 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 1214 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 1215 1216 if (mmcdev) { 1217 struct pci_dev *sd_dev; 1218 1219 sd_dev = NULL; 1220 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 1221 mmcdev, sd_dev)) != NULL) { 1222 if ((PCI_SLOT(chip->pdev->devfn) == 1223 PCI_SLOT(sd_dev->devfn)) && 1224 (chip->pdev->bus == sd_dev->bus)) 1225 break; 1226 } 1227 1228 if (sd_dev) { 1229 pci_dev_put(sd_dev); 1230 dev_info(&chip->pdev->dev, "Refusing to bind to " 1231 "secondary interface.\n"); 1232 return -ENODEV; 1233 } 1234 } 1235 1236 /* 1237 * JMicron chips need a bit of a nudge to enable the power 1238 * output pins. 1239 */ 1240 ret = jmicron_pmos(chip, 1); 1241 if (ret) { 1242 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1243 return ret; 1244 } 1245 1246 /* quirk for unsable RO-detection on JM388 chips */ 1247 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 1248 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1249 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 1250 1251 return 0; 1252 } 1253 1254 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 1255 { 1256 u8 scratch; 1257 1258 scratch = readb(host->ioaddr + 0xC0); 1259 1260 if (on) 1261 scratch |= 0x01; 1262 else 1263 scratch &= ~0x01; 1264 1265 writeb(scratch, host->ioaddr + 0xC0); 1266 } 1267 1268 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 1269 { 1270 if (slot->chip->pdev->revision == 0) { 1271 u16 version; 1272 1273 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 1274 version = (version & SDHCI_VENDOR_VER_MASK) >> 1275 SDHCI_VENDOR_VER_SHIFT; 1276 1277 /* 1278 * Older versions of the chip have lots of nasty glitches 1279 * in the ADMA engine. It's best just to avoid it 1280 * completely. 1281 */ 1282 if (version < 0xAC) 1283 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 1284 } 1285 1286 /* JM388 MMC doesn't support 1.8V while SD supports it */ 1287 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1288 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 1289 MMC_VDD_29_30 | MMC_VDD_30_31 | 1290 MMC_VDD_165_195; /* allow 1.8V */ 1291 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 1292 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 1293 } 1294 1295 /* 1296 * The secondary interface requires a bit set to get the 1297 * interrupts. 1298 */ 1299 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1300 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1301 jmicron_enable_mmc(slot->host, 1); 1302 1303 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 1304 1305 return 0; 1306 } 1307 1308 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 1309 { 1310 if (dead) 1311 return; 1312 1313 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1314 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1315 jmicron_enable_mmc(slot->host, 0); 1316 } 1317 1318 #ifdef CONFIG_PM_SLEEP 1319 static int jmicron_suspend(struct sdhci_pci_chip *chip) 1320 { 1321 int i, ret; 1322 1323 ret = sdhci_pci_suspend_host(chip); 1324 if (ret) 1325 return ret; 1326 1327 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1328 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1329 for (i = 0; i < chip->num_slots; i++) 1330 jmicron_enable_mmc(chip->slots[i]->host, 0); 1331 } 1332 1333 return 0; 1334 } 1335 1336 static int jmicron_resume(struct sdhci_pci_chip *chip) 1337 { 1338 int ret, i; 1339 1340 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1341 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1342 for (i = 0; i < chip->num_slots; i++) 1343 jmicron_enable_mmc(chip->slots[i]->host, 1); 1344 } 1345 1346 ret = jmicron_pmos(chip, 1); 1347 if (ret) { 1348 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1349 return ret; 1350 } 1351 1352 return sdhci_pci_resume_host(chip); 1353 } 1354 #endif 1355 1356 static const struct sdhci_pci_fixes sdhci_jmicron = { 1357 .probe = jmicron_probe, 1358 1359 .probe_slot = jmicron_probe_slot, 1360 .remove_slot = jmicron_remove_slot, 1361 1362 #ifdef CONFIG_PM_SLEEP 1363 .suspend = jmicron_suspend, 1364 .resume = jmicron_resume, 1365 #endif 1366 }; 1367 1368 /* SysKonnect CardBus2SDIO extra registers */ 1369 #define SYSKT_CTRL 0x200 1370 #define SYSKT_RDFIFO_STAT 0x204 1371 #define SYSKT_WRFIFO_STAT 0x208 1372 #define SYSKT_POWER_DATA 0x20c 1373 #define SYSKT_POWER_330 0xef 1374 #define SYSKT_POWER_300 0xf8 1375 #define SYSKT_POWER_184 0xcc 1376 #define SYSKT_POWER_CMD 0x20d 1377 #define SYSKT_POWER_START (1 << 7) 1378 #define SYSKT_POWER_STATUS 0x20e 1379 #define SYSKT_POWER_STATUS_OK (1 << 0) 1380 #define SYSKT_BOARD_REV 0x210 1381 #define SYSKT_CHIP_REV 0x211 1382 #define SYSKT_CONF_DATA 0x212 1383 #define SYSKT_CONF_DATA_1V8 (1 << 2) 1384 #define SYSKT_CONF_DATA_2V5 (1 << 1) 1385 #define SYSKT_CONF_DATA_3V3 (1 << 0) 1386 1387 static int syskt_probe(struct sdhci_pci_chip *chip) 1388 { 1389 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1390 chip->pdev->class &= ~0x0000FF; 1391 chip->pdev->class |= PCI_SDHCI_IFDMA; 1392 } 1393 return 0; 1394 } 1395 1396 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 1397 { 1398 int tm, ps; 1399 1400 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 1401 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 1402 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 1403 "board rev %d.%d, chip rev %d.%d\n", 1404 board_rev >> 4, board_rev & 0xf, 1405 chip_rev >> 4, chip_rev & 0xf); 1406 if (chip_rev >= 0x20) 1407 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 1408 1409 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 1410 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 1411 udelay(50); 1412 tm = 10; /* Wait max 1 ms */ 1413 do { 1414 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 1415 if (ps & SYSKT_POWER_STATUS_OK) 1416 break; 1417 udelay(100); 1418 } while (--tm); 1419 if (!tm) { 1420 dev_err(&slot->chip->pdev->dev, 1421 "power regulator never stabilized"); 1422 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 1423 return -ENODEV; 1424 } 1425 1426 return 0; 1427 } 1428 1429 static const struct sdhci_pci_fixes sdhci_syskt = { 1430 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 1431 .probe = syskt_probe, 1432 .probe_slot = syskt_probe_slot, 1433 }; 1434 1435 static int via_probe(struct sdhci_pci_chip *chip) 1436 { 1437 if (chip->pdev->revision == 0x10) 1438 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 1439 1440 return 0; 1441 } 1442 1443 static const struct sdhci_pci_fixes sdhci_via = { 1444 .probe = via_probe, 1445 }; 1446 1447 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 1448 { 1449 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 1450 return 0; 1451 } 1452 1453 static const struct sdhci_pci_fixes sdhci_rtsx = { 1454 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1455 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 1456 SDHCI_QUIRK2_BROKEN_DDR50, 1457 .probe_slot = rtsx_probe_slot, 1458 }; 1459 1460 /*AMD chipset generation*/ 1461 enum amd_chipset_gen { 1462 AMD_CHIPSET_BEFORE_ML, 1463 AMD_CHIPSET_CZ, 1464 AMD_CHIPSET_NL, 1465 AMD_CHIPSET_UNKNOWN, 1466 }; 1467 1468 /* AMD registers */ 1469 #define AMD_SD_AUTO_PATTERN 0xB8 1470 #define AMD_MSLEEP_DURATION 4 1471 #define AMD_SD_MISC_CONTROL 0xD0 1472 #define AMD_MAX_TUNE_VALUE 0x0B 1473 #define AMD_AUTO_TUNE_SEL 0x10800 1474 #define AMD_FIFO_PTR 0x30 1475 #define AMD_BIT_MASK 0x1F 1476 1477 static void amd_tuning_reset(struct sdhci_host *host) 1478 { 1479 unsigned int val; 1480 1481 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1482 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 1483 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1484 1485 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1486 val &= ~SDHCI_CTRL_EXEC_TUNING; 1487 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1488 } 1489 1490 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 1491 { 1492 unsigned int val; 1493 1494 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 1495 val &= ~AMD_BIT_MASK; 1496 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 1497 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 1498 } 1499 1500 static void amd_enable_manual_tuning(struct pci_dev *pdev) 1501 { 1502 unsigned int val; 1503 1504 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 1505 val |= AMD_FIFO_PTR; 1506 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 1507 } 1508 1509 static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode) 1510 { 1511 struct sdhci_pci_slot *slot = sdhci_priv(host); 1512 struct pci_dev *pdev = slot->chip->pdev; 1513 u8 valid_win = 0; 1514 u8 valid_win_max = 0; 1515 u8 valid_win_end = 0; 1516 u8 ctrl, tune_around; 1517 1518 amd_tuning_reset(host); 1519 1520 for (tune_around = 0; tune_around < 12; tune_around++) { 1521 amd_config_tuning_phase(pdev, tune_around); 1522 1523 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1524 valid_win = 0; 1525 msleep(AMD_MSLEEP_DURATION); 1526 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 1527 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 1528 } else if (++valid_win > valid_win_max) { 1529 valid_win_max = valid_win; 1530 valid_win_end = tune_around; 1531 } 1532 } 1533 1534 if (!valid_win_max) { 1535 dev_err(&pdev->dev, "no tuning point found\n"); 1536 return -EIO; 1537 } 1538 1539 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 1540 1541 amd_enable_manual_tuning(pdev); 1542 1543 host->mmc->retune_period = 0; 1544 1545 return 0; 1546 } 1547 1548 static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode) 1549 { 1550 struct sdhci_host *host = mmc_priv(mmc); 1551 1552 /* AMD requires custom HS200 tuning */ 1553 if (host->timing == MMC_TIMING_MMC_HS200) 1554 return amd_execute_tuning_hs200(host, opcode); 1555 1556 /* Otherwise perform standard SDHCI tuning */ 1557 return sdhci_execute_tuning(mmc, opcode); 1558 } 1559 1560 static int amd_probe_slot(struct sdhci_pci_slot *slot) 1561 { 1562 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 1563 1564 ops->execute_tuning = amd_execute_tuning; 1565 1566 return 0; 1567 } 1568 1569 static int amd_probe(struct sdhci_pci_chip *chip) 1570 { 1571 struct pci_dev *smbus_dev; 1572 enum amd_chipset_gen gen; 1573 1574 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1575 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 1576 if (smbus_dev) { 1577 gen = AMD_CHIPSET_BEFORE_ML; 1578 } else { 1579 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1580 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1581 if (smbus_dev) { 1582 if (smbus_dev->revision < 0x51) 1583 gen = AMD_CHIPSET_CZ; 1584 else 1585 gen = AMD_CHIPSET_NL; 1586 } else { 1587 gen = AMD_CHIPSET_UNKNOWN; 1588 } 1589 } 1590 1591 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1592 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1593 1594 return 0; 1595 } 1596 1597 static const struct sdhci_ops amd_sdhci_pci_ops = { 1598 .set_clock = sdhci_set_clock, 1599 .enable_dma = sdhci_pci_enable_dma, 1600 .set_bus_width = sdhci_set_bus_width, 1601 .reset = sdhci_reset, 1602 .set_uhs_signaling = sdhci_set_uhs_signaling, 1603 }; 1604 1605 static const struct sdhci_pci_fixes sdhci_amd = { 1606 .probe = amd_probe, 1607 .ops = &amd_sdhci_pci_ops, 1608 .probe_slot = amd_probe_slot, 1609 }; 1610 1611 static const struct pci_device_id pci_ids[] = { 1612 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh), 1613 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc), 1614 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc), 1615 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc), 1616 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712), 1617 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712), 1618 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714), 1619 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714), 1620 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe), 1621 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron), 1622 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron), 1623 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron), 1624 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron), 1625 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt), 1626 SDHCI_PCI_DEVICE(VIA, 95D0, via), 1627 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx), 1628 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk), 1629 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0), 1630 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2), 1631 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2), 1632 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd), 1633 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio), 1634 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio), 1635 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc), 1636 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc), 1637 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio), 1638 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio), 1639 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc), 1640 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio), 1641 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio), 1642 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd), 1643 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc), 1644 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc), 1645 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio), 1646 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd), 1647 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd), 1648 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio), 1649 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio), 1650 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc), 1651 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc), 1652 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc), 1653 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc), 1654 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio), 1655 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd), 1656 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc), 1657 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc), 1658 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc), 1659 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio), 1660 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd), 1661 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc), 1662 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio), 1663 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd), 1664 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc), 1665 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio), 1666 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd), 1667 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc), 1668 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio), 1669 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd), 1670 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc), 1671 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd), 1672 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd), 1673 SDHCI_PCI_DEVICE(INTEL, ICP_EMMC, intel_glk_emmc), 1674 SDHCI_PCI_DEVICE(INTEL, ICP_SD, intel_byt_sd), 1675 SDHCI_PCI_DEVICE(INTEL, CML_EMMC, intel_glk_emmc), 1676 SDHCI_PCI_DEVICE(INTEL, CML_SD, intel_byt_sd), 1677 SDHCI_PCI_DEVICE(O2, 8120, o2), 1678 SDHCI_PCI_DEVICE(O2, 8220, o2), 1679 SDHCI_PCI_DEVICE(O2, 8221, o2), 1680 SDHCI_PCI_DEVICE(O2, 8320, o2), 1681 SDHCI_PCI_DEVICE(O2, 8321, o2), 1682 SDHCI_PCI_DEVICE(O2, FUJIN2, o2), 1683 SDHCI_PCI_DEVICE(O2, SDS0, o2), 1684 SDHCI_PCI_DEVICE(O2, SDS1, o2), 1685 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2), 1686 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), 1687 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan), 1688 SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps), 1689 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), 1690 /* Generic SD host controller */ 1691 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, 1692 { /* end: all zeroes */ }, 1693 }; 1694 1695 MODULE_DEVICE_TABLE(pci, pci_ids); 1696 1697 /*****************************************************************************\ 1698 * * 1699 * SDHCI core callbacks * 1700 * * 1701 \*****************************************************************************/ 1702 1703 int sdhci_pci_enable_dma(struct sdhci_host *host) 1704 { 1705 struct sdhci_pci_slot *slot; 1706 struct pci_dev *pdev; 1707 1708 slot = sdhci_priv(host); 1709 pdev = slot->chip->pdev; 1710 1711 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1712 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1713 (host->flags & SDHCI_USE_SDMA)) { 1714 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1715 "doesn't fully claim to support it.\n"); 1716 } 1717 1718 pci_set_master(pdev); 1719 1720 return 0; 1721 } 1722 1723 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1724 { 1725 struct sdhci_pci_slot *slot = sdhci_priv(host); 1726 int rst_n_gpio = slot->rst_n_gpio; 1727 1728 if (!gpio_is_valid(rst_n_gpio)) 1729 return; 1730 gpio_set_value_cansleep(rst_n_gpio, 0); 1731 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1732 udelay(10); 1733 gpio_set_value_cansleep(rst_n_gpio, 1); 1734 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1735 usleep_range(300, 1000); 1736 } 1737 1738 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1739 { 1740 struct sdhci_pci_slot *slot = sdhci_priv(host); 1741 1742 if (slot->hw_reset) 1743 slot->hw_reset(host); 1744 } 1745 1746 static const struct sdhci_ops sdhci_pci_ops = { 1747 .set_clock = sdhci_set_clock, 1748 .enable_dma = sdhci_pci_enable_dma, 1749 .set_bus_width = sdhci_set_bus_width, 1750 .reset = sdhci_reset, 1751 .set_uhs_signaling = sdhci_set_uhs_signaling, 1752 .hw_reset = sdhci_pci_hw_reset, 1753 }; 1754 1755 /*****************************************************************************\ 1756 * * 1757 * Suspend/resume * 1758 * * 1759 \*****************************************************************************/ 1760 1761 #ifdef CONFIG_PM_SLEEP 1762 static int sdhci_pci_suspend(struct device *dev) 1763 { 1764 struct pci_dev *pdev = to_pci_dev(dev); 1765 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1766 1767 if (!chip) 1768 return 0; 1769 1770 if (chip->fixes && chip->fixes->suspend) 1771 return chip->fixes->suspend(chip); 1772 1773 return sdhci_pci_suspend_host(chip); 1774 } 1775 1776 static int sdhci_pci_resume(struct device *dev) 1777 { 1778 struct pci_dev *pdev = to_pci_dev(dev); 1779 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1780 1781 if (!chip) 1782 return 0; 1783 1784 if (chip->fixes && chip->fixes->resume) 1785 return chip->fixes->resume(chip); 1786 1787 return sdhci_pci_resume_host(chip); 1788 } 1789 #endif 1790 1791 #ifdef CONFIG_PM 1792 static int sdhci_pci_runtime_suspend(struct device *dev) 1793 { 1794 struct pci_dev *pdev = to_pci_dev(dev); 1795 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1796 1797 if (!chip) 1798 return 0; 1799 1800 if (chip->fixes && chip->fixes->runtime_suspend) 1801 return chip->fixes->runtime_suspend(chip); 1802 1803 return sdhci_pci_runtime_suspend_host(chip); 1804 } 1805 1806 static int sdhci_pci_runtime_resume(struct device *dev) 1807 { 1808 struct pci_dev *pdev = to_pci_dev(dev); 1809 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1810 1811 if (!chip) 1812 return 0; 1813 1814 if (chip->fixes && chip->fixes->runtime_resume) 1815 return chip->fixes->runtime_resume(chip); 1816 1817 return sdhci_pci_runtime_resume_host(chip); 1818 } 1819 #endif 1820 1821 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1822 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1823 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1824 sdhci_pci_runtime_resume, NULL) 1825 }; 1826 1827 /*****************************************************************************\ 1828 * * 1829 * Device probing/removal * 1830 * * 1831 \*****************************************************************************/ 1832 1833 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1834 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1835 int slotno) 1836 { 1837 struct sdhci_pci_slot *slot; 1838 struct sdhci_host *host; 1839 int ret, bar = first_bar + slotno; 1840 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 1841 1842 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1843 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1844 return ERR_PTR(-ENODEV); 1845 } 1846 1847 if (pci_resource_len(pdev, bar) < 0x100) { 1848 dev_err(&pdev->dev, "Invalid iomem size. You may " 1849 "experience problems.\n"); 1850 } 1851 1852 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1853 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1854 return ERR_PTR(-ENODEV); 1855 } 1856 1857 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1858 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1859 return ERR_PTR(-ENODEV); 1860 } 1861 1862 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 1863 if (IS_ERR(host)) { 1864 dev_err(&pdev->dev, "cannot allocate host\n"); 1865 return ERR_CAST(host); 1866 } 1867 1868 slot = sdhci_priv(host); 1869 1870 slot->chip = chip; 1871 slot->host = host; 1872 slot->rst_n_gpio = -EINVAL; 1873 slot->cd_gpio = -EINVAL; 1874 slot->cd_idx = -1; 1875 1876 /* Retrieve platform data if there is any */ 1877 if (*sdhci_pci_get_data) 1878 slot->data = sdhci_pci_get_data(pdev, slotno); 1879 1880 if (slot->data) { 1881 if (slot->data->setup) { 1882 ret = slot->data->setup(slot->data); 1883 if (ret) { 1884 dev_err(&pdev->dev, "platform setup failed\n"); 1885 goto free; 1886 } 1887 } 1888 slot->rst_n_gpio = slot->data->rst_n_gpio; 1889 slot->cd_gpio = slot->data->cd_gpio; 1890 } 1891 1892 host->hw_name = "PCI"; 1893 host->ops = chip->fixes && chip->fixes->ops ? 1894 chip->fixes->ops : 1895 &sdhci_pci_ops; 1896 host->quirks = chip->quirks; 1897 host->quirks2 = chip->quirks2; 1898 1899 host->irq = pdev->irq; 1900 1901 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1902 if (ret) { 1903 dev_err(&pdev->dev, "cannot request region\n"); 1904 goto cleanup; 1905 } 1906 1907 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1908 1909 if (chip->fixes && chip->fixes->probe_slot) { 1910 ret = chip->fixes->probe_slot(slot); 1911 if (ret) 1912 goto cleanup; 1913 } 1914 1915 if (gpio_is_valid(slot->rst_n_gpio)) { 1916 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1917 gpio_direction_output(slot->rst_n_gpio, 1); 1918 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1919 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1920 } else { 1921 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1922 slot->rst_n_gpio = -EINVAL; 1923 } 1924 } 1925 1926 host->mmc->pm_caps = MMC_PM_KEEP_POWER; 1927 host->mmc->slotno = slotno; 1928 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1929 1930 if (device_can_wakeup(&pdev->dev)) 1931 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ; 1932 1933 if (host->mmc->caps & MMC_CAP_CD_WAKE) 1934 device_init_wakeup(&pdev->dev, true); 1935 1936 if (slot->cd_idx >= 0) { 1937 ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx, 1938 slot->cd_override_level, 0, NULL); 1939 if (ret && ret != -EPROBE_DEFER) 1940 ret = mmc_gpiod_request_cd(host->mmc, NULL, 1941 slot->cd_idx, 1942 slot->cd_override_level, 1943 0, NULL); 1944 if (ret == -EPROBE_DEFER) 1945 goto remove; 1946 1947 if (ret) { 1948 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 1949 slot->cd_idx = -1; 1950 } 1951 } 1952 1953 if (chip->fixes && chip->fixes->add_host) 1954 ret = chip->fixes->add_host(slot); 1955 else 1956 ret = sdhci_add_host(host); 1957 if (ret) 1958 goto remove; 1959 1960 sdhci_pci_add_own_cd(slot); 1961 1962 /* 1963 * Check if the chip needs a separate GPIO for card detect to wake up 1964 * from runtime suspend. If it is not there, don't allow runtime PM. 1965 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 1966 */ 1967 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 1968 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 1969 chip->allow_runtime_pm = false; 1970 1971 return slot; 1972 1973 remove: 1974 if (chip->fixes && chip->fixes->remove_slot) 1975 chip->fixes->remove_slot(slot, 0); 1976 1977 cleanup: 1978 if (slot->data && slot->data->cleanup) 1979 slot->data->cleanup(slot->data); 1980 1981 free: 1982 sdhci_free_host(host); 1983 1984 return ERR_PTR(ret); 1985 } 1986 1987 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 1988 { 1989 int dead; 1990 u32 scratch; 1991 1992 sdhci_pci_remove_own_cd(slot); 1993 1994 dead = 0; 1995 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 1996 if (scratch == (u32)-1) 1997 dead = 1; 1998 1999 sdhci_remove_host(slot->host, dead); 2000 2001 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 2002 slot->chip->fixes->remove_slot(slot, dead); 2003 2004 if (slot->data && slot->data->cleanup) 2005 slot->data->cleanup(slot->data); 2006 2007 sdhci_free_host(slot->host); 2008 } 2009 2010 static void sdhci_pci_runtime_pm_allow(struct device *dev) 2011 { 2012 pm_suspend_ignore_children(dev, 1); 2013 pm_runtime_set_autosuspend_delay(dev, 50); 2014 pm_runtime_use_autosuspend(dev); 2015 pm_runtime_allow(dev); 2016 /* Stay active until mmc core scans for a card */ 2017 pm_runtime_put_noidle(dev); 2018 } 2019 2020 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 2021 { 2022 pm_runtime_forbid(dev); 2023 pm_runtime_get_noresume(dev); 2024 } 2025 2026 static int sdhci_pci_probe(struct pci_dev *pdev, 2027 const struct pci_device_id *ent) 2028 { 2029 struct sdhci_pci_chip *chip; 2030 struct sdhci_pci_slot *slot; 2031 2032 u8 slots, first_bar; 2033 int ret, i; 2034 2035 BUG_ON(pdev == NULL); 2036 BUG_ON(ent == NULL); 2037 2038 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 2039 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 2040 2041 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 2042 if (ret) 2043 return ret; 2044 2045 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 2046 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 2047 if (slots == 0) 2048 return -ENODEV; 2049 2050 BUG_ON(slots > MAX_SLOTS); 2051 2052 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 2053 if (ret) 2054 return ret; 2055 2056 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 2057 2058 if (first_bar > 5) { 2059 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 2060 return -ENODEV; 2061 } 2062 2063 ret = pcim_enable_device(pdev); 2064 if (ret) 2065 return ret; 2066 2067 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 2068 if (!chip) 2069 return -ENOMEM; 2070 2071 chip->pdev = pdev; 2072 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 2073 if (chip->fixes) { 2074 chip->quirks = chip->fixes->quirks; 2075 chip->quirks2 = chip->fixes->quirks2; 2076 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 2077 } 2078 chip->num_slots = slots; 2079 chip->pm_retune = true; 2080 chip->rpm_retune = true; 2081 2082 pci_set_drvdata(pdev, chip); 2083 2084 if (chip->fixes && chip->fixes->probe) { 2085 ret = chip->fixes->probe(chip); 2086 if (ret) 2087 return ret; 2088 } 2089 2090 slots = chip->num_slots; /* Quirk may have changed this */ 2091 2092 for (i = 0; i < slots; i++) { 2093 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 2094 if (IS_ERR(slot)) { 2095 for (i--; i >= 0; i--) 2096 sdhci_pci_remove_slot(chip->slots[i]); 2097 return PTR_ERR(slot); 2098 } 2099 2100 chip->slots[i] = slot; 2101 } 2102 2103 if (chip->allow_runtime_pm) 2104 sdhci_pci_runtime_pm_allow(&pdev->dev); 2105 2106 return 0; 2107 } 2108 2109 static void sdhci_pci_remove(struct pci_dev *pdev) 2110 { 2111 int i; 2112 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 2113 2114 if (chip->allow_runtime_pm) 2115 sdhci_pci_runtime_pm_forbid(&pdev->dev); 2116 2117 for (i = 0; i < chip->num_slots; i++) 2118 sdhci_pci_remove_slot(chip->slots[i]); 2119 } 2120 2121 static struct pci_driver sdhci_driver = { 2122 .name = "sdhci-pci", 2123 .id_table = pci_ids, 2124 .probe = sdhci_pci_probe, 2125 .remove = sdhci_pci_remove, 2126 .driver = { 2127 .pm = &sdhci_pci_pm_ops 2128 }, 2129 }; 2130 2131 module_pci_driver(sdhci_driver); 2132 2133 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 2134 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 2135 MODULE_LICENSE("GPL"); 2136