1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 2 * 3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 * 10 * Thanks to the following companies for their support: 11 * 12 * - JMicron (hardware and technical support) 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/highmem.h> 17 #include <linux/module.h> 18 #include <linux/pci.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/slab.h> 21 #include <linux/device.h> 22 #include <linux/mmc/host.h> 23 #include <linux/mmc/mmc.h> 24 #include <linux/scatterlist.h> 25 #include <linux/io.h> 26 #include <linux/gpio.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/mmc/slot-gpio.h> 29 #include <linux/mmc/sdhci-pci-data.h> 30 #include <linux/acpi.h> 31 32 #include "sdhci.h" 33 #include "sdhci-pci.h" 34 #include "sdhci-pci-o2micro.h" 35 36 static int sdhci_pci_enable_dma(struct sdhci_host *host); 37 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width); 38 static void sdhci_pci_hw_reset(struct sdhci_host *host); 39 static int sdhci_pci_select_drive_strength(struct sdhci_host *host, 40 struct mmc_card *card, 41 unsigned int max_dtr, int host_drv, 42 int card_drv, int *drv_type); 43 44 /*****************************************************************************\ 45 * * 46 * Hardware specific quirk handling * 47 * * 48 \*****************************************************************************/ 49 50 static int ricoh_probe(struct sdhci_pci_chip *chip) 51 { 52 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 53 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 54 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 55 return 0; 56 } 57 58 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 59 { 60 slot->host->caps = 61 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 62 & SDHCI_TIMEOUT_CLK_MASK) | 63 64 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 65 & SDHCI_CLOCK_BASE_MASK) | 66 67 SDHCI_TIMEOUT_CLK_UNIT | 68 SDHCI_CAN_VDD_330 | 69 SDHCI_CAN_DO_HISPD | 70 SDHCI_CAN_DO_SDMA; 71 return 0; 72 } 73 74 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 75 { 76 /* Apply a delay to allow controller to settle */ 77 /* Otherwise it becomes confused if card state changed 78 during suspend */ 79 msleep(500); 80 return 0; 81 } 82 83 static const struct sdhci_pci_fixes sdhci_ricoh = { 84 .probe = ricoh_probe, 85 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 86 SDHCI_QUIRK_FORCE_DMA | 87 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 88 }; 89 90 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 91 .probe_slot = ricoh_mmc_probe_slot, 92 .resume = ricoh_mmc_resume, 93 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 94 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 95 SDHCI_QUIRK_NO_CARD_NO_RESET | 96 SDHCI_QUIRK_MISSING_CAPS 97 }; 98 99 static const struct sdhci_pci_fixes sdhci_ene_712 = { 100 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 101 SDHCI_QUIRK_BROKEN_DMA, 102 }; 103 104 static const struct sdhci_pci_fixes sdhci_ene_714 = { 105 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 106 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 107 SDHCI_QUIRK_BROKEN_DMA, 108 }; 109 110 static const struct sdhci_pci_fixes sdhci_cafe = { 111 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 112 SDHCI_QUIRK_NO_BUSY_IRQ | 113 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 114 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 115 }; 116 117 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 118 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 119 }; 120 121 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 122 { 123 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 124 return 0; 125 } 126 127 /* 128 * ADMA operation is disabled for Moorestown platform due to 129 * hardware bugs. 130 */ 131 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 132 { 133 /* 134 * slots number is fixed here for MRST as SDIO3/5 are never used and 135 * have hardware bugs. 136 */ 137 chip->num_slots = 1; 138 return 0; 139 } 140 141 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 142 { 143 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 144 return 0; 145 } 146 147 #ifdef CONFIG_PM 148 149 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 150 { 151 struct sdhci_pci_slot *slot = dev_id; 152 struct sdhci_host *host = slot->host; 153 154 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 155 return IRQ_HANDLED; 156 } 157 158 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 159 { 160 int err, irq, gpio = slot->cd_gpio; 161 162 slot->cd_gpio = -EINVAL; 163 slot->cd_irq = -EINVAL; 164 165 if (!gpio_is_valid(gpio)) 166 return; 167 168 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 169 if (err < 0) 170 goto out; 171 172 err = gpio_direction_input(gpio); 173 if (err < 0) 174 goto out_free; 175 176 irq = gpio_to_irq(gpio); 177 if (irq < 0) 178 goto out_free; 179 180 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 181 IRQF_TRIGGER_FALLING, "sd_cd", slot); 182 if (err) 183 goto out_free; 184 185 slot->cd_gpio = gpio; 186 slot->cd_irq = irq; 187 188 return; 189 190 out_free: 191 devm_gpio_free(&slot->chip->pdev->dev, gpio); 192 out: 193 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 194 } 195 196 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 197 { 198 if (slot->cd_irq >= 0) 199 free_irq(slot->cd_irq, slot); 200 } 201 202 #else 203 204 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 205 { 206 } 207 208 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 209 { 210 } 211 212 #endif 213 214 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 215 { 216 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 217 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC | 218 MMC_CAP2_HC_ERASE_SZ; 219 return 0; 220 } 221 222 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 223 { 224 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 225 return 0; 226 } 227 228 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 229 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 230 .probe_slot = mrst_hc_probe_slot, 231 }; 232 233 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 234 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 235 .probe = mrst_hc_probe, 236 }; 237 238 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 239 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 240 .allow_runtime_pm = true, 241 .own_cd_for_runtime_pm = true, 242 }; 243 244 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 245 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 246 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 247 .allow_runtime_pm = true, 248 .probe_slot = mfd_sdio_probe_slot, 249 }; 250 251 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 252 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 253 .allow_runtime_pm = true, 254 .probe_slot = mfd_emmc_probe_slot, 255 }; 256 257 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 258 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 259 .probe_slot = pch_hc_probe_slot, 260 }; 261 262 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 263 { 264 u8 reg; 265 266 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 267 reg |= 0x10; 268 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 269 /* For eMMC, minimum is 1us but give it 9us for good measure */ 270 udelay(9); 271 reg &= ~0x10; 272 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 273 /* For eMMC, minimum is 200us but give it 300us for good measure */ 274 usleep_range(300, 1000); 275 } 276 277 static int spt_select_drive_strength(struct sdhci_host *host, 278 struct mmc_card *card, 279 unsigned int max_dtr, 280 int host_drv, int card_drv, int *drv_type) 281 { 282 int drive_strength; 283 284 if (sdhci_pci_spt_drive_strength > 0) 285 drive_strength = sdhci_pci_spt_drive_strength & 0xf; 286 else 287 drive_strength = 0; /* Default 50-ohm */ 288 289 if ((mmc_driver_type_mask(drive_strength) & card_drv) == 0) 290 drive_strength = 0; /* Default 50-ohm */ 291 292 return drive_strength; 293 } 294 295 /* Try to read the drive strength from the card */ 296 static void spt_read_drive_strength(struct sdhci_host *host) 297 { 298 u32 val, i, t; 299 u16 m; 300 301 if (sdhci_pci_spt_drive_strength) 302 return; 303 304 sdhci_pci_spt_drive_strength = -1; 305 306 m = sdhci_readw(host, SDHCI_HOST_CONTROL2) & 0x7; 307 if (m != 3 && m != 5) 308 return; 309 val = sdhci_readl(host, SDHCI_PRESENT_STATE); 310 if (val & 0x3) 311 return; 312 sdhci_writel(host, 0x007f0023, SDHCI_INT_ENABLE); 313 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 314 sdhci_writew(host, 0x10, SDHCI_TRANSFER_MODE); 315 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 316 sdhci_writew(host, 512, SDHCI_BLOCK_SIZE); 317 sdhci_writew(host, 1, SDHCI_BLOCK_COUNT); 318 sdhci_writel(host, 0, SDHCI_ARGUMENT); 319 sdhci_writew(host, 0x83b, SDHCI_COMMAND); 320 for (i = 0; i < 1000; i++) { 321 val = sdhci_readl(host, SDHCI_INT_STATUS); 322 if (val & 0xffff8000) 323 return; 324 if (val & 0x20) 325 break; 326 udelay(1); 327 } 328 val = sdhci_readl(host, SDHCI_PRESENT_STATE); 329 if (!(val & 0x800)) 330 return; 331 for (i = 0; i < 47; i++) 332 val = sdhci_readl(host, SDHCI_BUFFER); 333 t = val & 0xf00; 334 if (t != 0x200 && t != 0x300) 335 return; 336 337 sdhci_pci_spt_drive_strength = 0x10 | ((val >> 12) & 0xf); 338 } 339 340 static int bxt_get_cd(struct mmc_host *mmc) 341 { 342 int gpio_cd = mmc_gpio_get_cd(mmc); 343 struct sdhci_host *host = mmc_priv(mmc); 344 unsigned long flags; 345 int ret = 0; 346 347 if (!gpio_cd) 348 return 0; 349 350 spin_lock_irqsave(&host->lock, flags); 351 352 if (host->flags & SDHCI_DEVICE_DEAD) 353 goto out; 354 355 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 356 out: 357 spin_unlock_irqrestore(&host->lock, flags); 358 359 return ret; 360 } 361 362 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 363 { 364 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 365 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 366 MMC_CAP_CMD_DURING_TFR | 367 MMC_CAP_WAIT_WHILE_BUSY; 368 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ; 369 slot->hw_reset = sdhci_pci_int_hw_reset; 370 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 371 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 372 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_SPT_EMMC) { 373 spt_read_drive_strength(slot->host); 374 slot->select_drive_strength = spt_select_drive_strength; 375 } 376 return 0; 377 } 378 379 #ifdef CONFIG_ACPI 380 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 381 { 382 acpi_status status; 383 unsigned long long max_freq; 384 385 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 386 "MXFQ", NULL, &max_freq); 387 if (ACPI_FAILURE(status)) { 388 dev_err(&slot->chip->pdev->dev, 389 "MXFQ not found in acpi table\n"); 390 return -EINVAL; 391 } 392 393 slot->host->mmc->f_max = max_freq * 1000000; 394 395 return 0; 396 } 397 #else 398 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 399 { 400 return 0; 401 } 402 #endif 403 404 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 405 { 406 int err; 407 408 err = ni_set_max_freq(slot); 409 if (err) 410 return err; 411 412 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 413 MMC_CAP_WAIT_WHILE_BUSY; 414 return 0; 415 } 416 417 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 418 { 419 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 420 MMC_CAP_WAIT_WHILE_BUSY; 421 return 0; 422 } 423 424 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 425 { 426 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 427 slot->cd_idx = 0; 428 slot->cd_override_level = true; 429 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 430 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 431 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 432 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) { 433 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 434 slot->host->mmc->caps |= MMC_CAP_AGGRESSIVE_PM; 435 } 436 437 return 0; 438 } 439 440 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 441 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 442 443 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 444 unsigned short vdd) 445 { 446 int cntr; 447 u8 reg; 448 449 sdhci_set_power(host, mode, vdd); 450 451 if (mode == MMC_POWER_OFF) 452 return; 453 454 /* 455 * Bus power might not enable after D3 -> D0 transition due to the 456 * present state not yet having propagated. Retry for up to 2ms. 457 */ 458 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 459 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 460 if (reg & SDHCI_POWER_ON) 461 break; 462 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 463 reg |= SDHCI_POWER_ON; 464 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 465 } 466 } 467 468 static const struct sdhci_ops sdhci_intel_byt_ops = { 469 .set_clock = sdhci_set_clock, 470 .set_power = sdhci_intel_set_power, 471 .enable_dma = sdhci_pci_enable_dma, 472 .set_bus_width = sdhci_pci_set_bus_width, 473 .reset = sdhci_reset, 474 .set_uhs_signaling = sdhci_set_uhs_signaling, 475 .hw_reset = sdhci_pci_hw_reset, 476 .select_drive_strength = sdhci_pci_select_drive_strength, 477 }; 478 479 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 480 .allow_runtime_pm = true, 481 .probe_slot = byt_emmc_probe_slot, 482 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 483 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 484 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 485 SDHCI_QUIRK2_STOP_WITH_TC, 486 .ops = &sdhci_intel_byt_ops, 487 }; 488 489 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 490 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 491 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 492 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 493 .allow_runtime_pm = true, 494 .probe_slot = ni_byt_sdio_probe_slot, 495 .ops = &sdhci_intel_byt_ops, 496 }; 497 498 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 499 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 500 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 501 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 502 .allow_runtime_pm = true, 503 .probe_slot = byt_sdio_probe_slot, 504 .ops = &sdhci_intel_byt_ops, 505 }; 506 507 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 508 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 509 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 510 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 511 SDHCI_QUIRK2_STOP_WITH_TC, 512 .allow_runtime_pm = true, 513 .own_cd_for_runtime_pm = true, 514 .probe_slot = byt_sd_probe_slot, 515 .ops = &sdhci_intel_byt_ops, 516 }; 517 518 /* Define Host controllers for Intel Merrifield platform */ 519 #define INTEL_MRFLD_EMMC_0 0 520 #define INTEL_MRFLD_EMMC_1 1 521 #define INTEL_MRFLD_SD 2 522 #define INTEL_MRFLD_SDIO 3 523 524 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 525 { 526 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 527 528 switch (func) { 529 case INTEL_MRFLD_EMMC_0: 530 case INTEL_MRFLD_EMMC_1: 531 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 532 MMC_CAP_8_BIT_DATA | 533 MMC_CAP_1_8V_DDR; 534 break; 535 case INTEL_MRFLD_SD: 536 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 537 break; 538 case INTEL_MRFLD_SDIO: 539 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 540 MMC_CAP_POWER_OFF_CARD; 541 break; 542 default: 543 return -ENODEV; 544 } 545 return 0; 546 } 547 548 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 549 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 550 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 551 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 552 .allow_runtime_pm = true, 553 .probe_slot = intel_mrfld_mmc_probe_slot, 554 }; 555 556 /* O2Micro extra registers */ 557 #define O2_SD_LOCK_WP 0xD3 558 #define O2_SD_MULTI_VCC3V 0xEE 559 #define O2_SD_CLKREQ 0xEC 560 #define O2_SD_CAPS 0xE0 561 #define O2_SD_ADMA1 0xE2 562 #define O2_SD_ADMA2 0xE7 563 #define O2_SD_INF_MOD 0xF1 564 565 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 566 { 567 u8 scratch; 568 int ret; 569 570 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 571 if (ret) 572 return ret; 573 574 /* 575 * Turn PMOS on [bit 0], set over current detection to 2.4 V 576 * [bit 1:2] and enable over current debouncing [bit 6]. 577 */ 578 if (on) 579 scratch |= 0x47; 580 else 581 scratch &= ~0x47; 582 583 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 584 } 585 586 static int jmicron_probe(struct sdhci_pci_chip *chip) 587 { 588 int ret; 589 u16 mmcdev = 0; 590 591 if (chip->pdev->revision == 0) { 592 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 593 SDHCI_QUIRK_32BIT_DMA_SIZE | 594 SDHCI_QUIRK_32BIT_ADMA_SIZE | 595 SDHCI_QUIRK_RESET_AFTER_REQUEST | 596 SDHCI_QUIRK_BROKEN_SMALL_PIO; 597 } 598 599 /* 600 * JMicron chips can have two interfaces to the same hardware 601 * in order to work around limitations in Microsoft's driver. 602 * We need to make sure we only bind to one of them. 603 * 604 * This code assumes two things: 605 * 606 * 1. The PCI code adds subfunctions in order. 607 * 608 * 2. The MMC interface has a lower subfunction number 609 * than the SD interface. 610 */ 611 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 612 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 613 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 614 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 615 616 if (mmcdev) { 617 struct pci_dev *sd_dev; 618 619 sd_dev = NULL; 620 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 621 mmcdev, sd_dev)) != NULL) { 622 if ((PCI_SLOT(chip->pdev->devfn) == 623 PCI_SLOT(sd_dev->devfn)) && 624 (chip->pdev->bus == sd_dev->bus)) 625 break; 626 } 627 628 if (sd_dev) { 629 pci_dev_put(sd_dev); 630 dev_info(&chip->pdev->dev, "Refusing to bind to " 631 "secondary interface.\n"); 632 return -ENODEV; 633 } 634 } 635 636 /* 637 * JMicron chips need a bit of a nudge to enable the power 638 * output pins. 639 */ 640 ret = jmicron_pmos(chip, 1); 641 if (ret) { 642 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 643 return ret; 644 } 645 646 /* quirk for unsable RO-detection on JM388 chips */ 647 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 648 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 649 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 650 651 return 0; 652 } 653 654 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 655 { 656 u8 scratch; 657 658 scratch = readb(host->ioaddr + 0xC0); 659 660 if (on) 661 scratch |= 0x01; 662 else 663 scratch &= ~0x01; 664 665 writeb(scratch, host->ioaddr + 0xC0); 666 } 667 668 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 669 { 670 if (slot->chip->pdev->revision == 0) { 671 u16 version; 672 673 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 674 version = (version & SDHCI_VENDOR_VER_MASK) >> 675 SDHCI_VENDOR_VER_SHIFT; 676 677 /* 678 * Older versions of the chip have lots of nasty glitches 679 * in the ADMA engine. It's best just to avoid it 680 * completely. 681 */ 682 if (version < 0xAC) 683 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 684 } 685 686 /* JM388 MMC doesn't support 1.8V while SD supports it */ 687 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 688 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 689 MMC_VDD_29_30 | MMC_VDD_30_31 | 690 MMC_VDD_165_195; /* allow 1.8V */ 691 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 692 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 693 } 694 695 /* 696 * The secondary interface requires a bit set to get the 697 * interrupts. 698 */ 699 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 700 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 701 jmicron_enable_mmc(slot->host, 1); 702 703 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 704 705 return 0; 706 } 707 708 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 709 { 710 if (dead) 711 return; 712 713 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 714 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 715 jmicron_enable_mmc(slot->host, 0); 716 } 717 718 static int jmicron_suspend(struct sdhci_pci_chip *chip) 719 { 720 int i; 721 722 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 723 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 724 for (i = 0; i < chip->num_slots; i++) 725 jmicron_enable_mmc(chip->slots[i]->host, 0); 726 } 727 728 return 0; 729 } 730 731 static int jmicron_resume(struct sdhci_pci_chip *chip) 732 { 733 int ret, i; 734 735 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 736 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 737 for (i = 0; i < chip->num_slots; i++) 738 jmicron_enable_mmc(chip->slots[i]->host, 1); 739 } 740 741 ret = jmicron_pmos(chip, 1); 742 if (ret) { 743 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 744 return ret; 745 } 746 747 return 0; 748 } 749 750 static const struct sdhci_pci_fixes sdhci_o2 = { 751 .probe = sdhci_pci_o2_probe, 752 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 753 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 754 .probe_slot = sdhci_pci_o2_probe_slot, 755 .resume = sdhci_pci_o2_resume, 756 }; 757 758 static const struct sdhci_pci_fixes sdhci_jmicron = { 759 .probe = jmicron_probe, 760 761 .probe_slot = jmicron_probe_slot, 762 .remove_slot = jmicron_remove_slot, 763 764 .suspend = jmicron_suspend, 765 .resume = jmicron_resume, 766 }; 767 768 /* SysKonnect CardBus2SDIO extra registers */ 769 #define SYSKT_CTRL 0x200 770 #define SYSKT_RDFIFO_STAT 0x204 771 #define SYSKT_WRFIFO_STAT 0x208 772 #define SYSKT_POWER_DATA 0x20c 773 #define SYSKT_POWER_330 0xef 774 #define SYSKT_POWER_300 0xf8 775 #define SYSKT_POWER_184 0xcc 776 #define SYSKT_POWER_CMD 0x20d 777 #define SYSKT_POWER_START (1 << 7) 778 #define SYSKT_POWER_STATUS 0x20e 779 #define SYSKT_POWER_STATUS_OK (1 << 0) 780 #define SYSKT_BOARD_REV 0x210 781 #define SYSKT_CHIP_REV 0x211 782 #define SYSKT_CONF_DATA 0x212 783 #define SYSKT_CONF_DATA_1V8 (1 << 2) 784 #define SYSKT_CONF_DATA_2V5 (1 << 1) 785 #define SYSKT_CONF_DATA_3V3 (1 << 0) 786 787 static int syskt_probe(struct sdhci_pci_chip *chip) 788 { 789 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 790 chip->pdev->class &= ~0x0000FF; 791 chip->pdev->class |= PCI_SDHCI_IFDMA; 792 } 793 return 0; 794 } 795 796 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 797 { 798 int tm, ps; 799 800 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 801 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 802 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 803 "board rev %d.%d, chip rev %d.%d\n", 804 board_rev >> 4, board_rev & 0xf, 805 chip_rev >> 4, chip_rev & 0xf); 806 if (chip_rev >= 0x20) 807 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 808 809 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 810 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 811 udelay(50); 812 tm = 10; /* Wait max 1 ms */ 813 do { 814 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 815 if (ps & SYSKT_POWER_STATUS_OK) 816 break; 817 udelay(100); 818 } while (--tm); 819 if (!tm) { 820 dev_err(&slot->chip->pdev->dev, 821 "power regulator never stabilized"); 822 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 823 return -ENODEV; 824 } 825 826 return 0; 827 } 828 829 static const struct sdhci_pci_fixes sdhci_syskt = { 830 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 831 .probe = syskt_probe, 832 .probe_slot = syskt_probe_slot, 833 }; 834 835 static int via_probe(struct sdhci_pci_chip *chip) 836 { 837 if (chip->pdev->revision == 0x10) 838 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 839 840 return 0; 841 } 842 843 static const struct sdhci_pci_fixes sdhci_via = { 844 .probe = via_probe, 845 }; 846 847 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 848 { 849 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 850 return 0; 851 } 852 853 static const struct sdhci_pci_fixes sdhci_rtsx = { 854 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 855 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 856 SDHCI_QUIRK2_BROKEN_DDR50, 857 .probe_slot = rtsx_probe_slot, 858 }; 859 860 /*AMD chipset generation*/ 861 enum amd_chipset_gen { 862 AMD_CHIPSET_BEFORE_ML, 863 AMD_CHIPSET_CZ, 864 AMD_CHIPSET_NL, 865 AMD_CHIPSET_UNKNOWN, 866 }; 867 868 static int amd_probe(struct sdhci_pci_chip *chip) 869 { 870 struct pci_dev *smbus_dev; 871 enum amd_chipset_gen gen; 872 873 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 874 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 875 if (smbus_dev) { 876 gen = AMD_CHIPSET_BEFORE_ML; 877 } else { 878 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 879 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 880 if (smbus_dev) { 881 if (smbus_dev->revision < 0x51) 882 gen = AMD_CHIPSET_CZ; 883 else 884 gen = AMD_CHIPSET_NL; 885 } else { 886 gen = AMD_CHIPSET_UNKNOWN; 887 } 888 } 889 890 if ((gen == AMD_CHIPSET_BEFORE_ML) || (gen == AMD_CHIPSET_CZ)) { 891 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 892 chip->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 893 } 894 895 return 0; 896 } 897 898 static const struct sdhci_pci_fixes sdhci_amd = { 899 .probe = amd_probe, 900 }; 901 902 static const struct pci_device_id pci_ids[] = { 903 { 904 .vendor = PCI_VENDOR_ID_RICOH, 905 .device = PCI_DEVICE_ID_RICOH_R5C822, 906 .subvendor = PCI_ANY_ID, 907 .subdevice = PCI_ANY_ID, 908 .driver_data = (kernel_ulong_t)&sdhci_ricoh, 909 }, 910 911 { 912 .vendor = PCI_VENDOR_ID_RICOH, 913 .device = 0x843, 914 .subvendor = PCI_ANY_ID, 915 .subdevice = PCI_ANY_ID, 916 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 917 }, 918 919 { 920 .vendor = PCI_VENDOR_ID_RICOH, 921 .device = 0xe822, 922 .subvendor = PCI_ANY_ID, 923 .subdevice = PCI_ANY_ID, 924 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 925 }, 926 927 { 928 .vendor = PCI_VENDOR_ID_RICOH, 929 .device = 0xe823, 930 .subvendor = PCI_ANY_ID, 931 .subdevice = PCI_ANY_ID, 932 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 933 }, 934 935 { 936 .vendor = PCI_VENDOR_ID_ENE, 937 .device = PCI_DEVICE_ID_ENE_CB712_SD, 938 .subvendor = PCI_ANY_ID, 939 .subdevice = PCI_ANY_ID, 940 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 941 }, 942 943 { 944 .vendor = PCI_VENDOR_ID_ENE, 945 .device = PCI_DEVICE_ID_ENE_CB712_SD_2, 946 .subvendor = PCI_ANY_ID, 947 .subdevice = PCI_ANY_ID, 948 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 949 }, 950 951 { 952 .vendor = PCI_VENDOR_ID_ENE, 953 .device = PCI_DEVICE_ID_ENE_CB714_SD, 954 .subvendor = PCI_ANY_ID, 955 .subdevice = PCI_ANY_ID, 956 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 957 }, 958 959 { 960 .vendor = PCI_VENDOR_ID_ENE, 961 .device = PCI_DEVICE_ID_ENE_CB714_SD_2, 962 .subvendor = PCI_ANY_ID, 963 .subdevice = PCI_ANY_ID, 964 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 965 }, 966 967 { 968 .vendor = PCI_VENDOR_ID_MARVELL, 969 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD, 970 .subvendor = PCI_ANY_ID, 971 .subdevice = PCI_ANY_ID, 972 .driver_data = (kernel_ulong_t)&sdhci_cafe, 973 }, 974 975 { 976 .vendor = PCI_VENDOR_ID_JMICRON, 977 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD, 978 .subvendor = PCI_ANY_ID, 979 .subdevice = PCI_ANY_ID, 980 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 981 }, 982 983 { 984 .vendor = PCI_VENDOR_ID_JMICRON, 985 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC, 986 .subvendor = PCI_ANY_ID, 987 .subdevice = PCI_ANY_ID, 988 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 989 }, 990 991 { 992 .vendor = PCI_VENDOR_ID_JMICRON, 993 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD, 994 .subvendor = PCI_ANY_ID, 995 .subdevice = PCI_ANY_ID, 996 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 997 }, 998 999 { 1000 .vendor = PCI_VENDOR_ID_JMICRON, 1001 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD, 1002 .subvendor = PCI_ANY_ID, 1003 .subdevice = PCI_ANY_ID, 1004 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1005 }, 1006 1007 { 1008 .vendor = PCI_VENDOR_ID_SYSKONNECT, 1009 .device = 0x8000, 1010 .subvendor = PCI_ANY_ID, 1011 .subdevice = PCI_ANY_ID, 1012 .driver_data = (kernel_ulong_t)&sdhci_syskt, 1013 }, 1014 1015 { 1016 .vendor = PCI_VENDOR_ID_VIA, 1017 .device = 0x95d0, 1018 .subvendor = PCI_ANY_ID, 1019 .subdevice = PCI_ANY_ID, 1020 .driver_data = (kernel_ulong_t)&sdhci_via, 1021 }, 1022 1023 { 1024 .vendor = PCI_VENDOR_ID_REALTEK, 1025 .device = 0x5250, 1026 .subvendor = PCI_ANY_ID, 1027 .subdevice = PCI_ANY_ID, 1028 .driver_data = (kernel_ulong_t)&sdhci_rtsx, 1029 }, 1030 1031 { 1032 .vendor = PCI_VENDOR_ID_INTEL, 1033 .device = PCI_DEVICE_ID_INTEL_QRK_SD, 1034 .subvendor = PCI_ANY_ID, 1035 .subdevice = PCI_ANY_ID, 1036 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk, 1037 }, 1038 1039 { 1040 .vendor = PCI_VENDOR_ID_INTEL, 1041 .device = PCI_DEVICE_ID_INTEL_MRST_SD0, 1042 .subvendor = PCI_ANY_ID, 1043 .subdevice = PCI_ANY_ID, 1044 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0, 1045 }, 1046 1047 { 1048 .vendor = PCI_VENDOR_ID_INTEL, 1049 .device = PCI_DEVICE_ID_INTEL_MRST_SD1, 1050 .subvendor = PCI_ANY_ID, 1051 .subdevice = PCI_ANY_ID, 1052 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 1053 }, 1054 1055 { 1056 .vendor = PCI_VENDOR_ID_INTEL, 1057 .device = PCI_DEVICE_ID_INTEL_MRST_SD2, 1058 .subvendor = PCI_ANY_ID, 1059 .subdevice = PCI_ANY_ID, 1060 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 1061 }, 1062 1063 { 1064 .vendor = PCI_VENDOR_ID_INTEL, 1065 .device = PCI_DEVICE_ID_INTEL_MFD_SD, 1066 .subvendor = PCI_ANY_ID, 1067 .subdevice = PCI_ANY_ID, 1068 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1069 }, 1070 1071 { 1072 .vendor = PCI_VENDOR_ID_INTEL, 1073 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1, 1074 .subvendor = PCI_ANY_ID, 1075 .subdevice = PCI_ANY_ID, 1076 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1077 }, 1078 1079 { 1080 .vendor = PCI_VENDOR_ID_INTEL, 1081 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2, 1082 .subvendor = PCI_ANY_ID, 1083 .subdevice = PCI_ANY_ID, 1084 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1085 }, 1086 1087 { 1088 .vendor = PCI_VENDOR_ID_INTEL, 1089 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0, 1090 .subvendor = PCI_ANY_ID, 1091 .subdevice = PCI_ANY_ID, 1092 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1093 }, 1094 1095 { 1096 .vendor = PCI_VENDOR_ID_INTEL, 1097 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1, 1098 .subvendor = PCI_ANY_ID, 1099 .subdevice = PCI_ANY_ID, 1100 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1101 }, 1102 1103 { 1104 .vendor = PCI_VENDOR_ID_INTEL, 1105 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0, 1106 .subvendor = PCI_ANY_ID, 1107 .subdevice = PCI_ANY_ID, 1108 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1109 }, 1110 1111 { 1112 .vendor = PCI_VENDOR_ID_INTEL, 1113 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1, 1114 .subvendor = PCI_ANY_ID, 1115 .subdevice = PCI_ANY_ID, 1116 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1117 }, 1118 1119 { 1120 .vendor = PCI_VENDOR_ID_INTEL, 1121 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC, 1122 .subvendor = PCI_ANY_ID, 1123 .subdevice = PCI_ANY_ID, 1124 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1125 }, 1126 1127 { 1128 .vendor = PCI_VENDOR_ID_INTEL, 1129 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, 1130 .subvendor = PCI_VENDOR_ID_NI, 1131 .subdevice = 0x7884, 1132 .driver_data = (kernel_ulong_t)&sdhci_ni_byt_sdio, 1133 }, 1134 1135 { 1136 .vendor = PCI_VENDOR_ID_INTEL, 1137 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, 1138 .subvendor = PCI_ANY_ID, 1139 .subdevice = PCI_ANY_ID, 1140 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1141 }, 1142 1143 { 1144 .vendor = PCI_VENDOR_ID_INTEL, 1145 .device = PCI_DEVICE_ID_INTEL_BYT_SD, 1146 .subvendor = PCI_ANY_ID, 1147 .subdevice = PCI_ANY_ID, 1148 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1149 }, 1150 1151 { 1152 .vendor = PCI_VENDOR_ID_INTEL, 1153 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2, 1154 .subvendor = PCI_ANY_ID, 1155 .subdevice = PCI_ANY_ID, 1156 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1157 }, 1158 1159 { 1160 .vendor = PCI_VENDOR_ID_INTEL, 1161 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC, 1162 .subvendor = PCI_ANY_ID, 1163 .subdevice = PCI_ANY_ID, 1164 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1165 }, 1166 1167 { 1168 .vendor = PCI_VENDOR_ID_INTEL, 1169 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO, 1170 .subvendor = PCI_ANY_ID, 1171 .subdevice = PCI_ANY_ID, 1172 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1173 }, 1174 1175 { 1176 .vendor = PCI_VENDOR_ID_INTEL, 1177 .device = PCI_DEVICE_ID_INTEL_BSW_SD, 1178 .subvendor = PCI_ANY_ID, 1179 .subdevice = PCI_ANY_ID, 1180 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1181 }, 1182 1183 { 1184 .vendor = PCI_VENDOR_ID_INTEL, 1185 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0, 1186 .subvendor = PCI_ANY_ID, 1187 .subdevice = PCI_ANY_ID, 1188 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1189 }, 1190 1191 { 1192 .vendor = PCI_VENDOR_ID_INTEL, 1193 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1, 1194 .subvendor = PCI_ANY_ID, 1195 .subdevice = PCI_ANY_ID, 1196 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1197 }, 1198 1199 { 1200 .vendor = PCI_VENDOR_ID_INTEL, 1201 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2, 1202 .subvendor = PCI_ANY_ID, 1203 .subdevice = PCI_ANY_ID, 1204 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1205 }, 1206 1207 { 1208 .vendor = PCI_VENDOR_ID_INTEL, 1209 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0, 1210 .subvendor = PCI_ANY_ID, 1211 .subdevice = PCI_ANY_ID, 1212 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1213 }, 1214 1215 { 1216 .vendor = PCI_VENDOR_ID_INTEL, 1217 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1, 1218 .subvendor = PCI_ANY_ID, 1219 .subdevice = PCI_ANY_ID, 1220 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1221 }, 1222 1223 { 1224 .vendor = PCI_VENDOR_ID_INTEL, 1225 .device = PCI_DEVICE_ID_INTEL_MRFLD_MMC, 1226 .subvendor = PCI_ANY_ID, 1227 .subdevice = PCI_ANY_ID, 1228 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfld_mmc, 1229 }, 1230 1231 { 1232 .vendor = PCI_VENDOR_ID_INTEL, 1233 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC, 1234 .subvendor = PCI_ANY_ID, 1235 .subdevice = PCI_ANY_ID, 1236 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1237 }, 1238 1239 { 1240 .vendor = PCI_VENDOR_ID_INTEL, 1241 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO, 1242 .subvendor = PCI_ANY_ID, 1243 .subdevice = PCI_ANY_ID, 1244 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1245 }, 1246 1247 { 1248 .vendor = PCI_VENDOR_ID_INTEL, 1249 .device = PCI_DEVICE_ID_INTEL_SPT_SD, 1250 .subvendor = PCI_ANY_ID, 1251 .subdevice = PCI_ANY_ID, 1252 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1253 }, 1254 1255 { 1256 .vendor = PCI_VENDOR_ID_INTEL, 1257 .device = PCI_DEVICE_ID_INTEL_DNV_EMMC, 1258 .subvendor = PCI_ANY_ID, 1259 .subdevice = PCI_ANY_ID, 1260 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1261 }, 1262 1263 { 1264 .vendor = PCI_VENDOR_ID_INTEL, 1265 .device = PCI_DEVICE_ID_INTEL_BXT_EMMC, 1266 .subvendor = PCI_ANY_ID, 1267 .subdevice = PCI_ANY_ID, 1268 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1269 }, 1270 1271 { 1272 .vendor = PCI_VENDOR_ID_INTEL, 1273 .device = PCI_DEVICE_ID_INTEL_BXT_SDIO, 1274 .subvendor = PCI_ANY_ID, 1275 .subdevice = PCI_ANY_ID, 1276 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1277 }, 1278 1279 { 1280 .vendor = PCI_VENDOR_ID_INTEL, 1281 .device = PCI_DEVICE_ID_INTEL_BXT_SD, 1282 .subvendor = PCI_ANY_ID, 1283 .subdevice = PCI_ANY_ID, 1284 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1285 }, 1286 1287 { 1288 .vendor = PCI_VENDOR_ID_INTEL, 1289 .device = PCI_DEVICE_ID_INTEL_BXTM_EMMC, 1290 .subvendor = PCI_ANY_ID, 1291 .subdevice = PCI_ANY_ID, 1292 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1293 }, 1294 1295 { 1296 .vendor = PCI_VENDOR_ID_INTEL, 1297 .device = PCI_DEVICE_ID_INTEL_BXTM_SDIO, 1298 .subvendor = PCI_ANY_ID, 1299 .subdevice = PCI_ANY_ID, 1300 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1301 }, 1302 1303 { 1304 .vendor = PCI_VENDOR_ID_INTEL, 1305 .device = PCI_DEVICE_ID_INTEL_BXTM_SD, 1306 .subvendor = PCI_ANY_ID, 1307 .subdevice = PCI_ANY_ID, 1308 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1309 }, 1310 1311 { 1312 .vendor = PCI_VENDOR_ID_INTEL, 1313 .device = PCI_DEVICE_ID_INTEL_APL_EMMC, 1314 .subvendor = PCI_ANY_ID, 1315 .subdevice = PCI_ANY_ID, 1316 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1317 }, 1318 1319 { 1320 .vendor = PCI_VENDOR_ID_INTEL, 1321 .device = PCI_DEVICE_ID_INTEL_APL_SDIO, 1322 .subvendor = PCI_ANY_ID, 1323 .subdevice = PCI_ANY_ID, 1324 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1325 }, 1326 1327 { 1328 .vendor = PCI_VENDOR_ID_INTEL, 1329 .device = PCI_DEVICE_ID_INTEL_APL_SD, 1330 .subvendor = PCI_ANY_ID, 1331 .subdevice = PCI_ANY_ID, 1332 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1333 }, 1334 1335 { 1336 .vendor = PCI_VENDOR_ID_INTEL, 1337 .device = PCI_DEVICE_ID_INTEL_GLK_EMMC, 1338 .subvendor = PCI_ANY_ID, 1339 .subdevice = PCI_ANY_ID, 1340 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1341 }, 1342 1343 { 1344 .vendor = PCI_VENDOR_ID_INTEL, 1345 .device = PCI_DEVICE_ID_INTEL_GLK_SDIO, 1346 .subvendor = PCI_ANY_ID, 1347 .subdevice = PCI_ANY_ID, 1348 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1349 }, 1350 1351 { 1352 .vendor = PCI_VENDOR_ID_INTEL, 1353 .device = PCI_DEVICE_ID_INTEL_GLK_SD, 1354 .subvendor = PCI_ANY_ID, 1355 .subdevice = PCI_ANY_ID, 1356 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1357 }, 1358 1359 { 1360 .vendor = PCI_VENDOR_ID_O2, 1361 .device = PCI_DEVICE_ID_O2_8120, 1362 .subvendor = PCI_ANY_ID, 1363 .subdevice = PCI_ANY_ID, 1364 .driver_data = (kernel_ulong_t)&sdhci_o2, 1365 }, 1366 1367 { 1368 .vendor = PCI_VENDOR_ID_O2, 1369 .device = PCI_DEVICE_ID_O2_8220, 1370 .subvendor = PCI_ANY_ID, 1371 .subdevice = PCI_ANY_ID, 1372 .driver_data = (kernel_ulong_t)&sdhci_o2, 1373 }, 1374 1375 { 1376 .vendor = PCI_VENDOR_ID_O2, 1377 .device = PCI_DEVICE_ID_O2_8221, 1378 .subvendor = PCI_ANY_ID, 1379 .subdevice = PCI_ANY_ID, 1380 .driver_data = (kernel_ulong_t)&sdhci_o2, 1381 }, 1382 1383 { 1384 .vendor = PCI_VENDOR_ID_O2, 1385 .device = PCI_DEVICE_ID_O2_8320, 1386 .subvendor = PCI_ANY_ID, 1387 .subdevice = PCI_ANY_ID, 1388 .driver_data = (kernel_ulong_t)&sdhci_o2, 1389 }, 1390 1391 { 1392 .vendor = PCI_VENDOR_ID_O2, 1393 .device = PCI_DEVICE_ID_O2_8321, 1394 .subvendor = PCI_ANY_ID, 1395 .subdevice = PCI_ANY_ID, 1396 .driver_data = (kernel_ulong_t)&sdhci_o2, 1397 }, 1398 1399 { 1400 .vendor = PCI_VENDOR_ID_O2, 1401 .device = PCI_DEVICE_ID_O2_FUJIN2, 1402 .subvendor = PCI_ANY_ID, 1403 .subdevice = PCI_ANY_ID, 1404 .driver_data = (kernel_ulong_t)&sdhci_o2, 1405 }, 1406 1407 { 1408 .vendor = PCI_VENDOR_ID_O2, 1409 .device = PCI_DEVICE_ID_O2_SDS0, 1410 .subvendor = PCI_ANY_ID, 1411 .subdevice = PCI_ANY_ID, 1412 .driver_data = (kernel_ulong_t)&sdhci_o2, 1413 }, 1414 1415 { 1416 .vendor = PCI_VENDOR_ID_O2, 1417 .device = PCI_DEVICE_ID_O2_SDS1, 1418 .subvendor = PCI_ANY_ID, 1419 .subdevice = PCI_ANY_ID, 1420 .driver_data = (kernel_ulong_t)&sdhci_o2, 1421 }, 1422 1423 { 1424 .vendor = PCI_VENDOR_ID_O2, 1425 .device = PCI_DEVICE_ID_O2_SEABIRD0, 1426 .subvendor = PCI_ANY_ID, 1427 .subdevice = PCI_ANY_ID, 1428 .driver_data = (kernel_ulong_t)&sdhci_o2, 1429 }, 1430 1431 { 1432 .vendor = PCI_VENDOR_ID_O2, 1433 .device = PCI_DEVICE_ID_O2_SEABIRD1, 1434 .subvendor = PCI_ANY_ID, 1435 .subdevice = PCI_ANY_ID, 1436 .driver_data = (kernel_ulong_t)&sdhci_o2, 1437 }, 1438 { 1439 .vendor = PCI_VENDOR_ID_AMD, 1440 .device = PCI_ANY_ID, 1441 .class = PCI_CLASS_SYSTEM_SDHCI << 8, 1442 .class_mask = 0xFFFF00, 1443 .subvendor = PCI_ANY_ID, 1444 .subdevice = PCI_ANY_ID, 1445 .driver_data = (kernel_ulong_t)&sdhci_amd, 1446 }, 1447 { /* Generic SD host controller */ 1448 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) 1449 }, 1450 1451 { /* end: all zeroes */ }, 1452 }; 1453 1454 MODULE_DEVICE_TABLE(pci, pci_ids); 1455 1456 /*****************************************************************************\ 1457 * * 1458 * SDHCI core callbacks * 1459 * * 1460 \*****************************************************************************/ 1461 1462 static int sdhci_pci_enable_dma(struct sdhci_host *host) 1463 { 1464 struct sdhci_pci_slot *slot; 1465 struct pci_dev *pdev; 1466 1467 slot = sdhci_priv(host); 1468 pdev = slot->chip->pdev; 1469 1470 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1471 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1472 (host->flags & SDHCI_USE_SDMA)) { 1473 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1474 "doesn't fully claim to support it.\n"); 1475 } 1476 1477 pci_set_master(pdev); 1478 1479 return 0; 1480 } 1481 1482 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width) 1483 { 1484 u8 ctrl; 1485 1486 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1487 1488 switch (width) { 1489 case MMC_BUS_WIDTH_8: 1490 ctrl |= SDHCI_CTRL_8BITBUS; 1491 ctrl &= ~SDHCI_CTRL_4BITBUS; 1492 break; 1493 case MMC_BUS_WIDTH_4: 1494 ctrl |= SDHCI_CTRL_4BITBUS; 1495 ctrl &= ~SDHCI_CTRL_8BITBUS; 1496 break; 1497 default: 1498 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS); 1499 break; 1500 } 1501 1502 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1503 } 1504 1505 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1506 { 1507 struct sdhci_pci_slot *slot = sdhci_priv(host); 1508 int rst_n_gpio = slot->rst_n_gpio; 1509 1510 if (!gpio_is_valid(rst_n_gpio)) 1511 return; 1512 gpio_set_value_cansleep(rst_n_gpio, 0); 1513 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1514 udelay(10); 1515 gpio_set_value_cansleep(rst_n_gpio, 1); 1516 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1517 usleep_range(300, 1000); 1518 } 1519 1520 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1521 { 1522 struct sdhci_pci_slot *slot = sdhci_priv(host); 1523 1524 if (slot->hw_reset) 1525 slot->hw_reset(host); 1526 } 1527 1528 static int sdhci_pci_select_drive_strength(struct sdhci_host *host, 1529 struct mmc_card *card, 1530 unsigned int max_dtr, int host_drv, 1531 int card_drv, int *drv_type) 1532 { 1533 struct sdhci_pci_slot *slot = sdhci_priv(host); 1534 1535 if (!slot->select_drive_strength) 1536 return 0; 1537 1538 return slot->select_drive_strength(host, card, max_dtr, host_drv, 1539 card_drv, drv_type); 1540 } 1541 1542 static const struct sdhci_ops sdhci_pci_ops = { 1543 .set_clock = sdhci_set_clock, 1544 .enable_dma = sdhci_pci_enable_dma, 1545 .set_bus_width = sdhci_pci_set_bus_width, 1546 .reset = sdhci_reset, 1547 .set_uhs_signaling = sdhci_set_uhs_signaling, 1548 .hw_reset = sdhci_pci_hw_reset, 1549 .select_drive_strength = sdhci_pci_select_drive_strength, 1550 }; 1551 1552 /*****************************************************************************\ 1553 * * 1554 * Suspend/resume * 1555 * * 1556 \*****************************************************************************/ 1557 1558 #ifdef CONFIG_PM_SLEEP 1559 static int sdhci_pci_suspend(struct device *dev) 1560 { 1561 struct pci_dev *pdev = to_pci_dev(dev); 1562 struct sdhci_pci_chip *chip; 1563 struct sdhci_pci_slot *slot; 1564 mmc_pm_flag_t slot_pm_flags; 1565 mmc_pm_flag_t pm_flags = 0; 1566 int i, ret; 1567 1568 chip = pci_get_drvdata(pdev); 1569 if (!chip) 1570 return 0; 1571 1572 for (i = 0; i < chip->num_slots; i++) { 1573 slot = chip->slots[i]; 1574 if (!slot) 1575 continue; 1576 1577 ret = sdhci_suspend_host(slot->host); 1578 1579 if (ret) 1580 goto err_pci_suspend; 1581 1582 slot_pm_flags = slot->host->mmc->pm_flags; 1583 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1584 sdhci_enable_irq_wakeups(slot->host); 1585 1586 pm_flags |= slot_pm_flags; 1587 } 1588 1589 if (chip->fixes && chip->fixes->suspend) { 1590 ret = chip->fixes->suspend(chip); 1591 if (ret) 1592 goto err_pci_suspend; 1593 } 1594 1595 if (pm_flags & MMC_PM_KEEP_POWER) { 1596 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1597 device_init_wakeup(dev, true); 1598 else 1599 device_init_wakeup(dev, false); 1600 } else 1601 device_init_wakeup(dev, false); 1602 1603 return 0; 1604 1605 err_pci_suspend: 1606 while (--i >= 0) 1607 sdhci_resume_host(chip->slots[i]->host); 1608 return ret; 1609 } 1610 1611 static int sdhci_pci_resume(struct device *dev) 1612 { 1613 struct pci_dev *pdev = to_pci_dev(dev); 1614 struct sdhci_pci_chip *chip; 1615 struct sdhci_pci_slot *slot; 1616 int i, ret; 1617 1618 chip = pci_get_drvdata(pdev); 1619 if (!chip) 1620 return 0; 1621 1622 if (chip->fixes && chip->fixes->resume) { 1623 ret = chip->fixes->resume(chip); 1624 if (ret) 1625 return ret; 1626 } 1627 1628 for (i = 0; i < chip->num_slots; i++) { 1629 slot = chip->slots[i]; 1630 if (!slot) 1631 continue; 1632 1633 ret = sdhci_resume_host(slot->host); 1634 if (ret) 1635 return ret; 1636 } 1637 1638 return 0; 1639 } 1640 #endif 1641 1642 #ifdef CONFIG_PM 1643 static int sdhci_pci_runtime_suspend(struct device *dev) 1644 { 1645 struct pci_dev *pdev = to_pci_dev(dev); 1646 struct sdhci_pci_chip *chip; 1647 struct sdhci_pci_slot *slot; 1648 int i, ret; 1649 1650 chip = pci_get_drvdata(pdev); 1651 if (!chip) 1652 return 0; 1653 1654 for (i = 0; i < chip->num_slots; i++) { 1655 slot = chip->slots[i]; 1656 if (!slot) 1657 continue; 1658 1659 ret = sdhci_runtime_suspend_host(slot->host); 1660 1661 if (ret) 1662 goto err_pci_runtime_suspend; 1663 } 1664 1665 if (chip->fixes && chip->fixes->suspend) { 1666 ret = chip->fixes->suspend(chip); 1667 if (ret) 1668 goto err_pci_runtime_suspend; 1669 } 1670 1671 return 0; 1672 1673 err_pci_runtime_suspend: 1674 while (--i >= 0) 1675 sdhci_runtime_resume_host(chip->slots[i]->host); 1676 return ret; 1677 } 1678 1679 static int sdhci_pci_runtime_resume(struct device *dev) 1680 { 1681 struct pci_dev *pdev = to_pci_dev(dev); 1682 struct sdhci_pci_chip *chip; 1683 struct sdhci_pci_slot *slot; 1684 int i, ret; 1685 1686 chip = pci_get_drvdata(pdev); 1687 if (!chip) 1688 return 0; 1689 1690 if (chip->fixes && chip->fixes->resume) { 1691 ret = chip->fixes->resume(chip); 1692 if (ret) 1693 return ret; 1694 } 1695 1696 for (i = 0; i < chip->num_slots; i++) { 1697 slot = chip->slots[i]; 1698 if (!slot) 1699 continue; 1700 1701 ret = sdhci_runtime_resume_host(slot->host); 1702 if (ret) 1703 return ret; 1704 } 1705 1706 return 0; 1707 } 1708 #endif 1709 1710 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1711 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1712 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1713 sdhci_pci_runtime_resume, NULL) 1714 }; 1715 1716 /*****************************************************************************\ 1717 * * 1718 * Device probing/removal * 1719 * * 1720 \*****************************************************************************/ 1721 1722 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1723 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1724 int slotno) 1725 { 1726 struct sdhci_pci_slot *slot; 1727 struct sdhci_host *host; 1728 int ret, bar = first_bar + slotno; 1729 1730 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1731 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1732 return ERR_PTR(-ENODEV); 1733 } 1734 1735 if (pci_resource_len(pdev, bar) < 0x100) { 1736 dev_err(&pdev->dev, "Invalid iomem size. You may " 1737 "experience problems.\n"); 1738 } 1739 1740 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1741 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1742 return ERR_PTR(-ENODEV); 1743 } 1744 1745 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1746 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1747 return ERR_PTR(-ENODEV); 1748 } 1749 1750 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot)); 1751 if (IS_ERR(host)) { 1752 dev_err(&pdev->dev, "cannot allocate host\n"); 1753 return ERR_CAST(host); 1754 } 1755 1756 slot = sdhci_priv(host); 1757 1758 slot->chip = chip; 1759 slot->host = host; 1760 slot->rst_n_gpio = -EINVAL; 1761 slot->cd_gpio = -EINVAL; 1762 slot->cd_idx = -1; 1763 1764 /* Retrieve platform data if there is any */ 1765 if (*sdhci_pci_get_data) 1766 slot->data = sdhci_pci_get_data(pdev, slotno); 1767 1768 if (slot->data) { 1769 if (slot->data->setup) { 1770 ret = slot->data->setup(slot->data); 1771 if (ret) { 1772 dev_err(&pdev->dev, "platform setup failed\n"); 1773 goto free; 1774 } 1775 } 1776 slot->rst_n_gpio = slot->data->rst_n_gpio; 1777 slot->cd_gpio = slot->data->cd_gpio; 1778 } 1779 1780 host->hw_name = "PCI"; 1781 host->ops = chip->fixes && chip->fixes->ops ? 1782 chip->fixes->ops : 1783 &sdhci_pci_ops; 1784 host->quirks = chip->quirks; 1785 host->quirks2 = chip->quirks2; 1786 1787 host->irq = pdev->irq; 1788 1789 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1790 if (ret) { 1791 dev_err(&pdev->dev, "cannot request region\n"); 1792 goto cleanup; 1793 } 1794 1795 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1796 1797 if (chip->fixes && chip->fixes->probe_slot) { 1798 ret = chip->fixes->probe_slot(slot); 1799 if (ret) 1800 goto cleanup; 1801 } 1802 1803 if (gpio_is_valid(slot->rst_n_gpio)) { 1804 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1805 gpio_direction_output(slot->rst_n_gpio, 1); 1806 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1807 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1808 } else { 1809 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1810 slot->rst_n_gpio = -EINVAL; 1811 } 1812 } 1813 1814 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; 1815 host->mmc->slotno = slotno; 1816 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1817 1818 if (slot->cd_idx >= 0) { 1819 ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx, 1820 slot->cd_override_level, 0, NULL); 1821 if (ret == -EPROBE_DEFER) 1822 goto remove; 1823 1824 if (ret) { 1825 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 1826 slot->cd_idx = -1; 1827 } 1828 } 1829 1830 ret = sdhci_add_host(host); 1831 if (ret) 1832 goto remove; 1833 1834 sdhci_pci_add_own_cd(slot); 1835 1836 /* 1837 * Check if the chip needs a separate GPIO for card detect to wake up 1838 * from runtime suspend. If it is not there, don't allow runtime PM. 1839 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 1840 */ 1841 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 1842 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 1843 chip->allow_runtime_pm = false; 1844 1845 return slot; 1846 1847 remove: 1848 if (chip->fixes && chip->fixes->remove_slot) 1849 chip->fixes->remove_slot(slot, 0); 1850 1851 cleanup: 1852 if (slot->data && slot->data->cleanup) 1853 slot->data->cleanup(slot->data); 1854 1855 free: 1856 sdhci_free_host(host); 1857 1858 return ERR_PTR(ret); 1859 } 1860 1861 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 1862 { 1863 int dead; 1864 u32 scratch; 1865 1866 sdhci_pci_remove_own_cd(slot); 1867 1868 dead = 0; 1869 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 1870 if (scratch == (u32)-1) 1871 dead = 1; 1872 1873 sdhci_remove_host(slot->host, dead); 1874 1875 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 1876 slot->chip->fixes->remove_slot(slot, dead); 1877 1878 if (slot->data && slot->data->cleanup) 1879 slot->data->cleanup(slot->data); 1880 1881 sdhci_free_host(slot->host); 1882 } 1883 1884 static void sdhci_pci_runtime_pm_allow(struct device *dev) 1885 { 1886 pm_suspend_ignore_children(dev, 1); 1887 pm_runtime_set_autosuspend_delay(dev, 50); 1888 pm_runtime_use_autosuspend(dev); 1889 pm_runtime_allow(dev); 1890 /* Stay active until mmc core scans for a card */ 1891 pm_runtime_put_noidle(dev); 1892 } 1893 1894 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 1895 { 1896 pm_runtime_forbid(dev); 1897 pm_runtime_get_noresume(dev); 1898 } 1899 1900 static int sdhci_pci_probe(struct pci_dev *pdev, 1901 const struct pci_device_id *ent) 1902 { 1903 struct sdhci_pci_chip *chip; 1904 struct sdhci_pci_slot *slot; 1905 1906 u8 slots, first_bar; 1907 int ret, i; 1908 1909 BUG_ON(pdev == NULL); 1910 BUG_ON(ent == NULL); 1911 1912 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 1913 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 1914 1915 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 1916 if (ret) 1917 return ret; 1918 1919 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 1920 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 1921 if (slots == 0) 1922 return -ENODEV; 1923 1924 BUG_ON(slots > MAX_SLOTS); 1925 1926 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 1927 if (ret) 1928 return ret; 1929 1930 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 1931 1932 if (first_bar > 5) { 1933 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 1934 return -ENODEV; 1935 } 1936 1937 ret = pcim_enable_device(pdev); 1938 if (ret) 1939 return ret; 1940 1941 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 1942 if (!chip) 1943 return -ENOMEM; 1944 1945 chip->pdev = pdev; 1946 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 1947 if (chip->fixes) { 1948 chip->quirks = chip->fixes->quirks; 1949 chip->quirks2 = chip->fixes->quirks2; 1950 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 1951 } 1952 chip->num_slots = slots; 1953 1954 pci_set_drvdata(pdev, chip); 1955 1956 if (chip->fixes && chip->fixes->probe) { 1957 ret = chip->fixes->probe(chip); 1958 if (ret) 1959 return ret; 1960 } 1961 1962 slots = chip->num_slots; /* Quirk may have changed this */ 1963 1964 for (i = 0; i < slots; i++) { 1965 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 1966 if (IS_ERR(slot)) { 1967 for (i--; i >= 0; i--) 1968 sdhci_pci_remove_slot(chip->slots[i]); 1969 return PTR_ERR(slot); 1970 } 1971 1972 chip->slots[i] = slot; 1973 } 1974 1975 if (chip->allow_runtime_pm) 1976 sdhci_pci_runtime_pm_allow(&pdev->dev); 1977 1978 return 0; 1979 } 1980 1981 static void sdhci_pci_remove(struct pci_dev *pdev) 1982 { 1983 int i; 1984 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1985 1986 if (chip->allow_runtime_pm) 1987 sdhci_pci_runtime_pm_forbid(&pdev->dev); 1988 1989 for (i = 0; i < chip->num_slots; i++) 1990 sdhci_pci_remove_slot(chip->slots[i]); 1991 } 1992 1993 static struct pci_driver sdhci_driver = { 1994 .name = "sdhci-pci", 1995 .id_table = pci_ids, 1996 .probe = sdhci_pci_probe, 1997 .remove = sdhci_pci_remove, 1998 .driver = { 1999 .pm = &sdhci_pci_pm_ops 2000 }, 2001 }; 2002 2003 module_pci_driver(sdhci_driver); 2004 2005 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 2006 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 2007 MODULE_LICENSE("GPL"); 2008