1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 2 * 3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 * 10 * Thanks to the following companies for their support: 11 * 12 * - JMicron (hardware and technical support) 13 */ 14 15 #include <linux/string.h> 16 #include <linux/delay.h> 17 #include <linux/highmem.h> 18 #include <linux/module.h> 19 #include <linux/pci.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/slab.h> 22 #include <linux/device.h> 23 #include <linux/mmc/host.h> 24 #include <linux/mmc/mmc.h> 25 #include <linux/scatterlist.h> 26 #include <linux/io.h> 27 #include <linux/gpio.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/mmc/slot-gpio.h> 30 #include <linux/mmc/sdhci-pci-data.h> 31 #include <linux/acpi.h> 32 33 #include "sdhci.h" 34 #include "sdhci-pci.h" 35 36 static int sdhci_pci_enable_dma(struct sdhci_host *host); 37 static void sdhci_pci_hw_reset(struct sdhci_host *host); 38 39 #ifdef CONFIG_PM_SLEEP 40 static int __sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 41 { 42 int i, ret; 43 44 for (i = 0; i < chip->num_slots; i++) { 45 struct sdhci_pci_slot *slot = chip->slots[i]; 46 struct sdhci_host *host; 47 48 if (!slot) 49 continue; 50 51 host = slot->host; 52 53 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 54 mmc_retune_needed(host->mmc); 55 56 ret = sdhci_suspend_host(host); 57 if (ret) 58 goto err_pci_suspend; 59 60 if (host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ) 61 sdhci_enable_irq_wakeups(host); 62 } 63 64 return 0; 65 66 err_pci_suspend: 67 while (--i >= 0) 68 sdhci_resume_host(chip->slots[i]->host); 69 return ret; 70 } 71 72 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip) 73 { 74 mmc_pm_flag_t pm_flags = 0; 75 int i; 76 77 for (i = 0; i < chip->num_slots; i++) { 78 struct sdhci_pci_slot *slot = chip->slots[i]; 79 80 if (slot) 81 pm_flags |= slot->host->mmc->pm_flags; 82 } 83 84 return device_init_wakeup(&chip->pdev->dev, 85 (pm_flags & MMC_PM_KEEP_POWER) && 86 (pm_flags & MMC_PM_WAKE_SDIO_IRQ)); 87 } 88 89 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 90 { 91 int ret; 92 93 ret = __sdhci_pci_suspend_host(chip); 94 if (ret) 95 return ret; 96 97 sdhci_pci_init_wakeup(chip); 98 99 return 0; 100 } 101 102 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip) 103 { 104 struct sdhci_pci_slot *slot; 105 int i, ret; 106 107 for (i = 0; i < chip->num_slots; i++) { 108 slot = chip->slots[i]; 109 if (!slot) 110 continue; 111 112 ret = sdhci_resume_host(slot->host); 113 if (ret) 114 return ret; 115 } 116 117 return 0; 118 } 119 #endif 120 121 #ifdef CONFIG_PM 122 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip) 123 { 124 struct sdhci_pci_slot *slot; 125 struct sdhci_host *host; 126 int i, ret; 127 128 for (i = 0; i < chip->num_slots; i++) { 129 slot = chip->slots[i]; 130 if (!slot) 131 continue; 132 133 host = slot->host; 134 135 ret = sdhci_runtime_suspend_host(host); 136 if (ret) 137 goto err_pci_runtime_suspend; 138 139 if (chip->rpm_retune && 140 host->tuning_mode != SDHCI_TUNING_MODE_3) 141 mmc_retune_needed(host->mmc); 142 } 143 144 return 0; 145 146 err_pci_runtime_suspend: 147 while (--i >= 0) 148 sdhci_runtime_resume_host(chip->slots[i]->host); 149 return ret; 150 } 151 152 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip) 153 { 154 struct sdhci_pci_slot *slot; 155 int i, ret; 156 157 for (i = 0; i < chip->num_slots; i++) { 158 slot = chip->slots[i]; 159 if (!slot) 160 continue; 161 162 ret = sdhci_runtime_resume_host(slot->host); 163 if (ret) 164 return ret; 165 } 166 167 return 0; 168 } 169 #endif 170 171 /*****************************************************************************\ 172 * * 173 * Hardware specific quirk handling * 174 * * 175 \*****************************************************************************/ 176 177 static int ricoh_probe(struct sdhci_pci_chip *chip) 178 { 179 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 180 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 181 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 182 return 0; 183 } 184 185 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 186 { 187 slot->host->caps = 188 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 189 & SDHCI_TIMEOUT_CLK_MASK) | 190 191 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 192 & SDHCI_CLOCK_BASE_MASK) | 193 194 SDHCI_TIMEOUT_CLK_UNIT | 195 SDHCI_CAN_VDD_330 | 196 SDHCI_CAN_DO_HISPD | 197 SDHCI_CAN_DO_SDMA; 198 return 0; 199 } 200 201 #ifdef CONFIG_PM_SLEEP 202 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 203 { 204 /* Apply a delay to allow controller to settle */ 205 /* Otherwise it becomes confused if card state changed 206 during suspend */ 207 msleep(500); 208 return sdhci_pci_resume_host(chip); 209 } 210 #endif 211 212 static const struct sdhci_pci_fixes sdhci_ricoh = { 213 .probe = ricoh_probe, 214 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 215 SDHCI_QUIRK_FORCE_DMA | 216 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 217 }; 218 219 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 220 .probe_slot = ricoh_mmc_probe_slot, 221 #ifdef CONFIG_PM_SLEEP 222 .resume = ricoh_mmc_resume, 223 #endif 224 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 225 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 226 SDHCI_QUIRK_NO_CARD_NO_RESET | 227 SDHCI_QUIRK_MISSING_CAPS 228 }; 229 230 static const struct sdhci_pci_fixes sdhci_ene_712 = { 231 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 232 SDHCI_QUIRK_BROKEN_DMA, 233 }; 234 235 static const struct sdhci_pci_fixes sdhci_ene_714 = { 236 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 237 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 238 SDHCI_QUIRK_BROKEN_DMA, 239 }; 240 241 static const struct sdhci_pci_fixes sdhci_cafe = { 242 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 243 SDHCI_QUIRK_NO_BUSY_IRQ | 244 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 245 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 246 }; 247 248 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 249 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 250 }; 251 252 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 253 { 254 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 255 return 0; 256 } 257 258 /* 259 * ADMA operation is disabled for Moorestown platform due to 260 * hardware bugs. 261 */ 262 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 263 { 264 /* 265 * slots number is fixed here for MRST as SDIO3/5 are never used and 266 * have hardware bugs. 267 */ 268 chip->num_slots = 1; 269 return 0; 270 } 271 272 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 273 { 274 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 275 return 0; 276 } 277 278 #ifdef CONFIG_PM 279 280 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 281 { 282 struct sdhci_pci_slot *slot = dev_id; 283 struct sdhci_host *host = slot->host; 284 285 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 286 return IRQ_HANDLED; 287 } 288 289 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 290 { 291 int err, irq, gpio = slot->cd_gpio; 292 293 slot->cd_gpio = -EINVAL; 294 slot->cd_irq = -EINVAL; 295 296 if (!gpio_is_valid(gpio)) 297 return; 298 299 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 300 if (err < 0) 301 goto out; 302 303 err = gpio_direction_input(gpio); 304 if (err < 0) 305 goto out_free; 306 307 irq = gpio_to_irq(gpio); 308 if (irq < 0) 309 goto out_free; 310 311 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 312 IRQF_TRIGGER_FALLING, "sd_cd", slot); 313 if (err) 314 goto out_free; 315 316 slot->cd_gpio = gpio; 317 slot->cd_irq = irq; 318 319 return; 320 321 out_free: 322 devm_gpio_free(&slot->chip->pdev->dev, gpio); 323 out: 324 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 325 } 326 327 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 328 { 329 if (slot->cd_irq >= 0) 330 free_irq(slot->cd_irq, slot); 331 } 332 333 #else 334 335 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 336 { 337 } 338 339 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 340 { 341 } 342 343 #endif 344 345 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 346 { 347 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 348 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC; 349 return 0; 350 } 351 352 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 353 { 354 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 355 return 0; 356 } 357 358 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 359 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 360 .probe_slot = mrst_hc_probe_slot, 361 }; 362 363 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 364 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 365 .probe = mrst_hc_probe, 366 }; 367 368 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 369 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 370 .allow_runtime_pm = true, 371 .own_cd_for_runtime_pm = true, 372 }; 373 374 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 375 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 376 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 377 .allow_runtime_pm = true, 378 .probe_slot = mfd_sdio_probe_slot, 379 }; 380 381 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 382 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 383 .allow_runtime_pm = true, 384 .probe_slot = mfd_emmc_probe_slot, 385 }; 386 387 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 388 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 389 .probe_slot = pch_hc_probe_slot, 390 }; 391 392 enum { 393 INTEL_DSM_FNS = 0, 394 INTEL_DSM_V18_SWITCH = 3, 395 INTEL_DSM_DRV_STRENGTH = 9, 396 INTEL_DSM_D3_RETUNE = 10, 397 }; 398 399 struct intel_host { 400 u32 dsm_fns; 401 int drv_strength; 402 bool d3_retune; 403 }; 404 405 static const guid_t intel_dsm_guid = 406 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F, 407 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61); 408 409 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 410 unsigned int fn, u32 *result) 411 { 412 union acpi_object *obj; 413 int err = 0; 414 size_t len; 415 416 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL); 417 if (!obj) 418 return -EOPNOTSUPP; 419 420 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { 421 err = -EINVAL; 422 goto out; 423 } 424 425 len = min_t(size_t, obj->buffer.length, 4); 426 427 *result = 0; 428 memcpy(result, obj->buffer.pointer, len); 429 out: 430 ACPI_FREE(obj); 431 432 return err; 433 } 434 435 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 436 unsigned int fn, u32 *result) 437 { 438 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 439 return -EOPNOTSUPP; 440 441 return __intel_dsm(intel_host, dev, fn, result); 442 } 443 444 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 445 struct mmc_host *mmc) 446 { 447 int err; 448 u32 val; 449 450 intel_host->d3_retune = true; 451 452 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 453 if (err) { 454 pr_debug("%s: DSM not supported, error %d\n", 455 mmc_hostname(mmc), err); 456 return; 457 } 458 459 pr_debug("%s: DSM function mask %#x\n", 460 mmc_hostname(mmc), intel_host->dsm_fns); 461 462 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 463 intel_host->drv_strength = err ? 0 : val; 464 465 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 466 intel_host->d3_retune = err ? true : !!val; 467 } 468 469 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 470 { 471 u8 reg; 472 473 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 474 reg |= 0x10; 475 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 476 /* For eMMC, minimum is 1us but give it 9us for good measure */ 477 udelay(9); 478 reg &= ~0x10; 479 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 480 /* For eMMC, minimum is 200us but give it 300us for good measure */ 481 usleep_range(300, 1000); 482 } 483 484 static int intel_select_drive_strength(struct mmc_card *card, 485 unsigned int max_dtr, int host_drv, 486 int card_drv, int *drv_type) 487 { 488 struct sdhci_host *host = mmc_priv(card->host); 489 struct sdhci_pci_slot *slot = sdhci_priv(host); 490 struct intel_host *intel_host = sdhci_pci_priv(slot); 491 492 return intel_host->drv_strength; 493 } 494 495 static int bxt_get_cd(struct mmc_host *mmc) 496 { 497 int gpio_cd = mmc_gpio_get_cd(mmc); 498 struct sdhci_host *host = mmc_priv(mmc); 499 unsigned long flags; 500 int ret = 0; 501 502 if (!gpio_cd) 503 return 0; 504 505 spin_lock_irqsave(&host->lock, flags); 506 507 if (host->flags & SDHCI_DEVICE_DEAD) 508 goto out; 509 510 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 511 out: 512 spin_unlock_irqrestore(&host->lock, flags); 513 514 return ret; 515 } 516 517 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 518 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 519 520 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 521 unsigned short vdd) 522 { 523 int cntr; 524 u8 reg; 525 526 sdhci_set_power(host, mode, vdd); 527 528 if (mode == MMC_POWER_OFF) 529 return; 530 531 /* 532 * Bus power might not enable after D3 -> D0 transition due to the 533 * present state not yet having propagated. Retry for up to 2ms. 534 */ 535 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 536 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 537 if (reg & SDHCI_POWER_ON) 538 break; 539 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 540 reg |= SDHCI_POWER_ON; 541 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 542 } 543 } 544 545 #define INTEL_HS400_ES_REG 0x78 546 #define INTEL_HS400_ES_BIT BIT(0) 547 548 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc, 549 struct mmc_ios *ios) 550 { 551 struct sdhci_host *host = mmc_priv(mmc); 552 u32 val; 553 554 val = sdhci_readl(host, INTEL_HS400_ES_REG); 555 if (ios->enhanced_strobe) 556 val |= INTEL_HS400_ES_BIT; 557 else 558 val &= ~INTEL_HS400_ES_BIT; 559 sdhci_writel(host, val, INTEL_HS400_ES_REG); 560 } 561 562 static void sdhci_intel_voltage_switch(struct sdhci_host *host) 563 { 564 struct sdhci_pci_slot *slot = sdhci_priv(host); 565 struct intel_host *intel_host = sdhci_pci_priv(slot); 566 struct device *dev = &slot->chip->pdev->dev; 567 u32 result = 0; 568 int err; 569 570 err = intel_dsm(intel_host, dev, INTEL_DSM_V18_SWITCH, &result); 571 pr_debug("%s: %s DSM error %d result %u\n", 572 mmc_hostname(host->mmc), __func__, err, result); 573 } 574 575 static const struct sdhci_ops sdhci_intel_byt_ops = { 576 .set_clock = sdhci_set_clock, 577 .set_power = sdhci_intel_set_power, 578 .enable_dma = sdhci_pci_enable_dma, 579 .set_bus_width = sdhci_set_bus_width, 580 .reset = sdhci_reset, 581 .set_uhs_signaling = sdhci_set_uhs_signaling, 582 .hw_reset = sdhci_pci_hw_reset, 583 .voltage_switch = sdhci_intel_voltage_switch, 584 }; 585 586 static void byt_read_dsm(struct sdhci_pci_slot *slot) 587 { 588 struct intel_host *intel_host = sdhci_pci_priv(slot); 589 struct device *dev = &slot->chip->pdev->dev; 590 struct mmc_host *mmc = slot->host->mmc; 591 592 intel_dsm_init(intel_host, dev, mmc); 593 slot->chip->rpm_retune = intel_host->d3_retune; 594 } 595 596 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 597 { 598 byt_read_dsm(slot); 599 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 600 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 601 MMC_CAP_CMD_DURING_TFR | 602 MMC_CAP_WAIT_WHILE_BUSY; 603 slot->hw_reset = sdhci_pci_int_hw_reset; 604 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 605 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 606 slot->host->mmc_host_ops.select_drive_strength = 607 intel_select_drive_strength; 608 return 0; 609 } 610 611 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot) 612 { 613 int ret = byt_emmc_probe_slot(slot); 614 615 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) { 616 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES, 617 slot->host->mmc_host_ops.hs400_enhanced_strobe = 618 intel_hs400_enhanced_strobe; 619 } 620 621 return ret; 622 } 623 624 #ifdef CONFIG_ACPI 625 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 626 { 627 acpi_status status; 628 unsigned long long max_freq; 629 630 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 631 "MXFQ", NULL, &max_freq); 632 if (ACPI_FAILURE(status)) { 633 dev_err(&slot->chip->pdev->dev, 634 "MXFQ not found in acpi table\n"); 635 return -EINVAL; 636 } 637 638 slot->host->mmc->f_max = max_freq * 1000000; 639 640 return 0; 641 } 642 #else 643 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 644 { 645 return 0; 646 } 647 #endif 648 649 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 650 { 651 int err; 652 653 byt_read_dsm(slot); 654 655 err = ni_set_max_freq(slot); 656 if (err) 657 return err; 658 659 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 660 MMC_CAP_WAIT_WHILE_BUSY; 661 return 0; 662 } 663 664 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 665 { 666 byt_read_dsm(slot); 667 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 668 MMC_CAP_WAIT_WHILE_BUSY; 669 return 0; 670 } 671 672 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 673 { 674 byt_read_dsm(slot); 675 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | 676 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE; 677 slot->cd_idx = 0; 678 slot->cd_override_level = true; 679 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 680 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 681 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 682 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) 683 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 684 685 return 0; 686 } 687 688 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 689 .allow_runtime_pm = true, 690 .probe_slot = byt_emmc_probe_slot, 691 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 692 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 693 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 694 SDHCI_QUIRK2_STOP_WITH_TC, 695 .ops = &sdhci_intel_byt_ops, 696 .priv_size = sizeof(struct intel_host), 697 }; 698 699 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = { 700 .allow_runtime_pm = true, 701 .probe_slot = glk_emmc_probe_slot, 702 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 703 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 704 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 705 SDHCI_QUIRK2_STOP_WITH_TC, 706 .ops = &sdhci_intel_byt_ops, 707 .priv_size = sizeof(struct intel_host), 708 }; 709 710 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 711 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 712 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 713 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 714 .allow_runtime_pm = true, 715 .probe_slot = ni_byt_sdio_probe_slot, 716 .ops = &sdhci_intel_byt_ops, 717 .priv_size = sizeof(struct intel_host), 718 }; 719 720 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 721 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 722 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 723 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 724 .allow_runtime_pm = true, 725 .probe_slot = byt_sdio_probe_slot, 726 .ops = &sdhci_intel_byt_ops, 727 .priv_size = sizeof(struct intel_host), 728 }; 729 730 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 731 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 732 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 733 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 734 SDHCI_QUIRK2_STOP_WITH_TC, 735 .allow_runtime_pm = true, 736 .own_cd_for_runtime_pm = true, 737 .probe_slot = byt_sd_probe_slot, 738 .ops = &sdhci_intel_byt_ops, 739 .priv_size = sizeof(struct intel_host), 740 }; 741 742 /* Define Host controllers for Intel Merrifield platform */ 743 #define INTEL_MRFLD_EMMC_0 0 744 #define INTEL_MRFLD_EMMC_1 1 745 #define INTEL_MRFLD_SD 2 746 #define INTEL_MRFLD_SDIO 3 747 748 #ifdef CONFIG_ACPI 749 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) 750 { 751 struct acpi_device *device, *child; 752 753 device = ACPI_COMPANION(&slot->chip->pdev->dev); 754 if (!device) 755 return; 756 757 acpi_device_fix_up_power(device); 758 list_for_each_entry(child, &device->children, node) 759 if (child->status.present && child->status.enabled) 760 acpi_device_fix_up_power(child); 761 } 762 #else 763 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {} 764 #endif 765 766 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 767 { 768 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 769 770 switch (func) { 771 case INTEL_MRFLD_EMMC_0: 772 case INTEL_MRFLD_EMMC_1: 773 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 774 MMC_CAP_8_BIT_DATA | 775 MMC_CAP_1_8V_DDR; 776 break; 777 case INTEL_MRFLD_SD: 778 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 779 break; 780 case INTEL_MRFLD_SDIO: 781 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 782 MMC_CAP_POWER_OFF_CARD; 783 break; 784 default: 785 return -ENODEV; 786 } 787 788 intel_mrfld_mmc_fix_up_power_slot(slot); 789 return 0; 790 } 791 792 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 793 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 794 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 795 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 796 .allow_runtime_pm = true, 797 .probe_slot = intel_mrfld_mmc_probe_slot, 798 }; 799 800 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 801 { 802 u8 scratch; 803 int ret; 804 805 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 806 if (ret) 807 return ret; 808 809 /* 810 * Turn PMOS on [bit 0], set over current detection to 2.4 V 811 * [bit 1:2] and enable over current debouncing [bit 6]. 812 */ 813 if (on) 814 scratch |= 0x47; 815 else 816 scratch &= ~0x47; 817 818 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 819 } 820 821 static int jmicron_probe(struct sdhci_pci_chip *chip) 822 { 823 int ret; 824 u16 mmcdev = 0; 825 826 if (chip->pdev->revision == 0) { 827 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 828 SDHCI_QUIRK_32BIT_DMA_SIZE | 829 SDHCI_QUIRK_32BIT_ADMA_SIZE | 830 SDHCI_QUIRK_RESET_AFTER_REQUEST | 831 SDHCI_QUIRK_BROKEN_SMALL_PIO; 832 } 833 834 /* 835 * JMicron chips can have two interfaces to the same hardware 836 * in order to work around limitations in Microsoft's driver. 837 * We need to make sure we only bind to one of them. 838 * 839 * This code assumes two things: 840 * 841 * 1. The PCI code adds subfunctions in order. 842 * 843 * 2. The MMC interface has a lower subfunction number 844 * than the SD interface. 845 */ 846 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 847 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 848 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 849 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 850 851 if (mmcdev) { 852 struct pci_dev *sd_dev; 853 854 sd_dev = NULL; 855 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 856 mmcdev, sd_dev)) != NULL) { 857 if ((PCI_SLOT(chip->pdev->devfn) == 858 PCI_SLOT(sd_dev->devfn)) && 859 (chip->pdev->bus == sd_dev->bus)) 860 break; 861 } 862 863 if (sd_dev) { 864 pci_dev_put(sd_dev); 865 dev_info(&chip->pdev->dev, "Refusing to bind to " 866 "secondary interface.\n"); 867 return -ENODEV; 868 } 869 } 870 871 /* 872 * JMicron chips need a bit of a nudge to enable the power 873 * output pins. 874 */ 875 ret = jmicron_pmos(chip, 1); 876 if (ret) { 877 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 878 return ret; 879 } 880 881 /* quirk for unsable RO-detection on JM388 chips */ 882 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 883 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 884 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 885 886 return 0; 887 } 888 889 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 890 { 891 u8 scratch; 892 893 scratch = readb(host->ioaddr + 0xC0); 894 895 if (on) 896 scratch |= 0x01; 897 else 898 scratch &= ~0x01; 899 900 writeb(scratch, host->ioaddr + 0xC0); 901 } 902 903 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 904 { 905 if (slot->chip->pdev->revision == 0) { 906 u16 version; 907 908 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 909 version = (version & SDHCI_VENDOR_VER_MASK) >> 910 SDHCI_VENDOR_VER_SHIFT; 911 912 /* 913 * Older versions of the chip have lots of nasty glitches 914 * in the ADMA engine. It's best just to avoid it 915 * completely. 916 */ 917 if (version < 0xAC) 918 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 919 } 920 921 /* JM388 MMC doesn't support 1.8V while SD supports it */ 922 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 923 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 924 MMC_VDD_29_30 | MMC_VDD_30_31 | 925 MMC_VDD_165_195; /* allow 1.8V */ 926 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 927 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 928 } 929 930 /* 931 * The secondary interface requires a bit set to get the 932 * interrupts. 933 */ 934 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 935 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 936 jmicron_enable_mmc(slot->host, 1); 937 938 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 939 940 return 0; 941 } 942 943 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 944 { 945 if (dead) 946 return; 947 948 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 949 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 950 jmicron_enable_mmc(slot->host, 0); 951 } 952 953 #ifdef CONFIG_PM_SLEEP 954 static int jmicron_suspend(struct sdhci_pci_chip *chip) 955 { 956 int i, ret; 957 958 ret = __sdhci_pci_suspend_host(chip); 959 if (ret) 960 return ret; 961 962 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 963 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 964 for (i = 0; i < chip->num_slots; i++) 965 jmicron_enable_mmc(chip->slots[i]->host, 0); 966 } 967 968 sdhci_pci_init_wakeup(chip); 969 970 return 0; 971 } 972 973 static int jmicron_resume(struct sdhci_pci_chip *chip) 974 { 975 int ret, i; 976 977 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 978 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 979 for (i = 0; i < chip->num_slots; i++) 980 jmicron_enable_mmc(chip->slots[i]->host, 1); 981 } 982 983 ret = jmicron_pmos(chip, 1); 984 if (ret) { 985 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 986 return ret; 987 } 988 989 return sdhci_pci_resume_host(chip); 990 } 991 #endif 992 993 static const struct sdhci_pci_fixes sdhci_o2 = { 994 .probe = sdhci_pci_o2_probe, 995 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 996 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 997 .probe_slot = sdhci_pci_o2_probe_slot, 998 #ifdef CONFIG_PM_SLEEP 999 .resume = sdhci_pci_o2_resume, 1000 #endif 1001 }; 1002 1003 static const struct sdhci_pci_fixes sdhci_jmicron = { 1004 .probe = jmicron_probe, 1005 1006 .probe_slot = jmicron_probe_slot, 1007 .remove_slot = jmicron_remove_slot, 1008 1009 #ifdef CONFIG_PM_SLEEP 1010 .suspend = jmicron_suspend, 1011 .resume = jmicron_resume, 1012 #endif 1013 }; 1014 1015 /* SysKonnect CardBus2SDIO extra registers */ 1016 #define SYSKT_CTRL 0x200 1017 #define SYSKT_RDFIFO_STAT 0x204 1018 #define SYSKT_WRFIFO_STAT 0x208 1019 #define SYSKT_POWER_DATA 0x20c 1020 #define SYSKT_POWER_330 0xef 1021 #define SYSKT_POWER_300 0xf8 1022 #define SYSKT_POWER_184 0xcc 1023 #define SYSKT_POWER_CMD 0x20d 1024 #define SYSKT_POWER_START (1 << 7) 1025 #define SYSKT_POWER_STATUS 0x20e 1026 #define SYSKT_POWER_STATUS_OK (1 << 0) 1027 #define SYSKT_BOARD_REV 0x210 1028 #define SYSKT_CHIP_REV 0x211 1029 #define SYSKT_CONF_DATA 0x212 1030 #define SYSKT_CONF_DATA_1V8 (1 << 2) 1031 #define SYSKT_CONF_DATA_2V5 (1 << 1) 1032 #define SYSKT_CONF_DATA_3V3 (1 << 0) 1033 1034 static int syskt_probe(struct sdhci_pci_chip *chip) 1035 { 1036 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1037 chip->pdev->class &= ~0x0000FF; 1038 chip->pdev->class |= PCI_SDHCI_IFDMA; 1039 } 1040 return 0; 1041 } 1042 1043 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 1044 { 1045 int tm, ps; 1046 1047 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 1048 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 1049 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 1050 "board rev %d.%d, chip rev %d.%d\n", 1051 board_rev >> 4, board_rev & 0xf, 1052 chip_rev >> 4, chip_rev & 0xf); 1053 if (chip_rev >= 0x20) 1054 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 1055 1056 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 1057 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 1058 udelay(50); 1059 tm = 10; /* Wait max 1 ms */ 1060 do { 1061 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 1062 if (ps & SYSKT_POWER_STATUS_OK) 1063 break; 1064 udelay(100); 1065 } while (--tm); 1066 if (!tm) { 1067 dev_err(&slot->chip->pdev->dev, 1068 "power regulator never stabilized"); 1069 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 1070 return -ENODEV; 1071 } 1072 1073 return 0; 1074 } 1075 1076 static const struct sdhci_pci_fixes sdhci_syskt = { 1077 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 1078 .probe = syskt_probe, 1079 .probe_slot = syskt_probe_slot, 1080 }; 1081 1082 static int via_probe(struct sdhci_pci_chip *chip) 1083 { 1084 if (chip->pdev->revision == 0x10) 1085 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 1086 1087 return 0; 1088 } 1089 1090 static const struct sdhci_pci_fixes sdhci_via = { 1091 .probe = via_probe, 1092 }; 1093 1094 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 1095 { 1096 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 1097 return 0; 1098 } 1099 1100 static const struct sdhci_pci_fixes sdhci_rtsx = { 1101 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1102 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 1103 SDHCI_QUIRK2_BROKEN_DDR50, 1104 .probe_slot = rtsx_probe_slot, 1105 }; 1106 1107 /*AMD chipset generation*/ 1108 enum amd_chipset_gen { 1109 AMD_CHIPSET_BEFORE_ML, 1110 AMD_CHIPSET_CZ, 1111 AMD_CHIPSET_NL, 1112 AMD_CHIPSET_UNKNOWN, 1113 }; 1114 1115 /* AMD registers */ 1116 #define AMD_SD_AUTO_PATTERN 0xB8 1117 #define AMD_MSLEEP_DURATION 4 1118 #define AMD_SD_MISC_CONTROL 0xD0 1119 #define AMD_MAX_TUNE_VALUE 0x0B 1120 #define AMD_AUTO_TUNE_SEL 0x10800 1121 #define AMD_FIFO_PTR 0x30 1122 #define AMD_BIT_MASK 0x1F 1123 1124 static void amd_tuning_reset(struct sdhci_host *host) 1125 { 1126 unsigned int val; 1127 1128 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1129 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 1130 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1131 1132 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1133 val &= ~SDHCI_CTRL_EXEC_TUNING; 1134 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1135 } 1136 1137 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 1138 { 1139 unsigned int val; 1140 1141 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 1142 val &= ~AMD_BIT_MASK; 1143 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 1144 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 1145 } 1146 1147 static void amd_enable_manual_tuning(struct pci_dev *pdev) 1148 { 1149 unsigned int val; 1150 1151 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 1152 val |= AMD_FIFO_PTR; 1153 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 1154 } 1155 1156 static int amd_execute_tuning(struct sdhci_host *host, u32 opcode) 1157 { 1158 struct sdhci_pci_slot *slot = sdhci_priv(host); 1159 struct pci_dev *pdev = slot->chip->pdev; 1160 u8 valid_win = 0; 1161 u8 valid_win_max = 0; 1162 u8 valid_win_end = 0; 1163 u8 ctrl, tune_around; 1164 1165 amd_tuning_reset(host); 1166 1167 for (tune_around = 0; tune_around < 12; tune_around++) { 1168 amd_config_tuning_phase(pdev, tune_around); 1169 1170 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1171 valid_win = 0; 1172 msleep(AMD_MSLEEP_DURATION); 1173 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 1174 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 1175 } else if (++valid_win > valid_win_max) { 1176 valid_win_max = valid_win; 1177 valid_win_end = tune_around; 1178 } 1179 } 1180 1181 if (!valid_win_max) { 1182 dev_err(&pdev->dev, "no tuning point found\n"); 1183 return -EIO; 1184 } 1185 1186 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 1187 1188 amd_enable_manual_tuning(pdev); 1189 1190 host->mmc->retune_period = 0; 1191 1192 return 0; 1193 } 1194 1195 static int amd_probe(struct sdhci_pci_chip *chip) 1196 { 1197 struct pci_dev *smbus_dev; 1198 enum amd_chipset_gen gen; 1199 1200 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1201 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 1202 if (smbus_dev) { 1203 gen = AMD_CHIPSET_BEFORE_ML; 1204 } else { 1205 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1206 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1207 if (smbus_dev) { 1208 if (smbus_dev->revision < 0x51) 1209 gen = AMD_CHIPSET_CZ; 1210 else 1211 gen = AMD_CHIPSET_NL; 1212 } else { 1213 gen = AMD_CHIPSET_UNKNOWN; 1214 } 1215 } 1216 1217 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1218 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1219 1220 return 0; 1221 } 1222 1223 static const struct sdhci_ops amd_sdhci_pci_ops = { 1224 .set_clock = sdhci_set_clock, 1225 .enable_dma = sdhci_pci_enable_dma, 1226 .set_bus_width = sdhci_set_bus_width, 1227 .reset = sdhci_reset, 1228 .set_uhs_signaling = sdhci_set_uhs_signaling, 1229 .platform_execute_tuning = amd_execute_tuning, 1230 }; 1231 1232 static const struct sdhci_pci_fixes sdhci_amd = { 1233 .probe = amd_probe, 1234 .ops = &amd_sdhci_pci_ops, 1235 }; 1236 1237 static const struct pci_device_id pci_ids[] = { 1238 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh), 1239 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc), 1240 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc), 1241 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc), 1242 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712), 1243 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712), 1244 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714), 1245 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714), 1246 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe), 1247 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron), 1248 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron), 1249 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron), 1250 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron), 1251 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt), 1252 SDHCI_PCI_DEVICE(VIA, 95D0, via), 1253 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx), 1254 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk), 1255 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0), 1256 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2), 1257 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2), 1258 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd), 1259 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio), 1260 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio), 1261 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc), 1262 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc), 1263 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio), 1264 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio), 1265 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc), 1266 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio), 1267 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio), 1268 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd), 1269 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc), 1270 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc), 1271 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio), 1272 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd), 1273 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd), 1274 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio), 1275 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio), 1276 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc), 1277 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc), 1278 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc), 1279 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc), 1280 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio), 1281 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd), 1282 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc), 1283 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc), 1284 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc), 1285 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio), 1286 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd), 1287 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc), 1288 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio), 1289 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd), 1290 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc), 1291 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio), 1292 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd), 1293 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc), 1294 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio), 1295 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd), 1296 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc), 1297 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd), 1298 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd), 1299 SDHCI_PCI_DEVICE(O2, 8120, o2), 1300 SDHCI_PCI_DEVICE(O2, 8220, o2), 1301 SDHCI_PCI_DEVICE(O2, 8221, o2), 1302 SDHCI_PCI_DEVICE(O2, 8320, o2), 1303 SDHCI_PCI_DEVICE(O2, 8321, o2), 1304 SDHCI_PCI_DEVICE(O2, FUJIN2, o2), 1305 SDHCI_PCI_DEVICE(O2, SDS0, o2), 1306 SDHCI_PCI_DEVICE(O2, SDS1, o2), 1307 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2), 1308 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), 1309 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), 1310 /* Generic SD host controller */ 1311 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, 1312 { /* end: all zeroes */ }, 1313 }; 1314 1315 MODULE_DEVICE_TABLE(pci, pci_ids); 1316 1317 /*****************************************************************************\ 1318 * * 1319 * SDHCI core callbacks * 1320 * * 1321 \*****************************************************************************/ 1322 1323 static int sdhci_pci_enable_dma(struct sdhci_host *host) 1324 { 1325 struct sdhci_pci_slot *slot; 1326 struct pci_dev *pdev; 1327 1328 slot = sdhci_priv(host); 1329 pdev = slot->chip->pdev; 1330 1331 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1332 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1333 (host->flags & SDHCI_USE_SDMA)) { 1334 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1335 "doesn't fully claim to support it.\n"); 1336 } 1337 1338 pci_set_master(pdev); 1339 1340 return 0; 1341 } 1342 1343 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1344 { 1345 struct sdhci_pci_slot *slot = sdhci_priv(host); 1346 int rst_n_gpio = slot->rst_n_gpio; 1347 1348 if (!gpio_is_valid(rst_n_gpio)) 1349 return; 1350 gpio_set_value_cansleep(rst_n_gpio, 0); 1351 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1352 udelay(10); 1353 gpio_set_value_cansleep(rst_n_gpio, 1); 1354 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1355 usleep_range(300, 1000); 1356 } 1357 1358 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1359 { 1360 struct sdhci_pci_slot *slot = sdhci_priv(host); 1361 1362 if (slot->hw_reset) 1363 slot->hw_reset(host); 1364 } 1365 1366 static const struct sdhci_ops sdhci_pci_ops = { 1367 .set_clock = sdhci_set_clock, 1368 .enable_dma = sdhci_pci_enable_dma, 1369 .set_bus_width = sdhci_set_bus_width, 1370 .reset = sdhci_reset, 1371 .set_uhs_signaling = sdhci_set_uhs_signaling, 1372 .hw_reset = sdhci_pci_hw_reset, 1373 }; 1374 1375 /*****************************************************************************\ 1376 * * 1377 * Suspend/resume * 1378 * * 1379 \*****************************************************************************/ 1380 1381 #ifdef CONFIG_PM_SLEEP 1382 static int sdhci_pci_suspend(struct device *dev) 1383 { 1384 struct pci_dev *pdev = to_pci_dev(dev); 1385 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1386 1387 if (!chip) 1388 return 0; 1389 1390 if (chip->fixes && chip->fixes->suspend) 1391 return chip->fixes->suspend(chip); 1392 1393 return sdhci_pci_suspend_host(chip); 1394 } 1395 1396 static int sdhci_pci_resume(struct device *dev) 1397 { 1398 struct pci_dev *pdev = to_pci_dev(dev); 1399 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1400 1401 if (!chip) 1402 return 0; 1403 1404 if (chip->fixes && chip->fixes->resume) 1405 return chip->fixes->resume(chip); 1406 1407 return sdhci_pci_resume_host(chip); 1408 } 1409 #endif 1410 1411 #ifdef CONFIG_PM 1412 static int sdhci_pci_runtime_suspend(struct device *dev) 1413 { 1414 struct pci_dev *pdev = to_pci_dev(dev); 1415 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1416 1417 if (!chip) 1418 return 0; 1419 1420 if (chip->fixes && chip->fixes->runtime_suspend) 1421 return chip->fixes->runtime_suspend(chip); 1422 1423 return sdhci_pci_runtime_suspend_host(chip); 1424 } 1425 1426 static int sdhci_pci_runtime_resume(struct device *dev) 1427 { 1428 struct pci_dev *pdev = to_pci_dev(dev); 1429 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1430 1431 if (!chip) 1432 return 0; 1433 1434 if (chip->fixes && chip->fixes->runtime_resume) 1435 return chip->fixes->runtime_resume(chip); 1436 1437 return sdhci_pci_runtime_resume_host(chip); 1438 } 1439 #endif 1440 1441 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1442 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1443 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1444 sdhci_pci_runtime_resume, NULL) 1445 }; 1446 1447 /*****************************************************************************\ 1448 * * 1449 * Device probing/removal * 1450 * * 1451 \*****************************************************************************/ 1452 1453 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1454 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1455 int slotno) 1456 { 1457 struct sdhci_pci_slot *slot; 1458 struct sdhci_host *host; 1459 int ret, bar = first_bar + slotno; 1460 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 1461 1462 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1463 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1464 return ERR_PTR(-ENODEV); 1465 } 1466 1467 if (pci_resource_len(pdev, bar) < 0x100) { 1468 dev_err(&pdev->dev, "Invalid iomem size. You may " 1469 "experience problems.\n"); 1470 } 1471 1472 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1473 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1474 return ERR_PTR(-ENODEV); 1475 } 1476 1477 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1478 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1479 return ERR_PTR(-ENODEV); 1480 } 1481 1482 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 1483 if (IS_ERR(host)) { 1484 dev_err(&pdev->dev, "cannot allocate host\n"); 1485 return ERR_CAST(host); 1486 } 1487 1488 slot = sdhci_priv(host); 1489 1490 slot->chip = chip; 1491 slot->host = host; 1492 slot->rst_n_gpio = -EINVAL; 1493 slot->cd_gpio = -EINVAL; 1494 slot->cd_idx = -1; 1495 1496 /* Retrieve platform data if there is any */ 1497 if (*sdhci_pci_get_data) 1498 slot->data = sdhci_pci_get_data(pdev, slotno); 1499 1500 if (slot->data) { 1501 if (slot->data->setup) { 1502 ret = slot->data->setup(slot->data); 1503 if (ret) { 1504 dev_err(&pdev->dev, "platform setup failed\n"); 1505 goto free; 1506 } 1507 } 1508 slot->rst_n_gpio = slot->data->rst_n_gpio; 1509 slot->cd_gpio = slot->data->cd_gpio; 1510 } 1511 1512 host->hw_name = "PCI"; 1513 host->ops = chip->fixes && chip->fixes->ops ? 1514 chip->fixes->ops : 1515 &sdhci_pci_ops; 1516 host->quirks = chip->quirks; 1517 host->quirks2 = chip->quirks2; 1518 1519 host->irq = pdev->irq; 1520 1521 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1522 if (ret) { 1523 dev_err(&pdev->dev, "cannot request region\n"); 1524 goto cleanup; 1525 } 1526 1527 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1528 1529 if (chip->fixes && chip->fixes->probe_slot) { 1530 ret = chip->fixes->probe_slot(slot); 1531 if (ret) 1532 goto cleanup; 1533 } 1534 1535 if (gpio_is_valid(slot->rst_n_gpio)) { 1536 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1537 gpio_direction_output(slot->rst_n_gpio, 1); 1538 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1539 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1540 } else { 1541 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1542 slot->rst_n_gpio = -EINVAL; 1543 } 1544 } 1545 1546 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; 1547 host->mmc->slotno = slotno; 1548 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1549 1550 if (slot->cd_idx >= 0) { 1551 ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx, 1552 slot->cd_override_level, 0, NULL); 1553 if (ret == -EPROBE_DEFER) 1554 goto remove; 1555 1556 if (ret) { 1557 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 1558 slot->cd_idx = -1; 1559 } 1560 } 1561 1562 if (chip->fixes && chip->fixes->add_host) 1563 ret = chip->fixes->add_host(slot); 1564 else 1565 ret = sdhci_add_host(host); 1566 if (ret) 1567 goto remove; 1568 1569 sdhci_pci_add_own_cd(slot); 1570 1571 /* 1572 * Check if the chip needs a separate GPIO for card detect to wake up 1573 * from runtime suspend. If it is not there, don't allow runtime PM. 1574 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 1575 */ 1576 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 1577 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 1578 chip->allow_runtime_pm = false; 1579 1580 return slot; 1581 1582 remove: 1583 if (chip->fixes && chip->fixes->remove_slot) 1584 chip->fixes->remove_slot(slot, 0); 1585 1586 cleanup: 1587 if (slot->data && slot->data->cleanup) 1588 slot->data->cleanup(slot->data); 1589 1590 free: 1591 sdhci_free_host(host); 1592 1593 return ERR_PTR(ret); 1594 } 1595 1596 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 1597 { 1598 int dead; 1599 u32 scratch; 1600 1601 sdhci_pci_remove_own_cd(slot); 1602 1603 dead = 0; 1604 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 1605 if (scratch == (u32)-1) 1606 dead = 1; 1607 1608 sdhci_remove_host(slot->host, dead); 1609 1610 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 1611 slot->chip->fixes->remove_slot(slot, dead); 1612 1613 if (slot->data && slot->data->cleanup) 1614 slot->data->cleanup(slot->data); 1615 1616 sdhci_free_host(slot->host); 1617 } 1618 1619 static void sdhci_pci_runtime_pm_allow(struct device *dev) 1620 { 1621 pm_suspend_ignore_children(dev, 1); 1622 pm_runtime_set_autosuspend_delay(dev, 50); 1623 pm_runtime_use_autosuspend(dev); 1624 pm_runtime_allow(dev); 1625 /* Stay active until mmc core scans for a card */ 1626 pm_runtime_put_noidle(dev); 1627 } 1628 1629 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 1630 { 1631 pm_runtime_forbid(dev); 1632 pm_runtime_get_noresume(dev); 1633 } 1634 1635 static int sdhci_pci_probe(struct pci_dev *pdev, 1636 const struct pci_device_id *ent) 1637 { 1638 struct sdhci_pci_chip *chip; 1639 struct sdhci_pci_slot *slot; 1640 1641 u8 slots, first_bar; 1642 int ret, i; 1643 1644 BUG_ON(pdev == NULL); 1645 BUG_ON(ent == NULL); 1646 1647 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 1648 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 1649 1650 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 1651 if (ret) 1652 return ret; 1653 1654 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 1655 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 1656 if (slots == 0) 1657 return -ENODEV; 1658 1659 BUG_ON(slots > MAX_SLOTS); 1660 1661 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 1662 if (ret) 1663 return ret; 1664 1665 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 1666 1667 if (first_bar > 5) { 1668 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 1669 return -ENODEV; 1670 } 1671 1672 ret = pcim_enable_device(pdev); 1673 if (ret) 1674 return ret; 1675 1676 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 1677 if (!chip) 1678 return -ENOMEM; 1679 1680 chip->pdev = pdev; 1681 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 1682 if (chip->fixes) { 1683 chip->quirks = chip->fixes->quirks; 1684 chip->quirks2 = chip->fixes->quirks2; 1685 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 1686 } 1687 chip->num_slots = slots; 1688 chip->pm_retune = true; 1689 chip->rpm_retune = true; 1690 1691 pci_set_drvdata(pdev, chip); 1692 1693 if (chip->fixes && chip->fixes->probe) { 1694 ret = chip->fixes->probe(chip); 1695 if (ret) 1696 return ret; 1697 } 1698 1699 slots = chip->num_slots; /* Quirk may have changed this */ 1700 1701 for (i = 0; i < slots; i++) { 1702 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 1703 if (IS_ERR(slot)) { 1704 for (i--; i >= 0; i--) 1705 sdhci_pci_remove_slot(chip->slots[i]); 1706 return PTR_ERR(slot); 1707 } 1708 1709 chip->slots[i] = slot; 1710 } 1711 1712 if (chip->allow_runtime_pm) 1713 sdhci_pci_runtime_pm_allow(&pdev->dev); 1714 1715 return 0; 1716 } 1717 1718 static void sdhci_pci_remove(struct pci_dev *pdev) 1719 { 1720 int i; 1721 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1722 1723 if (chip->allow_runtime_pm) 1724 sdhci_pci_runtime_pm_forbid(&pdev->dev); 1725 1726 for (i = 0; i < chip->num_slots; i++) 1727 sdhci_pci_remove_slot(chip->slots[i]); 1728 } 1729 1730 static struct pci_driver sdhci_driver = { 1731 .name = "sdhci-pci", 1732 .id_table = pci_ids, 1733 .probe = sdhci_pci_probe, 1734 .remove = sdhci_pci_remove, 1735 .driver = { 1736 .pm = &sdhci_pci_pm_ops 1737 }, 1738 }; 1739 1740 module_pci_driver(sdhci_driver); 1741 1742 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 1743 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 1744 MODULE_LICENSE("GPL"); 1745