1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 2 * 3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 * 10 * Thanks to the following companies for their support: 11 * 12 * - JMicron (hardware and technical support) 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/highmem.h> 17 #include <linux/module.h> 18 #include <linux/pci.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/slab.h> 21 #include <linux/device.h> 22 #include <linux/mmc/host.h> 23 #include <linux/mmc/mmc.h> 24 #include <linux/scatterlist.h> 25 #include <linux/io.h> 26 #include <linux/gpio.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/mmc/slot-gpio.h> 29 #include <linux/mmc/sdhci-pci-data.h> 30 31 #include "sdhci.h" 32 #include "sdhci-pci.h" 33 #include "sdhci-pci-o2micro.h" 34 35 /*****************************************************************************\ 36 * * 37 * Hardware specific quirk handling * 38 * * 39 \*****************************************************************************/ 40 41 static int ricoh_probe(struct sdhci_pci_chip *chip) 42 { 43 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 44 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 45 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 46 return 0; 47 } 48 49 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 50 { 51 slot->host->caps = 52 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 53 & SDHCI_TIMEOUT_CLK_MASK) | 54 55 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 56 & SDHCI_CLOCK_BASE_MASK) | 57 58 SDHCI_TIMEOUT_CLK_UNIT | 59 SDHCI_CAN_VDD_330 | 60 SDHCI_CAN_DO_HISPD | 61 SDHCI_CAN_DO_SDMA; 62 return 0; 63 } 64 65 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 66 { 67 /* Apply a delay to allow controller to settle */ 68 /* Otherwise it becomes confused if card state changed 69 during suspend */ 70 msleep(500); 71 return 0; 72 } 73 74 static const struct sdhci_pci_fixes sdhci_ricoh = { 75 .probe = ricoh_probe, 76 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 77 SDHCI_QUIRK_FORCE_DMA | 78 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 79 }; 80 81 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 82 .probe_slot = ricoh_mmc_probe_slot, 83 .resume = ricoh_mmc_resume, 84 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 85 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 86 SDHCI_QUIRK_NO_CARD_NO_RESET | 87 SDHCI_QUIRK_MISSING_CAPS 88 }; 89 90 static const struct sdhci_pci_fixes sdhci_ene_712 = { 91 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 92 SDHCI_QUIRK_BROKEN_DMA, 93 }; 94 95 static const struct sdhci_pci_fixes sdhci_ene_714 = { 96 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 97 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 98 SDHCI_QUIRK_BROKEN_DMA, 99 }; 100 101 static const struct sdhci_pci_fixes sdhci_cafe = { 102 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 103 SDHCI_QUIRK_NO_BUSY_IRQ | 104 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 105 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 106 }; 107 108 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 109 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 110 }; 111 112 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 113 { 114 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 115 return 0; 116 } 117 118 /* 119 * ADMA operation is disabled for Moorestown platform due to 120 * hardware bugs. 121 */ 122 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 123 { 124 /* 125 * slots number is fixed here for MRST as SDIO3/5 are never used and 126 * have hardware bugs. 127 */ 128 chip->num_slots = 1; 129 return 0; 130 } 131 132 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 133 { 134 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 135 return 0; 136 } 137 138 #ifdef CONFIG_PM 139 140 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 141 { 142 struct sdhci_pci_slot *slot = dev_id; 143 struct sdhci_host *host = slot->host; 144 145 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 146 return IRQ_HANDLED; 147 } 148 149 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 150 { 151 int err, irq, gpio = slot->cd_gpio; 152 153 slot->cd_gpio = -EINVAL; 154 slot->cd_irq = -EINVAL; 155 156 if (!gpio_is_valid(gpio)) 157 return; 158 159 err = gpio_request(gpio, "sd_cd"); 160 if (err < 0) 161 goto out; 162 163 err = gpio_direction_input(gpio); 164 if (err < 0) 165 goto out_free; 166 167 irq = gpio_to_irq(gpio); 168 if (irq < 0) 169 goto out_free; 170 171 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 172 IRQF_TRIGGER_FALLING, "sd_cd", slot); 173 if (err) 174 goto out_free; 175 176 slot->cd_gpio = gpio; 177 slot->cd_irq = irq; 178 179 return; 180 181 out_free: 182 gpio_free(gpio); 183 out: 184 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 185 } 186 187 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 188 { 189 if (slot->cd_irq >= 0) 190 free_irq(slot->cd_irq, slot); 191 if (gpio_is_valid(slot->cd_gpio)) 192 gpio_free(slot->cd_gpio); 193 } 194 195 #else 196 197 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 198 { 199 } 200 201 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 202 { 203 } 204 205 #endif 206 207 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 208 { 209 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 210 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC | 211 MMC_CAP2_HC_ERASE_SZ; 212 return 0; 213 } 214 215 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 216 { 217 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 218 return 0; 219 } 220 221 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 222 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 223 .probe_slot = mrst_hc_probe_slot, 224 }; 225 226 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 227 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 228 .probe = mrst_hc_probe, 229 }; 230 231 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 232 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 233 .allow_runtime_pm = true, 234 .own_cd_for_runtime_pm = true, 235 }; 236 237 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 238 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 239 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 240 .allow_runtime_pm = true, 241 .probe_slot = mfd_sdio_probe_slot, 242 }; 243 244 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 245 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 246 .allow_runtime_pm = true, 247 .probe_slot = mfd_emmc_probe_slot, 248 }; 249 250 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 251 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 252 .probe_slot = pch_hc_probe_slot, 253 }; 254 255 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 256 { 257 u8 reg; 258 259 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 260 reg |= 0x10; 261 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 262 /* For eMMC, minimum is 1us but give it 9us for good measure */ 263 udelay(9); 264 reg &= ~0x10; 265 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 266 /* For eMMC, minimum is 200us but give it 300us for good measure */ 267 usleep_range(300, 1000); 268 } 269 270 static int spt_select_drive_strength(struct sdhci_host *host, 271 struct mmc_card *card, 272 unsigned int max_dtr, 273 int host_drv, int card_drv, int *drv_type) 274 { 275 int drive_strength; 276 277 if (sdhci_pci_spt_drive_strength > 0) 278 drive_strength = sdhci_pci_spt_drive_strength & 0xf; 279 else 280 drive_strength = 1; /* 33-ohm */ 281 282 if ((mmc_driver_type_mask(drive_strength) & card_drv) == 0) 283 drive_strength = 0; /* Default 50-ohm */ 284 285 return drive_strength; 286 } 287 288 /* Try to read the drive strength from the card */ 289 static void spt_read_drive_strength(struct sdhci_host *host) 290 { 291 u32 val, i, t; 292 u16 m; 293 294 if (sdhci_pci_spt_drive_strength) 295 return; 296 297 sdhci_pci_spt_drive_strength = -1; 298 299 m = sdhci_readw(host, SDHCI_HOST_CONTROL2) & 0x7; 300 if (m != 3 && m != 5) 301 return; 302 val = sdhci_readl(host, SDHCI_PRESENT_STATE); 303 if (val & 0x3) 304 return; 305 sdhci_writel(host, 0x007f0023, SDHCI_INT_ENABLE); 306 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 307 sdhci_writew(host, 0x10, SDHCI_TRANSFER_MODE); 308 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 309 sdhci_writew(host, 512, SDHCI_BLOCK_SIZE); 310 sdhci_writew(host, 1, SDHCI_BLOCK_COUNT); 311 sdhci_writel(host, 0, SDHCI_ARGUMENT); 312 sdhci_writew(host, 0x83b, SDHCI_COMMAND); 313 for (i = 0; i < 1000; i++) { 314 val = sdhci_readl(host, SDHCI_INT_STATUS); 315 if (val & 0xffff8000) 316 return; 317 if (val & 0x20) 318 break; 319 udelay(1); 320 } 321 val = sdhci_readl(host, SDHCI_PRESENT_STATE); 322 if (!(val & 0x800)) 323 return; 324 for (i = 0; i < 47; i++) 325 val = sdhci_readl(host, SDHCI_BUFFER); 326 t = val & 0xf00; 327 if (t != 0x200 && t != 0x300) 328 return; 329 330 sdhci_pci_spt_drive_strength = 0x10 | ((val >> 12) & 0xf); 331 } 332 333 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 334 { 335 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 336 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 337 MMC_CAP_BUS_WIDTH_TEST | 338 MMC_CAP_WAIT_WHILE_BUSY; 339 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ; 340 slot->hw_reset = sdhci_pci_int_hw_reset; 341 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 342 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 343 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_SPT_EMMC) { 344 spt_read_drive_strength(slot->host); 345 slot->select_drive_strength = spt_select_drive_strength; 346 } 347 return 0; 348 } 349 350 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 351 { 352 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 353 MMC_CAP_BUS_WIDTH_TEST | 354 MMC_CAP_WAIT_WHILE_BUSY; 355 return 0; 356 } 357 358 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 359 { 360 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST | 361 MMC_CAP_WAIT_WHILE_BUSY; 362 slot->cd_con_id = NULL; 363 slot->cd_idx = 0; 364 slot->cd_override_level = true; 365 return 0; 366 } 367 368 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 369 .allow_runtime_pm = true, 370 .probe_slot = byt_emmc_probe_slot, 371 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 372 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 373 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 374 SDHCI_QUIRK2_STOP_WITH_TC, 375 }; 376 377 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 378 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 379 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 380 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 381 .allow_runtime_pm = true, 382 .probe_slot = byt_sdio_probe_slot, 383 }; 384 385 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 386 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 387 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 388 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 389 SDHCI_QUIRK2_STOP_WITH_TC, 390 .allow_runtime_pm = true, 391 .own_cd_for_runtime_pm = true, 392 .probe_slot = byt_sd_probe_slot, 393 }; 394 395 /* Define Host controllers for Intel Merrifield platform */ 396 #define INTEL_MRFL_EMMC_0 0 397 #define INTEL_MRFL_EMMC_1 1 398 399 static int intel_mrfl_mmc_probe_slot(struct sdhci_pci_slot *slot) 400 { 401 if ((PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_0) && 402 (PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_1)) 403 /* SD support is not ready yet */ 404 return -ENODEV; 405 406 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 407 MMC_CAP_1_8V_DDR; 408 409 return 0; 410 } 411 412 static const struct sdhci_pci_fixes sdhci_intel_mrfl_mmc = { 413 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 414 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 415 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 416 .allow_runtime_pm = true, 417 .probe_slot = intel_mrfl_mmc_probe_slot, 418 }; 419 420 /* O2Micro extra registers */ 421 #define O2_SD_LOCK_WP 0xD3 422 #define O2_SD_MULTI_VCC3V 0xEE 423 #define O2_SD_CLKREQ 0xEC 424 #define O2_SD_CAPS 0xE0 425 #define O2_SD_ADMA1 0xE2 426 #define O2_SD_ADMA2 0xE7 427 #define O2_SD_INF_MOD 0xF1 428 429 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 430 { 431 u8 scratch; 432 int ret; 433 434 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 435 if (ret) 436 return ret; 437 438 /* 439 * Turn PMOS on [bit 0], set over current detection to 2.4 V 440 * [bit 1:2] and enable over current debouncing [bit 6]. 441 */ 442 if (on) 443 scratch |= 0x47; 444 else 445 scratch &= ~0x47; 446 447 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch); 448 if (ret) 449 return ret; 450 451 return 0; 452 } 453 454 static int jmicron_probe(struct sdhci_pci_chip *chip) 455 { 456 int ret; 457 u16 mmcdev = 0; 458 459 if (chip->pdev->revision == 0) { 460 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 461 SDHCI_QUIRK_32BIT_DMA_SIZE | 462 SDHCI_QUIRK_32BIT_ADMA_SIZE | 463 SDHCI_QUIRK_RESET_AFTER_REQUEST | 464 SDHCI_QUIRK_BROKEN_SMALL_PIO; 465 } 466 467 /* 468 * JMicron chips can have two interfaces to the same hardware 469 * in order to work around limitations in Microsoft's driver. 470 * We need to make sure we only bind to one of them. 471 * 472 * This code assumes two things: 473 * 474 * 1. The PCI code adds subfunctions in order. 475 * 476 * 2. The MMC interface has a lower subfunction number 477 * than the SD interface. 478 */ 479 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 480 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 481 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 482 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 483 484 if (mmcdev) { 485 struct pci_dev *sd_dev; 486 487 sd_dev = NULL; 488 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 489 mmcdev, sd_dev)) != NULL) { 490 if ((PCI_SLOT(chip->pdev->devfn) == 491 PCI_SLOT(sd_dev->devfn)) && 492 (chip->pdev->bus == sd_dev->bus)) 493 break; 494 } 495 496 if (sd_dev) { 497 pci_dev_put(sd_dev); 498 dev_info(&chip->pdev->dev, "Refusing to bind to " 499 "secondary interface.\n"); 500 return -ENODEV; 501 } 502 } 503 504 /* 505 * JMicron chips need a bit of a nudge to enable the power 506 * output pins. 507 */ 508 ret = jmicron_pmos(chip, 1); 509 if (ret) { 510 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 511 return ret; 512 } 513 514 /* quirk for unsable RO-detection on JM388 chips */ 515 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 516 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 517 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 518 519 return 0; 520 } 521 522 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 523 { 524 u8 scratch; 525 526 scratch = readb(host->ioaddr + 0xC0); 527 528 if (on) 529 scratch |= 0x01; 530 else 531 scratch &= ~0x01; 532 533 writeb(scratch, host->ioaddr + 0xC0); 534 } 535 536 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 537 { 538 if (slot->chip->pdev->revision == 0) { 539 u16 version; 540 541 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 542 version = (version & SDHCI_VENDOR_VER_MASK) >> 543 SDHCI_VENDOR_VER_SHIFT; 544 545 /* 546 * Older versions of the chip have lots of nasty glitches 547 * in the ADMA engine. It's best just to avoid it 548 * completely. 549 */ 550 if (version < 0xAC) 551 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 552 } 553 554 /* JM388 MMC doesn't support 1.8V while SD supports it */ 555 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 556 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 557 MMC_VDD_29_30 | MMC_VDD_30_31 | 558 MMC_VDD_165_195; /* allow 1.8V */ 559 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 560 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 561 } 562 563 /* 564 * The secondary interface requires a bit set to get the 565 * interrupts. 566 */ 567 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 568 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 569 jmicron_enable_mmc(slot->host, 1); 570 571 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 572 573 return 0; 574 } 575 576 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 577 { 578 if (dead) 579 return; 580 581 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 582 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 583 jmicron_enable_mmc(slot->host, 0); 584 } 585 586 static int jmicron_suspend(struct sdhci_pci_chip *chip) 587 { 588 int i; 589 590 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 591 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 592 for (i = 0; i < chip->num_slots; i++) 593 jmicron_enable_mmc(chip->slots[i]->host, 0); 594 } 595 596 return 0; 597 } 598 599 static int jmicron_resume(struct sdhci_pci_chip *chip) 600 { 601 int ret, i; 602 603 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 604 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 605 for (i = 0; i < chip->num_slots; i++) 606 jmicron_enable_mmc(chip->slots[i]->host, 1); 607 } 608 609 ret = jmicron_pmos(chip, 1); 610 if (ret) { 611 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 612 return ret; 613 } 614 615 return 0; 616 } 617 618 static const struct sdhci_pci_fixes sdhci_o2 = { 619 .probe = sdhci_pci_o2_probe, 620 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 621 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 622 .probe_slot = sdhci_pci_o2_probe_slot, 623 .resume = sdhci_pci_o2_resume, 624 }; 625 626 static const struct sdhci_pci_fixes sdhci_jmicron = { 627 .probe = jmicron_probe, 628 629 .probe_slot = jmicron_probe_slot, 630 .remove_slot = jmicron_remove_slot, 631 632 .suspend = jmicron_suspend, 633 .resume = jmicron_resume, 634 }; 635 636 /* SysKonnect CardBus2SDIO extra registers */ 637 #define SYSKT_CTRL 0x200 638 #define SYSKT_RDFIFO_STAT 0x204 639 #define SYSKT_WRFIFO_STAT 0x208 640 #define SYSKT_POWER_DATA 0x20c 641 #define SYSKT_POWER_330 0xef 642 #define SYSKT_POWER_300 0xf8 643 #define SYSKT_POWER_184 0xcc 644 #define SYSKT_POWER_CMD 0x20d 645 #define SYSKT_POWER_START (1 << 7) 646 #define SYSKT_POWER_STATUS 0x20e 647 #define SYSKT_POWER_STATUS_OK (1 << 0) 648 #define SYSKT_BOARD_REV 0x210 649 #define SYSKT_CHIP_REV 0x211 650 #define SYSKT_CONF_DATA 0x212 651 #define SYSKT_CONF_DATA_1V8 (1 << 2) 652 #define SYSKT_CONF_DATA_2V5 (1 << 1) 653 #define SYSKT_CONF_DATA_3V3 (1 << 0) 654 655 static int syskt_probe(struct sdhci_pci_chip *chip) 656 { 657 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 658 chip->pdev->class &= ~0x0000FF; 659 chip->pdev->class |= PCI_SDHCI_IFDMA; 660 } 661 return 0; 662 } 663 664 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 665 { 666 int tm, ps; 667 668 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 669 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 670 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 671 "board rev %d.%d, chip rev %d.%d\n", 672 board_rev >> 4, board_rev & 0xf, 673 chip_rev >> 4, chip_rev & 0xf); 674 if (chip_rev >= 0x20) 675 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 676 677 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 678 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 679 udelay(50); 680 tm = 10; /* Wait max 1 ms */ 681 do { 682 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 683 if (ps & SYSKT_POWER_STATUS_OK) 684 break; 685 udelay(100); 686 } while (--tm); 687 if (!tm) { 688 dev_err(&slot->chip->pdev->dev, 689 "power regulator never stabilized"); 690 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 691 return -ENODEV; 692 } 693 694 return 0; 695 } 696 697 static const struct sdhci_pci_fixes sdhci_syskt = { 698 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 699 .probe = syskt_probe, 700 .probe_slot = syskt_probe_slot, 701 }; 702 703 static int via_probe(struct sdhci_pci_chip *chip) 704 { 705 if (chip->pdev->revision == 0x10) 706 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 707 708 return 0; 709 } 710 711 static const struct sdhci_pci_fixes sdhci_via = { 712 .probe = via_probe, 713 }; 714 715 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 716 { 717 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 718 return 0; 719 } 720 721 static const struct sdhci_pci_fixes sdhci_rtsx = { 722 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 723 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 724 SDHCI_QUIRK2_BROKEN_DDR50, 725 .probe_slot = rtsx_probe_slot, 726 }; 727 728 /*AMD chipset generation*/ 729 enum amd_chipset_gen { 730 AMD_CHIPSET_BEFORE_ML, 731 AMD_CHIPSET_CZ, 732 AMD_CHIPSET_NL, 733 AMD_CHIPSET_UNKNOWN, 734 }; 735 736 static int amd_probe(struct sdhci_pci_chip *chip) 737 { 738 struct pci_dev *smbus_dev; 739 enum amd_chipset_gen gen; 740 741 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 742 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 743 if (smbus_dev) { 744 gen = AMD_CHIPSET_BEFORE_ML; 745 } else { 746 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 747 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 748 if (smbus_dev) { 749 if (smbus_dev->revision < 0x51) 750 gen = AMD_CHIPSET_CZ; 751 else 752 gen = AMD_CHIPSET_NL; 753 } else { 754 gen = AMD_CHIPSET_UNKNOWN; 755 } 756 } 757 758 if ((gen == AMD_CHIPSET_BEFORE_ML) || (gen == AMD_CHIPSET_CZ)) { 759 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 760 chip->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 761 } 762 763 return 0; 764 } 765 766 static const struct sdhci_pci_fixes sdhci_amd = { 767 .probe = amd_probe, 768 }; 769 770 static const struct pci_device_id pci_ids[] = { 771 { 772 .vendor = PCI_VENDOR_ID_RICOH, 773 .device = PCI_DEVICE_ID_RICOH_R5C822, 774 .subvendor = PCI_ANY_ID, 775 .subdevice = PCI_ANY_ID, 776 .driver_data = (kernel_ulong_t)&sdhci_ricoh, 777 }, 778 779 { 780 .vendor = PCI_VENDOR_ID_RICOH, 781 .device = 0x843, 782 .subvendor = PCI_ANY_ID, 783 .subdevice = PCI_ANY_ID, 784 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 785 }, 786 787 { 788 .vendor = PCI_VENDOR_ID_RICOH, 789 .device = 0xe822, 790 .subvendor = PCI_ANY_ID, 791 .subdevice = PCI_ANY_ID, 792 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 793 }, 794 795 { 796 .vendor = PCI_VENDOR_ID_RICOH, 797 .device = 0xe823, 798 .subvendor = PCI_ANY_ID, 799 .subdevice = PCI_ANY_ID, 800 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 801 }, 802 803 { 804 .vendor = PCI_VENDOR_ID_ENE, 805 .device = PCI_DEVICE_ID_ENE_CB712_SD, 806 .subvendor = PCI_ANY_ID, 807 .subdevice = PCI_ANY_ID, 808 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 809 }, 810 811 { 812 .vendor = PCI_VENDOR_ID_ENE, 813 .device = PCI_DEVICE_ID_ENE_CB712_SD_2, 814 .subvendor = PCI_ANY_ID, 815 .subdevice = PCI_ANY_ID, 816 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 817 }, 818 819 { 820 .vendor = PCI_VENDOR_ID_ENE, 821 .device = PCI_DEVICE_ID_ENE_CB714_SD, 822 .subvendor = PCI_ANY_ID, 823 .subdevice = PCI_ANY_ID, 824 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 825 }, 826 827 { 828 .vendor = PCI_VENDOR_ID_ENE, 829 .device = PCI_DEVICE_ID_ENE_CB714_SD_2, 830 .subvendor = PCI_ANY_ID, 831 .subdevice = PCI_ANY_ID, 832 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 833 }, 834 835 { 836 .vendor = PCI_VENDOR_ID_MARVELL, 837 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD, 838 .subvendor = PCI_ANY_ID, 839 .subdevice = PCI_ANY_ID, 840 .driver_data = (kernel_ulong_t)&sdhci_cafe, 841 }, 842 843 { 844 .vendor = PCI_VENDOR_ID_JMICRON, 845 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD, 846 .subvendor = PCI_ANY_ID, 847 .subdevice = PCI_ANY_ID, 848 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 849 }, 850 851 { 852 .vendor = PCI_VENDOR_ID_JMICRON, 853 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC, 854 .subvendor = PCI_ANY_ID, 855 .subdevice = PCI_ANY_ID, 856 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 857 }, 858 859 { 860 .vendor = PCI_VENDOR_ID_JMICRON, 861 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD, 862 .subvendor = PCI_ANY_ID, 863 .subdevice = PCI_ANY_ID, 864 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 865 }, 866 867 { 868 .vendor = PCI_VENDOR_ID_JMICRON, 869 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD, 870 .subvendor = PCI_ANY_ID, 871 .subdevice = PCI_ANY_ID, 872 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 873 }, 874 875 { 876 .vendor = PCI_VENDOR_ID_SYSKONNECT, 877 .device = 0x8000, 878 .subvendor = PCI_ANY_ID, 879 .subdevice = PCI_ANY_ID, 880 .driver_data = (kernel_ulong_t)&sdhci_syskt, 881 }, 882 883 { 884 .vendor = PCI_VENDOR_ID_VIA, 885 .device = 0x95d0, 886 .subvendor = PCI_ANY_ID, 887 .subdevice = PCI_ANY_ID, 888 .driver_data = (kernel_ulong_t)&sdhci_via, 889 }, 890 891 { 892 .vendor = PCI_VENDOR_ID_REALTEK, 893 .device = 0x5250, 894 .subvendor = PCI_ANY_ID, 895 .subdevice = PCI_ANY_ID, 896 .driver_data = (kernel_ulong_t)&sdhci_rtsx, 897 }, 898 899 { 900 .vendor = PCI_VENDOR_ID_INTEL, 901 .device = PCI_DEVICE_ID_INTEL_QRK_SD, 902 .subvendor = PCI_ANY_ID, 903 .subdevice = PCI_ANY_ID, 904 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk, 905 }, 906 907 { 908 .vendor = PCI_VENDOR_ID_INTEL, 909 .device = PCI_DEVICE_ID_INTEL_MRST_SD0, 910 .subvendor = PCI_ANY_ID, 911 .subdevice = PCI_ANY_ID, 912 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0, 913 }, 914 915 { 916 .vendor = PCI_VENDOR_ID_INTEL, 917 .device = PCI_DEVICE_ID_INTEL_MRST_SD1, 918 .subvendor = PCI_ANY_ID, 919 .subdevice = PCI_ANY_ID, 920 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 921 }, 922 923 { 924 .vendor = PCI_VENDOR_ID_INTEL, 925 .device = PCI_DEVICE_ID_INTEL_MRST_SD2, 926 .subvendor = PCI_ANY_ID, 927 .subdevice = PCI_ANY_ID, 928 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 929 }, 930 931 { 932 .vendor = PCI_VENDOR_ID_INTEL, 933 .device = PCI_DEVICE_ID_INTEL_MFD_SD, 934 .subvendor = PCI_ANY_ID, 935 .subdevice = PCI_ANY_ID, 936 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 937 }, 938 939 { 940 .vendor = PCI_VENDOR_ID_INTEL, 941 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1, 942 .subvendor = PCI_ANY_ID, 943 .subdevice = PCI_ANY_ID, 944 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 945 }, 946 947 { 948 .vendor = PCI_VENDOR_ID_INTEL, 949 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2, 950 .subvendor = PCI_ANY_ID, 951 .subdevice = PCI_ANY_ID, 952 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 953 }, 954 955 { 956 .vendor = PCI_VENDOR_ID_INTEL, 957 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0, 958 .subvendor = PCI_ANY_ID, 959 .subdevice = PCI_ANY_ID, 960 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 961 }, 962 963 { 964 .vendor = PCI_VENDOR_ID_INTEL, 965 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1, 966 .subvendor = PCI_ANY_ID, 967 .subdevice = PCI_ANY_ID, 968 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 969 }, 970 971 { 972 .vendor = PCI_VENDOR_ID_INTEL, 973 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0, 974 .subvendor = PCI_ANY_ID, 975 .subdevice = PCI_ANY_ID, 976 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 977 }, 978 979 { 980 .vendor = PCI_VENDOR_ID_INTEL, 981 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1, 982 .subvendor = PCI_ANY_ID, 983 .subdevice = PCI_ANY_ID, 984 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 985 }, 986 987 { 988 .vendor = PCI_VENDOR_ID_INTEL, 989 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC, 990 .subvendor = PCI_ANY_ID, 991 .subdevice = PCI_ANY_ID, 992 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 993 }, 994 995 { 996 .vendor = PCI_VENDOR_ID_INTEL, 997 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, 998 .subvendor = PCI_ANY_ID, 999 .subdevice = PCI_ANY_ID, 1000 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1001 }, 1002 1003 { 1004 .vendor = PCI_VENDOR_ID_INTEL, 1005 .device = PCI_DEVICE_ID_INTEL_BYT_SD, 1006 .subvendor = PCI_ANY_ID, 1007 .subdevice = PCI_ANY_ID, 1008 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1009 }, 1010 1011 { 1012 .vendor = PCI_VENDOR_ID_INTEL, 1013 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2, 1014 .subvendor = PCI_ANY_ID, 1015 .subdevice = PCI_ANY_ID, 1016 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1017 }, 1018 1019 { 1020 .vendor = PCI_VENDOR_ID_INTEL, 1021 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC, 1022 .subvendor = PCI_ANY_ID, 1023 .subdevice = PCI_ANY_ID, 1024 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1025 }, 1026 1027 { 1028 .vendor = PCI_VENDOR_ID_INTEL, 1029 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO, 1030 .subvendor = PCI_ANY_ID, 1031 .subdevice = PCI_ANY_ID, 1032 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1033 }, 1034 1035 { 1036 .vendor = PCI_VENDOR_ID_INTEL, 1037 .device = PCI_DEVICE_ID_INTEL_BSW_SD, 1038 .subvendor = PCI_ANY_ID, 1039 .subdevice = PCI_ANY_ID, 1040 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1041 }, 1042 1043 { 1044 .vendor = PCI_VENDOR_ID_INTEL, 1045 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0, 1046 .subvendor = PCI_ANY_ID, 1047 .subdevice = PCI_ANY_ID, 1048 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1049 }, 1050 1051 { 1052 .vendor = PCI_VENDOR_ID_INTEL, 1053 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1, 1054 .subvendor = PCI_ANY_ID, 1055 .subdevice = PCI_ANY_ID, 1056 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1057 }, 1058 1059 { 1060 .vendor = PCI_VENDOR_ID_INTEL, 1061 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2, 1062 .subvendor = PCI_ANY_ID, 1063 .subdevice = PCI_ANY_ID, 1064 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1065 }, 1066 1067 { 1068 .vendor = PCI_VENDOR_ID_INTEL, 1069 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0, 1070 .subvendor = PCI_ANY_ID, 1071 .subdevice = PCI_ANY_ID, 1072 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1073 }, 1074 1075 { 1076 .vendor = PCI_VENDOR_ID_INTEL, 1077 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1, 1078 .subvendor = PCI_ANY_ID, 1079 .subdevice = PCI_ANY_ID, 1080 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1081 }, 1082 1083 { 1084 .vendor = PCI_VENDOR_ID_INTEL, 1085 .device = PCI_DEVICE_ID_INTEL_MRFL_MMC, 1086 .subvendor = PCI_ANY_ID, 1087 .subdevice = PCI_ANY_ID, 1088 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfl_mmc, 1089 }, 1090 1091 { 1092 .vendor = PCI_VENDOR_ID_INTEL, 1093 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC, 1094 .subvendor = PCI_ANY_ID, 1095 .subdevice = PCI_ANY_ID, 1096 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1097 }, 1098 1099 { 1100 .vendor = PCI_VENDOR_ID_INTEL, 1101 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO, 1102 .subvendor = PCI_ANY_ID, 1103 .subdevice = PCI_ANY_ID, 1104 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1105 }, 1106 1107 { 1108 .vendor = PCI_VENDOR_ID_INTEL, 1109 .device = PCI_DEVICE_ID_INTEL_SPT_SD, 1110 .subvendor = PCI_ANY_ID, 1111 .subdevice = PCI_ANY_ID, 1112 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1113 }, 1114 1115 { 1116 .vendor = PCI_VENDOR_ID_O2, 1117 .device = PCI_DEVICE_ID_O2_8120, 1118 .subvendor = PCI_ANY_ID, 1119 .subdevice = PCI_ANY_ID, 1120 .driver_data = (kernel_ulong_t)&sdhci_o2, 1121 }, 1122 1123 { 1124 .vendor = PCI_VENDOR_ID_O2, 1125 .device = PCI_DEVICE_ID_O2_8220, 1126 .subvendor = PCI_ANY_ID, 1127 .subdevice = PCI_ANY_ID, 1128 .driver_data = (kernel_ulong_t)&sdhci_o2, 1129 }, 1130 1131 { 1132 .vendor = PCI_VENDOR_ID_O2, 1133 .device = PCI_DEVICE_ID_O2_8221, 1134 .subvendor = PCI_ANY_ID, 1135 .subdevice = PCI_ANY_ID, 1136 .driver_data = (kernel_ulong_t)&sdhci_o2, 1137 }, 1138 1139 { 1140 .vendor = PCI_VENDOR_ID_O2, 1141 .device = PCI_DEVICE_ID_O2_8320, 1142 .subvendor = PCI_ANY_ID, 1143 .subdevice = PCI_ANY_ID, 1144 .driver_data = (kernel_ulong_t)&sdhci_o2, 1145 }, 1146 1147 { 1148 .vendor = PCI_VENDOR_ID_O2, 1149 .device = PCI_DEVICE_ID_O2_8321, 1150 .subvendor = PCI_ANY_ID, 1151 .subdevice = PCI_ANY_ID, 1152 .driver_data = (kernel_ulong_t)&sdhci_o2, 1153 }, 1154 1155 { 1156 .vendor = PCI_VENDOR_ID_O2, 1157 .device = PCI_DEVICE_ID_O2_FUJIN2, 1158 .subvendor = PCI_ANY_ID, 1159 .subdevice = PCI_ANY_ID, 1160 .driver_data = (kernel_ulong_t)&sdhci_o2, 1161 }, 1162 1163 { 1164 .vendor = PCI_VENDOR_ID_O2, 1165 .device = PCI_DEVICE_ID_O2_SDS0, 1166 .subvendor = PCI_ANY_ID, 1167 .subdevice = PCI_ANY_ID, 1168 .driver_data = (kernel_ulong_t)&sdhci_o2, 1169 }, 1170 1171 { 1172 .vendor = PCI_VENDOR_ID_O2, 1173 .device = PCI_DEVICE_ID_O2_SDS1, 1174 .subvendor = PCI_ANY_ID, 1175 .subdevice = PCI_ANY_ID, 1176 .driver_data = (kernel_ulong_t)&sdhci_o2, 1177 }, 1178 1179 { 1180 .vendor = PCI_VENDOR_ID_O2, 1181 .device = PCI_DEVICE_ID_O2_SEABIRD0, 1182 .subvendor = PCI_ANY_ID, 1183 .subdevice = PCI_ANY_ID, 1184 .driver_data = (kernel_ulong_t)&sdhci_o2, 1185 }, 1186 1187 { 1188 .vendor = PCI_VENDOR_ID_O2, 1189 .device = PCI_DEVICE_ID_O2_SEABIRD1, 1190 .subvendor = PCI_ANY_ID, 1191 .subdevice = PCI_ANY_ID, 1192 .driver_data = (kernel_ulong_t)&sdhci_o2, 1193 }, 1194 { 1195 .vendor = PCI_VENDOR_ID_AMD, 1196 .device = PCI_ANY_ID, 1197 .class = PCI_CLASS_SYSTEM_SDHCI << 8, 1198 .class_mask = 0xFFFF00, 1199 .subvendor = PCI_ANY_ID, 1200 .subdevice = PCI_ANY_ID, 1201 .driver_data = (kernel_ulong_t)&sdhci_amd, 1202 }, 1203 { /* Generic SD host controller */ 1204 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) 1205 }, 1206 1207 { /* end: all zeroes */ }, 1208 }; 1209 1210 MODULE_DEVICE_TABLE(pci, pci_ids); 1211 1212 /*****************************************************************************\ 1213 * * 1214 * SDHCI core callbacks * 1215 * * 1216 \*****************************************************************************/ 1217 1218 static int sdhci_pci_enable_dma(struct sdhci_host *host) 1219 { 1220 struct sdhci_pci_slot *slot; 1221 struct pci_dev *pdev; 1222 int ret = -1; 1223 1224 slot = sdhci_priv(host); 1225 pdev = slot->chip->pdev; 1226 1227 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1228 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1229 (host->flags & SDHCI_USE_SDMA)) { 1230 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1231 "doesn't fully claim to support it.\n"); 1232 } 1233 1234 if (host->flags & SDHCI_USE_64_BIT_DMA) { 1235 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA) { 1236 host->flags &= ~SDHCI_USE_64_BIT_DMA; 1237 } else { 1238 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 1239 if (ret) 1240 dev_warn(&pdev->dev, "Failed to set 64-bit DMA mask\n"); 1241 } 1242 } 1243 if (ret) 1244 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 1245 if (ret) 1246 return ret; 1247 1248 pci_set_master(pdev); 1249 1250 return 0; 1251 } 1252 1253 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width) 1254 { 1255 u8 ctrl; 1256 1257 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1258 1259 switch (width) { 1260 case MMC_BUS_WIDTH_8: 1261 ctrl |= SDHCI_CTRL_8BITBUS; 1262 ctrl &= ~SDHCI_CTRL_4BITBUS; 1263 break; 1264 case MMC_BUS_WIDTH_4: 1265 ctrl |= SDHCI_CTRL_4BITBUS; 1266 ctrl &= ~SDHCI_CTRL_8BITBUS; 1267 break; 1268 default: 1269 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS); 1270 break; 1271 } 1272 1273 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1274 } 1275 1276 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1277 { 1278 struct sdhci_pci_slot *slot = sdhci_priv(host); 1279 int rst_n_gpio = slot->rst_n_gpio; 1280 1281 if (!gpio_is_valid(rst_n_gpio)) 1282 return; 1283 gpio_set_value_cansleep(rst_n_gpio, 0); 1284 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1285 udelay(10); 1286 gpio_set_value_cansleep(rst_n_gpio, 1); 1287 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1288 usleep_range(300, 1000); 1289 } 1290 1291 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1292 { 1293 struct sdhci_pci_slot *slot = sdhci_priv(host); 1294 1295 if (slot->hw_reset) 1296 slot->hw_reset(host); 1297 } 1298 1299 static int sdhci_pci_select_drive_strength(struct sdhci_host *host, 1300 struct mmc_card *card, 1301 unsigned int max_dtr, int host_drv, 1302 int card_drv, int *drv_type) 1303 { 1304 struct sdhci_pci_slot *slot = sdhci_priv(host); 1305 1306 if (!slot->select_drive_strength) 1307 return 0; 1308 1309 return slot->select_drive_strength(host, card, max_dtr, host_drv, 1310 card_drv, drv_type); 1311 } 1312 1313 static const struct sdhci_ops sdhci_pci_ops = { 1314 .set_clock = sdhci_set_clock, 1315 .enable_dma = sdhci_pci_enable_dma, 1316 .set_bus_width = sdhci_pci_set_bus_width, 1317 .reset = sdhci_reset, 1318 .set_uhs_signaling = sdhci_set_uhs_signaling, 1319 .hw_reset = sdhci_pci_hw_reset, 1320 .select_drive_strength = sdhci_pci_select_drive_strength, 1321 }; 1322 1323 /*****************************************************************************\ 1324 * * 1325 * Suspend/resume * 1326 * * 1327 \*****************************************************************************/ 1328 1329 #ifdef CONFIG_PM 1330 1331 static int sdhci_pci_suspend(struct device *dev) 1332 { 1333 struct pci_dev *pdev = to_pci_dev(dev); 1334 struct sdhci_pci_chip *chip; 1335 struct sdhci_pci_slot *slot; 1336 mmc_pm_flag_t slot_pm_flags; 1337 mmc_pm_flag_t pm_flags = 0; 1338 int i, ret; 1339 1340 chip = pci_get_drvdata(pdev); 1341 if (!chip) 1342 return 0; 1343 1344 for (i = 0; i < chip->num_slots; i++) { 1345 slot = chip->slots[i]; 1346 if (!slot) 1347 continue; 1348 1349 ret = sdhci_suspend_host(slot->host); 1350 1351 if (ret) 1352 goto err_pci_suspend; 1353 1354 slot_pm_flags = slot->host->mmc->pm_flags; 1355 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1356 sdhci_enable_irq_wakeups(slot->host); 1357 1358 pm_flags |= slot_pm_flags; 1359 } 1360 1361 if (chip->fixes && chip->fixes->suspend) { 1362 ret = chip->fixes->suspend(chip); 1363 if (ret) 1364 goto err_pci_suspend; 1365 } 1366 1367 if (pm_flags & MMC_PM_KEEP_POWER) { 1368 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1369 device_init_wakeup(dev, true); 1370 else 1371 device_init_wakeup(dev, false); 1372 } else 1373 device_init_wakeup(dev, false); 1374 1375 return 0; 1376 1377 err_pci_suspend: 1378 while (--i >= 0) 1379 sdhci_resume_host(chip->slots[i]->host); 1380 return ret; 1381 } 1382 1383 static int sdhci_pci_resume(struct device *dev) 1384 { 1385 struct pci_dev *pdev = to_pci_dev(dev); 1386 struct sdhci_pci_chip *chip; 1387 struct sdhci_pci_slot *slot; 1388 int i, ret; 1389 1390 chip = pci_get_drvdata(pdev); 1391 if (!chip) 1392 return 0; 1393 1394 if (chip->fixes && chip->fixes->resume) { 1395 ret = chip->fixes->resume(chip); 1396 if (ret) 1397 return ret; 1398 } 1399 1400 for (i = 0; i < chip->num_slots; i++) { 1401 slot = chip->slots[i]; 1402 if (!slot) 1403 continue; 1404 1405 ret = sdhci_resume_host(slot->host); 1406 if (ret) 1407 return ret; 1408 } 1409 1410 return 0; 1411 } 1412 1413 static int sdhci_pci_runtime_suspend(struct device *dev) 1414 { 1415 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); 1416 struct sdhci_pci_chip *chip; 1417 struct sdhci_pci_slot *slot; 1418 int i, ret; 1419 1420 chip = pci_get_drvdata(pdev); 1421 if (!chip) 1422 return 0; 1423 1424 for (i = 0; i < chip->num_slots; i++) { 1425 slot = chip->slots[i]; 1426 if (!slot) 1427 continue; 1428 1429 ret = sdhci_runtime_suspend_host(slot->host); 1430 1431 if (ret) 1432 goto err_pci_runtime_suspend; 1433 } 1434 1435 if (chip->fixes && chip->fixes->suspend) { 1436 ret = chip->fixes->suspend(chip); 1437 if (ret) 1438 goto err_pci_runtime_suspend; 1439 } 1440 1441 return 0; 1442 1443 err_pci_runtime_suspend: 1444 while (--i >= 0) 1445 sdhci_runtime_resume_host(chip->slots[i]->host); 1446 return ret; 1447 } 1448 1449 static int sdhci_pci_runtime_resume(struct device *dev) 1450 { 1451 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); 1452 struct sdhci_pci_chip *chip; 1453 struct sdhci_pci_slot *slot; 1454 int i, ret; 1455 1456 chip = pci_get_drvdata(pdev); 1457 if (!chip) 1458 return 0; 1459 1460 if (chip->fixes && chip->fixes->resume) { 1461 ret = chip->fixes->resume(chip); 1462 if (ret) 1463 return ret; 1464 } 1465 1466 for (i = 0; i < chip->num_slots; i++) { 1467 slot = chip->slots[i]; 1468 if (!slot) 1469 continue; 1470 1471 ret = sdhci_runtime_resume_host(slot->host); 1472 if (ret) 1473 return ret; 1474 } 1475 1476 return 0; 1477 } 1478 1479 #else /* CONFIG_PM */ 1480 1481 #define sdhci_pci_suspend NULL 1482 #define sdhci_pci_resume NULL 1483 1484 #endif /* CONFIG_PM */ 1485 1486 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1487 .suspend = sdhci_pci_suspend, 1488 .resume = sdhci_pci_resume, 1489 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1490 sdhci_pci_runtime_resume, NULL) 1491 }; 1492 1493 /*****************************************************************************\ 1494 * * 1495 * Device probing/removal * 1496 * * 1497 \*****************************************************************************/ 1498 1499 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1500 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1501 int slotno) 1502 { 1503 struct sdhci_pci_slot *slot; 1504 struct sdhci_host *host; 1505 int ret, bar = first_bar + slotno; 1506 1507 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1508 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1509 return ERR_PTR(-ENODEV); 1510 } 1511 1512 if (pci_resource_len(pdev, bar) < 0x100) { 1513 dev_err(&pdev->dev, "Invalid iomem size. You may " 1514 "experience problems.\n"); 1515 } 1516 1517 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1518 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1519 return ERR_PTR(-ENODEV); 1520 } 1521 1522 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1523 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1524 return ERR_PTR(-ENODEV); 1525 } 1526 1527 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot)); 1528 if (IS_ERR(host)) { 1529 dev_err(&pdev->dev, "cannot allocate host\n"); 1530 return ERR_CAST(host); 1531 } 1532 1533 slot = sdhci_priv(host); 1534 1535 slot->chip = chip; 1536 slot->host = host; 1537 slot->pci_bar = bar; 1538 slot->rst_n_gpio = -EINVAL; 1539 slot->cd_gpio = -EINVAL; 1540 slot->cd_idx = -1; 1541 1542 /* Retrieve platform data if there is any */ 1543 if (*sdhci_pci_get_data) 1544 slot->data = sdhci_pci_get_data(pdev, slotno); 1545 1546 if (slot->data) { 1547 if (slot->data->setup) { 1548 ret = slot->data->setup(slot->data); 1549 if (ret) { 1550 dev_err(&pdev->dev, "platform setup failed\n"); 1551 goto free; 1552 } 1553 } 1554 slot->rst_n_gpio = slot->data->rst_n_gpio; 1555 slot->cd_gpio = slot->data->cd_gpio; 1556 } 1557 1558 host->hw_name = "PCI"; 1559 host->ops = &sdhci_pci_ops; 1560 host->quirks = chip->quirks; 1561 host->quirks2 = chip->quirks2; 1562 1563 host->irq = pdev->irq; 1564 1565 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc)); 1566 if (ret) { 1567 dev_err(&pdev->dev, "cannot request region\n"); 1568 goto cleanup; 1569 } 1570 1571 host->ioaddr = pci_ioremap_bar(pdev, bar); 1572 if (!host->ioaddr) { 1573 dev_err(&pdev->dev, "failed to remap registers\n"); 1574 ret = -ENOMEM; 1575 goto release; 1576 } 1577 1578 if (chip->fixes && chip->fixes->probe_slot) { 1579 ret = chip->fixes->probe_slot(slot); 1580 if (ret) 1581 goto unmap; 1582 } 1583 1584 if (gpio_is_valid(slot->rst_n_gpio)) { 1585 if (!gpio_request(slot->rst_n_gpio, "eMMC_reset")) { 1586 gpio_direction_output(slot->rst_n_gpio, 1); 1587 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1588 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1589 } else { 1590 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1591 slot->rst_n_gpio = -EINVAL; 1592 } 1593 } 1594 1595 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; 1596 host->mmc->slotno = slotno; 1597 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1598 1599 if (slot->cd_idx >= 0 && 1600 mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx, 1601 slot->cd_override_level, 0, NULL)) { 1602 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 1603 slot->cd_idx = -1; 1604 } 1605 1606 ret = sdhci_add_host(host); 1607 if (ret) 1608 goto remove; 1609 1610 sdhci_pci_add_own_cd(slot); 1611 1612 /* 1613 * Check if the chip needs a separate GPIO for card detect to wake up 1614 * from runtime suspend. If it is not there, don't allow runtime PM. 1615 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 1616 */ 1617 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 1618 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 1619 chip->allow_runtime_pm = false; 1620 1621 return slot; 1622 1623 remove: 1624 if (gpio_is_valid(slot->rst_n_gpio)) 1625 gpio_free(slot->rst_n_gpio); 1626 1627 if (chip->fixes && chip->fixes->remove_slot) 1628 chip->fixes->remove_slot(slot, 0); 1629 1630 unmap: 1631 iounmap(host->ioaddr); 1632 1633 release: 1634 pci_release_region(pdev, bar); 1635 1636 cleanup: 1637 if (slot->data && slot->data->cleanup) 1638 slot->data->cleanup(slot->data); 1639 1640 free: 1641 sdhci_free_host(host); 1642 1643 return ERR_PTR(ret); 1644 } 1645 1646 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 1647 { 1648 int dead; 1649 u32 scratch; 1650 1651 sdhci_pci_remove_own_cd(slot); 1652 1653 dead = 0; 1654 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 1655 if (scratch == (u32)-1) 1656 dead = 1; 1657 1658 sdhci_remove_host(slot->host, dead); 1659 1660 if (gpio_is_valid(slot->rst_n_gpio)) 1661 gpio_free(slot->rst_n_gpio); 1662 1663 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 1664 slot->chip->fixes->remove_slot(slot, dead); 1665 1666 if (slot->data && slot->data->cleanup) 1667 slot->data->cleanup(slot->data); 1668 1669 pci_release_region(slot->chip->pdev, slot->pci_bar); 1670 1671 sdhci_free_host(slot->host); 1672 } 1673 1674 static void sdhci_pci_runtime_pm_allow(struct device *dev) 1675 { 1676 pm_runtime_put_noidle(dev); 1677 pm_runtime_allow(dev); 1678 pm_runtime_set_autosuspend_delay(dev, 50); 1679 pm_runtime_use_autosuspend(dev); 1680 pm_suspend_ignore_children(dev, 1); 1681 } 1682 1683 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 1684 { 1685 pm_runtime_forbid(dev); 1686 pm_runtime_get_noresume(dev); 1687 } 1688 1689 static int sdhci_pci_probe(struct pci_dev *pdev, 1690 const struct pci_device_id *ent) 1691 { 1692 struct sdhci_pci_chip *chip; 1693 struct sdhci_pci_slot *slot; 1694 1695 u8 slots, first_bar; 1696 int ret, i; 1697 1698 BUG_ON(pdev == NULL); 1699 BUG_ON(ent == NULL); 1700 1701 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 1702 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 1703 1704 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 1705 if (ret) 1706 return ret; 1707 1708 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 1709 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 1710 if (slots == 0) 1711 return -ENODEV; 1712 1713 BUG_ON(slots > MAX_SLOTS); 1714 1715 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 1716 if (ret) 1717 return ret; 1718 1719 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 1720 1721 if (first_bar > 5) { 1722 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 1723 return -ENODEV; 1724 } 1725 1726 ret = pci_enable_device(pdev); 1727 if (ret) 1728 return ret; 1729 1730 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL); 1731 if (!chip) { 1732 ret = -ENOMEM; 1733 goto err; 1734 } 1735 1736 chip->pdev = pdev; 1737 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 1738 if (chip->fixes) { 1739 chip->quirks = chip->fixes->quirks; 1740 chip->quirks2 = chip->fixes->quirks2; 1741 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 1742 } 1743 chip->num_slots = slots; 1744 1745 pci_set_drvdata(pdev, chip); 1746 1747 if (chip->fixes && chip->fixes->probe) { 1748 ret = chip->fixes->probe(chip); 1749 if (ret) 1750 goto free; 1751 } 1752 1753 slots = chip->num_slots; /* Quirk may have changed this */ 1754 1755 for (i = 0; i < slots; i++) { 1756 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 1757 if (IS_ERR(slot)) { 1758 for (i--; i >= 0; i--) 1759 sdhci_pci_remove_slot(chip->slots[i]); 1760 ret = PTR_ERR(slot); 1761 goto free; 1762 } 1763 1764 chip->slots[i] = slot; 1765 } 1766 1767 if (chip->allow_runtime_pm) 1768 sdhci_pci_runtime_pm_allow(&pdev->dev); 1769 1770 return 0; 1771 1772 free: 1773 pci_set_drvdata(pdev, NULL); 1774 kfree(chip); 1775 1776 err: 1777 pci_disable_device(pdev); 1778 return ret; 1779 } 1780 1781 static void sdhci_pci_remove(struct pci_dev *pdev) 1782 { 1783 int i; 1784 struct sdhci_pci_chip *chip; 1785 1786 chip = pci_get_drvdata(pdev); 1787 1788 if (chip) { 1789 if (chip->allow_runtime_pm) 1790 sdhci_pci_runtime_pm_forbid(&pdev->dev); 1791 1792 for (i = 0; i < chip->num_slots; i++) 1793 sdhci_pci_remove_slot(chip->slots[i]); 1794 1795 pci_set_drvdata(pdev, NULL); 1796 kfree(chip); 1797 } 1798 1799 pci_disable_device(pdev); 1800 } 1801 1802 static struct pci_driver sdhci_driver = { 1803 .name = "sdhci-pci", 1804 .id_table = pci_ids, 1805 .probe = sdhci_pci_probe, 1806 .remove = sdhci_pci_remove, 1807 .driver = { 1808 .pm = &sdhci_pci_pm_ops 1809 }, 1810 }; 1811 1812 module_pci_driver(sdhci_driver); 1813 1814 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 1815 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 1816 MODULE_LICENSE("GPL"); 1817