1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 3 * 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 5 * 6 * Thanks to the following companies for their support: 7 * 8 * - JMicron (hardware and technical support) 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/string.h> 13 #include <linux/delay.h> 14 #include <linux/highmem.h> 15 #include <linux/module.h> 16 #include <linux/pci.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/slab.h> 19 #include <linux/device.h> 20 #include <linux/scatterlist.h> 21 #include <linux/io.h> 22 #include <linux/iopoll.h> 23 #include <linux/gpio.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/pm_qos.h> 26 #include <linux/debugfs.h> 27 #include <linux/acpi.h> 28 #include <linux/dmi.h> 29 30 #include <linux/mmc/host.h> 31 #include <linux/mmc/mmc.h> 32 #include <linux/mmc/slot-gpio.h> 33 34 #ifdef CONFIG_X86 35 #include <asm/iosf_mbi.h> 36 #endif 37 38 #include "cqhci.h" 39 40 #include "sdhci.h" 41 #include "sdhci-pci.h" 42 43 static void sdhci_pci_hw_reset(struct sdhci_host *host); 44 45 #ifdef CONFIG_PM_SLEEP 46 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip) 47 { 48 mmc_pm_flag_t pm_flags = 0; 49 bool cap_cd_wake = false; 50 int i; 51 52 for (i = 0; i < chip->num_slots; i++) { 53 struct sdhci_pci_slot *slot = chip->slots[i]; 54 55 if (slot) { 56 pm_flags |= slot->host->mmc->pm_flags; 57 if (slot->host->mmc->caps & MMC_CAP_CD_WAKE) 58 cap_cd_wake = true; 59 } 60 } 61 62 if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ)) 63 return device_wakeup_enable(&chip->pdev->dev); 64 else if (!cap_cd_wake) 65 return device_wakeup_disable(&chip->pdev->dev); 66 67 return 0; 68 } 69 70 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 71 { 72 int i, ret; 73 74 sdhci_pci_init_wakeup(chip); 75 76 for (i = 0; i < chip->num_slots; i++) { 77 struct sdhci_pci_slot *slot = chip->slots[i]; 78 struct sdhci_host *host; 79 80 if (!slot) 81 continue; 82 83 host = slot->host; 84 85 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 86 mmc_retune_needed(host->mmc); 87 88 ret = sdhci_suspend_host(host); 89 if (ret) 90 goto err_pci_suspend; 91 92 if (device_may_wakeup(&chip->pdev->dev)) 93 mmc_gpio_set_cd_wake(host->mmc, true); 94 } 95 96 return 0; 97 98 err_pci_suspend: 99 while (--i >= 0) 100 sdhci_resume_host(chip->slots[i]->host); 101 return ret; 102 } 103 104 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip) 105 { 106 struct sdhci_pci_slot *slot; 107 int i, ret; 108 109 for (i = 0; i < chip->num_slots; i++) { 110 slot = chip->slots[i]; 111 if (!slot) 112 continue; 113 114 ret = sdhci_resume_host(slot->host); 115 if (ret) 116 return ret; 117 118 mmc_gpio_set_cd_wake(slot->host->mmc, false); 119 } 120 121 return 0; 122 } 123 124 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip) 125 { 126 int ret; 127 128 ret = cqhci_suspend(chip->slots[0]->host->mmc); 129 if (ret) 130 return ret; 131 132 return sdhci_pci_suspend_host(chip); 133 } 134 135 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip) 136 { 137 int ret; 138 139 ret = sdhci_pci_resume_host(chip); 140 if (ret) 141 return ret; 142 143 return cqhci_resume(chip->slots[0]->host->mmc); 144 } 145 #endif 146 147 #ifdef CONFIG_PM 148 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip) 149 { 150 struct sdhci_pci_slot *slot; 151 struct sdhci_host *host; 152 int i, ret; 153 154 for (i = 0; i < chip->num_slots; i++) { 155 slot = chip->slots[i]; 156 if (!slot) 157 continue; 158 159 host = slot->host; 160 161 ret = sdhci_runtime_suspend_host(host); 162 if (ret) 163 goto err_pci_runtime_suspend; 164 165 if (chip->rpm_retune && 166 host->tuning_mode != SDHCI_TUNING_MODE_3) 167 mmc_retune_needed(host->mmc); 168 } 169 170 return 0; 171 172 err_pci_runtime_suspend: 173 while (--i >= 0) 174 sdhci_runtime_resume_host(chip->slots[i]->host, 0); 175 return ret; 176 } 177 178 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip) 179 { 180 struct sdhci_pci_slot *slot; 181 int i, ret; 182 183 for (i = 0; i < chip->num_slots; i++) { 184 slot = chip->slots[i]; 185 if (!slot) 186 continue; 187 188 ret = sdhci_runtime_resume_host(slot->host, 0); 189 if (ret) 190 return ret; 191 } 192 193 return 0; 194 } 195 196 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip) 197 { 198 int ret; 199 200 ret = cqhci_suspend(chip->slots[0]->host->mmc); 201 if (ret) 202 return ret; 203 204 return sdhci_pci_runtime_suspend_host(chip); 205 } 206 207 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip) 208 { 209 int ret; 210 211 ret = sdhci_pci_runtime_resume_host(chip); 212 if (ret) 213 return ret; 214 215 return cqhci_resume(chip->slots[0]->host->mmc); 216 } 217 #endif 218 219 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask) 220 { 221 int cmd_error = 0; 222 int data_error = 0; 223 224 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 225 return intmask; 226 227 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 228 229 return 0; 230 } 231 232 static void sdhci_pci_dumpregs(struct mmc_host *mmc) 233 { 234 sdhci_dumpregs(mmc_priv(mmc)); 235 } 236 237 static void sdhci_cqhci_reset(struct sdhci_host *host, u8 mask) 238 { 239 if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) && 240 host->mmc->cqe_private) 241 cqhci_deactivate(host->mmc); 242 sdhci_reset(host, mask); 243 } 244 245 /*****************************************************************************\ 246 * * 247 * Hardware specific quirk handling * 248 * * 249 \*****************************************************************************/ 250 251 static int ricoh_probe(struct sdhci_pci_chip *chip) 252 { 253 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 254 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 255 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 256 return 0; 257 } 258 259 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 260 { 261 slot->host->caps = 262 FIELD_PREP(SDHCI_TIMEOUT_CLK_MASK, 0x21) | 263 FIELD_PREP(SDHCI_CLOCK_BASE_MASK, 0x21) | 264 SDHCI_TIMEOUT_CLK_UNIT | 265 SDHCI_CAN_VDD_330 | 266 SDHCI_CAN_DO_HISPD | 267 SDHCI_CAN_DO_SDMA; 268 return 0; 269 } 270 271 #ifdef CONFIG_PM_SLEEP 272 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 273 { 274 /* Apply a delay to allow controller to settle */ 275 /* Otherwise it becomes confused if card state changed 276 during suspend */ 277 msleep(500); 278 return sdhci_pci_resume_host(chip); 279 } 280 #endif 281 282 static const struct sdhci_pci_fixes sdhci_ricoh = { 283 .probe = ricoh_probe, 284 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 285 SDHCI_QUIRK_FORCE_DMA | 286 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 287 }; 288 289 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 290 .probe_slot = ricoh_mmc_probe_slot, 291 #ifdef CONFIG_PM_SLEEP 292 .resume = ricoh_mmc_resume, 293 #endif 294 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 295 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 296 SDHCI_QUIRK_NO_CARD_NO_RESET | 297 SDHCI_QUIRK_MISSING_CAPS 298 }; 299 300 static const struct sdhci_pci_fixes sdhci_ene_712 = { 301 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 302 SDHCI_QUIRK_BROKEN_DMA, 303 }; 304 305 static const struct sdhci_pci_fixes sdhci_ene_714 = { 306 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 307 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 308 SDHCI_QUIRK_BROKEN_DMA, 309 }; 310 311 static const struct sdhci_pci_fixes sdhci_cafe = { 312 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 313 SDHCI_QUIRK_NO_BUSY_IRQ | 314 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 315 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 316 }; 317 318 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 319 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 320 }; 321 322 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 323 { 324 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 325 return 0; 326 } 327 328 /* 329 * ADMA operation is disabled for Moorestown platform due to 330 * hardware bugs. 331 */ 332 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 333 { 334 /* 335 * slots number is fixed here for MRST as SDIO3/5 are never used and 336 * have hardware bugs. 337 */ 338 chip->num_slots = 1; 339 return 0; 340 } 341 342 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 343 { 344 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 345 return 0; 346 } 347 348 #ifdef CONFIG_PM 349 350 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 351 { 352 struct sdhci_pci_slot *slot = dev_id; 353 struct sdhci_host *host = slot->host; 354 355 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 356 return IRQ_HANDLED; 357 } 358 359 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 360 { 361 int err, irq, gpio = slot->cd_gpio; 362 363 slot->cd_gpio = -EINVAL; 364 slot->cd_irq = -EINVAL; 365 366 if (!gpio_is_valid(gpio)) 367 return; 368 369 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 370 if (err < 0) 371 goto out; 372 373 err = gpio_direction_input(gpio); 374 if (err < 0) 375 goto out_free; 376 377 irq = gpio_to_irq(gpio); 378 if (irq < 0) 379 goto out_free; 380 381 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 382 IRQF_TRIGGER_FALLING, "sd_cd", slot); 383 if (err) 384 goto out_free; 385 386 slot->cd_gpio = gpio; 387 slot->cd_irq = irq; 388 389 return; 390 391 out_free: 392 devm_gpio_free(&slot->chip->pdev->dev, gpio); 393 out: 394 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 395 } 396 397 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 398 { 399 if (slot->cd_irq >= 0) 400 free_irq(slot->cd_irq, slot); 401 } 402 403 #else 404 405 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 406 { 407 } 408 409 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 410 { 411 } 412 413 #endif 414 415 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 416 { 417 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 418 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC; 419 return 0; 420 } 421 422 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 423 { 424 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 425 return 0; 426 } 427 428 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 429 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 430 .probe_slot = mrst_hc_probe_slot, 431 }; 432 433 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 434 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 435 .probe = mrst_hc_probe, 436 }; 437 438 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 439 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 440 .allow_runtime_pm = true, 441 .own_cd_for_runtime_pm = true, 442 }; 443 444 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 445 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 446 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 447 .allow_runtime_pm = true, 448 .probe_slot = mfd_sdio_probe_slot, 449 }; 450 451 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 452 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 453 .allow_runtime_pm = true, 454 .probe_slot = mfd_emmc_probe_slot, 455 }; 456 457 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 458 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 459 .probe_slot = pch_hc_probe_slot, 460 }; 461 462 #ifdef CONFIG_X86 463 464 #define BYT_IOSF_SCCEP 0x63 465 #define BYT_IOSF_OCP_NETCTRL0 0x1078 466 #define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8) 467 468 static void byt_ocp_setting(struct pci_dev *pdev) 469 { 470 u32 val = 0; 471 472 if (pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC && 473 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SDIO && 474 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SD && 475 pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC2) 476 return; 477 478 if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0, 479 &val)) { 480 dev_err(&pdev->dev, "%s read error\n", __func__); 481 return; 482 } 483 484 if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE)) 485 return; 486 487 val &= ~BYT_IOSF_OCP_TIMEOUT_BASE; 488 489 if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0, 490 val)) { 491 dev_err(&pdev->dev, "%s write error\n", __func__); 492 return; 493 } 494 495 dev_dbg(&pdev->dev, "%s completed\n", __func__); 496 } 497 498 #else 499 500 static inline void byt_ocp_setting(struct pci_dev *pdev) 501 { 502 } 503 504 #endif 505 506 enum { 507 INTEL_DSM_FNS = 0, 508 INTEL_DSM_V18_SWITCH = 3, 509 INTEL_DSM_V33_SWITCH = 4, 510 INTEL_DSM_DRV_STRENGTH = 9, 511 INTEL_DSM_D3_RETUNE = 10, 512 }; 513 514 struct intel_host { 515 u32 dsm_fns; 516 int drv_strength; 517 bool d3_retune; 518 bool rpm_retune_ok; 519 bool needs_pwr_off; 520 u32 glk_rx_ctrl1; 521 u32 glk_tun_val; 522 u32 active_ltr; 523 u32 idle_ltr; 524 }; 525 526 static const guid_t intel_dsm_guid = 527 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F, 528 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61); 529 530 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 531 unsigned int fn, u32 *result) 532 { 533 union acpi_object *obj; 534 int err = 0; 535 size_t len; 536 537 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL); 538 if (!obj) 539 return -EOPNOTSUPP; 540 541 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { 542 err = -EINVAL; 543 goto out; 544 } 545 546 len = min_t(size_t, obj->buffer.length, 4); 547 548 *result = 0; 549 memcpy(result, obj->buffer.pointer, len); 550 out: 551 ACPI_FREE(obj); 552 553 return err; 554 } 555 556 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 557 unsigned int fn, u32 *result) 558 { 559 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 560 return -EOPNOTSUPP; 561 562 return __intel_dsm(intel_host, dev, fn, result); 563 } 564 565 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 566 struct mmc_host *mmc) 567 { 568 int err; 569 u32 val; 570 571 intel_host->d3_retune = true; 572 573 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 574 if (err) { 575 pr_debug("%s: DSM not supported, error %d\n", 576 mmc_hostname(mmc), err); 577 return; 578 } 579 580 pr_debug("%s: DSM function mask %#x\n", 581 mmc_hostname(mmc), intel_host->dsm_fns); 582 583 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 584 intel_host->drv_strength = err ? 0 : val; 585 586 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 587 intel_host->d3_retune = err ? true : !!val; 588 } 589 590 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 591 { 592 u8 reg; 593 594 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 595 reg |= 0x10; 596 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 597 /* For eMMC, minimum is 1us but give it 9us for good measure */ 598 udelay(9); 599 reg &= ~0x10; 600 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 601 /* For eMMC, minimum is 200us but give it 300us for good measure */ 602 usleep_range(300, 1000); 603 } 604 605 static int intel_select_drive_strength(struct mmc_card *card, 606 unsigned int max_dtr, int host_drv, 607 int card_drv, int *drv_type) 608 { 609 struct sdhci_host *host = mmc_priv(card->host); 610 struct sdhci_pci_slot *slot = sdhci_priv(host); 611 struct intel_host *intel_host = sdhci_pci_priv(slot); 612 613 if (!(mmc_driver_type_mask(intel_host->drv_strength) & card_drv)) 614 return 0; 615 616 return intel_host->drv_strength; 617 } 618 619 static int bxt_get_cd(struct mmc_host *mmc) 620 { 621 int gpio_cd = mmc_gpio_get_cd(mmc); 622 623 if (!gpio_cd) 624 return 0; 625 626 return sdhci_get_cd_nogpio(mmc); 627 } 628 629 static int mrfld_get_cd(struct mmc_host *mmc) 630 { 631 return sdhci_get_cd_nogpio(mmc); 632 } 633 634 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 635 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 636 637 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 638 unsigned short vdd) 639 { 640 struct sdhci_pci_slot *slot = sdhci_priv(host); 641 struct intel_host *intel_host = sdhci_pci_priv(slot); 642 int cntr; 643 u8 reg; 644 645 /* 646 * Bus power may control card power, but a full reset still may not 647 * reset the power, whereas a direct write to SDHCI_POWER_CONTROL can. 648 * That might be needed to initialize correctly, if the card was left 649 * powered on previously. 650 */ 651 if (intel_host->needs_pwr_off) { 652 intel_host->needs_pwr_off = false; 653 if (mode != MMC_POWER_OFF) { 654 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 655 usleep_range(10000, 12500); 656 } 657 } 658 659 sdhci_set_power(host, mode, vdd); 660 661 if (mode == MMC_POWER_OFF) 662 return; 663 664 /* 665 * Bus power might not enable after D3 -> D0 transition due to the 666 * present state not yet having propagated. Retry for up to 2ms. 667 */ 668 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 669 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 670 if (reg & SDHCI_POWER_ON) 671 break; 672 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 673 reg |= SDHCI_POWER_ON; 674 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 675 } 676 } 677 678 static void sdhci_intel_set_uhs_signaling(struct sdhci_host *host, 679 unsigned int timing) 680 { 681 /* Set UHS timing to SDR25 for High Speed mode */ 682 if (timing == MMC_TIMING_MMC_HS || timing == MMC_TIMING_SD_HS) 683 timing = MMC_TIMING_UHS_SDR25; 684 sdhci_set_uhs_signaling(host, timing); 685 } 686 687 #define INTEL_HS400_ES_REG 0x78 688 #define INTEL_HS400_ES_BIT BIT(0) 689 690 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc, 691 struct mmc_ios *ios) 692 { 693 struct sdhci_host *host = mmc_priv(mmc); 694 u32 val; 695 696 val = sdhci_readl(host, INTEL_HS400_ES_REG); 697 if (ios->enhanced_strobe) 698 val |= INTEL_HS400_ES_BIT; 699 else 700 val &= ~INTEL_HS400_ES_BIT; 701 sdhci_writel(host, val, INTEL_HS400_ES_REG); 702 } 703 704 static int intel_start_signal_voltage_switch(struct mmc_host *mmc, 705 struct mmc_ios *ios) 706 { 707 struct device *dev = mmc_dev(mmc); 708 struct sdhci_host *host = mmc_priv(mmc); 709 struct sdhci_pci_slot *slot = sdhci_priv(host); 710 struct intel_host *intel_host = sdhci_pci_priv(slot); 711 unsigned int fn; 712 u32 result = 0; 713 int err; 714 715 err = sdhci_start_signal_voltage_switch(mmc, ios); 716 if (err) 717 return err; 718 719 switch (ios->signal_voltage) { 720 case MMC_SIGNAL_VOLTAGE_330: 721 fn = INTEL_DSM_V33_SWITCH; 722 break; 723 case MMC_SIGNAL_VOLTAGE_180: 724 fn = INTEL_DSM_V18_SWITCH; 725 break; 726 default: 727 return 0; 728 } 729 730 err = intel_dsm(intel_host, dev, fn, &result); 731 pr_debug("%s: %s DSM fn %u error %d result %u\n", 732 mmc_hostname(mmc), __func__, fn, err, result); 733 734 return 0; 735 } 736 737 static const struct sdhci_ops sdhci_intel_byt_ops = { 738 .set_clock = sdhci_set_clock, 739 .set_power = sdhci_intel_set_power, 740 .enable_dma = sdhci_pci_enable_dma, 741 .set_bus_width = sdhci_set_bus_width, 742 .reset = sdhci_reset, 743 .set_uhs_signaling = sdhci_intel_set_uhs_signaling, 744 .hw_reset = sdhci_pci_hw_reset, 745 }; 746 747 static const struct sdhci_ops sdhci_intel_glk_ops = { 748 .set_clock = sdhci_set_clock, 749 .set_power = sdhci_intel_set_power, 750 .enable_dma = sdhci_pci_enable_dma, 751 .set_bus_width = sdhci_set_bus_width, 752 .reset = sdhci_cqhci_reset, 753 .set_uhs_signaling = sdhci_intel_set_uhs_signaling, 754 .hw_reset = sdhci_pci_hw_reset, 755 .irq = sdhci_cqhci_irq, 756 }; 757 758 static void byt_read_dsm(struct sdhci_pci_slot *slot) 759 { 760 struct intel_host *intel_host = sdhci_pci_priv(slot); 761 struct device *dev = &slot->chip->pdev->dev; 762 struct mmc_host *mmc = slot->host->mmc; 763 764 intel_dsm_init(intel_host, dev, mmc); 765 slot->chip->rpm_retune = intel_host->d3_retune; 766 } 767 768 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode) 769 { 770 int err = sdhci_execute_tuning(mmc, opcode); 771 struct sdhci_host *host = mmc_priv(mmc); 772 773 if (err) 774 return err; 775 776 /* 777 * Tuning can leave the IP in an active state (Buffer Read Enable bit 778 * set) which prevents the entry to low power states (i.e. S0i3). Data 779 * reset will clear it. 780 */ 781 sdhci_reset(host, SDHCI_RESET_DATA); 782 783 return 0; 784 } 785 786 #define INTEL_ACTIVELTR 0x804 787 #define INTEL_IDLELTR 0x808 788 789 #define INTEL_LTR_REQ BIT(15) 790 #define INTEL_LTR_SCALE_MASK GENMASK(11, 10) 791 #define INTEL_LTR_SCALE_1US (2 << 10) 792 #define INTEL_LTR_SCALE_32US (3 << 10) 793 #define INTEL_LTR_VALUE_MASK GENMASK(9, 0) 794 795 static void intel_cache_ltr(struct sdhci_pci_slot *slot) 796 { 797 struct intel_host *intel_host = sdhci_pci_priv(slot); 798 struct sdhci_host *host = slot->host; 799 800 intel_host->active_ltr = readl(host->ioaddr + INTEL_ACTIVELTR); 801 intel_host->idle_ltr = readl(host->ioaddr + INTEL_IDLELTR); 802 } 803 804 static void intel_ltr_set(struct device *dev, s32 val) 805 { 806 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 807 struct sdhci_pci_slot *slot = chip->slots[0]; 808 struct intel_host *intel_host = sdhci_pci_priv(slot); 809 struct sdhci_host *host = slot->host; 810 u32 ltr; 811 812 pm_runtime_get_sync(dev); 813 814 /* 815 * Program latency tolerance (LTR) accordingly what has been asked 816 * by the PM QoS layer or disable it in case we were passed 817 * negative value or PM_QOS_LATENCY_ANY. 818 */ 819 ltr = readl(host->ioaddr + INTEL_ACTIVELTR); 820 821 if (val == PM_QOS_LATENCY_ANY || val < 0) { 822 ltr &= ~INTEL_LTR_REQ; 823 } else { 824 ltr |= INTEL_LTR_REQ; 825 ltr &= ~INTEL_LTR_SCALE_MASK; 826 ltr &= ~INTEL_LTR_VALUE_MASK; 827 828 if (val > INTEL_LTR_VALUE_MASK) { 829 val >>= 5; 830 if (val > INTEL_LTR_VALUE_MASK) 831 val = INTEL_LTR_VALUE_MASK; 832 ltr |= INTEL_LTR_SCALE_32US | val; 833 } else { 834 ltr |= INTEL_LTR_SCALE_1US | val; 835 } 836 } 837 838 if (ltr == intel_host->active_ltr) 839 goto out; 840 841 writel(ltr, host->ioaddr + INTEL_ACTIVELTR); 842 writel(ltr, host->ioaddr + INTEL_IDLELTR); 843 844 /* Cache the values into lpss structure */ 845 intel_cache_ltr(slot); 846 out: 847 pm_runtime_put_autosuspend(dev); 848 } 849 850 static bool intel_use_ltr(struct sdhci_pci_chip *chip) 851 { 852 switch (chip->pdev->device) { 853 case PCI_DEVICE_ID_INTEL_BYT_EMMC: 854 case PCI_DEVICE_ID_INTEL_BYT_EMMC2: 855 case PCI_DEVICE_ID_INTEL_BYT_SDIO: 856 case PCI_DEVICE_ID_INTEL_BYT_SD: 857 case PCI_DEVICE_ID_INTEL_BSW_EMMC: 858 case PCI_DEVICE_ID_INTEL_BSW_SDIO: 859 case PCI_DEVICE_ID_INTEL_BSW_SD: 860 return false; 861 default: 862 return true; 863 } 864 } 865 866 static void intel_ltr_expose(struct sdhci_pci_chip *chip) 867 { 868 struct device *dev = &chip->pdev->dev; 869 870 if (!intel_use_ltr(chip)) 871 return; 872 873 dev->power.set_latency_tolerance = intel_ltr_set; 874 dev_pm_qos_expose_latency_tolerance(dev); 875 } 876 877 static void intel_ltr_hide(struct sdhci_pci_chip *chip) 878 { 879 struct device *dev = &chip->pdev->dev; 880 881 if (!intel_use_ltr(chip)) 882 return; 883 884 dev_pm_qos_hide_latency_tolerance(dev); 885 dev->power.set_latency_tolerance = NULL; 886 } 887 888 static void byt_probe_slot(struct sdhci_pci_slot *slot) 889 { 890 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 891 struct device *dev = &slot->chip->pdev->dev; 892 struct mmc_host *mmc = slot->host->mmc; 893 894 byt_read_dsm(slot); 895 896 byt_ocp_setting(slot->chip->pdev); 897 898 ops->execute_tuning = intel_execute_tuning; 899 ops->start_signal_voltage_switch = intel_start_signal_voltage_switch; 900 901 device_property_read_u32(dev, "max-frequency", &mmc->f_max); 902 903 if (!mmc->slotno) { 904 slot->chip->slots[mmc->slotno] = slot; 905 intel_ltr_expose(slot->chip); 906 } 907 } 908 909 static void byt_add_debugfs(struct sdhci_pci_slot *slot) 910 { 911 struct intel_host *intel_host = sdhci_pci_priv(slot); 912 struct mmc_host *mmc = slot->host->mmc; 913 struct dentry *dir = mmc->debugfs_root; 914 915 if (!intel_use_ltr(slot->chip)) 916 return; 917 918 debugfs_create_x32("active_ltr", 0444, dir, &intel_host->active_ltr); 919 debugfs_create_x32("idle_ltr", 0444, dir, &intel_host->idle_ltr); 920 921 intel_cache_ltr(slot); 922 } 923 924 static int byt_add_host(struct sdhci_pci_slot *slot) 925 { 926 int ret = sdhci_add_host(slot->host); 927 928 if (!ret) 929 byt_add_debugfs(slot); 930 return ret; 931 } 932 933 static void byt_remove_slot(struct sdhci_pci_slot *slot, int dead) 934 { 935 struct mmc_host *mmc = slot->host->mmc; 936 937 if (!mmc->slotno) 938 intel_ltr_hide(slot->chip); 939 } 940 941 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 942 { 943 byt_probe_slot(slot); 944 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 945 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 946 MMC_CAP_CMD_DURING_TFR | 947 MMC_CAP_WAIT_WHILE_BUSY; 948 slot->hw_reset = sdhci_pci_int_hw_reset; 949 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 950 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 951 slot->host->mmc_host_ops.select_drive_strength = 952 intel_select_drive_strength; 953 return 0; 954 } 955 956 static bool glk_broken_cqhci(struct sdhci_pci_slot *slot) 957 { 958 return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 959 (dmi_match(DMI_BIOS_VENDOR, "LENOVO") || 960 dmi_match(DMI_SYS_VENDOR, "IRBIS")); 961 } 962 963 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot) 964 { 965 int ret = byt_emmc_probe_slot(slot); 966 967 if (!glk_broken_cqhci(slot)) 968 slot->host->mmc->caps2 |= MMC_CAP2_CQE; 969 970 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) { 971 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES; 972 slot->host->mmc_host_ops.hs400_enhanced_strobe = 973 intel_hs400_enhanced_strobe; 974 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; 975 } 976 977 return ret; 978 } 979 980 static const struct cqhci_host_ops glk_cqhci_ops = { 981 .enable = sdhci_cqe_enable, 982 .disable = sdhci_cqe_disable, 983 .dumpregs = sdhci_pci_dumpregs, 984 }; 985 986 static int glk_emmc_add_host(struct sdhci_pci_slot *slot) 987 { 988 struct device *dev = &slot->chip->pdev->dev; 989 struct sdhci_host *host = slot->host; 990 struct cqhci_host *cq_host; 991 bool dma64; 992 int ret; 993 994 ret = sdhci_setup_host(host); 995 if (ret) 996 return ret; 997 998 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); 999 if (!cq_host) { 1000 ret = -ENOMEM; 1001 goto cleanup; 1002 } 1003 1004 cq_host->mmio = host->ioaddr + 0x200; 1005 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 1006 cq_host->ops = &glk_cqhci_ops; 1007 1008 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 1009 if (dma64) 1010 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 1011 1012 ret = cqhci_init(cq_host, host->mmc, dma64); 1013 if (ret) 1014 goto cleanup; 1015 1016 ret = __sdhci_add_host(host); 1017 if (ret) 1018 goto cleanup; 1019 1020 byt_add_debugfs(slot); 1021 1022 return 0; 1023 1024 cleanup: 1025 sdhci_cleanup_host(host); 1026 return ret; 1027 } 1028 1029 #ifdef CONFIG_PM 1030 #define GLK_RX_CTRL1 0x834 1031 #define GLK_TUN_VAL 0x840 1032 #define GLK_PATH_PLL GENMASK(13, 8) 1033 #define GLK_DLY GENMASK(6, 0) 1034 /* Workaround firmware failing to restore the tuning value */ 1035 static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp) 1036 { 1037 struct sdhci_pci_slot *slot = chip->slots[0]; 1038 struct intel_host *intel_host = sdhci_pci_priv(slot); 1039 struct sdhci_host *host = slot->host; 1040 u32 glk_rx_ctrl1; 1041 u32 glk_tun_val; 1042 u32 dly; 1043 1044 if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc)) 1045 return; 1046 1047 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1); 1048 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL); 1049 1050 if (susp) { 1051 intel_host->glk_rx_ctrl1 = glk_rx_ctrl1; 1052 intel_host->glk_tun_val = glk_tun_val; 1053 return; 1054 } 1055 1056 if (!intel_host->glk_tun_val) 1057 return; 1058 1059 if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) { 1060 intel_host->rpm_retune_ok = true; 1061 return; 1062 } 1063 1064 dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) + 1065 (intel_host->glk_tun_val << 1)); 1066 if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1)) 1067 return; 1068 1069 glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly; 1070 sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1); 1071 1072 intel_host->rpm_retune_ok = true; 1073 chip->rpm_retune = true; 1074 mmc_retune_needed(host->mmc); 1075 pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc)); 1076 } 1077 1078 static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp) 1079 { 1080 if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 1081 !chip->rpm_retune) 1082 glk_rpm_retune_wa(chip, susp); 1083 } 1084 1085 static int glk_runtime_suspend(struct sdhci_pci_chip *chip) 1086 { 1087 glk_rpm_retune_chk(chip, true); 1088 1089 return sdhci_cqhci_runtime_suspend(chip); 1090 } 1091 1092 static int glk_runtime_resume(struct sdhci_pci_chip *chip) 1093 { 1094 glk_rpm_retune_chk(chip, false); 1095 1096 return sdhci_cqhci_runtime_resume(chip); 1097 } 1098 #endif 1099 1100 #ifdef CONFIG_ACPI 1101 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 1102 { 1103 acpi_status status; 1104 unsigned long long max_freq; 1105 1106 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 1107 "MXFQ", NULL, &max_freq); 1108 if (ACPI_FAILURE(status)) { 1109 dev_err(&slot->chip->pdev->dev, 1110 "MXFQ not found in acpi table\n"); 1111 return -EINVAL; 1112 } 1113 1114 slot->host->mmc->f_max = max_freq * 1000000; 1115 1116 return 0; 1117 } 1118 #else 1119 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 1120 { 1121 return 0; 1122 } 1123 #endif 1124 1125 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 1126 { 1127 int err; 1128 1129 byt_probe_slot(slot); 1130 1131 err = ni_set_max_freq(slot); 1132 if (err) 1133 return err; 1134 1135 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 1136 MMC_CAP_WAIT_WHILE_BUSY; 1137 return 0; 1138 } 1139 1140 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 1141 { 1142 byt_probe_slot(slot); 1143 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 1144 MMC_CAP_WAIT_WHILE_BUSY; 1145 return 0; 1146 } 1147 1148 static void byt_needs_pwr_off(struct sdhci_pci_slot *slot) 1149 { 1150 struct intel_host *intel_host = sdhci_pci_priv(slot); 1151 u8 reg = sdhci_readb(slot->host, SDHCI_POWER_CONTROL); 1152 1153 intel_host->needs_pwr_off = reg & SDHCI_POWER_ON; 1154 } 1155 1156 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 1157 { 1158 byt_probe_slot(slot); 1159 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | 1160 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE; 1161 slot->cd_idx = 0; 1162 slot->cd_override_level = true; 1163 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 1164 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 1165 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 1166 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) 1167 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 1168 1169 if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI && 1170 slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3) 1171 slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V; 1172 1173 byt_needs_pwr_off(slot); 1174 1175 return 0; 1176 } 1177 1178 #ifdef CONFIG_PM_SLEEP 1179 1180 static int byt_resume(struct sdhci_pci_chip *chip) 1181 { 1182 byt_ocp_setting(chip->pdev); 1183 1184 return sdhci_pci_resume_host(chip); 1185 } 1186 1187 #endif 1188 1189 #ifdef CONFIG_PM 1190 1191 static int byt_runtime_resume(struct sdhci_pci_chip *chip) 1192 { 1193 byt_ocp_setting(chip->pdev); 1194 1195 return sdhci_pci_runtime_resume_host(chip); 1196 } 1197 1198 #endif 1199 1200 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 1201 #ifdef CONFIG_PM_SLEEP 1202 .resume = byt_resume, 1203 #endif 1204 #ifdef CONFIG_PM 1205 .runtime_resume = byt_runtime_resume, 1206 #endif 1207 .allow_runtime_pm = true, 1208 .probe_slot = byt_emmc_probe_slot, 1209 .add_host = byt_add_host, 1210 .remove_slot = byt_remove_slot, 1211 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1212 SDHCI_QUIRK_NO_LED, 1213 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1214 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1215 SDHCI_QUIRK2_STOP_WITH_TC, 1216 .ops = &sdhci_intel_byt_ops, 1217 .priv_size = sizeof(struct intel_host), 1218 }; 1219 1220 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = { 1221 .allow_runtime_pm = true, 1222 .probe_slot = glk_emmc_probe_slot, 1223 .add_host = glk_emmc_add_host, 1224 .remove_slot = byt_remove_slot, 1225 #ifdef CONFIG_PM_SLEEP 1226 .suspend = sdhci_cqhci_suspend, 1227 .resume = sdhci_cqhci_resume, 1228 #endif 1229 #ifdef CONFIG_PM 1230 .runtime_suspend = glk_runtime_suspend, 1231 .runtime_resume = glk_runtime_resume, 1232 #endif 1233 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1234 SDHCI_QUIRK_NO_LED, 1235 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1236 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1237 SDHCI_QUIRK2_STOP_WITH_TC, 1238 .ops = &sdhci_intel_glk_ops, 1239 .priv_size = sizeof(struct intel_host), 1240 }; 1241 1242 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 1243 #ifdef CONFIG_PM_SLEEP 1244 .resume = byt_resume, 1245 #endif 1246 #ifdef CONFIG_PM 1247 .runtime_resume = byt_runtime_resume, 1248 #endif 1249 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1250 SDHCI_QUIRK_NO_LED, 1251 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1252 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1253 .allow_runtime_pm = true, 1254 .probe_slot = ni_byt_sdio_probe_slot, 1255 .add_host = byt_add_host, 1256 .remove_slot = byt_remove_slot, 1257 .ops = &sdhci_intel_byt_ops, 1258 .priv_size = sizeof(struct intel_host), 1259 }; 1260 1261 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 1262 #ifdef CONFIG_PM_SLEEP 1263 .resume = byt_resume, 1264 #endif 1265 #ifdef CONFIG_PM 1266 .runtime_resume = byt_runtime_resume, 1267 #endif 1268 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1269 SDHCI_QUIRK_NO_LED, 1270 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1271 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1272 .allow_runtime_pm = true, 1273 .probe_slot = byt_sdio_probe_slot, 1274 .add_host = byt_add_host, 1275 .remove_slot = byt_remove_slot, 1276 .ops = &sdhci_intel_byt_ops, 1277 .priv_size = sizeof(struct intel_host), 1278 }; 1279 1280 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 1281 #ifdef CONFIG_PM_SLEEP 1282 .resume = byt_resume, 1283 #endif 1284 #ifdef CONFIG_PM 1285 .runtime_resume = byt_runtime_resume, 1286 #endif 1287 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1288 SDHCI_QUIRK_NO_LED, 1289 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 1290 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1291 SDHCI_QUIRK2_STOP_WITH_TC, 1292 .allow_runtime_pm = true, 1293 .own_cd_for_runtime_pm = true, 1294 .probe_slot = byt_sd_probe_slot, 1295 .add_host = byt_add_host, 1296 .remove_slot = byt_remove_slot, 1297 .ops = &sdhci_intel_byt_ops, 1298 .priv_size = sizeof(struct intel_host), 1299 }; 1300 1301 /* Define Host controllers for Intel Merrifield platform */ 1302 #define INTEL_MRFLD_EMMC_0 0 1303 #define INTEL_MRFLD_EMMC_1 1 1304 #define INTEL_MRFLD_SD 2 1305 #define INTEL_MRFLD_SDIO 3 1306 1307 #ifdef CONFIG_ACPI 1308 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) 1309 { 1310 struct acpi_device *device, *child; 1311 1312 device = ACPI_COMPANION(&slot->chip->pdev->dev); 1313 if (!device) 1314 return; 1315 1316 acpi_device_fix_up_power(device); 1317 list_for_each_entry(child, &device->children, node) 1318 if (child->status.present && child->status.enabled) 1319 acpi_device_fix_up_power(child); 1320 } 1321 #else 1322 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {} 1323 #endif 1324 1325 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 1326 { 1327 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 1328 1329 switch (func) { 1330 case INTEL_MRFLD_EMMC_0: 1331 case INTEL_MRFLD_EMMC_1: 1332 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1333 MMC_CAP_8_BIT_DATA | 1334 MMC_CAP_1_8V_DDR; 1335 break; 1336 case INTEL_MRFLD_SD: 1337 slot->cd_idx = 0; 1338 slot->cd_override_level = true; 1339 /* 1340 * There are two PCB designs of SD card slot with the opposite 1341 * card detection sense. Quirk this out by ignoring GPIO state 1342 * completely in the custom ->get_cd() callback. 1343 */ 1344 slot->host->mmc_host_ops.get_cd = mrfld_get_cd; 1345 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1346 break; 1347 case INTEL_MRFLD_SDIO: 1348 /* Advertise 2.0v for compatibility with the SDIO card's OCR */ 1349 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195; 1350 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1351 MMC_CAP_POWER_OFF_CARD; 1352 break; 1353 default: 1354 return -ENODEV; 1355 } 1356 1357 intel_mrfld_mmc_fix_up_power_slot(slot); 1358 return 0; 1359 } 1360 1361 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 1362 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1363 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 1364 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1365 .allow_runtime_pm = true, 1366 .probe_slot = intel_mrfld_mmc_probe_slot, 1367 }; 1368 1369 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 1370 { 1371 u8 scratch; 1372 int ret; 1373 1374 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 1375 if (ret) 1376 return ret; 1377 1378 /* 1379 * Turn PMOS on [bit 0], set over current detection to 2.4 V 1380 * [bit 1:2] and enable over current debouncing [bit 6]. 1381 */ 1382 if (on) 1383 scratch |= 0x47; 1384 else 1385 scratch &= ~0x47; 1386 1387 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 1388 } 1389 1390 static int jmicron_probe(struct sdhci_pci_chip *chip) 1391 { 1392 int ret; 1393 u16 mmcdev = 0; 1394 1395 if (chip->pdev->revision == 0) { 1396 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 1397 SDHCI_QUIRK_32BIT_DMA_SIZE | 1398 SDHCI_QUIRK_32BIT_ADMA_SIZE | 1399 SDHCI_QUIRK_RESET_AFTER_REQUEST | 1400 SDHCI_QUIRK_BROKEN_SMALL_PIO; 1401 } 1402 1403 /* 1404 * JMicron chips can have two interfaces to the same hardware 1405 * in order to work around limitations in Microsoft's driver. 1406 * We need to make sure we only bind to one of them. 1407 * 1408 * This code assumes two things: 1409 * 1410 * 1. The PCI code adds subfunctions in order. 1411 * 1412 * 2. The MMC interface has a lower subfunction number 1413 * than the SD interface. 1414 */ 1415 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 1416 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 1417 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 1418 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 1419 1420 if (mmcdev) { 1421 struct pci_dev *sd_dev; 1422 1423 sd_dev = NULL; 1424 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 1425 mmcdev, sd_dev)) != NULL) { 1426 if ((PCI_SLOT(chip->pdev->devfn) == 1427 PCI_SLOT(sd_dev->devfn)) && 1428 (chip->pdev->bus == sd_dev->bus)) 1429 break; 1430 } 1431 1432 if (sd_dev) { 1433 pci_dev_put(sd_dev); 1434 dev_info(&chip->pdev->dev, "Refusing to bind to " 1435 "secondary interface.\n"); 1436 return -ENODEV; 1437 } 1438 } 1439 1440 /* 1441 * JMicron chips need a bit of a nudge to enable the power 1442 * output pins. 1443 */ 1444 ret = jmicron_pmos(chip, 1); 1445 if (ret) { 1446 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1447 return ret; 1448 } 1449 1450 /* quirk for unsable RO-detection on JM388 chips */ 1451 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 1452 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1453 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 1454 1455 return 0; 1456 } 1457 1458 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 1459 { 1460 u8 scratch; 1461 1462 scratch = readb(host->ioaddr + 0xC0); 1463 1464 if (on) 1465 scratch |= 0x01; 1466 else 1467 scratch &= ~0x01; 1468 1469 writeb(scratch, host->ioaddr + 0xC0); 1470 } 1471 1472 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 1473 { 1474 if (slot->chip->pdev->revision == 0) { 1475 u16 version; 1476 1477 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 1478 version = (version & SDHCI_VENDOR_VER_MASK) >> 1479 SDHCI_VENDOR_VER_SHIFT; 1480 1481 /* 1482 * Older versions of the chip have lots of nasty glitches 1483 * in the ADMA engine. It's best just to avoid it 1484 * completely. 1485 */ 1486 if (version < 0xAC) 1487 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 1488 } 1489 1490 /* JM388 MMC doesn't support 1.8V while SD supports it */ 1491 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1492 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 1493 MMC_VDD_29_30 | MMC_VDD_30_31 | 1494 MMC_VDD_165_195; /* allow 1.8V */ 1495 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 1496 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 1497 } 1498 1499 /* 1500 * The secondary interface requires a bit set to get the 1501 * interrupts. 1502 */ 1503 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1504 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1505 jmicron_enable_mmc(slot->host, 1); 1506 1507 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 1508 1509 return 0; 1510 } 1511 1512 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 1513 { 1514 if (dead) 1515 return; 1516 1517 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1518 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1519 jmicron_enable_mmc(slot->host, 0); 1520 } 1521 1522 #ifdef CONFIG_PM_SLEEP 1523 static int jmicron_suspend(struct sdhci_pci_chip *chip) 1524 { 1525 int i, ret; 1526 1527 ret = sdhci_pci_suspend_host(chip); 1528 if (ret) 1529 return ret; 1530 1531 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1532 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1533 for (i = 0; i < chip->num_slots; i++) 1534 jmicron_enable_mmc(chip->slots[i]->host, 0); 1535 } 1536 1537 return 0; 1538 } 1539 1540 static int jmicron_resume(struct sdhci_pci_chip *chip) 1541 { 1542 int ret, i; 1543 1544 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1545 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1546 for (i = 0; i < chip->num_slots; i++) 1547 jmicron_enable_mmc(chip->slots[i]->host, 1); 1548 } 1549 1550 ret = jmicron_pmos(chip, 1); 1551 if (ret) { 1552 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1553 return ret; 1554 } 1555 1556 return sdhci_pci_resume_host(chip); 1557 } 1558 #endif 1559 1560 static const struct sdhci_pci_fixes sdhci_jmicron = { 1561 .probe = jmicron_probe, 1562 1563 .probe_slot = jmicron_probe_slot, 1564 .remove_slot = jmicron_remove_slot, 1565 1566 #ifdef CONFIG_PM_SLEEP 1567 .suspend = jmicron_suspend, 1568 .resume = jmicron_resume, 1569 #endif 1570 }; 1571 1572 /* SysKonnect CardBus2SDIO extra registers */ 1573 #define SYSKT_CTRL 0x200 1574 #define SYSKT_RDFIFO_STAT 0x204 1575 #define SYSKT_WRFIFO_STAT 0x208 1576 #define SYSKT_POWER_DATA 0x20c 1577 #define SYSKT_POWER_330 0xef 1578 #define SYSKT_POWER_300 0xf8 1579 #define SYSKT_POWER_184 0xcc 1580 #define SYSKT_POWER_CMD 0x20d 1581 #define SYSKT_POWER_START (1 << 7) 1582 #define SYSKT_POWER_STATUS 0x20e 1583 #define SYSKT_POWER_STATUS_OK (1 << 0) 1584 #define SYSKT_BOARD_REV 0x210 1585 #define SYSKT_CHIP_REV 0x211 1586 #define SYSKT_CONF_DATA 0x212 1587 #define SYSKT_CONF_DATA_1V8 (1 << 2) 1588 #define SYSKT_CONF_DATA_2V5 (1 << 1) 1589 #define SYSKT_CONF_DATA_3V3 (1 << 0) 1590 1591 static int syskt_probe(struct sdhci_pci_chip *chip) 1592 { 1593 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1594 chip->pdev->class &= ~0x0000FF; 1595 chip->pdev->class |= PCI_SDHCI_IFDMA; 1596 } 1597 return 0; 1598 } 1599 1600 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 1601 { 1602 int tm, ps; 1603 1604 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 1605 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 1606 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 1607 "board rev %d.%d, chip rev %d.%d\n", 1608 board_rev >> 4, board_rev & 0xf, 1609 chip_rev >> 4, chip_rev & 0xf); 1610 if (chip_rev >= 0x20) 1611 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 1612 1613 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 1614 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 1615 udelay(50); 1616 tm = 10; /* Wait max 1 ms */ 1617 do { 1618 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 1619 if (ps & SYSKT_POWER_STATUS_OK) 1620 break; 1621 udelay(100); 1622 } while (--tm); 1623 if (!tm) { 1624 dev_err(&slot->chip->pdev->dev, 1625 "power regulator never stabilized"); 1626 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 1627 return -ENODEV; 1628 } 1629 1630 return 0; 1631 } 1632 1633 static const struct sdhci_pci_fixes sdhci_syskt = { 1634 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 1635 .probe = syskt_probe, 1636 .probe_slot = syskt_probe_slot, 1637 }; 1638 1639 static int via_probe(struct sdhci_pci_chip *chip) 1640 { 1641 if (chip->pdev->revision == 0x10) 1642 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 1643 1644 return 0; 1645 } 1646 1647 static const struct sdhci_pci_fixes sdhci_via = { 1648 .probe = via_probe, 1649 }; 1650 1651 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 1652 { 1653 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 1654 return 0; 1655 } 1656 1657 static const struct sdhci_pci_fixes sdhci_rtsx = { 1658 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1659 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 1660 SDHCI_QUIRK2_BROKEN_DDR50, 1661 .probe_slot = rtsx_probe_slot, 1662 }; 1663 1664 /*AMD chipset generation*/ 1665 enum amd_chipset_gen { 1666 AMD_CHIPSET_BEFORE_ML, 1667 AMD_CHIPSET_CZ, 1668 AMD_CHIPSET_NL, 1669 AMD_CHIPSET_UNKNOWN, 1670 }; 1671 1672 /* AMD registers */ 1673 #define AMD_SD_AUTO_PATTERN 0xB8 1674 #define AMD_MSLEEP_DURATION 4 1675 #define AMD_SD_MISC_CONTROL 0xD0 1676 #define AMD_MAX_TUNE_VALUE 0x0B 1677 #define AMD_AUTO_TUNE_SEL 0x10800 1678 #define AMD_FIFO_PTR 0x30 1679 #define AMD_BIT_MASK 0x1F 1680 1681 static void amd_tuning_reset(struct sdhci_host *host) 1682 { 1683 unsigned int val; 1684 1685 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1686 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 1687 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1688 1689 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1690 val &= ~SDHCI_CTRL_EXEC_TUNING; 1691 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1692 } 1693 1694 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 1695 { 1696 unsigned int val; 1697 1698 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 1699 val &= ~AMD_BIT_MASK; 1700 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 1701 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 1702 } 1703 1704 static void amd_enable_manual_tuning(struct pci_dev *pdev) 1705 { 1706 unsigned int val; 1707 1708 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 1709 val |= AMD_FIFO_PTR; 1710 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 1711 } 1712 1713 static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode) 1714 { 1715 struct sdhci_pci_slot *slot = sdhci_priv(host); 1716 struct pci_dev *pdev = slot->chip->pdev; 1717 u8 valid_win = 0; 1718 u8 valid_win_max = 0; 1719 u8 valid_win_end = 0; 1720 u8 ctrl, tune_around; 1721 1722 amd_tuning_reset(host); 1723 1724 for (tune_around = 0; tune_around < 12; tune_around++) { 1725 amd_config_tuning_phase(pdev, tune_around); 1726 1727 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1728 valid_win = 0; 1729 msleep(AMD_MSLEEP_DURATION); 1730 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 1731 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 1732 } else if (++valid_win > valid_win_max) { 1733 valid_win_max = valid_win; 1734 valid_win_end = tune_around; 1735 } 1736 } 1737 1738 if (!valid_win_max) { 1739 dev_err(&pdev->dev, "no tuning point found\n"); 1740 return -EIO; 1741 } 1742 1743 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 1744 1745 amd_enable_manual_tuning(pdev); 1746 1747 host->mmc->retune_period = 0; 1748 1749 return 0; 1750 } 1751 1752 static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode) 1753 { 1754 struct sdhci_host *host = mmc_priv(mmc); 1755 1756 /* AMD requires custom HS200 tuning */ 1757 if (host->timing == MMC_TIMING_MMC_HS200) 1758 return amd_execute_tuning_hs200(host, opcode); 1759 1760 /* Otherwise perform standard SDHCI tuning */ 1761 return sdhci_execute_tuning(mmc, opcode); 1762 } 1763 1764 static int amd_probe_slot(struct sdhci_pci_slot *slot) 1765 { 1766 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 1767 1768 ops->execute_tuning = amd_execute_tuning; 1769 1770 return 0; 1771 } 1772 1773 static int amd_probe(struct sdhci_pci_chip *chip) 1774 { 1775 struct pci_dev *smbus_dev; 1776 enum amd_chipset_gen gen; 1777 1778 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1779 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 1780 if (smbus_dev) { 1781 gen = AMD_CHIPSET_BEFORE_ML; 1782 } else { 1783 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1784 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1785 if (smbus_dev) { 1786 if (smbus_dev->revision < 0x51) 1787 gen = AMD_CHIPSET_CZ; 1788 else 1789 gen = AMD_CHIPSET_NL; 1790 } else { 1791 gen = AMD_CHIPSET_UNKNOWN; 1792 } 1793 } 1794 1795 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1796 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1797 1798 return 0; 1799 } 1800 1801 static u32 sdhci_read_present_state(struct sdhci_host *host) 1802 { 1803 return sdhci_readl(host, SDHCI_PRESENT_STATE); 1804 } 1805 1806 static void amd_sdhci_reset(struct sdhci_host *host, u8 mask) 1807 { 1808 struct sdhci_pci_slot *slot = sdhci_priv(host); 1809 struct pci_dev *pdev = slot->chip->pdev; 1810 u32 present_state; 1811 1812 /* 1813 * SDHC 0x7906 requires a hard reset to clear all internal state. 1814 * Otherwise it can get into a bad state where the DATA lines are always 1815 * read as zeros. 1816 */ 1817 if (pdev->device == 0x7906 && (mask & SDHCI_RESET_ALL)) { 1818 pci_clear_master(pdev); 1819 1820 pci_save_state(pdev); 1821 1822 pci_set_power_state(pdev, PCI_D3cold); 1823 pr_debug("%s: power_state=%u\n", mmc_hostname(host->mmc), 1824 pdev->current_state); 1825 pci_set_power_state(pdev, PCI_D0); 1826 1827 pci_restore_state(pdev); 1828 1829 /* 1830 * SDHCI_RESET_ALL says the card detect logic should not be 1831 * reset, but since we need to reset the entire controller 1832 * we should wait until the card detect logic has stabilized. 1833 * 1834 * This normally takes about 40ms. 1835 */ 1836 readx_poll_timeout( 1837 sdhci_read_present_state, 1838 host, 1839 present_state, 1840 present_state & SDHCI_CD_STABLE, 1841 10000, 1842 100000 1843 ); 1844 } 1845 1846 return sdhci_reset(host, mask); 1847 } 1848 1849 static const struct sdhci_ops amd_sdhci_pci_ops = { 1850 .set_clock = sdhci_set_clock, 1851 .enable_dma = sdhci_pci_enable_dma, 1852 .set_bus_width = sdhci_set_bus_width, 1853 .reset = amd_sdhci_reset, 1854 .set_uhs_signaling = sdhci_set_uhs_signaling, 1855 }; 1856 1857 static const struct sdhci_pci_fixes sdhci_amd = { 1858 .probe = amd_probe, 1859 .ops = &amd_sdhci_pci_ops, 1860 .probe_slot = amd_probe_slot, 1861 }; 1862 1863 static const struct pci_device_id pci_ids[] = { 1864 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh), 1865 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc), 1866 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc), 1867 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc), 1868 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712), 1869 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712), 1870 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714), 1871 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714), 1872 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe), 1873 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron), 1874 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron), 1875 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron), 1876 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron), 1877 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt), 1878 SDHCI_PCI_DEVICE(VIA, 95D0, via), 1879 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx), 1880 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk), 1881 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0), 1882 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2), 1883 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2), 1884 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd), 1885 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio), 1886 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio), 1887 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc), 1888 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc), 1889 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio), 1890 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio), 1891 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc), 1892 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio), 1893 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio), 1894 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd), 1895 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc), 1896 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc), 1897 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio), 1898 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd), 1899 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd), 1900 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio), 1901 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio), 1902 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc), 1903 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc), 1904 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc), 1905 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc), 1906 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio), 1907 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd), 1908 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc), 1909 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc), 1910 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc), 1911 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio), 1912 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd), 1913 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc), 1914 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio), 1915 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd), 1916 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc), 1917 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio), 1918 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd), 1919 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc), 1920 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio), 1921 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd), 1922 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc), 1923 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd), 1924 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd), 1925 SDHCI_PCI_DEVICE(INTEL, ICP_EMMC, intel_glk_emmc), 1926 SDHCI_PCI_DEVICE(INTEL, ICP_SD, intel_byt_sd), 1927 SDHCI_PCI_DEVICE(INTEL, EHL_EMMC, intel_glk_emmc), 1928 SDHCI_PCI_DEVICE(INTEL, EHL_SD, intel_byt_sd), 1929 SDHCI_PCI_DEVICE(INTEL, CML_EMMC, intel_glk_emmc), 1930 SDHCI_PCI_DEVICE(INTEL, CML_SD, intel_byt_sd), 1931 SDHCI_PCI_DEVICE(INTEL, CMLH_SD, intel_byt_sd), 1932 SDHCI_PCI_DEVICE(INTEL, JSL_EMMC, intel_glk_emmc), 1933 SDHCI_PCI_DEVICE(INTEL, JSL_SD, intel_byt_sd), 1934 SDHCI_PCI_DEVICE(INTEL, LKF_EMMC, intel_glk_emmc), 1935 SDHCI_PCI_DEVICE(INTEL, LKF_SD, intel_byt_sd), 1936 SDHCI_PCI_DEVICE(O2, 8120, o2), 1937 SDHCI_PCI_DEVICE(O2, 8220, o2), 1938 SDHCI_PCI_DEVICE(O2, 8221, o2), 1939 SDHCI_PCI_DEVICE(O2, 8320, o2), 1940 SDHCI_PCI_DEVICE(O2, 8321, o2), 1941 SDHCI_PCI_DEVICE(O2, FUJIN2, o2), 1942 SDHCI_PCI_DEVICE(O2, SDS0, o2), 1943 SDHCI_PCI_DEVICE(O2, SDS1, o2), 1944 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2), 1945 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), 1946 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan), 1947 SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps), 1948 SDHCI_PCI_DEVICE(GLI, 9750, gl9750), 1949 SDHCI_PCI_DEVICE(GLI, 9755, gl9755), 1950 SDHCI_PCI_DEVICE(GLI, 9763E, gl9763e), 1951 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), 1952 /* Generic SD host controller */ 1953 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, 1954 { /* end: all zeroes */ }, 1955 }; 1956 1957 MODULE_DEVICE_TABLE(pci, pci_ids); 1958 1959 /*****************************************************************************\ 1960 * * 1961 * SDHCI core callbacks * 1962 * * 1963 \*****************************************************************************/ 1964 1965 int sdhci_pci_enable_dma(struct sdhci_host *host) 1966 { 1967 struct sdhci_pci_slot *slot; 1968 struct pci_dev *pdev; 1969 1970 slot = sdhci_priv(host); 1971 pdev = slot->chip->pdev; 1972 1973 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1974 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1975 (host->flags & SDHCI_USE_SDMA)) { 1976 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1977 "doesn't fully claim to support it.\n"); 1978 } 1979 1980 pci_set_master(pdev); 1981 1982 return 0; 1983 } 1984 1985 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1986 { 1987 struct sdhci_pci_slot *slot = sdhci_priv(host); 1988 int rst_n_gpio = slot->rst_n_gpio; 1989 1990 if (!gpio_is_valid(rst_n_gpio)) 1991 return; 1992 gpio_set_value_cansleep(rst_n_gpio, 0); 1993 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1994 udelay(10); 1995 gpio_set_value_cansleep(rst_n_gpio, 1); 1996 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1997 usleep_range(300, 1000); 1998 } 1999 2000 static void sdhci_pci_hw_reset(struct sdhci_host *host) 2001 { 2002 struct sdhci_pci_slot *slot = sdhci_priv(host); 2003 2004 if (slot->hw_reset) 2005 slot->hw_reset(host); 2006 } 2007 2008 static const struct sdhci_ops sdhci_pci_ops = { 2009 .set_clock = sdhci_set_clock, 2010 .enable_dma = sdhci_pci_enable_dma, 2011 .set_bus_width = sdhci_set_bus_width, 2012 .reset = sdhci_reset, 2013 .set_uhs_signaling = sdhci_set_uhs_signaling, 2014 .hw_reset = sdhci_pci_hw_reset, 2015 }; 2016 2017 /*****************************************************************************\ 2018 * * 2019 * Suspend/resume * 2020 * * 2021 \*****************************************************************************/ 2022 2023 #ifdef CONFIG_PM_SLEEP 2024 static int sdhci_pci_suspend(struct device *dev) 2025 { 2026 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2027 2028 if (!chip) 2029 return 0; 2030 2031 if (chip->fixes && chip->fixes->suspend) 2032 return chip->fixes->suspend(chip); 2033 2034 return sdhci_pci_suspend_host(chip); 2035 } 2036 2037 static int sdhci_pci_resume(struct device *dev) 2038 { 2039 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2040 2041 if (!chip) 2042 return 0; 2043 2044 if (chip->fixes && chip->fixes->resume) 2045 return chip->fixes->resume(chip); 2046 2047 return sdhci_pci_resume_host(chip); 2048 } 2049 #endif 2050 2051 #ifdef CONFIG_PM 2052 static int sdhci_pci_runtime_suspend(struct device *dev) 2053 { 2054 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2055 2056 if (!chip) 2057 return 0; 2058 2059 if (chip->fixes && chip->fixes->runtime_suspend) 2060 return chip->fixes->runtime_suspend(chip); 2061 2062 return sdhci_pci_runtime_suspend_host(chip); 2063 } 2064 2065 static int sdhci_pci_runtime_resume(struct device *dev) 2066 { 2067 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2068 2069 if (!chip) 2070 return 0; 2071 2072 if (chip->fixes && chip->fixes->runtime_resume) 2073 return chip->fixes->runtime_resume(chip); 2074 2075 return sdhci_pci_runtime_resume_host(chip); 2076 } 2077 #endif 2078 2079 static const struct dev_pm_ops sdhci_pci_pm_ops = { 2080 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 2081 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 2082 sdhci_pci_runtime_resume, NULL) 2083 }; 2084 2085 /*****************************************************************************\ 2086 * * 2087 * Device probing/removal * 2088 * * 2089 \*****************************************************************************/ 2090 2091 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 2092 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 2093 int slotno) 2094 { 2095 struct sdhci_pci_slot *slot; 2096 struct sdhci_host *host; 2097 int ret, bar = first_bar + slotno; 2098 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 2099 2100 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 2101 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 2102 return ERR_PTR(-ENODEV); 2103 } 2104 2105 if (pci_resource_len(pdev, bar) < 0x100) { 2106 dev_err(&pdev->dev, "Invalid iomem size. You may " 2107 "experience problems.\n"); 2108 } 2109 2110 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 2111 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 2112 return ERR_PTR(-ENODEV); 2113 } 2114 2115 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 2116 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 2117 return ERR_PTR(-ENODEV); 2118 } 2119 2120 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 2121 if (IS_ERR(host)) { 2122 dev_err(&pdev->dev, "cannot allocate host\n"); 2123 return ERR_CAST(host); 2124 } 2125 2126 slot = sdhci_priv(host); 2127 2128 slot->chip = chip; 2129 slot->host = host; 2130 slot->rst_n_gpio = -EINVAL; 2131 slot->cd_gpio = -EINVAL; 2132 slot->cd_idx = -1; 2133 2134 host->hw_name = "PCI"; 2135 host->ops = chip->fixes && chip->fixes->ops ? 2136 chip->fixes->ops : 2137 &sdhci_pci_ops; 2138 host->quirks = chip->quirks; 2139 host->quirks2 = chip->quirks2; 2140 2141 host->irq = pdev->irq; 2142 2143 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 2144 if (ret) { 2145 dev_err(&pdev->dev, "cannot request region\n"); 2146 goto cleanup; 2147 } 2148 2149 host->ioaddr = pcim_iomap_table(pdev)[bar]; 2150 2151 if (chip->fixes && chip->fixes->probe_slot) { 2152 ret = chip->fixes->probe_slot(slot); 2153 if (ret) 2154 goto cleanup; 2155 } 2156 2157 if (gpio_is_valid(slot->rst_n_gpio)) { 2158 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 2159 gpio_direction_output(slot->rst_n_gpio, 1); 2160 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 2161 slot->hw_reset = sdhci_pci_gpio_hw_reset; 2162 } else { 2163 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 2164 slot->rst_n_gpio = -EINVAL; 2165 } 2166 } 2167 2168 host->mmc->pm_caps = MMC_PM_KEEP_POWER; 2169 host->mmc->slotno = slotno; 2170 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 2171 2172 if (device_can_wakeup(&pdev->dev)) 2173 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ; 2174 2175 if (host->mmc->caps & MMC_CAP_CD_WAKE) 2176 device_init_wakeup(&pdev->dev, true); 2177 2178 if (slot->cd_idx >= 0) { 2179 ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx, 2180 slot->cd_override_level, 0); 2181 if (ret && ret != -EPROBE_DEFER) 2182 ret = mmc_gpiod_request_cd(host->mmc, NULL, 2183 slot->cd_idx, 2184 slot->cd_override_level, 2185 0); 2186 if (ret == -EPROBE_DEFER) 2187 goto remove; 2188 2189 if (ret) { 2190 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 2191 slot->cd_idx = -1; 2192 } 2193 } 2194 2195 if (chip->fixes && chip->fixes->add_host) 2196 ret = chip->fixes->add_host(slot); 2197 else 2198 ret = sdhci_add_host(host); 2199 if (ret) 2200 goto remove; 2201 2202 sdhci_pci_add_own_cd(slot); 2203 2204 /* 2205 * Check if the chip needs a separate GPIO for card detect to wake up 2206 * from runtime suspend. If it is not there, don't allow runtime PM. 2207 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 2208 */ 2209 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 2210 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 2211 chip->allow_runtime_pm = false; 2212 2213 return slot; 2214 2215 remove: 2216 if (chip->fixes && chip->fixes->remove_slot) 2217 chip->fixes->remove_slot(slot, 0); 2218 2219 cleanup: 2220 sdhci_free_host(host); 2221 2222 return ERR_PTR(ret); 2223 } 2224 2225 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 2226 { 2227 int dead; 2228 u32 scratch; 2229 2230 sdhci_pci_remove_own_cd(slot); 2231 2232 dead = 0; 2233 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 2234 if (scratch == (u32)-1) 2235 dead = 1; 2236 2237 sdhci_remove_host(slot->host, dead); 2238 2239 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 2240 slot->chip->fixes->remove_slot(slot, dead); 2241 2242 sdhci_free_host(slot->host); 2243 } 2244 2245 static void sdhci_pci_runtime_pm_allow(struct device *dev) 2246 { 2247 pm_suspend_ignore_children(dev, 1); 2248 pm_runtime_set_autosuspend_delay(dev, 50); 2249 pm_runtime_use_autosuspend(dev); 2250 pm_runtime_allow(dev); 2251 /* Stay active until mmc core scans for a card */ 2252 pm_runtime_put_noidle(dev); 2253 } 2254 2255 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 2256 { 2257 pm_runtime_forbid(dev); 2258 pm_runtime_get_noresume(dev); 2259 } 2260 2261 static int sdhci_pci_probe(struct pci_dev *pdev, 2262 const struct pci_device_id *ent) 2263 { 2264 struct sdhci_pci_chip *chip; 2265 struct sdhci_pci_slot *slot; 2266 2267 u8 slots, first_bar; 2268 int ret, i; 2269 2270 BUG_ON(pdev == NULL); 2271 BUG_ON(ent == NULL); 2272 2273 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 2274 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 2275 2276 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 2277 if (ret) 2278 return ret; 2279 2280 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 2281 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 2282 2283 BUG_ON(slots > MAX_SLOTS); 2284 2285 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 2286 if (ret) 2287 return ret; 2288 2289 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 2290 2291 if (first_bar > 5) { 2292 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 2293 return -ENODEV; 2294 } 2295 2296 ret = pcim_enable_device(pdev); 2297 if (ret) 2298 return ret; 2299 2300 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 2301 if (!chip) 2302 return -ENOMEM; 2303 2304 chip->pdev = pdev; 2305 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 2306 if (chip->fixes) { 2307 chip->quirks = chip->fixes->quirks; 2308 chip->quirks2 = chip->fixes->quirks2; 2309 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 2310 } 2311 chip->num_slots = slots; 2312 chip->pm_retune = true; 2313 chip->rpm_retune = true; 2314 2315 pci_set_drvdata(pdev, chip); 2316 2317 if (chip->fixes && chip->fixes->probe) { 2318 ret = chip->fixes->probe(chip); 2319 if (ret) 2320 return ret; 2321 } 2322 2323 slots = chip->num_slots; /* Quirk may have changed this */ 2324 2325 for (i = 0; i < slots; i++) { 2326 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 2327 if (IS_ERR(slot)) { 2328 for (i--; i >= 0; i--) 2329 sdhci_pci_remove_slot(chip->slots[i]); 2330 return PTR_ERR(slot); 2331 } 2332 2333 chip->slots[i] = slot; 2334 } 2335 2336 if (chip->allow_runtime_pm) 2337 sdhci_pci_runtime_pm_allow(&pdev->dev); 2338 2339 return 0; 2340 } 2341 2342 static void sdhci_pci_remove(struct pci_dev *pdev) 2343 { 2344 int i; 2345 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 2346 2347 if (chip->allow_runtime_pm) 2348 sdhci_pci_runtime_pm_forbid(&pdev->dev); 2349 2350 for (i = 0; i < chip->num_slots; i++) 2351 sdhci_pci_remove_slot(chip->slots[i]); 2352 } 2353 2354 static struct pci_driver sdhci_driver = { 2355 .name = "sdhci-pci", 2356 .id_table = pci_ids, 2357 .probe = sdhci_pci_probe, 2358 .remove = sdhci_pci_remove, 2359 .driver = { 2360 .pm = &sdhci_pci_pm_ops 2361 }, 2362 }; 2363 2364 module_pci_driver(sdhci_driver); 2365 2366 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 2367 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 2368 MODULE_LICENSE("GPL"); 2369