1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 2 * 3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 * 10 * Thanks to the following companies for their support: 11 * 12 * - JMicron (hardware and technical support) 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/highmem.h> 17 #include <linux/module.h> 18 #include <linux/pci.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/slab.h> 21 #include <linux/device.h> 22 #include <linux/mmc/host.h> 23 #include <linux/mmc/mmc.h> 24 #include <linux/scatterlist.h> 25 #include <linux/io.h> 26 #include <linux/gpio.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/mmc/slot-gpio.h> 29 #include <linux/mmc/sdhci-pci-data.h> 30 #include <linux/acpi.h> 31 32 #include "sdhci.h" 33 #include "sdhci-pci.h" 34 #include "sdhci-pci-o2micro.h" 35 36 static int sdhci_pci_enable_dma(struct sdhci_host *host); 37 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width); 38 static void sdhci_pci_hw_reset(struct sdhci_host *host); 39 static int sdhci_pci_select_drive_strength(struct sdhci_host *host, 40 struct mmc_card *card, 41 unsigned int max_dtr, int host_drv, 42 int card_drv, int *drv_type); 43 44 /*****************************************************************************\ 45 * * 46 * Hardware specific quirk handling * 47 * * 48 \*****************************************************************************/ 49 50 static int ricoh_probe(struct sdhci_pci_chip *chip) 51 { 52 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 53 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 54 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 55 return 0; 56 } 57 58 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 59 { 60 slot->host->caps = 61 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 62 & SDHCI_TIMEOUT_CLK_MASK) | 63 64 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 65 & SDHCI_CLOCK_BASE_MASK) | 66 67 SDHCI_TIMEOUT_CLK_UNIT | 68 SDHCI_CAN_VDD_330 | 69 SDHCI_CAN_DO_HISPD | 70 SDHCI_CAN_DO_SDMA; 71 return 0; 72 } 73 74 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 75 { 76 /* Apply a delay to allow controller to settle */ 77 /* Otherwise it becomes confused if card state changed 78 during suspend */ 79 msleep(500); 80 return 0; 81 } 82 83 static const struct sdhci_pci_fixes sdhci_ricoh = { 84 .probe = ricoh_probe, 85 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 86 SDHCI_QUIRK_FORCE_DMA | 87 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 88 }; 89 90 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 91 .probe_slot = ricoh_mmc_probe_slot, 92 .resume = ricoh_mmc_resume, 93 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 94 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 95 SDHCI_QUIRK_NO_CARD_NO_RESET | 96 SDHCI_QUIRK_MISSING_CAPS 97 }; 98 99 static const struct sdhci_pci_fixes sdhci_ene_712 = { 100 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 101 SDHCI_QUIRK_BROKEN_DMA, 102 }; 103 104 static const struct sdhci_pci_fixes sdhci_ene_714 = { 105 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 106 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 107 SDHCI_QUIRK_BROKEN_DMA, 108 }; 109 110 static const struct sdhci_pci_fixes sdhci_cafe = { 111 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 112 SDHCI_QUIRK_NO_BUSY_IRQ | 113 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 114 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 115 }; 116 117 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 118 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 119 }; 120 121 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 122 { 123 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 124 return 0; 125 } 126 127 /* 128 * ADMA operation is disabled for Moorestown platform due to 129 * hardware bugs. 130 */ 131 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 132 { 133 /* 134 * slots number is fixed here for MRST as SDIO3/5 are never used and 135 * have hardware bugs. 136 */ 137 chip->num_slots = 1; 138 return 0; 139 } 140 141 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 142 { 143 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 144 return 0; 145 } 146 147 #ifdef CONFIG_PM 148 149 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 150 { 151 struct sdhci_pci_slot *slot = dev_id; 152 struct sdhci_host *host = slot->host; 153 154 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 155 return IRQ_HANDLED; 156 } 157 158 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 159 { 160 int err, irq, gpio = slot->cd_gpio; 161 162 slot->cd_gpio = -EINVAL; 163 slot->cd_irq = -EINVAL; 164 165 if (!gpio_is_valid(gpio)) 166 return; 167 168 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 169 if (err < 0) 170 goto out; 171 172 err = gpio_direction_input(gpio); 173 if (err < 0) 174 goto out_free; 175 176 irq = gpio_to_irq(gpio); 177 if (irq < 0) 178 goto out_free; 179 180 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 181 IRQF_TRIGGER_FALLING, "sd_cd", slot); 182 if (err) 183 goto out_free; 184 185 slot->cd_gpio = gpio; 186 slot->cd_irq = irq; 187 188 return; 189 190 out_free: 191 devm_gpio_free(&slot->chip->pdev->dev, gpio); 192 out: 193 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 194 } 195 196 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 197 { 198 if (slot->cd_irq >= 0) 199 free_irq(slot->cd_irq, slot); 200 } 201 202 #else 203 204 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 205 { 206 } 207 208 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 209 { 210 } 211 212 #endif 213 214 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 215 { 216 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 217 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC | 218 MMC_CAP2_HC_ERASE_SZ; 219 return 0; 220 } 221 222 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 223 { 224 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 225 return 0; 226 } 227 228 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 229 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 230 .probe_slot = mrst_hc_probe_slot, 231 }; 232 233 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 234 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 235 .probe = mrst_hc_probe, 236 }; 237 238 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 239 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 240 .allow_runtime_pm = true, 241 .own_cd_for_runtime_pm = true, 242 }; 243 244 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 245 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 246 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 247 .allow_runtime_pm = true, 248 .probe_slot = mfd_sdio_probe_slot, 249 }; 250 251 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 252 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 253 .allow_runtime_pm = true, 254 .probe_slot = mfd_emmc_probe_slot, 255 }; 256 257 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 258 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 259 .probe_slot = pch_hc_probe_slot, 260 }; 261 262 enum { 263 INTEL_DSM_FNS = 0, 264 INTEL_DSM_DRV_STRENGTH = 9, 265 INTEL_DSM_D3_RETUNE = 10, 266 }; 267 268 struct intel_host { 269 u32 dsm_fns; 270 int drv_strength; 271 bool d3_retune; 272 }; 273 274 const u8 intel_dsm_uuid[] = { 275 0xA5, 0x3E, 0xC1, 0xF6, 0xCD, 0x65, 0x1F, 0x46, 276 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61, 277 }; 278 279 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 280 unsigned int fn, u32 *result) 281 { 282 union acpi_object *obj; 283 int err = 0; 284 285 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), intel_dsm_uuid, 0, fn, NULL); 286 if (!obj) 287 return -EOPNOTSUPP; 288 289 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { 290 err = -EINVAL; 291 goto out; 292 } 293 294 if (obj->buffer.length >= 4) 295 *result = *(u32 *)obj->buffer.pointer; 296 else if (obj->buffer.length >= 2) 297 *result = *(u16 *)obj->buffer.pointer; 298 else 299 *result = *(u8 *)obj->buffer.pointer; 300 out: 301 ACPI_FREE(obj); 302 303 return err; 304 } 305 306 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 307 unsigned int fn, u32 *result) 308 { 309 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 310 return -EOPNOTSUPP; 311 312 return __intel_dsm(intel_host, dev, fn, result); 313 } 314 315 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 316 struct mmc_host *mmc) 317 { 318 int err; 319 u32 val; 320 321 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 322 if (err) { 323 pr_debug("%s: DSM not supported, error %d\n", 324 mmc_hostname(mmc), err); 325 return; 326 } 327 328 pr_debug("%s: DSM function mask %#x\n", 329 mmc_hostname(mmc), intel_host->dsm_fns); 330 331 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 332 intel_host->drv_strength = err ? 0 : val; 333 334 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 335 intel_host->d3_retune = err ? true : !!val; 336 } 337 338 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 339 { 340 u8 reg; 341 342 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 343 reg |= 0x10; 344 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 345 /* For eMMC, minimum is 1us but give it 9us for good measure */ 346 udelay(9); 347 reg &= ~0x10; 348 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 349 /* For eMMC, minimum is 200us but give it 300us for good measure */ 350 usleep_range(300, 1000); 351 } 352 353 static int intel_select_drive_strength(struct mmc_card *card, 354 unsigned int max_dtr, int host_drv, 355 int card_drv, int *drv_type) 356 { 357 struct sdhci_host *host = mmc_priv(card->host); 358 struct sdhci_pci_slot *slot = sdhci_priv(host); 359 struct intel_host *intel_host = sdhci_pci_priv(slot); 360 361 return intel_host->drv_strength; 362 } 363 364 static int bxt_get_cd(struct mmc_host *mmc) 365 { 366 int gpio_cd = mmc_gpio_get_cd(mmc); 367 struct sdhci_host *host = mmc_priv(mmc); 368 unsigned long flags; 369 int ret = 0; 370 371 if (!gpio_cd) 372 return 0; 373 374 spin_lock_irqsave(&host->lock, flags); 375 376 if (host->flags & SDHCI_DEVICE_DEAD) 377 goto out; 378 379 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 380 out: 381 spin_unlock_irqrestore(&host->lock, flags); 382 383 return ret; 384 } 385 386 static void byt_read_dsm(struct sdhci_pci_slot *slot) 387 { 388 struct intel_host *intel_host = sdhci_pci_priv(slot); 389 struct device *dev = &slot->chip->pdev->dev; 390 struct mmc_host *mmc = slot->host->mmc; 391 392 intel_dsm_init(intel_host, dev, mmc); 393 slot->chip->rpm_retune = intel_host->d3_retune; 394 } 395 396 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 397 { 398 byt_read_dsm(slot); 399 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 400 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 401 MMC_CAP_CMD_DURING_TFR | 402 MMC_CAP_WAIT_WHILE_BUSY; 403 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ; 404 slot->hw_reset = sdhci_pci_int_hw_reset; 405 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 406 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 407 slot->host->mmc_host_ops.select_drive_strength = 408 intel_select_drive_strength; 409 return 0; 410 } 411 412 #ifdef CONFIG_ACPI 413 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 414 { 415 acpi_status status; 416 unsigned long long max_freq; 417 418 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 419 "MXFQ", NULL, &max_freq); 420 if (ACPI_FAILURE(status)) { 421 dev_err(&slot->chip->pdev->dev, 422 "MXFQ not found in acpi table\n"); 423 return -EINVAL; 424 } 425 426 slot->host->mmc->f_max = max_freq * 1000000; 427 428 return 0; 429 } 430 #else 431 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 432 { 433 return 0; 434 } 435 #endif 436 437 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 438 { 439 int err; 440 441 byt_read_dsm(slot); 442 443 err = ni_set_max_freq(slot); 444 if (err) 445 return err; 446 447 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 448 MMC_CAP_WAIT_WHILE_BUSY; 449 return 0; 450 } 451 452 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 453 { 454 byt_read_dsm(slot); 455 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 456 MMC_CAP_WAIT_WHILE_BUSY; 457 return 0; 458 } 459 460 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 461 { 462 byt_read_dsm(slot); 463 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 464 slot->cd_idx = 0; 465 slot->cd_override_level = true; 466 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 467 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 468 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 469 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) { 470 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 471 slot->host->mmc->caps |= MMC_CAP_AGGRESSIVE_PM; 472 } 473 474 return 0; 475 } 476 477 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 478 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 479 480 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 481 unsigned short vdd) 482 { 483 int cntr; 484 u8 reg; 485 486 sdhci_set_power(host, mode, vdd); 487 488 if (mode == MMC_POWER_OFF) 489 return; 490 491 spin_unlock_irq(&host->lock); 492 493 /* 494 * Bus power might not enable after D3 -> D0 transition due to the 495 * present state not yet having propagated. Retry for up to 2ms. 496 */ 497 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 498 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 499 if (reg & SDHCI_POWER_ON) 500 break; 501 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 502 reg |= SDHCI_POWER_ON; 503 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 504 } 505 506 spin_lock_irq(&host->lock); 507 } 508 509 static const struct sdhci_ops sdhci_intel_byt_ops = { 510 .set_clock = sdhci_set_clock, 511 .set_power = sdhci_intel_set_power, 512 .enable_dma = sdhci_pci_enable_dma, 513 .set_bus_width = sdhci_pci_set_bus_width, 514 .reset = sdhci_reset, 515 .set_uhs_signaling = sdhci_set_uhs_signaling, 516 .hw_reset = sdhci_pci_hw_reset, 517 .select_drive_strength = sdhci_pci_select_drive_strength, 518 }; 519 520 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 521 .allow_runtime_pm = true, 522 .probe_slot = byt_emmc_probe_slot, 523 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 524 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 525 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 526 SDHCI_QUIRK2_STOP_WITH_TC, 527 .ops = &sdhci_intel_byt_ops, 528 .priv_size = sizeof(struct intel_host), 529 }; 530 531 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 532 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 533 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 534 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 535 .allow_runtime_pm = true, 536 .probe_slot = ni_byt_sdio_probe_slot, 537 .ops = &sdhci_intel_byt_ops, 538 .priv_size = sizeof(struct intel_host), 539 }; 540 541 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 542 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 543 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 544 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 545 .allow_runtime_pm = true, 546 .probe_slot = byt_sdio_probe_slot, 547 .ops = &sdhci_intel_byt_ops, 548 .priv_size = sizeof(struct intel_host), 549 }; 550 551 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 552 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 553 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 554 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 555 SDHCI_QUIRK2_STOP_WITH_TC, 556 .allow_runtime_pm = true, 557 .own_cd_for_runtime_pm = true, 558 .probe_slot = byt_sd_probe_slot, 559 .ops = &sdhci_intel_byt_ops, 560 .priv_size = sizeof(struct intel_host), 561 }; 562 563 /* Define Host controllers for Intel Merrifield platform */ 564 #define INTEL_MRFLD_EMMC_0 0 565 #define INTEL_MRFLD_EMMC_1 1 566 #define INTEL_MRFLD_SD 2 567 #define INTEL_MRFLD_SDIO 3 568 569 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 570 { 571 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 572 573 switch (func) { 574 case INTEL_MRFLD_EMMC_0: 575 case INTEL_MRFLD_EMMC_1: 576 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 577 MMC_CAP_8_BIT_DATA | 578 MMC_CAP_1_8V_DDR; 579 break; 580 case INTEL_MRFLD_SD: 581 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 582 break; 583 case INTEL_MRFLD_SDIO: 584 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 585 MMC_CAP_POWER_OFF_CARD; 586 break; 587 default: 588 return -ENODEV; 589 } 590 return 0; 591 } 592 593 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 594 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 595 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 596 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 597 .allow_runtime_pm = true, 598 .probe_slot = intel_mrfld_mmc_probe_slot, 599 }; 600 601 /* O2Micro extra registers */ 602 #define O2_SD_LOCK_WP 0xD3 603 #define O2_SD_MULTI_VCC3V 0xEE 604 #define O2_SD_CLKREQ 0xEC 605 #define O2_SD_CAPS 0xE0 606 #define O2_SD_ADMA1 0xE2 607 #define O2_SD_ADMA2 0xE7 608 #define O2_SD_INF_MOD 0xF1 609 610 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 611 { 612 u8 scratch; 613 int ret; 614 615 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 616 if (ret) 617 return ret; 618 619 /* 620 * Turn PMOS on [bit 0], set over current detection to 2.4 V 621 * [bit 1:2] and enable over current debouncing [bit 6]. 622 */ 623 if (on) 624 scratch |= 0x47; 625 else 626 scratch &= ~0x47; 627 628 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 629 } 630 631 static int jmicron_probe(struct sdhci_pci_chip *chip) 632 { 633 int ret; 634 u16 mmcdev = 0; 635 636 if (chip->pdev->revision == 0) { 637 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 638 SDHCI_QUIRK_32BIT_DMA_SIZE | 639 SDHCI_QUIRK_32BIT_ADMA_SIZE | 640 SDHCI_QUIRK_RESET_AFTER_REQUEST | 641 SDHCI_QUIRK_BROKEN_SMALL_PIO; 642 } 643 644 /* 645 * JMicron chips can have two interfaces to the same hardware 646 * in order to work around limitations in Microsoft's driver. 647 * We need to make sure we only bind to one of them. 648 * 649 * This code assumes two things: 650 * 651 * 1. The PCI code adds subfunctions in order. 652 * 653 * 2. The MMC interface has a lower subfunction number 654 * than the SD interface. 655 */ 656 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 657 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 658 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 659 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 660 661 if (mmcdev) { 662 struct pci_dev *sd_dev; 663 664 sd_dev = NULL; 665 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 666 mmcdev, sd_dev)) != NULL) { 667 if ((PCI_SLOT(chip->pdev->devfn) == 668 PCI_SLOT(sd_dev->devfn)) && 669 (chip->pdev->bus == sd_dev->bus)) 670 break; 671 } 672 673 if (sd_dev) { 674 pci_dev_put(sd_dev); 675 dev_info(&chip->pdev->dev, "Refusing to bind to " 676 "secondary interface.\n"); 677 return -ENODEV; 678 } 679 } 680 681 /* 682 * JMicron chips need a bit of a nudge to enable the power 683 * output pins. 684 */ 685 ret = jmicron_pmos(chip, 1); 686 if (ret) { 687 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 688 return ret; 689 } 690 691 /* quirk for unsable RO-detection on JM388 chips */ 692 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 693 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 694 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 695 696 return 0; 697 } 698 699 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 700 { 701 u8 scratch; 702 703 scratch = readb(host->ioaddr + 0xC0); 704 705 if (on) 706 scratch |= 0x01; 707 else 708 scratch &= ~0x01; 709 710 writeb(scratch, host->ioaddr + 0xC0); 711 } 712 713 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 714 { 715 if (slot->chip->pdev->revision == 0) { 716 u16 version; 717 718 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 719 version = (version & SDHCI_VENDOR_VER_MASK) >> 720 SDHCI_VENDOR_VER_SHIFT; 721 722 /* 723 * Older versions of the chip have lots of nasty glitches 724 * in the ADMA engine. It's best just to avoid it 725 * completely. 726 */ 727 if (version < 0xAC) 728 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 729 } 730 731 /* JM388 MMC doesn't support 1.8V while SD supports it */ 732 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 733 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 734 MMC_VDD_29_30 | MMC_VDD_30_31 | 735 MMC_VDD_165_195; /* allow 1.8V */ 736 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 737 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 738 } 739 740 /* 741 * The secondary interface requires a bit set to get the 742 * interrupts. 743 */ 744 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 745 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 746 jmicron_enable_mmc(slot->host, 1); 747 748 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 749 750 return 0; 751 } 752 753 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 754 { 755 if (dead) 756 return; 757 758 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 759 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 760 jmicron_enable_mmc(slot->host, 0); 761 } 762 763 static int jmicron_suspend(struct sdhci_pci_chip *chip) 764 { 765 int i; 766 767 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 768 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 769 for (i = 0; i < chip->num_slots; i++) 770 jmicron_enable_mmc(chip->slots[i]->host, 0); 771 } 772 773 return 0; 774 } 775 776 static int jmicron_resume(struct sdhci_pci_chip *chip) 777 { 778 int ret, i; 779 780 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 781 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 782 for (i = 0; i < chip->num_slots; i++) 783 jmicron_enable_mmc(chip->slots[i]->host, 1); 784 } 785 786 ret = jmicron_pmos(chip, 1); 787 if (ret) { 788 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 789 return ret; 790 } 791 792 return 0; 793 } 794 795 static const struct sdhci_pci_fixes sdhci_o2 = { 796 .probe = sdhci_pci_o2_probe, 797 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 798 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 799 .probe_slot = sdhci_pci_o2_probe_slot, 800 .resume = sdhci_pci_o2_resume, 801 }; 802 803 static const struct sdhci_pci_fixes sdhci_jmicron = { 804 .probe = jmicron_probe, 805 806 .probe_slot = jmicron_probe_slot, 807 .remove_slot = jmicron_remove_slot, 808 809 .suspend = jmicron_suspend, 810 .resume = jmicron_resume, 811 }; 812 813 /* SysKonnect CardBus2SDIO extra registers */ 814 #define SYSKT_CTRL 0x200 815 #define SYSKT_RDFIFO_STAT 0x204 816 #define SYSKT_WRFIFO_STAT 0x208 817 #define SYSKT_POWER_DATA 0x20c 818 #define SYSKT_POWER_330 0xef 819 #define SYSKT_POWER_300 0xf8 820 #define SYSKT_POWER_184 0xcc 821 #define SYSKT_POWER_CMD 0x20d 822 #define SYSKT_POWER_START (1 << 7) 823 #define SYSKT_POWER_STATUS 0x20e 824 #define SYSKT_POWER_STATUS_OK (1 << 0) 825 #define SYSKT_BOARD_REV 0x210 826 #define SYSKT_CHIP_REV 0x211 827 #define SYSKT_CONF_DATA 0x212 828 #define SYSKT_CONF_DATA_1V8 (1 << 2) 829 #define SYSKT_CONF_DATA_2V5 (1 << 1) 830 #define SYSKT_CONF_DATA_3V3 (1 << 0) 831 832 static int syskt_probe(struct sdhci_pci_chip *chip) 833 { 834 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 835 chip->pdev->class &= ~0x0000FF; 836 chip->pdev->class |= PCI_SDHCI_IFDMA; 837 } 838 return 0; 839 } 840 841 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 842 { 843 int tm, ps; 844 845 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 846 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 847 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 848 "board rev %d.%d, chip rev %d.%d\n", 849 board_rev >> 4, board_rev & 0xf, 850 chip_rev >> 4, chip_rev & 0xf); 851 if (chip_rev >= 0x20) 852 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 853 854 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 855 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 856 udelay(50); 857 tm = 10; /* Wait max 1 ms */ 858 do { 859 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 860 if (ps & SYSKT_POWER_STATUS_OK) 861 break; 862 udelay(100); 863 } while (--tm); 864 if (!tm) { 865 dev_err(&slot->chip->pdev->dev, 866 "power regulator never stabilized"); 867 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 868 return -ENODEV; 869 } 870 871 return 0; 872 } 873 874 static const struct sdhci_pci_fixes sdhci_syskt = { 875 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 876 .probe = syskt_probe, 877 .probe_slot = syskt_probe_slot, 878 }; 879 880 static int via_probe(struct sdhci_pci_chip *chip) 881 { 882 if (chip->pdev->revision == 0x10) 883 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 884 885 return 0; 886 } 887 888 static const struct sdhci_pci_fixes sdhci_via = { 889 .probe = via_probe, 890 }; 891 892 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 893 { 894 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 895 return 0; 896 } 897 898 static const struct sdhci_pci_fixes sdhci_rtsx = { 899 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 900 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 901 SDHCI_QUIRK2_BROKEN_DDR50, 902 .probe_slot = rtsx_probe_slot, 903 }; 904 905 /*AMD chipset generation*/ 906 enum amd_chipset_gen { 907 AMD_CHIPSET_BEFORE_ML, 908 AMD_CHIPSET_CZ, 909 AMD_CHIPSET_NL, 910 AMD_CHIPSET_UNKNOWN, 911 }; 912 913 /* AMD registers */ 914 #define AMD_SD_AUTO_PATTERN 0xB8 915 #define AMD_MSLEEP_DURATION 4 916 #define AMD_SD_MISC_CONTROL 0xD0 917 #define AMD_MAX_TUNE_VALUE 0x0B 918 #define AMD_AUTO_TUNE_SEL 0x10800 919 #define AMD_FIFO_PTR 0x30 920 #define AMD_BIT_MASK 0x1F 921 922 static void amd_tuning_reset(struct sdhci_host *host) 923 { 924 unsigned int val; 925 926 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 927 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 928 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 929 930 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 931 val &= ~SDHCI_CTRL_EXEC_TUNING; 932 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 933 } 934 935 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 936 { 937 unsigned int val; 938 939 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 940 val &= ~AMD_BIT_MASK; 941 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 942 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 943 } 944 945 static void amd_enable_manual_tuning(struct pci_dev *pdev) 946 { 947 unsigned int val; 948 949 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 950 val |= AMD_FIFO_PTR; 951 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 952 } 953 954 static int amd_execute_tuning(struct sdhci_host *host, u32 opcode) 955 { 956 struct sdhci_pci_slot *slot = sdhci_priv(host); 957 struct pci_dev *pdev = slot->chip->pdev; 958 u8 valid_win = 0; 959 u8 valid_win_max = 0; 960 u8 valid_win_end = 0; 961 u8 ctrl, tune_around; 962 963 amd_tuning_reset(host); 964 965 for (tune_around = 0; tune_around < 12; tune_around++) { 966 amd_config_tuning_phase(pdev, tune_around); 967 968 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 969 valid_win = 0; 970 msleep(AMD_MSLEEP_DURATION); 971 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 972 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 973 } else if (++valid_win > valid_win_max) { 974 valid_win_max = valid_win; 975 valid_win_end = tune_around; 976 } 977 } 978 979 if (!valid_win_max) { 980 dev_err(&pdev->dev, "no tuning point found\n"); 981 return -EIO; 982 } 983 984 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 985 986 amd_enable_manual_tuning(pdev); 987 988 host->mmc->retune_period = 0; 989 990 return 0; 991 } 992 993 static int amd_probe(struct sdhci_pci_chip *chip) 994 { 995 struct pci_dev *smbus_dev; 996 enum amd_chipset_gen gen; 997 998 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 999 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 1000 if (smbus_dev) { 1001 gen = AMD_CHIPSET_BEFORE_ML; 1002 } else { 1003 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1004 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1005 if (smbus_dev) { 1006 if (smbus_dev->revision < 0x51) 1007 gen = AMD_CHIPSET_CZ; 1008 else 1009 gen = AMD_CHIPSET_NL; 1010 } else { 1011 gen = AMD_CHIPSET_UNKNOWN; 1012 } 1013 } 1014 1015 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1016 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1017 1018 return 0; 1019 } 1020 1021 static const struct sdhci_ops amd_sdhci_pci_ops = { 1022 .set_clock = sdhci_set_clock, 1023 .enable_dma = sdhci_pci_enable_dma, 1024 .set_bus_width = sdhci_pci_set_bus_width, 1025 .reset = sdhci_reset, 1026 .set_uhs_signaling = sdhci_set_uhs_signaling, 1027 .platform_execute_tuning = amd_execute_tuning, 1028 }; 1029 1030 static const struct sdhci_pci_fixes sdhci_amd = { 1031 .probe = amd_probe, 1032 .ops = &amd_sdhci_pci_ops, 1033 }; 1034 1035 static const struct pci_device_id pci_ids[] = { 1036 { 1037 .vendor = PCI_VENDOR_ID_RICOH, 1038 .device = PCI_DEVICE_ID_RICOH_R5C822, 1039 .subvendor = PCI_ANY_ID, 1040 .subdevice = PCI_ANY_ID, 1041 .driver_data = (kernel_ulong_t)&sdhci_ricoh, 1042 }, 1043 1044 { 1045 .vendor = PCI_VENDOR_ID_RICOH, 1046 .device = 0x843, 1047 .subvendor = PCI_ANY_ID, 1048 .subdevice = PCI_ANY_ID, 1049 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 1050 }, 1051 1052 { 1053 .vendor = PCI_VENDOR_ID_RICOH, 1054 .device = 0xe822, 1055 .subvendor = PCI_ANY_ID, 1056 .subdevice = PCI_ANY_ID, 1057 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 1058 }, 1059 1060 { 1061 .vendor = PCI_VENDOR_ID_RICOH, 1062 .device = 0xe823, 1063 .subvendor = PCI_ANY_ID, 1064 .subdevice = PCI_ANY_ID, 1065 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 1066 }, 1067 1068 { 1069 .vendor = PCI_VENDOR_ID_ENE, 1070 .device = PCI_DEVICE_ID_ENE_CB712_SD, 1071 .subvendor = PCI_ANY_ID, 1072 .subdevice = PCI_ANY_ID, 1073 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 1074 }, 1075 1076 { 1077 .vendor = PCI_VENDOR_ID_ENE, 1078 .device = PCI_DEVICE_ID_ENE_CB712_SD_2, 1079 .subvendor = PCI_ANY_ID, 1080 .subdevice = PCI_ANY_ID, 1081 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 1082 }, 1083 1084 { 1085 .vendor = PCI_VENDOR_ID_ENE, 1086 .device = PCI_DEVICE_ID_ENE_CB714_SD, 1087 .subvendor = PCI_ANY_ID, 1088 .subdevice = PCI_ANY_ID, 1089 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 1090 }, 1091 1092 { 1093 .vendor = PCI_VENDOR_ID_ENE, 1094 .device = PCI_DEVICE_ID_ENE_CB714_SD_2, 1095 .subvendor = PCI_ANY_ID, 1096 .subdevice = PCI_ANY_ID, 1097 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 1098 }, 1099 1100 { 1101 .vendor = PCI_VENDOR_ID_MARVELL, 1102 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD, 1103 .subvendor = PCI_ANY_ID, 1104 .subdevice = PCI_ANY_ID, 1105 .driver_data = (kernel_ulong_t)&sdhci_cafe, 1106 }, 1107 1108 { 1109 .vendor = PCI_VENDOR_ID_JMICRON, 1110 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD, 1111 .subvendor = PCI_ANY_ID, 1112 .subdevice = PCI_ANY_ID, 1113 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1114 }, 1115 1116 { 1117 .vendor = PCI_VENDOR_ID_JMICRON, 1118 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC, 1119 .subvendor = PCI_ANY_ID, 1120 .subdevice = PCI_ANY_ID, 1121 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1122 }, 1123 1124 { 1125 .vendor = PCI_VENDOR_ID_JMICRON, 1126 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD, 1127 .subvendor = PCI_ANY_ID, 1128 .subdevice = PCI_ANY_ID, 1129 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1130 }, 1131 1132 { 1133 .vendor = PCI_VENDOR_ID_JMICRON, 1134 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD, 1135 .subvendor = PCI_ANY_ID, 1136 .subdevice = PCI_ANY_ID, 1137 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1138 }, 1139 1140 { 1141 .vendor = PCI_VENDOR_ID_SYSKONNECT, 1142 .device = 0x8000, 1143 .subvendor = PCI_ANY_ID, 1144 .subdevice = PCI_ANY_ID, 1145 .driver_data = (kernel_ulong_t)&sdhci_syskt, 1146 }, 1147 1148 { 1149 .vendor = PCI_VENDOR_ID_VIA, 1150 .device = 0x95d0, 1151 .subvendor = PCI_ANY_ID, 1152 .subdevice = PCI_ANY_ID, 1153 .driver_data = (kernel_ulong_t)&sdhci_via, 1154 }, 1155 1156 { 1157 .vendor = PCI_VENDOR_ID_REALTEK, 1158 .device = 0x5250, 1159 .subvendor = PCI_ANY_ID, 1160 .subdevice = PCI_ANY_ID, 1161 .driver_data = (kernel_ulong_t)&sdhci_rtsx, 1162 }, 1163 1164 { 1165 .vendor = PCI_VENDOR_ID_INTEL, 1166 .device = PCI_DEVICE_ID_INTEL_QRK_SD, 1167 .subvendor = PCI_ANY_ID, 1168 .subdevice = PCI_ANY_ID, 1169 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk, 1170 }, 1171 1172 { 1173 .vendor = PCI_VENDOR_ID_INTEL, 1174 .device = PCI_DEVICE_ID_INTEL_MRST_SD0, 1175 .subvendor = PCI_ANY_ID, 1176 .subdevice = PCI_ANY_ID, 1177 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0, 1178 }, 1179 1180 { 1181 .vendor = PCI_VENDOR_ID_INTEL, 1182 .device = PCI_DEVICE_ID_INTEL_MRST_SD1, 1183 .subvendor = PCI_ANY_ID, 1184 .subdevice = PCI_ANY_ID, 1185 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 1186 }, 1187 1188 { 1189 .vendor = PCI_VENDOR_ID_INTEL, 1190 .device = PCI_DEVICE_ID_INTEL_MRST_SD2, 1191 .subvendor = PCI_ANY_ID, 1192 .subdevice = PCI_ANY_ID, 1193 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 1194 }, 1195 1196 { 1197 .vendor = PCI_VENDOR_ID_INTEL, 1198 .device = PCI_DEVICE_ID_INTEL_MFD_SD, 1199 .subvendor = PCI_ANY_ID, 1200 .subdevice = PCI_ANY_ID, 1201 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1202 }, 1203 1204 { 1205 .vendor = PCI_VENDOR_ID_INTEL, 1206 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1, 1207 .subvendor = PCI_ANY_ID, 1208 .subdevice = PCI_ANY_ID, 1209 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1210 }, 1211 1212 { 1213 .vendor = PCI_VENDOR_ID_INTEL, 1214 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2, 1215 .subvendor = PCI_ANY_ID, 1216 .subdevice = PCI_ANY_ID, 1217 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1218 }, 1219 1220 { 1221 .vendor = PCI_VENDOR_ID_INTEL, 1222 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0, 1223 .subvendor = PCI_ANY_ID, 1224 .subdevice = PCI_ANY_ID, 1225 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1226 }, 1227 1228 { 1229 .vendor = PCI_VENDOR_ID_INTEL, 1230 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1, 1231 .subvendor = PCI_ANY_ID, 1232 .subdevice = PCI_ANY_ID, 1233 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1234 }, 1235 1236 { 1237 .vendor = PCI_VENDOR_ID_INTEL, 1238 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0, 1239 .subvendor = PCI_ANY_ID, 1240 .subdevice = PCI_ANY_ID, 1241 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1242 }, 1243 1244 { 1245 .vendor = PCI_VENDOR_ID_INTEL, 1246 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1, 1247 .subvendor = PCI_ANY_ID, 1248 .subdevice = PCI_ANY_ID, 1249 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1250 }, 1251 1252 { 1253 .vendor = PCI_VENDOR_ID_INTEL, 1254 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC, 1255 .subvendor = PCI_ANY_ID, 1256 .subdevice = PCI_ANY_ID, 1257 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1258 }, 1259 1260 { 1261 .vendor = PCI_VENDOR_ID_INTEL, 1262 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, 1263 .subvendor = PCI_VENDOR_ID_NI, 1264 .subdevice = 0x7884, 1265 .driver_data = (kernel_ulong_t)&sdhci_ni_byt_sdio, 1266 }, 1267 1268 { 1269 .vendor = PCI_VENDOR_ID_INTEL, 1270 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, 1271 .subvendor = PCI_ANY_ID, 1272 .subdevice = PCI_ANY_ID, 1273 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1274 }, 1275 1276 { 1277 .vendor = PCI_VENDOR_ID_INTEL, 1278 .device = PCI_DEVICE_ID_INTEL_BYT_SD, 1279 .subvendor = PCI_ANY_ID, 1280 .subdevice = PCI_ANY_ID, 1281 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1282 }, 1283 1284 { 1285 .vendor = PCI_VENDOR_ID_INTEL, 1286 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2, 1287 .subvendor = PCI_ANY_ID, 1288 .subdevice = PCI_ANY_ID, 1289 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1290 }, 1291 1292 { 1293 .vendor = PCI_VENDOR_ID_INTEL, 1294 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC, 1295 .subvendor = PCI_ANY_ID, 1296 .subdevice = PCI_ANY_ID, 1297 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1298 }, 1299 1300 { 1301 .vendor = PCI_VENDOR_ID_INTEL, 1302 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO, 1303 .subvendor = PCI_ANY_ID, 1304 .subdevice = PCI_ANY_ID, 1305 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1306 }, 1307 1308 { 1309 .vendor = PCI_VENDOR_ID_INTEL, 1310 .device = PCI_DEVICE_ID_INTEL_BSW_SD, 1311 .subvendor = PCI_ANY_ID, 1312 .subdevice = PCI_ANY_ID, 1313 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1314 }, 1315 1316 { 1317 .vendor = PCI_VENDOR_ID_INTEL, 1318 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0, 1319 .subvendor = PCI_ANY_ID, 1320 .subdevice = PCI_ANY_ID, 1321 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1322 }, 1323 1324 { 1325 .vendor = PCI_VENDOR_ID_INTEL, 1326 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1, 1327 .subvendor = PCI_ANY_ID, 1328 .subdevice = PCI_ANY_ID, 1329 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1330 }, 1331 1332 { 1333 .vendor = PCI_VENDOR_ID_INTEL, 1334 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2, 1335 .subvendor = PCI_ANY_ID, 1336 .subdevice = PCI_ANY_ID, 1337 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1338 }, 1339 1340 { 1341 .vendor = PCI_VENDOR_ID_INTEL, 1342 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0, 1343 .subvendor = PCI_ANY_ID, 1344 .subdevice = PCI_ANY_ID, 1345 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1346 }, 1347 1348 { 1349 .vendor = PCI_VENDOR_ID_INTEL, 1350 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1, 1351 .subvendor = PCI_ANY_ID, 1352 .subdevice = PCI_ANY_ID, 1353 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1354 }, 1355 1356 { 1357 .vendor = PCI_VENDOR_ID_INTEL, 1358 .device = PCI_DEVICE_ID_INTEL_MRFLD_MMC, 1359 .subvendor = PCI_ANY_ID, 1360 .subdevice = PCI_ANY_ID, 1361 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfld_mmc, 1362 }, 1363 1364 { 1365 .vendor = PCI_VENDOR_ID_INTEL, 1366 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC, 1367 .subvendor = PCI_ANY_ID, 1368 .subdevice = PCI_ANY_ID, 1369 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1370 }, 1371 1372 { 1373 .vendor = PCI_VENDOR_ID_INTEL, 1374 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO, 1375 .subvendor = PCI_ANY_ID, 1376 .subdevice = PCI_ANY_ID, 1377 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1378 }, 1379 1380 { 1381 .vendor = PCI_VENDOR_ID_INTEL, 1382 .device = PCI_DEVICE_ID_INTEL_SPT_SD, 1383 .subvendor = PCI_ANY_ID, 1384 .subdevice = PCI_ANY_ID, 1385 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1386 }, 1387 1388 { 1389 .vendor = PCI_VENDOR_ID_INTEL, 1390 .device = PCI_DEVICE_ID_INTEL_DNV_EMMC, 1391 .subvendor = PCI_ANY_ID, 1392 .subdevice = PCI_ANY_ID, 1393 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1394 }, 1395 1396 { 1397 .vendor = PCI_VENDOR_ID_INTEL, 1398 .device = PCI_DEVICE_ID_INTEL_BXT_EMMC, 1399 .subvendor = PCI_ANY_ID, 1400 .subdevice = PCI_ANY_ID, 1401 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1402 }, 1403 1404 { 1405 .vendor = PCI_VENDOR_ID_INTEL, 1406 .device = PCI_DEVICE_ID_INTEL_BXT_SDIO, 1407 .subvendor = PCI_ANY_ID, 1408 .subdevice = PCI_ANY_ID, 1409 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1410 }, 1411 1412 { 1413 .vendor = PCI_VENDOR_ID_INTEL, 1414 .device = PCI_DEVICE_ID_INTEL_BXT_SD, 1415 .subvendor = PCI_ANY_ID, 1416 .subdevice = PCI_ANY_ID, 1417 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1418 }, 1419 1420 { 1421 .vendor = PCI_VENDOR_ID_INTEL, 1422 .device = PCI_DEVICE_ID_INTEL_BXTM_EMMC, 1423 .subvendor = PCI_ANY_ID, 1424 .subdevice = PCI_ANY_ID, 1425 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1426 }, 1427 1428 { 1429 .vendor = PCI_VENDOR_ID_INTEL, 1430 .device = PCI_DEVICE_ID_INTEL_BXTM_SDIO, 1431 .subvendor = PCI_ANY_ID, 1432 .subdevice = PCI_ANY_ID, 1433 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1434 }, 1435 1436 { 1437 .vendor = PCI_VENDOR_ID_INTEL, 1438 .device = PCI_DEVICE_ID_INTEL_BXTM_SD, 1439 .subvendor = PCI_ANY_ID, 1440 .subdevice = PCI_ANY_ID, 1441 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1442 }, 1443 1444 { 1445 .vendor = PCI_VENDOR_ID_INTEL, 1446 .device = PCI_DEVICE_ID_INTEL_APL_EMMC, 1447 .subvendor = PCI_ANY_ID, 1448 .subdevice = PCI_ANY_ID, 1449 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1450 }, 1451 1452 { 1453 .vendor = PCI_VENDOR_ID_INTEL, 1454 .device = PCI_DEVICE_ID_INTEL_APL_SDIO, 1455 .subvendor = PCI_ANY_ID, 1456 .subdevice = PCI_ANY_ID, 1457 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1458 }, 1459 1460 { 1461 .vendor = PCI_VENDOR_ID_INTEL, 1462 .device = PCI_DEVICE_ID_INTEL_APL_SD, 1463 .subvendor = PCI_ANY_ID, 1464 .subdevice = PCI_ANY_ID, 1465 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1466 }, 1467 1468 { 1469 .vendor = PCI_VENDOR_ID_INTEL, 1470 .device = PCI_DEVICE_ID_INTEL_GLK_EMMC, 1471 .subvendor = PCI_ANY_ID, 1472 .subdevice = PCI_ANY_ID, 1473 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1474 }, 1475 1476 { 1477 .vendor = PCI_VENDOR_ID_INTEL, 1478 .device = PCI_DEVICE_ID_INTEL_GLK_SDIO, 1479 .subvendor = PCI_ANY_ID, 1480 .subdevice = PCI_ANY_ID, 1481 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1482 }, 1483 1484 { 1485 .vendor = PCI_VENDOR_ID_INTEL, 1486 .device = PCI_DEVICE_ID_INTEL_GLK_SD, 1487 .subvendor = PCI_ANY_ID, 1488 .subdevice = PCI_ANY_ID, 1489 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1490 }, 1491 1492 { 1493 .vendor = PCI_VENDOR_ID_O2, 1494 .device = PCI_DEVICE_ID_O2_8120, 1495 .subvendor = PCI_ANY_ID, 1496 .subdevice = PCI_ANY_ID, 1497 .driver_data = (kernel_ulong_t)&sdhci_o2, 1498 }, 1499 1500 { 1501 .vendor = PCI_VENDOR_ID_O2, 1502 .device = PCI_DEVICE_ID_O2_8220, 1503 .subvendor = PCI_ANY_ID, 1504 .subdevice = PCI_ANY_ID, 1505 .driver_data = (kernel_ulong_t)&sdhci_o2, 1506 }, 1507 1508 { 1509 .vendor = PCI_VENDOR_ID_O2, 1510 .device = PCI_DEVICE_ID_O2_8221, 1511 .subvendor = PCI_ANY_ID, 1512 .subdevice = PCI_ANY_ID, 1513 .driver_data = (kernel_ulong_t)&sdhci_o2, 1514 }, 1515 1516 { 1517 .vendor = PCI_VENDOR_ID_O2, 1518 .device = PCI_DEVICE_ID_O2_8320, 1519 .subvendor = PCI_ANY_ID, 1520 .subdevice = PCI_ANY_ID, 1521 .driver_data = (kernel_ulong_t)&sdhci_o2, 1522 }, 1523 1524 { 1525 .vendor = PCI_VENDOR_ID_O2, 1526 .device = PCI_DEVICE_ID_O2_8321, 1527 .subvendor = PCI_ANY_ID, 1528 .subdevice = PCI_ANY_ID, 1529 .driver_data = (kernel_ulong_t)&sdhci_o2, 1530 }, 1531 1532 { 1533 .vendor = PCI_VENDOR_ID_O2, 1534 .device = PCI_DEVICE_ID_O2_FUJIN2, 1535 .subvendor = PCI_ANY_ID, 1536 .subdevice = PCI_ANY_ID, 1537 .driver_data = (kernel_ulong_t)&sdhci_o2, 1538 }, 1539 1540 { 1541 .vendor = PCI_VENDOR_ID_O2, 1542 .device = PCI_DEVICE_ID_O2_SDS0, 1543 .subvendor = PCI_ANY_ID, 1544 .subdevice = PCI_ANY_ID, 1545 .driver_data = (kernel_ulong_t)&sdhci_o2, 1546 }, 1547 1548 { 1549 .vendor = PCI_VENDOR_ID_O2, 1550 .device = PCI_DEVICE_ID_O2_SDS1, 1551 .subvendor = PCI_ANY_ID, 1552 .subdevice = PCI_ANY_ID, 1553 .driver_data = (kernel_ulong_t)&sdhci_o2, 1554 }, 1555 1556 { 1557 .vendor = PCI_VENDOR_ID_O2, 1558 .device = PCI_DEVICE_ID_O2_SEABIRD0, 1559 .subvendor = PCI_ANY_ID, 1560 .subdevice = PCI_ANY_ID, 1561 .driver_data = (kernel_ulong_t)&sdhci_o2, 1562 }, 1563 1564 { 1565 .vendor = PCI_VENDOR_ID_O2, 1566 .device = PCI_DEVICE_ID_O2_SEABIRD1, 1567 .subvendor = PCI_ANY_ID, 1568 .subdevice = PCI_ANY_ID, 1569 .driver_data = (kernel_ulong_t)&sdhci_o2, 1570 }, 1571 { 1572 .vendor = PCI_VENDOR_ID_AMD, 1573 .device = PCI_ANY_ID, 1574 .class = PCI_CLASS_SYSTEM_SDHCI << 8, 1575 .class_mask = 0xFFFF00, 1576 .subvendor = PCI_ANY_ID, 1577 .subdevice = PCI_ANY_ID, 1578 .driver_data = (kernel_ulong_t)&sdhci_amd, 1579 }, 1580 { /* Generic SD host controller */ 1581 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) 1582 }, 1583 1584 { /* end: all zeroes */ }, 1585 }; 1586 1587 MODULE_DEVICE_TABLE(pci, pci_ids); 1588 1589 /*****************************************************************************\ 1590 * * 1591 * SDHCI core callbacks * 1592 * * 1593 \*****************************************************************************/ 1594 1595 static int sdhci_pci_enable_dma(struct sdhci_host *host) 1596 { 1597 struct sdhci_pci_slot *slot; 1598 struct pci_dev *pdev; 1599 1600 slot = sdhci_priv(host); 1601 pdev = slot->chip->pdev; 1602 1603 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1604 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1605 (host->flags & SDHCI_USE_SDMA)) { 1606 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1607 "doesn't fully claim to support it.\n"); 1608 } 1609 1610 pci_set_master(pdev); 1611 1612 return 0; 1613 } 1614 1615 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width) 1616 { 1617 u8 ctrl; 1618 1619 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1620 1621 switch (width) { 1622 case MMC_BUS_WIDTH_8: 1623 ctrl |= SDHCI_CTRL_8BITBUS; 1624 ctrl &= ~SDHCI_CTRL_4BITBUS; 1625 break; 1626 case MMC_BUS_WIDTH_4: 1627 ctrl |= SDHCI_CTRL_4BITBUS; 1628 ctrl &= ~SDHCI_CTRL_8BITBUS; 1629 break; 1630 default: 1631 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS); 1632 break; 1633 } 1634 1635 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1636 } 1637 1638 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1639 { 1640 struct sdhci_pci_slot *slot = sdhci_priv(host); 1641 int rst_n_gpio = slot->rst_n_gpio; 1642 1643 if (!gpio_is_valid(rst_n_gpio)) 1644 return; 1645 gpio_set_value_cansleep(rst_n_gpio, 0); 1646 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1647 udelay(10); 1648 gpio_set_value_cansleep(rst_n_gpio, 1); 1649 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1650 usleep_range(300, 1000); 1651 } 1652 1653 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1654 { 1655 struct sdhci_pci_slot *slot = sdhci_priv(host); 1656 1657 if (slot->hw_reset) 1658 slot->hw_reset(host); 1659 } 1660 1661 static int sdhci_pci_select_drive_strength(struct sdhci_host *host, 1662 struct mmc_card *card, 1663 unsigned int max_dtr, int host_drv, 1664 int card_drv, int *drv_type) 1665 { 1666 struct sdhci_pci_slot *slot = sdhci_priv(host); 1667 1668 if (!slot->select_drive_strength) 1669 return 0; 1670 1671 return slot->select_drive_strength(host, card, max_dtr, host_drv, 1672 card_drv, drv_type); 1673 } 1674 1675 static const struct sdhci_ops sdhci_pci_ops = { 1676 .set_clock = sdhci_set_clock, 1677 .enable_dma = sdhci_pci_enable_dma, 1678 .set_bus_width = sdhci_pci_set_bus_width, 1679 .reset = sdhci_reset, 1680 .set_uhs_signaling = sdhci_set_uhs_signaling, 1681 .hw_reset = sdhci_pci_hw_reset, 1682 .select_drive_strength = sdhci_pci_select_drive_strength, 1683 }; 1684 1685 /*****************************************************************************\ 1686 * * 1687 * Suspend/resume * 1688 * * 1689 \*****************************************************************************/ 1690 1691 #ifdef CONFIG_PM_SLEEP 1692 static int sdhci_pci_suspend(struct device *dev) 1693 { 1694 struct pci_dev *pdev = to_pci_dev(dev); 1695 struct sdhci_pci_chip *chip; 1696 struct sdhci_pci_slot *slot; 1697 struct sdhci_host *host; 1698 mmc_pm_flag_t slot_pm_flags; 1699 mmc_pm_flag_t pm_flags = 0; 1700 int i, ret; 1701 1702 chip = pci_get_drvdata(pdev); 1703 if (!chip) 1704 return 0; 1705 1706 for (i = 0; i < chip->num_slots; i++) { 1707 slot = chip->slots[i]; 1708 if (!slot) 1709 continue; 1710 1711 host = slot->host; 1712 1713 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 1714 mmc_retune_needed(host->mmc); 1715 1716 ret = sdhci_suspend_host(host); 1717 1718 if (ret) 1719 goto err_pci_suspend; 1720 1721 slot_pm_flags = host->mmc->pm_flags; 1722 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1723 sdhci_enable_irq_wakeups(host); 1724 1725 pm_flags |= slot_pm_flags; 1726 } 1727 1728 if (chip->fixes && chip->fixes->suspend) { 1729 ret = chip->fixes->suspend(chip); 1730 if (ret) 1731 goto err_pci_suspend; 1732 } 1733 1734 if (pm_flags & MMC_PM_KEEP_POWER) { 1735 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1736 device_init_wakeup(dev, true); 1737 else 1738 device_init_wakeup(dev, false); 1739 } else 1740 device_init_wakeup(dev, false); 1741 1742 return 0; 1743 1744 err_pci_suspend: 1745 while (--i >= 0) 1746 sdhci_resume_host(chip->slots[i]->host); 1747 return ret; 1748 } 1749 1750 static int sdhci_pci_resume(struct device *dev) 1751 { 1752 struct pci_dev *pdev = to_pci_dev(dev); 1753 struct sdhci_pci_chip *chip; 1754 struct sdhci_pci_slot *slot; 1755 int i, ret; 1756 1757 chip = pci_get_drvdata(pdev); 1758 if (!chip) 1759 return 0; 1760 1761 if (chip->fixes && chip->fixes->resume) { 1762 ret = chip->fixes->resume(chip); 1763 if (ret) 1764 return ret; 1765 } 1766 1767 for (i = 0; i < chip->num_slots; i++) { 1768 slot = chip->slots[i]; 1769 if (!slot) 1770 continue; 1771 1772 ret = sdhci_resume_host(slot->host); 1773 if (ret) 1774 return ret; 1775 } 1776 1777 return 0; 1778 } 1779 #endif 1780 1781 #ifdef CONFIG_PM 1782 static int sdhci_pci_runtime_suspend(struct device *dev) 1783 { 1784 struct pci_dev *pdev = to_pci_dev(dev); 1785 struct sdhci_pci_chip *chip; 1786 struct sdhci_pci_slot *slot; 1787 struct sdhci_host *host; 1788 int i, ret; 1789 1790 chip = pci_get_drvdata(pdev); 1791 if (!chip) 1792 return 0; 1793 1794 for (i = 0; i < chip->num_slots; i++) { 1795 slot = chip->slots[i]; 1796 if (!slot) 1797 continue; 1798 1799 host = slot->host; 1800 1801 ret = sdhci_runtime_suspend_host(host); 1802 if (ret) 1803 goto err_pci_runtime_suspend; 1804 1805 if (chip->rpm_retune && 1806 host->tuning_mode != SDHCI_TUNING_MODE_3) 1807 mmc_retune_needed(host->mmc); 1808 } 1809 1810 if (chip->fixes && chip->fixes->suspend) { 1811 ret = chip->fixes->suspend(chip); 1812 if (ret) 1813 goto err_pci_runtime_suspend; 1814 } 1815 1816 return 0; 1817 1818 err_pci_runtime_suspend: 1819 while (--i >= 0) 1820 sdhci_runtime_resume_host(chip->slots[i]->host); 1821 return ret; 1822 } 1823 1824 static int sdhci_pci_runtime_resume(struct device *dev) 1825 { 1826 struct pci_dev *pdev = to_pci_dev(dev); 1827 struct sdhci_pci_chip *chip; 1828 struct sdhci_pci_slot *slot; 1829 int i, ret; 1830 1831 chip = pci_get_drvdata(pdev); 1832 if (!chip) 1833 return 0; 1834 1835 if (chip->fixes && chip->fixes->resume) { 1836 ret = chip->fixes->resume(chip); 1837 if (ret) 1838 return ret; 1839 } 1840 1841 for (i = 0; i < chip->num_slots; i++) { 1842 slot = chip->slots[i]; 1843 if (!slot) 1844 continue; 1845 1846 ret = sdhci_runtime_resume_host(slot->host); 1847 if (ret) 1848 return ret; 1849 } 1850 1851 return 0; 1852 } 1853 #endif 1854 1855 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1856 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1857 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1858 sdhci_pci_runtime_resume, NULL) 1859 }; 1860 1861 /*****************************************************************************\ 1862 * * 1863 * Device probing/removal * 1864 * * 1865 \*****************************************************************************/ 1866 1867 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1868 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1869 int slotno) 1870 { 1871 struct sdhci_pci_slot *slot; 1872 struct sdhci_host *host; 1873 int ret, bar = first_bar + slotno; 1874 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 1875 1876 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1877 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1878 return ERR_PTR(-ENODEV); 1879 } 1880 1881 if (pci_resource_len(pdev, bar) < 0x100) { 1882 dev_err(&pdev->dev, "Invalid iomem size. You may " 1883 "experience problems.\n"); 1884 } 1885 1886 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1887 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1888 return ERR_PTR(-ENODEV); 1889 } 1890 1891 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1892 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1893 return ERR_PTR(-ENODEV); 1894 } 1895 1896 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 1897 if (IS_ERR(host)) { 1898 dev_err(&pdev->dev, "cannot allocate host\n"); 1899 return ERR_CAST(host); 1900 } 1901 1902 slot = sdhci_priv(host); 1903 1904 slot->chip = chip; 1905 slot->host = host; 1906 slot->rst_n_gpio = -EINVAL; 1907 slot->cd_gpio = -EINVAL; 1908 slot->cd_idx = -1; 1909 1910 /* Retrieve platform data if there is any */ 1911 if (*sdhci_pci_get_data) 1912 slot->data = sdhci_pci_get_data(pdev, slotno); 1913 1914 if (slot->data) { 1915 if (slot->data->setup) { 1916 ret = slot->data->setup(slot->data); 1917 if (ret) { 1918 dev_err(&pdev->dev, "platform setup failed\n"); 1919 goto free; 1920 } 1921 } 1922 slot->rst_n_gpio = slot->data->rst_n_gpio; 1923 slot->cd_gpio = slot->data->cd_gpio; 1924 } 1925 1926 host->hw_name = "PCI"; 1927 host->ops = chip->fixes && chip->fixes->ops ? 1928 chip->fixes->ops : 1929 &sdhci_pci_ops; 1930 host->quirks = chip->quirks; 1931 host->quirks2 = chip->quirks2; 1932 1933 host->irq = pdev->irq; 1934 1935 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1936 if (ret) { 1937 dev_err(&pdev->dev, "cannot request region\n"); 1938 goto cleanup; 1939 } 1940 1941 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1942 1943 if (chip->fixes && chip->fixes->probe_slot) { 1944 ret = chip->fixes->probe_slot(slot); 1945 if (ret) 1946 goto cleanup; 1947 } 1948 1949 if (gpio_is_valid(slot->rst_n_gpio)) { 1950 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1951 gpio_direction_output(slot->rst_n_gpio, 1); 1952 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1953 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1954 } else { 1955 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1956 slot->rst_n_gpio = -EINVAL; 1957 } 1958 } 1959 1960 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; 1961 host->mmc->slotno = slotno; 1962 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1963 1964 if (slot->cd_idx >= 0) { 1965 ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx, 1966 slot->cd_override_level, 0, NULL); 1967 if (ret == -EPROBE_DEFER) 1968 goto remove; 1969 1970 if (ret) { 1971 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 1972 slot->cd_idx = -1; 1973 } 1974 } 1975 1976 ret = sdhci_add_host(host); 1977 if (ret) 1978 goto remove; 1979 1980 sdhci_pci_add_own_cd(slot); 1981 1982 /* 1983 * Check if the chip needs a separate GPIO for card detect to wake up 1984 * from runtime suspend. If it is not there, don't allow runtime PM. 1985 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 1986 */ 1987 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 1988 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 1989 chip->allow_runtime_pm = false; 1990 1991 return slot; 1992 1993 remove: 1994 if (chip->fixes && chip->fixes->remove_slot) 1995 chip->fixes->remove_slot(slot, 0); 1996 1997 cleanup: 1998 if (slot->data && slot->data->cleanup) 1999 slot->data->cleanup(slot->data); 2000 2001 free: 2002 sdhci_free_host(host); 2003 2004 return ERR_PTR(ret); 2005 } 2006 2007 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 2008 { 2009 int dead; 2010 u32 scratch; 2011 2012 sdhci_pci_remove_own_cd(slot); 2013 2014 dead = 0; 2015 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 2016 if (scratch == (u32)-1) 2017 dead = 1; 2018 2019 sdhci_remove_host(slot->host, dead); 2020 2021 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 2022 slot->chip->fixes->remove_slot(slot, dead); 2023 2024 if (slot->data && slot->data->cleanup) 2025 slot->data->cleanup(slot->data); 2026 2027 sdhci_free_host(slot->host); 2028 } 2029 2030 static void sdhci_pci_runtime_pm_allow(struct device *dev) 2031 { 2032 pm_suspend_ignore_children(dev, 1); 2033 pm_runtime_set_autosuspend_delay(dev, 50); 2034 pm_runtime_use_autosuspend(dev); 2035 pm_runtime_allow(dev); 2036 /* Stay active until mmc core scans for a card */ 2037 pm_runtime_put_noidle(dev); 2038 } 2039 2040 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 2041 { 2042 pm_runtime_forbid(dev); 2043 pm_runtime_get_noresume(dev); 2044 } 2045 2046 static int sdhci_pci_probe(struct pci_dev *pdev, 2047 const struct pci_device_id *ent) 2048 { 2049 struct sdhci_pci_chip *chip; 2050 struct sdhci_pci_slot *slot; 2051 2052 u8 slots, first_bar; 2053 int ret, i; 2054 2055 BUG_ON(pdev == NULL); 2056 BUG_ON(ent == NULL); 2057 2058 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 2059 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 2060 2061 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 2062 if (ret) 2063 return ret; 2064 2065 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 2066 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 2067 if (slots == 0) 2068 return -ENODEV; 2069 2070 BUG_ON(slots > MAX_SLOTS); 2071 2072 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 2073 if (ret) 2074 return ret; 2075 2076 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 2077 2078 if (first_bar > 5) { 2079 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 2080 return -ENODEV; 2081 } 2082 2083 ret = pcim_enable_device(pdev); 2084 if (ret) 2085 return ret; 2086 2087 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 2088 if (!chip) 2089 return -ENOMEM; 2090 2091 chip->pdev = pdev; 2092 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 2093 if (chip->fixes) { 2094 chip->quirks = chip->fixes->quirks; 2095 chip->quirks2 = chip->fixes->quirks2; 2096 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 2097 } 2098 chip->num_slots = slots; 2099 chip->pm_retune = true; 2100 chip->rpm_retune = true; 2101 2102 pci_set_drvdata(pdev, chip); 2103 2104 if (chip->fixes && chip->fixes->probe) { 2105 ret = chip->fixes->probe(chip); 2106 if (ret) 2107 return ret; 2108 } 2109 2110 slots = chip->num_slots; /* Quirk may have changed this */ 2111 2112 for (i = 0; i < slots; i++) { 2113 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 2114 if (IS_ERR(slot)) { 2115 for (i--; i >= 0; i--) 2116 sdhci_pci_remove_slot(chip->slots[i]); 2117 return PTR_ERR(slot); 2118 } 2119 2120 chip->slots[i] = slot; 2121 } 2122 2123 if (chip->allow_runtime_pm) 2124 sdhci_pci_runtime_pm_allow(&pdev->dev); 2125 2126 return 0; 2127 } 2128 2129 static void sdhci_pci_remove(struct pci_dev *pdev) 2130 { 2131 int i; 2132 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 2133 2134 if (chip->allow_runtime_pm) 2135 sdhci_pci_runtime_pm_forbid(&pdev->dev); 2136 2137 for (i = 0; i < chip->num_slots; i++) 2138 sdhci_pci_remove_slot(chip->slots[i]); 2139 } 2140 2141 static struct pci_driver sdhci_driver = { 2142 .name = "sdhci-pci", 2143 .id_table = pci_ids, 2144 .probe = sdhci_pci_probe, 2145 .remove = sdhci_pci_remove, 2146 .driver = { 2147 .pm = &sdhci_pci_pm_ops 2148 }, 2149 }; 2150 2151 module_pci_driver(sdhci_driver); 2152 2153 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 2154 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 2155 MODULE_LICENSE("GPL"); 2156