1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 3 * 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 5 * 6 * Thanks to the following companies for their support: 7 * 8 * - JMicron (hardware and technical support) 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/string.h> 13 #include <linux/delay.h> 14 #include <linux/highmem.h> 15 #include <linux/module.h> 16 #include <linux/pci.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/slab.h> 19 #include <linux/device.h> 20 #include <linux/mmc/host.h> 21 #include <linux/mmc/mmc.h> 22 #include <linux/scatterlist.h> 23 #include <linux/io.h> 24 #include <linux/iopoll.h> 25 #include <linux/gpio.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/pm_qos.h> 28 #include <linux/debugfs.h> 29 #include <linux/mmc/slot-gpio.h> 30 #include <linux/mmc/sdhci-pci-data.h> 31 #include <linux/acpi.h> 32 #include <linux/dmi.h> 33 34 #ifdef CONFIG_X86 35 #include <asm/iosf_mbi.h> 36 #endif 37 38 #include "cqhci.h" 39 40 #include "sdhci.h" 41 #include "sdhci-pci.h" 42 43 static void sdhci_pci_hw_reset(struct sdhci_host *host); 44 45 #ifdef CONFIG_PM_SLEEP 46 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip) 47 { 48 mmc_pm_flag_t pm_flags = 0; 49 bool cap_cd_wake = false; 50 int i; 51 52 for (i = 0; i < chip->num_slots; i++) { 53 struct sdhci_pci_slot *slot = chip->slots[i]; 54 55 if (slot) { 56 pm_flags |= slot->host->mmc->pm_flags; 57 if (slot->host->mmc->caps & MMC_CAP_CD_WAKE) 58 cap_cd_wake = true; 59 } 60 } 61 62 if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ)) 63 return device_wakeup_enable(&chip->pdev->dev); 64 else if (!cap_cd_wake) 65 return device_wakeup_disable(&chip->pdev->dev); 66 67 return 0; 68 } 69 70 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 71 { 72 int i, ret; 73 74 sdhci_pci_init_wakeup(chip); 75 76 for (i = 0; i < chip->num_slots; i++) { 77 struct sdhci_pci_slot *slot = chip->slots[i]; 78 struct sdhci_host *host; 79 80 if (!slot) 81 continue; 82 83 host = slot->host; 84 85 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 86 mmc_retune_needed(host->mmc); 87 88 ret = sdhci_suspend_host(host); 89 if (ret) 90 goto err_pci_suspend; 91 92 if (device_may_wakeup(&chip->pdev->dev)) 93 mmc_gpio_set_cd_wake(host->mmc, true); 94 } 95 96 return 0; 97 98 err_pci_suspend: 99 while (--i >= 0) 100 sdhci_resume_host(chip->slots[i]->host); 101 return ret; 102 } 103 104 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip) 105 { 106 struct sdhci_pci_slot *slot; 107 int i, ret; 108 109 for (i = 0; i < chip->num_slots; i++) { 110 slot = chip->slots[i]; 111 if (!slot) 112 continue; 113 114 ret = sdhci_resume_host(slot->host); 115 if (ret) 116 return ret; 117 118 mmc_gpio_set_cd_wake(slot->host->mmc, false); 119 } 120 121 return 0; 122 } 123 124 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip) 125 { 126 int ret; 127 128 ret = cqhci_suspend(chip->slots[0]->host->mmc); 129 if (ret) 130 return ret; 131 132 return sdhci_pci_suspend_host(chip); 133 } 134 135 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip) 136 { 137 int ret; 138 139 ret = sdhci_pci_resume_host(chip); 140 if (ret) 141 return ret; 142 143 return cqhci_resume(chip->slots[0]->host->mmc); 144 } 145 #endif 146 147 #ifdef CONFIG_PM 148 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip) 149 { 150 struct sdhci_pci_slot *slot; 151 struct sdhci_host *host; 152 int i, ret; 153 154 for (i = 0; i < chip->num_slots; i++) { 155 slot = chip->slots[i]; 156 if (!slot) 157 continue; 158 159 host = slot->host; 160 161 ret = sdhci_runtime_suspend_host(host); 162 if (ret) 163 goto err_pci_runtime_suspend; 164 165 if (chip->rpm_retune && 166 host->tuning_mode != SDHCI_TUNING_MODE_3) 167 mmc_retune_needed(host->mmc); 168 } 169 170 return 0; 171 172 err_pci_runtime_suspend: 173 while (--i >= 0) 174 sdhci_runtime_resume_host(chip->slots[i]->host, 0); 175 return ret; 176 } 177 178 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip) 179 { 180 struct sdhci_pci_slot *slot; 181 int i, ret; 182 183 for (i = 0; i < chip->num_slots; i++) { 184 slot = chip->slots[i]; 185 if (!slot) 186 continue; 187 188 ret = sdhci_runtime_resume_host(slot->host, 0); 189 if (ret) 190 return ret; 191 } 192 193 return 0; 194 } 195 196 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip) 197 { 198 int ret; 199 200 ret = cqhci_suspend(chip->slots[0]->host->mmc); 201 if (ret) 202 return ret; 203 204 return sdhci_pci_runtime_suspend_host(chip); 205 } 206 207 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip) 208 { 209 int ret; 210 211 ret = sdhci_pci_runtime_resume_host(chip); 212 if (ret) 213 return ret; 214 215 return cqhci_resume(chip->slots[0]->host->mmc); 216 } 217 #endif 218 219 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask) 220 { 221 int cmd_error = 0; 222 int data_error = 0; 223 224 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 225 return intmask; 226 227 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 228 229 return 0; 230 } 231 232 static void sdhci_pci_dumpregs(struct mmc_host *mmc) 233 { 234 sdhci_dumpregs(mmc_priv(mmc)); 235 } 236 237 static void sdhci_cqhci_reset(struct sdhci_host *host, u8 mask) 238 { 239 if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) && 240 host->mmc->cqe_private) 241 cqhci_deactivate(host->mmc); 242 sdhci_reset(host, mask); 243 } 244 245 /*****************************************************************************\ 246 * * 247 * Hardware specific quirk handling * 248 * * 249 \*****************************************************************************/ 250 251 static int ricoh_probe(struct sdhci_pci_chip *chip) 252 { 253 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 254 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 255 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 256 return 0; 257 } 258 259 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 260 { 261 slot->host->caps = 262 FIELD_PREP(SDHCI_TIMEOUT_CLK_MASK, 0x21) | 263 FIELD_PREP(SDHCI_CLOCK_BASE_MASK, 0x21) | 264 SDHCI_TIMEOUT_CLK_UNIT | 265 SDHCI_CAN_VDD_330 | 266 SDHCI_CAN_DO_HISPD | 267 SDHCI_CAN_DO_SDMA; 268 return 0; 269 } 270 271 #ifdef CONFIG_PM_SLEEP 272 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 273 { 274 /* Apply a delay to allow controller to settle */ 275 /* Otherwise it becomes confused if card state changed 276 during suspend */ 277 msleep(500); 278 return sdhci_pci_resume_host(chip); 279 } 280 #endif 281 282 static const struct sdhci_pci_fixes sdhci_ricoh = { 283 .probe = ricoh_probe, 284 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 285 SDHCI_QUIRK_FORCE_DMA | 286 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 287 }; 288 289 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 290 .probe_slot = ricoh_mmc_probe_slot, 291 #ifdef CONFIG_PM_SLEEP 292 .resume = ricoh_mmc_resume, 293 #endif 294 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 295 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 296 SDHCI_QUIRK_NO_CARD_NO_RESET | 297 SDHCI_QUIRK_MISSING_CAPS 298 }; 299 300 static const struct sdhci_pci_fixes sdhci_ene_712 = { 301 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 302 SDHCI_QUIRK_BROKEN_DMA, 303 }; 304 305 static const struct sdhci_pci_fixes sdhci_ene_714 = { 306 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 307 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 308 SDHCI_QUIRK_BROKEN_DMA, 309 }; 310 311 static const struct sdhci_pci_fixes sdhci_cafe = { 312 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 313 SDHCI_QUIRK_NO_BUSY_IRQ | 314 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 315 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 316 }; 317 318 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 319 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 320 }; 321 322 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 323 { 324 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 325 return 0; 326 } 327 328 /* 329 * ADMA operation is disabled for Moorestown platform due to 330 * hardware bugs. 331 */ 332 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 333 { 334 /* 335 * slots number is fixed here for MRST as SDIO3/5 are never used and 336 * have hardware bugs. 337 */ 338 chip->num_slots = 1; 339 return 0; 340 } 341 342 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 343 { 344 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 345 return 0; 346 } 347 348 #ifdef CONFIG_PM 349 350 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 351 { 352 struct sdhci_pci_slot *slot = dev_id; 353 struct sdhci_host *host = slot->host; 354 355 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 356 return IRQ_HANDLED; 357 } 358 359 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 360 { 361 int err, irq, gpio = slot->cd_gpio; 362 363 slot->cd_gpio = -EINVAL; 364 slot->cd_irq = -EINVAL; 365 366 if (!gpio_is_valid(gpio)) 367 return; 368 369 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 370 if (err < 0) 371 goto out; 372 373 err = gpio_direction_input(gpio); 374 if (err < 0) 375 goto out_free; 376 377 irq = gpio_to_irq(gpio); 378 if (irq < 0) 379 goto out_free; 380 381 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 382 IRQF_TRIGGER_FALLING, "sd_cd", slot); 383 if (err) 384 goto out_free; 385 386 slot->cd_gpio = gpio; 387 slot->cd_irq = irq; 388 389 return; 390 391 out_free: 392 devm_gpio_free(&slot->chip->pdev->dev, gpio); 393 out: 394 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 395 } 396 397 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 398 { 399 if (slot->cd_irq >= 0) 400 free_irq(slot->cd_irq, slot); 401 } 402 403 #else 404 405 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 406 { 407 } 408 409 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 410 { 411 } 412 413 #endif 414 415 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 416 { 417 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 418 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC; 419 return 0; 420 } 421 422 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 423 { 424 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 425 return 0; 426 } 427 428 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 429 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 430 .probe_slot = mrst_hc_probe_slot, 431 }; 432 433 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 434 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 435 .probe = mrst_hc_probe, 436 }; 437 438 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 439 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 440 .allow_runtime_pm = true, 441 .own_cd_for_runtime_pm = true, 442 }; 443 444 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 445 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 446 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 447 .allow_runtime_pm = true, 448 .probe_slot = mfd_sdio_probe_slot, 449 }; 450 451 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 452 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 453 .allow_runtime_pm = true, 454 .probe_slot = mfd_emmc_probe_slot, 455 }; 456 457 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 458 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 459 .probe_slot = pch_hc_probe_slot, 460 }; 461 462 #ifdef CONFIG_X86 463 464 #define BYT_IOSF_SCCEP 0x63 465 #define BYT_IOSF_OCP_NETCTRL0 0x1078 466 #define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8) 467 468 static void byt_ocp_setting(struct pci_dev *pdev) 469 { 470 u32 val = 0; 471 472 if (pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC && 473 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SDIO && 474 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SD && 475 pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC2) 476 return; 477 478 if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0, 479 &val)) { 480 dev_err(&pdev->dev, "%s read error\n", __func__); 481 return; 482 } 483 484 if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE)) 485 return; 486 487 val &= ~BYT_IOSF_OCP_TIMEOUT_BASE; 488 489 if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0, 490 val)) { 491 dev_err(&pdev->dev, "%s write error\n", __func__); 492 return; 493 } 494 495 dev_dbg(&pdev->dev, "%s completed\n", __func__); 496 } 497 498 #else 499 500 static inline void byt_ocp_setting(struct pci_dev *pdev) 501 { 502 } 503 504 #endif 505 506 enum { 507 INTEL_DSM_FNS = 0, 508 INTEL_DSM_V18_SWITCH = 3, 509 INTEL_DSM_V33_SWITCH = 4, 510 INTEL_DSM_DRV_STRENGTH = 9, 511 INTEL_DSM_D3_RETUNE = 10, 512 }; 513 514 struct intel_host { 515 u32 dsm_fns; 516 int drv_strength; 517 bool d3_retune; 518 bool rpm_retune_ok; 519 bool needs_pwr_off; 520 u32 glk_rx_ctrl1; 521 u32 glk_tun_val; 522 u32 active_ltr; 523 u32 idle_ltr; 524 }; 525 526 static const guid_t intel_dsm_guid = 527 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F, 528 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61); 529 530 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 531 unsigned int fn, u32 *result) 532 { 533 union acpi_object *obj; 534 int err = 0; 535 size_t len; 536 537 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL); 538 if (!obj) 539 return -EOPNOTSUPP; 540 541 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { 542 err = -EINVAL; 543 goto out; 544 } 545 546 len = min_t(size_t, obj->buffer.length, 4); 547 548 *result = 0; 549 memcpy(result, obj->buffer.pointer, len); 550 out: 551 ACPI_FREE(obj); 552 553 return err; 554 } 555 556 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 557 unsigned int fn, u32 *result) 558 { 559 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 560 return -EOPNOTSUPP; 561 562 return __intel_dsm(intel_host, dev, fn, result); 563 } 564 565 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 566 struct mmc_host *mmc) 567 { 568 int err; 569 u32 val; 570 571 intel_host->d3_retune = true; 572 573 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 574 if (err) { 575 pr_debug("%s: DSM not supported, error %d\n", 576 mmc_hostname(mmc), err); 577 return; 578 } 579 580 pr_debug("%s: DSM function mask %#x\n", 581 mmc_hostname(mmc), intel_host->dsm_fns); 582 583 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 584 intel_host->drv_strength = err ? 0 : val; 585 586 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 587 intel_host->d3_retune = err ? true : !!val; 588 } 589 590 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 591 { 592 u8 reg; 593 594 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 595 reg |= 0x10; 596 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 597 /* For eMMC, minimum is 1us but give it 9us for good measure */ 598 udelay(9); 599 reg &= ~0x10; 600 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 601 /* For eMMC, minimum is 200us but give it 300us for good measure */ 602 usleep_range(300, 1000); 603 } 604 605 static int intel_select_drive_strength(struct mmc_card *card, 606 unsigned int max_dtr, int host_drv, 607 int card_drv, int *drv_type) 608 { 609 struct sdhci_host *host = mmc_priv(card->host); 610 struct sdhci_pci_slot *slot = sdhci_priv(host); 611 struct intel_host *intel_host = sdhci_pci_priv(slot); 612 613 if (!(mmc_driver_type_mask(intel_host->drv_strength) & card_drv)) 614 return 0; 615 616 return intel_host->drv_strength; 617 } 618 619 static int sdhci_get_cd_nogpio(struct mmc_host *mmc) 620 { 621 struct sdhci_host *host = mmc_priv(mmc); 622 unsigned long flags; 623 int ret = 0; 624 625 spin_lock_irqsave(&host->lock, flags); 626 627 if (host->flags & SDHCI_DEVICE_DEAD) 628 goto out; 629 630 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 631 out: 632 spin_unlock_irqrestore(&host->lock, flags); 633 634 return ret; 635 } 636 637 static int bxt_get_cd(struct mmc_host *mmc) 638 { 639 int gpio_cd = mmc_gpio_get_cd(mmc); 640 641 if (!gpio_cd) 642 return 0; 643 644 return sdhci_get_cd_nogpio(mmc); 645 } 646 647 static int mrfld_get_cd(struct mmc_host *mmc) 648 { 649 return sdhci_get_cd_nogpio(mmc); 650 } 651 652 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 653 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 654 655 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 656 unsigned short vdd) 657 { 658 struct sdhci_pci_slot *slot = sdhci_priv(host); 659 struct intel_host *intel_host = sdhci_pci_priv(slot); 660 int cntr; 661 u8 reg; 662 663 /* 664 * Bus power may control card power, but a full reset still may not 665 * reset the power, whereas a direct write to SDHCI_POWER_CONTROL can. 666 * That might be needed to initialize correctly, if the card was left 667 * powered on previously. 668 */ 669 if (intel_host->needs_pwr_off) { 670 intel_host->needs_pwr_off = false; 671 if (mode != MMC_POWER_OFF) { 672 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 673 usleep_range(10000, 12500); 674 } 675 } 676 677 sdhci_set_power(host, mode, vdd); 678 679 if (mode == MMC_POWER_OFF) 680 return; 681 682 /* 683 * Bus power might not enable after D3 -> D0 transition due to the 684 * present state not yet having propagated. Retry for up to 2ms. 685 */ 686 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 687 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 688 if (reg & SDHCI_POWER_ON) 689 break; 690 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 691 reg |= SDHCI_POWER_ON; 692 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 693 } 694 } 695 696 static void sdhci_intel_set_uhs_signaling(struct sdhci_host *host, 697 unsigned int timing) 698 { 699 /* Set UHS timing to SDR25 for High Speed mode */ 700 if (timing == MMC_TIMING_MMC_HS || timing == MMC_TIMING_SD_HS) 701 timing = MMC_TIMING_UHS_SDR25; 702 sdhci_set_uhs_signaling(host, timing); 703 } 704 705 #define INTEL_HS400_ES_REG 0x78 706 #define INTEL_HS400_ES_BIT BIT(0) 707 708 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc, 709 struct mmc_ios *ios) 710 { 711 struct sdhci_host *host = mmc_priv(mmc); 712 u32 val; 713 714 val = sdhci_readl(host, INTEL_HS400_ES_REG); 715 if (ios->enhanced_strobe) 716 val |= INTEL_HS400_ES_BIT; 717 else 718 val &= ~INTEL_HS400_ES_BIT; 719 sdhci_writel(host, val, INTEL_HS400_ES_REG); 720 } 721 722 static int intel_start_signal_voltage_switch(struct mmc_host *mmc, 723 struct mmc_ios *ios) 724 { 725 struct device *dev = mmc_dev(mmc); 726 struct sdhci_host *host = mmc_priv(mmc); 727 struct sdhci_pci_slot *slot = sdhci_priv(host); 728 struct intel_host *intel_host = sdhci_pci_priv(slot); 729 unsigned int fn; 730 u32 result = 0; 731 int err; 732 733 err = sdhci_start_signal_voltage_switch(mmc, ios); 734 if (err) 735 return err; 736 737 switch (ios->signal_voltage) { 738 case MMC_SIGNAL_VOLTAGE_330: 739 fn = INTEL_DSM_V33_SWITCH; 740 break; 741 case MMC_SIGNAL_VOLTAGE_180: 742 fn = INTEL_DSM_V18_SWITCH; 743 break; 744 default: 745 return 0; 746 } 747 748 err = intel_dsm(intel_host, dev, fn, &result); 749 pr_debug("%s: %s DSM fn %u error %d result %u\n", 750 mmc_hostname(mmc), __func__, fn, err, result); 751 752 return 0; 753 } 754 755 static const struct sdhci_ops sdhci_intel_byt_ops = { 756 .set_clock = sdhci_set_clock, 757 .set_power = sdhci_intel_set_power, 758 .enable_dma = sdhci_pci_enable_dma, 759 .set_bus_width = sdhci_set_bus_width, 760 .reset = sdhci_reset, 761 .set_uhs_signaling = sdhci_intel_set_uhs_signaling, 762 .hw_reset = sdhci_pci_hw_reset, 763 }; 764 765 static const struct sdhci_ops sdhci_intel_glk_ops = { 766 .set_clock = sdhci_set_clock, 767 .set_power = sdhci_intel_set_power, 768 .enable_dma = sdhci_pci_enable_dma, 769 .set_bus_width = sdhci_set_bus_width, 770 .reset = sdhci_cqhci_reset, 771 .set_uhs_signaling = sdhci_intel_set_uhs_signaling, 772 .hw_reset = sdhci_pci_hw_reset, 773 .irq = sdhci_cqhci_irq, 774 }; 775 776 static void byt_read_dsm(struct sdhci_pci_slot *slot) 777 { 778 struct intel_host *intel_host = sdhci_pci_priv(slot); 779 struct device *dev = &slot->chip->pdev->dev; 780 struct mmc_host *mmc = slot->host->mmc; 781 782 intel_dsm_init(intel_host, dev, mmc); 783 slot->chip->rpm_retune = intel_host->d3_retune; 784 } 785 786 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode) 787 { 788 int err = sdhci_execute_tuning(mmc, opcode); 789 struct sdhci_host *host = mmc_priv(mmc); 790 791 if (err) 792 return err; 793 794 /* 795 * Tuning can leave the IP in an active state (Buffer Read Enable bit 796 * set) which prevents the entry to low power states (i.e. S0i3). Data 797 * reset will clear it. 798 */ 799 sdhci_reset(host, SDHCI_RESET_DATA); 800 801 return 0; 802 } 803 804 #define INTEL_ACTIVELTR 0x804 805 #define INTEL_IDLELTR 0x808 806 807 #define INTEL_LTR_REQ BIT(15) 808 #define INTEL_LTR_SCALE_MASK GENMASK(11, 10) 809 #define INTEL_LTR_SCALE_1US (2 << 10) 810 #define INTEL_LTR_SCALE_32US (3 << 10) 811 #define INTEL_LTR_VALUE_MASK GENMASK(9, 0) 812 813 static void intel_cache_ltr(struct sdhci_pci_slot *slot) 814 { 815 struct intel_host *intel_host = sdhci_pci_priv(slot); 816 struct sdhci_host *host = slot->host; 817 818 intel_host->active_ltr = readl(host->ioaddr + INTEL_ACTIVELTR); 819 intel_host->idle_ltr = readl(host->ioaddr + INTEL_IDLELTR); 820 } 821 822 static void intel_ltr_set(struct device *dev, s32 val) 823 { 824 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 825 struct sdhci_pci_slot *slot = chip->slots[0]; 826 struct intel_host *intel_host = sdhci_pci_priv(slot); 827 struct sdhci_host *host = slot->host; 828 u32 ltr; 829 830 pm_runtime_get_sync(dev); 831 832 /* 833 * Program latency tolerance (LTR) accordingly what has been asked 834 * by the PM QoS layer or disable it in case we were passed 835 * negative value or PM_QOS_LATENCY_ANY. 836 */ 837 ltr = readl(host->ioaddr + INTEL_ACTIVELTR); 838 839 if (val == PM_QOS_LATENCY_ANY || val < 0) { 840 ltr &= ~INTEL_LTR_REQ; 841 } else { 842 ltr |= INTEL_LTR_REQ; 843 ltr &= ~INTEL_LTR_SCALE_MASK; 844 ltr &= ~INTEL_LTR_VALUE_MASK; 845 846 if (val > INTEL_LTR_VALUE_MASK) { 847 val >>= 5; 848 if (val > INTEL_LTR_VALUE_MASK) 849 val = INTEL_LTR_VALUE_MASK; 850 ltr |= INTEL_LTR_SCALE_32US | val; 851 } else { 852 ltr |= INTEL_LTR_SCALE_1US | val; 853 } 854 } 855 856 if (ltr == intel_host->active_ltr) 857 goto out; 858 859 writel(ltr, host->ioaddr + INTEL_ACTIVELTR); 860 writel(ltr, host->ioaddr + INTEL_IDLELTR); 861 862 /* Cache the values into lpss structure */ 863 intel_cache_ltr(slot); 864 out: 865 pm_runtime_put_autosuspend(dev); 866 } 867 868 static bool intel_use_ltr(struct sdhci_pci_chip *chip) 869 { 870 switch (chip->pdev->device) { 871 case PCI_DEVICE_ID_INTEL_BYT_EMMC: 872 case PCI_DEVICE_ID_INTEL_BYT_EMMC2: 873 case PCI_DEVICE_ID_INTEL_BYT_SDIO: 874 case PCI_DEVICE_ID_INTEL_BYT_SD: 875 case PCI_DEVICE_ID_INTEL_BSW_EMMC: 876 case PCI_DEVICE_ID_INTEL_BSW_SDIO: 877 case PCI_DEVICE_ID_INTEL_BSW_SD: 878 return false; 879 default: 880 return true; 881 } 882 } 883 884 static void intel_ltr_expose(struct sdhci_pci_chip *chip) 885 { 886 struct device *dev = &chip->pdev->dev; 887 888 if (!intel_use_ltr(chip)) 889 return; 890 891 dev->power.set_latency_tolerance = intel_ltr_set; 892 dev_pm_qos_expose_latency_tolerance(dev); 893 } 894 895 static void intel_ltr_hide(struct sdhci_pci_chip *chip) 896 { 897 struct device *dev = &chip->pdev->dev; 898 899 if (!intel_use_ltr(chip)) 900 return; 901 902 dev_pm_qos_hide_latency_tolerance(dev); 903 dev->power.set_latency_tolerance = NULL; 904 } 905 906 static void byt_probe_slot(struct sdhci_pci_slot *slot) 907 { 908 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 909 struct device *dev = &slot->chip->pdev->dev; 910 struct mmc_host *mmc = slot->host->mmc; 911 912 byt_read_dsm(slot); 913 914 byt_ocp_setting(slot->chip->pdev); 915 916 ops->execute_tuning = intel_execute_tuning; 917 ops->start_signal_voltage_switch = intel_start_signal_voltage_switch; 918 919 device_property_read_u32(dev, "max-frequency", &mmc->f_max); 920 921 if (!mmc->slotno) { 922 slot->chip->slots[mmc->slotno] = slot; 923 intel_ltr_expose(slot->chip); 924 } 925 } 926 927 static void byt_add_debugfs(struct sdhci_pci_slot *slot) 928 { 929 struct intel_host *intel_host = sdhci_pci_priv(slot); 930 struct mmc_host *mmc = slot->host->mmc; 931 struct dentry *dir = mmc->debugfs_root; 932 933 if (!intel_use_ltr(slot->chip)) 934 return; 935 936 debugfs_create_x32("active_ltr", 0444, dir, &intel_host->active_ltr); 937 debugfs_create_x32("idle_ltr", 0444, dir, &intel_host->idle_ltr); 938 939 intel_cache_ltr(slot); 940 } 941 942 static int byt_add_host(struct sdhci_pci_slot *slot) 943 { 944 int ret = sdhci_add_host(slot->host); 945 946 if (!ret) 947 byt_add_debugfs(slot); 948 return ret; 949 } 950 951 static void byt_remove_slot(struct sdhci_pci_slot *slot, int dead) 952 { 953 struct mmc_host *mmc = slot->host->mmc; 954 955 if (!mmc->slotno) 956 intel_ltr_hide(slot->chip); 957 } 958 959 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 960 { 961 byt_probe_slot(slot); 962 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 963 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 964 MMC_CAP_CMD_DURING_TFR | 965 MMC_CAP_WAIT_WHILE_BUSY; 966 slot->hw_reset = sdhci_pci_int_hw_reset; 967 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 968 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 969 slot->host->mmc_host_ops.select_drive_strength = 970 intel_select_drive_strength; 971 return 0; 972 } 973 974 static bool glk_broken_cqhci(struct sdhci_pci_slot *slot) 975 { 976 return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 977 (dmi_match(DMI_BIOS_VENDOR, "LENOVO") || 978 dmi_match(DMI_SYS_VENDOR, "IRBIS")); 979 } 980 981 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot) 982 { 983 int ret = byt_emmc_probe_slot(slot); 984 985 if (!glk_broken_cqhci(slot)) 986 slot->host->mmc->caps2 |= MMC_CAP2_CQE; 987 988 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) { 989 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES; 990 slot->host->mmc_host_ops.hs400_enhanced_strobe = 991 intel_hs400_enhanced_strobe; 992 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; 993 } 994 995 return ret; 996 } 997 998 static const struct cqhci_host_ops glk_cqhci_ops = { 999 .enable = sdhci_cqe_enable, 1000 .disable = sdhci_cqe_disable, 1001 .dumpregs = sdhci_pci_dumpregs, 1002 }; 1003 1004 static int glk_emmc_add_host(struct sdhci_pci_slot *slot) 1005 { 1006 struct device *dev = &slot->chip->pdev->dev; 1007 struct sdhci_host *host = slot->host; 1008 struct cqhci_host *cq_host; 1009 bool dma64; 1010 int ret; 1011 1012 ret = sdhci_setup_host(host); 1013 if (ret) 1014 return ret; 1015 1016 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); 1017 if (!cq_host) { 1018 ret = -ENOMEM; 1019 goto cleanup; 1020 } 1021 1022 cq_host->mmio = host->ioaddr + 0x200; 1023 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 1024 cq_host->ops = &glk_cqhci_ops; 1025 1026 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 1027 if (dma64) 1028 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 1029 1030 ret = cqhci_init(cq_host, host->mmc, dma64); 1031 if (ret) 1032 goto cleanup; 1033 1034 ret = __sdhci_add_host(host); 1035 if (ret) 1036 goto cleanup; 1037 1038 byt_add_debugfs(slot); 1039 1040 return 0; 1041 1042 cleanup: 1043 sdhci_cleanup_host(host); 1044 return ret; 1045 } 1046 1047 #ifdef CONFIG_PM 1048 #define GLK_RX_CTRL1 0x834 1049 #define GLK_TUN_VAL 0x840 1050 #define GLK_PATH_PLL GENMASK(13, 8) 1051 #define GLK_DLY GENMASK(6, 0) 1052 /* Workaround firmware failing to restore the tuning value */ 1053 static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp) 1054 { 1055 struct sdhci_pci_slot *slot = chip->slots[0]; 1056 struct intel_host *intel_host = sdhci_pci_priv(slot); 1057 struct sdhci_host *host = slot->host; 1058 u32 glk_rx_ctrl1; 1059 u32 glk_tun_val; 1060 u32 dly; 1061 1062 if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc)) 1063 return; 1064 1065 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1); 1066 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL); 1067 1068 if (susp) { 1069 intel_host->glk_rx_ctrl1 = glk_rx_ctrl1; 1070 intel_host->glk_tun_val = glk_tun_val; 1071 return; 1072 } 1073 1074 if (!intel_host->glk_tun_val) 1075 return; 1076 1077 if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) { 1078 intel_host->rpm_retune_ok = true; 1079 return; 1080 } 1081 1082 dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) + 1083 (intel_host->glk_tun_val << 1)); 1084 if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1)) 1085 return; 1086 1087 glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly; 1088 sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1); 1089 1090 intel_host->rpm_retune_ok = true; 1091 chip->rpm_retune = true; 1092 mmc_retune_needed(host->mmc); 1093 pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc)); 1094 } 1095 1096 static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp) 1097 { 1098 if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 1099 !chip->rpm_retune) 1100 glk_rpm_retune_wa(chip, susp); 1101 } 1102 1103 static int glk_runtime_suspend(struct sdhci_pci_chip *chip) 1104 { 1105 glk_rpm_retune_chk(chip, true); 1106 1107 return sdhci_cqhci_runtime_suspend(chip); 1108 } 1109 1110 static int glk_runtime_resume(struct sdhci_pci_chip *chip) 1111 { 1112 glk_rpm_retune_chk(chip, false); 1113 1114 return sdhci_cqhci_runtime_resume(chip); 1115 } 1116 #endif 1117 1118 #ifdef CONFIG_ACPI 1119 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 1120 { 1121 acpi_status status; 1122 unsigned long long max_freq; 1123 1124 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 1125 "MXFQ", NULL, &max_freq); 1126 if (ACPI_FAILURE(status)) { 1127 dev_err(&slot->chip->pdev->dev, 1128 "MXFQ not found in acpi table\n"); 1129 return -EINVAL; 1130 } 1131 1132 slot->host->mmc->f_max = max_freq * 1000000; 1133 1134 return 0; 1135 } 1136 #else 1137 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 1138 { 1139 return 0; 1140 } 1141 #endif 1142 1143 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 1144 { 1145 int err; 1146 1147 byt_probe_slot(slot); 1148 1149 err = ni_set_max_freq(slot); 1150 if (err) 1151 return err; 1152 1153 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 1154 MMC_CAP_WAIT_WHILE_BUSY; 1155 return 0; 1156 } 1157 1158 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 1159 { 1160 byt_probe_slot(slot); 1161 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 1162 MMC_CAP_WAIT_WHILE_BUSY; 1163 return 0; 1164 } 1165 1166 static void byt_needs_pwr_off(struct sdhci_pci_slot *slot) 1167 { 1168 struct intel_host *intel_host = sdhci_pci_priv(slot); 1169 u8 reg = sdhci_readb(slot->host, SDHCI_POWER_CONTROL); 1170 1171 intel_host->needs_pwr_off = reg & SDHCI_POWER_ON; 1172 } 1173 1174 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 1175 { 1176 byt_probe_slot(slot); 1177 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | 1178 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE; 1179 slot->cd_idx = 0; 1180 slot->cd_override_level = true; 1181 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 1182 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 1183 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 1184 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) 1185 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 1186 1187 if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI && 1188 slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3) 1189 slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V; 1190 1191 byt_needs_pwr_off(slot); 1192 1193 return 0; 1194 } 1195 1196 #ifdef CONFIG_PM_SLEEP 1197 1198 static int byt_resume(struct sdhci_pci_chip *chip) 1199 { 1200 byt_ocp_setting(chip->pdev); 1201 1202 return sdhci_pci_resume_host(chip); 1203 } 1204 1205 #endif 1206 1207 #ifdef CONFIG_PM 1208 1209 static int byt_runtime_resume(struct sdhci_pci_chip *chip) 1210 { 1211 byt_ocp_setting(chip->pdev); 1212 1213 return sdhci_pci_runtime_resume_host(chip); 1214 } 1215 1216 #endif 1217 1218 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 1219 #ifdef CONFIG_PM_SLEEP 1220 .resume = byt_resume, 1221 #endif 1222 #ifdef CONFIG_PM 1223 .runtime_resume = byt_runtime_resume, 1224 #endif 1225 .allow_runtime_pm = true, 1226 .probe_slot = byt_emmc_probe_slot, 1227 .add_host = byt_add_host, 1228 .remove_slot = byt_remove_slot, 1229 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1230 SDHCI_QUIRK_NO_LED, 1231 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1232 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1233 SDHCI_QUIRK2_STOP_WITH_TC, 1234 .ops = &sdhci_intel_byt_ops, 1235 .priv_size = sizeof(struct intel_host), 1236 }; 1237 1238 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = { 1239 .allow_runtime_pm = true, 1240 .probe_slot = glk_emmc_probe_slot, 1241 .add_host = glk_emmc_add_host, 1242 .remove_slot = byt_remove_slot, 1243 #ifdef CONFIG_PM_SLEEP 1244 .suspend = sdhci_cqhci_suspend, 1245 .resume = sdhci_cqhci_resume, 1246 #endif 1247 #ifdef CONFIG_PM 1248 .runtime_suspend = glk_runtime_suspend, 1249 .runtime_resume = glk_runtime_resume, 1250 #endif 1251 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1252 SDHCI_QUIRK_NO_LED, 1253 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1254 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1255 SDHCI_QUIRK2_STOP_WITH_TC, 1256 .ops = &sdhci_intel_glk_ops, 1257 .priv_size = sizeof(struct intel_host), 1258 }; 1259 1260 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 1261 #ifdef CONFIG_PM_SLEEP 1262 .resume = byt_resume, 1263 #endif 1264 #ifdef CONFIG_PM 1265 .runtime_resume = byt_runtime_resume, 1266 #endif 1267 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1268 SDHCI_QUIRK_NO_LED, 1269 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1270 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1271 .allow_runtime_pm = true, 1272 .probe_slot = ni_byt_sdio_probe_slot, 1273 .add_host = byt_add_host, 1274 .remove_slot = byt_remove_slot, 1275 .ops = &sdhci_intel_byt_ops, 1276 .priv_size = sizeof(struct intel_host), 1277 }; 1278 1279 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 1280 #ifdef CONFIG_PM_SLEEP 1281 .resume = byt_resume, 1282 #endif 1283 #ifdef CONFIG_PM 1284 .runtime_resume = byt_runtime_resume, 1285 #endif 1286 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1287 SDHCI_QUIRK_NO_LED, 1288 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1289 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1290 .allow_runtime_pm = true, 1291 .probe_slot = byt_sdio_probe_slot, 1292 .add_host = byt_add_host, 1293 .remove_slot = byt_remove_slot, 1294 .ops = &sdhci_intel_byt_ops, 1295 .priv_size = sizeof(struct intel_host), 1296 }; 1297 1298 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 1299 #ifdef CONFIG_PM_SLEEP 1300 .resume = byt_resume, 1301 #endif 1302 #ifdef CONFIG_PM 1303 .runtime_resume = byt_runtime_resume, 1304 #endif 1305 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1306 SDHCI_QUIRK_NO_LED, 1307 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 1308 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1309 SDHCI_QUIRK2_STOP_WITH_TC, 1310 .allow_runtime_pm = true, 1311 .own_cd_for_runtime_pm = true, 1312 .probe_slot = byt_sd_probe_slot, 1313 .add_host = byt_add_host, 1314 .remove_slot = byt_remove_slot, 1315 .ops = &sdhci_intel_byt_ops, 1316 .priv_size = sizeof(struct intel_host), 1317 }; 1318 1319 /* Define Host controllers for Intel Merrifield platform */ 1320 #define INTEL_MRFLD_EMMC_0 0 1321 #define INTEL_MRFLD_EMMC_1 1 1322 #define INTEL_MRFLD_SD 2 1323 #define INTEL_MRFLD_SDIO 3 1324 1325 #ifdef CONFIG_ACPI 1326 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) 1327 { 1328 struct acpi_device *device, *child; 1329 1330 device = ACPI_COMPANION(&slot->chip->pdev->dev); 1331 if (!device) 1332 return; 1333 1334 acpi_device_fix_up_power(device); 1335 list_for_each_entry(child, &device->children, node) 1336 if (child->status.present && child->status.enabled) 1337 acpi_device_fix_up_power(child); 1338 } 1339 #else 1340 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {} 1341 #endif 1342 1343 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 1344 { 1345 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 1346 1347 switch (func) { 1348 case INTEL_MRFLD_EMMC_0: 1349 case INTEL_MRFLD_EMMC_1: 1350 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1351 MMC_CAP_8_BIT_DATA | 1352 MMC_CAP_1_8V_DDR; 1353 break; 1354 case INTEL_MRFLD_SD: 1355 slot->cd_idx = 0; 1356 slot->cd_override_level = true; 1357 /* 1358 * There are two PCB designs of SD card slot with the opposite 1359 * card detection sense. Quirk this out by ignoring GPIO state 1360 * completely in the custom ->get_cd() callback. 1361 */ 1362 slot->host->mmc_host_ops.get_cd = mrfld_get_cd; 1363 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1364 break; 1365 case INTEL_MRFLD_SDIO: 1366 /* Advertise 2.0v for compatibility with the SDIO card's OCR */ 1367 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195; 1368 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1369 MMC_CAP_POWER_OFF_CARD; 1370 break; 1371 default: 1372 return -ENODEV; 1373 } 1374 1375 intel_mrfld_mmc_fix_up_power_slot(slot); 1376 return 0; 1377 } 1378 1379 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 1380 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1381 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 1382 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1383 .allow_runtime_pm = true, 1384 .probe_slot = intel_mrfld_mmc_probe_slot, 1385 }; 1386 1387 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 1388 { 1389 u8 scratch; 1390 int ret; 1391 1392 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 1393 if (ret) 1394 return ret; 1395 1396 /* 1397 * Turn PMOS on [bit 0], set over current detection to 2.4 V 1398 * [bit 1:2] and enable over current debouncing [bit 6]. 1399 */ 1400 if (on) 1401 scratch |= 0x47; 1402 else 1403 scratch &= ~0x47; 1404 1405 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 1406 } 1407 1408 static int jmicron_probe(struct sdhci_pci_chip *chip) 1409 { 1410 int ret; 1411 u16 mmcdev = 0; 1412 1413 if (chip->pdev->revision == 0) { 1414 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 1415 SDHCI_QUIRK_32BIT_DMA_SIZE | 1416 SDHCI_QUIRK_32BIT_ADMA_SIZE | 1417 SDHCI_QUIRK_RESET_AFTER_REQUEST | 1418 SDHCI_QUIRK_BROKEN_SMALL_PIO; 1419 } 1420 1421 /* 1422 * JMicron chips can have two interfaces to the same hardware 1423 * in order to work around limitations in Microsoft's driver. 1424 * We need to make sure we only bind to one of them. 1425 * 1426 * This code assumes two things: 1427 * 1428 * 1. The PCI code adds subfunctions in order. 1429 * 1430 * 2. The MMC interface has a lower subfunction number 1431 * than the SD interface. 1432 */ 1433 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 1434 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 1435 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 1436 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 1437 1438 if (mmcdev) { 1439 struct pci_dev *sd_dev; 1440 1441 sd_dev = NULL; 1442 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 1443 mmcdev, sd_dev)) != NULL) { 1444 if ((PCI_SLOT(chip->pdev->devfn) == 1445 PCI_SLOT(sd_dev->devfn)) && 1446 (chip->pdev->bus == sd_dev->bus)) 1447 break; 1448 } 1449 1450 if (sd_dev) { 1451 pci_dev_put(sd_dev); 1452 dev_info(&chip->pdev->dev, "Refusing to bind to " 1453 "secondary interface.\n"); 1454 return -ENODEV; 1455 } 1456 } 1457 1458 /* 1459 * JMicron chips need a bit of a nudge to enable the power 1460 * output pins. 1461 */ 1462 ret = jmicron_pmos(chip, 1); 1463 if (ret) { 1464 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1465 return ret; 1466 } 1467 1468 /* quirk for unsable RO-detection on JM388 chips */ 1469 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 1470 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1471 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 1472 1473 return 0; 1474 } 1475 1476 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 1477 { 1478 u8 scratch; 1479 1480 scratch = readb(host->ioaddr + 0xC0); 1481 1482 if (on) 1483 scratch |= 0x01; 1484 else 1485 scratch &= ~0x01; 1486 1487 writeb(scratch, host->ioaddr + 0xC0); 1488 } 1489 1490 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 1491 { 1492 if (slot->chip->pdev->revision == 0) { 1493 u16 version; 1494 1495 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 1496 version = (version & SDHCI_VENDOR_VER_MASK) >> 1497 SDHCI_VENDOR_VER_SHIFT; 1498 1499 /* 1500 * Older versions of the chip have lots of nasty glitches 1501 * in the ADMA engine. It's best just to avoid it 1502 * completely. 1503 */ 1504 if (version < 0xAC) 1505 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 1506 } 1507 1508 /* JM388 MMC doesn't support 1.8V while SD supports it */ 1509 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1510 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 1511 MMC_VDD_29_30 | MMC_VDD_30_31 | 1512 MMC_VDD_165_195; /* allow 1.8V */ 1513 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 1514 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 1515 } 1516 1517 /* 1518 * The secondary interface requires a bit set to get the 1519 * interrupts. 1520 */ 1521 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1522 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1523 jmicron_enable_mmc(slot->host, 1); 1524 1525 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 1526 1527 return 0; 1528 } 1529 1530 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 1531 { 1532 if (dead) 1533 return; 1534 1535 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1536 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1537 jmicron_enable_mmc(slot->host, 0); 1538 } 1539 1540 #ifdef CONFIG_PM_SLEEP 1541 static int jmicron_suspend(struct sdhci_pci_chip *chip) 1542 { 1543 int i, ret; 1544 1545 ret = sdhci_pci_suspend_host(chip); 1546 if (ret) 1547 return ret; 1548 1549 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1550 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1551 for (i = 0; i < chip->num_slots; i++) 1552 jmicron_enable_mmc(chip->slots[i]->host, 0); 1553 } 1554 1555 return 0; 1556 } 1557 1558 static int jmicron_resume(struct sdhci_pci_chip *chip) 1559 { 1560 int ret, i; 1561 1562 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1563 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1564 for (i = 0; i < chip->num_slots; i++) 1565 jmicron_enable_mmc(chip->slots[i]->host, 1); 1566 } 1567 1568 ret = jmicron_pmos(chip, 1); 1569 if (ret) { 1570 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1571 return ret; 1572 } 1573 1574 return sdhci_pci_resume_host(chip); 1575 } 1576 #endif 1577 1578 static const struct sdhci_pci_fixes sdhci_jmicron = { 1579 .probe = jmicron_probe, 1580 1581 .probe_slot = jmicron_probe_slot, 1582 .remove_slot = jmicron_remove_slot, 1583 1584 #ifdef CONFIG_PM_SLEEP 1585 .suspend = jmicron_suspend, 1586 .resume = jmicron_resume, 1587 #endif 1588 }; 1589 1590 /* SysKonnect CardBus2SDIO extra registers */ 1591 #define SYSKT_CTRL 0x200 1592 #define SYSKT_RDFIFO_STAT 0x204 1593 #define SYSKT_WRFIFO_STAT 0x208 1594 #define SYSKT_POWER_DATA 0x20c 1595 #define SYSKT_POWER_330 0xef 1596 #define SYSKT_POWER_300 0xf8 1597 #define SYSKT_POWER_184 0xcc 1598 #define SYSKT_POWER_CMD 0x20d 1599 #define SYSKT_POWER_START (1 << 7) 1600 #define SYSKT_POWER_STATUS 0x20e 1601 #define SYSKT_POWER_STATUS_OK (1 << 0) 1602 #define SYSKT_BOARD_REV 0x210 1603 #define SYSKT_CHIP_REV 0x211 1604 #define SYSKT_CONF_DATA 0x212 1605 #define SYSKT_CONF_DATA_1V8 (1 << 2) 1606 #define SYSKT_CONF_DATA_2V5 (1 << 1) 1607 #define SYSKT_CONF_DATA_3V3 (1 << 0) 1608 1609 static int syskt_probe(struct sdhci_pci_chip *chip) 1610 { 1611 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1612 chip->pdev->class &= ~0x0000FF; 1613 chip->pdev->class |= PCI_SDHCI_IFDMA; 1614 } 1615 return 0; 1616 } 1617 1618 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 1619 { 1620 int tm, ps; 1621 1622 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 1623 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 1624 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 1625 "board rev %d.%d, chip rev %d.%d\n", 1626 board_rev >> 4, board_rev & 0xf, 1627 chip_rev >> 4, chip_rev & 0xf); 1628 if (chip_rev >= 0x20) 1629 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 1630 1631 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 1632 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 1633 udelay(50); 1634 tm = 10; /* Wait max 1 ms */ 1635 do { 1636 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 1637 if (ps & SYSKT_POWER_STATUS_OK) 1638 break; 1639 udelay(100); 1640 } while (--tm); 1641 if (!tm) { 1642 dev_err(&slot->chip->pdev->dev, 1643 "power regulator never stabilized"); 1644 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 1645 return -ENODEV; 1646 } 1647 1648 return 0; 1649 } 1650 1651 static const struct sdhci_pci_fixes sdhci_syskt = { 1652 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 1653 .probe = syskt_probe, 1654 .probe_slot = syskt_probe_slot, 1655 }; 1656 1657 static int via_probe(struct sdhci_pci_chip *chip) 1658 { 1659 if (chip->pdev->revision == 0x10) 1660 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 1661 1662 return 0; 1663 } 1664 1665 static const struct sdhci_pci_fixes sdhci_via = { 1666 .probe = via_probe, 1667 }; 1668 1669 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 1670 { 1671 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 1672 return 0; 1673 } 1674 1675 static const struct sdhci_pci_fixes sdhci_rtsx = { 1676 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1677 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 1678 SDHCI_QUIRK2_BROKEN_DDR50, 1679 .probe_slot = rtsx_probe_slot, 1680 }; 1681 1682 /*AMD chipset generation*/ 1683 enum amd_chipset_gen { 1684 AMD_CHIPSET_BEFORE_ML, 1685 AMD_CHIPSET_CZ, 1686 AMD_CHIPSET_NL, 1687 AMD_CHIPSET_UNKNOWN, 1688 }; 1689 1690 /* AMD registers */ 1691 #define AMD_SD_AUTO_PATTERN 0xB8 1692 #define AMD_MSLEEP_DURATION 4 1693 #define AMD_SD_MISC_CONTROL 0xD0 1694 #define AMD_MAX_TUNE_VALUE 0x0B 1695 #define AMD_AUTO_TUNE_SEL 0x10800 1696 #define AMD_FIFO_PTR 0x30 1697 #define AMD_BIT_MASK 0x1F 1698 1699 static void amd_tuning_reset(struct sdhci_host *host) 1700 { 1701 unsigned int val; 1702 1703 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1704 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 1705 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1706 1707 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1708 val &= ~SDHCI_CTRL_EXEC_TUNING; 1709 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1710 } 1711 1712 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 1713 { 1714 unsigned int val; 1715 1716 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 1717 val &= ~AMD_BIT_MASK; 1718 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 1719 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 1720 } 1721 1722 static void amd_enable_manual_tuning(struct pci_dev *pdev) 1723 { 1724 unsigned int val; 1725 1726 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 1727 val |= AMD_FIFO_PTR; 1728 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 1729 } 1730 1731 static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode) 1732 { 1733 struct sdhci_pci_slot *slot = sdhci_priv(host); 1734 struct pci_dev *pdev = slot->chip->pdev; 1735 u8 valid_win = 0; 1736 u8 valid_win_max = 0; 1737 u8 valid_win_end = 0; 1738 u8 ctrl, tune_around; 1739 1740 amd_tuning_reset(host); 1741 1742 for (tune_around = 0; tune_around < 12; tune_around++) { 1743 amd_config_tuning_phase(pdev, tune_around); 1744 1745 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1746 valid_win = 0; 1747 msleep(AMD_MSLEEP_DURATION); 1748 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 1749 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 1750 } else if (++valid_win > valid_win_max) { 1751 valid_win_max = valid_win; 1752 valid_win_end = tune_around; 1753 } 1754 } 1755 1756 if (!valid_win_max) { 1757 dev_err(&pdev->dev, "no tuning point found\n"); 1758 return -EIO; 1759 } 1760 1761 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 1762 1763 amd_enable_manual_tuning(pdev); 1764 1765 host->mmc->retune_period = 0; 1766 1767 return 0; 1768 } 1769 1770 static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode) 1771 { 1772 struct sdhci_host *host = mmc_priv(mmc); 1773 1774 /* AMD requires custom HS200 tuning */ 1775 if (host->timing == MMC_TIMING_MMC_HS200) 1776 return amd_execute_tuning_hs200(host, opcode); 1777 1778 /* Otherwise perform standard SDHCI tuning */ 1779 return sdhci_execute_tuning(mmc, opcode); 1780 } 1781 1782 static int amd_probe_slot(struct sdhci_pci_slot *slot) 1783 { 1784 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 1785 1786 ops->execute_tuning = amd_execute_tuning; 1787 1788 return 0; 1789 } 1790 1791 static int amd_probe(struct sdhci_pci_chip *chip) 1792 { 1793 struct pci_dev *smbus_dev; 1794 enum amd_chipset_gen gen; 1795 1796 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1797 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 1798 if (smbus_dev) { 1799 gen = AMD_CHIPSET_BEFORE_ML; 1800 } else { 1801 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1802 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1803 if (smbus_dev) { 1804 if (smbus_dev->revision < 0x51) 1805 gen = AMD_CHIPSET_CZ; 1806 else 1807 gen = AMD_CHIPSET_NL; 1808 } else { 1809 gen = AMD_CHIPSET_UNKNOWN; 1810 } 1811 } 1812 1813 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1814 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1815 1816 return 0; 1817 } 1818 1819 static u32 sdhci_read_present_state(struct sdhci_host *host) 1820 { 1821 return sdhci_readl(host, SDHCI_PRESENT_STATE); 1822 } 1823 1824 static void amd_sdhci_reset(struct sdhci_host *host, u8 mask) 1825 { 1826 struct sdhci_pci_slot *slot = sdhci_priv(host); 1827 struct pci_dev *pdev = slot->chip->pdev; 1828 u32 present_state; 1829 1830 /* 1831 * SDHC 0x7906 requires a hard reset to clear all internal state. 1832 * Otherwise it can get into a bad state where the DATA lines are always 1833 * read as zeros. 1834 */ 1835 if (pdev->device == 0x7906 && (mask & SDHCI_RESET_ALL)) { 1836 pci_clear_master(pdev); 1837 1838 pci_save_state(pdev); 1839 1840 pci_set_power_state(pdev, PCI_D3cold); 1841 pr_debug("%s: power_state=%u\n", mmc_hostname(host->mmc), 1842 pdev->current_state); 1843 pci_set_power_state(pdev, PCI_D0); 1844 1845 pci_restore_state(pdev); 1846 1847 /* 1848 * SDHCI_RESET_ALL says the card detect logic should not be 1849 * reset, but since we need to reset the entire controller 1850 * we should wait until the card detect logic has stabilized. 1851 * 1852 * This normally takes about 40ms. 1853 */ 1854 readx_poll_timeout( 1855 sdhci_read_present_state, 1856 host, 1857 present_state, 1858 present_state & SDHCI_CD_STABLE, 1859 10000, 1860 100000 1861 ); 1862 } 1863 1864 return sdhci_reset(host, mask); 1865 } 1866 1867 static const struct sdhci_ops amd_sdhci_pci_ops = { 1868 .set_clock = sdhci_set_clock, 1869 .enable_dma = sdhci_pci_enable_dma, 1870 .set_bus_width = sdhci_set_bus_width, 1871 .reset = amd_sdhci_reset, 1872 .set_uhs_signaling = sdhci_set_uhs_signaling, 1873 }; 1874 1875 static const struct sdhci_pci_fixes sdhci_amd = { 1876 .probe = amd_probe, 1877 .ops = &amd_sdhci_pci_ops, 1878 .probe_slot = amd_probe_slot, 1879 }; 1880 1881 static const struct pci_device_id pci_ids[] = { 1882 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh), 1883 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc), 1884 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc), 1885 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc), 1886 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712), 1887 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712), 1888 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714), 1889 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714), 1890 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe), 1891 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron), 1892 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron), 1893 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron), 1894 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron), 1895 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt), 1896 SDHCI_PCI_DEVICE(VIA, 95D0, via), 1897 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx), 1898 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk), 1899 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0), 1900 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2), 1901 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2), 1902 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd), 1903 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio), 1904 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio), 1905 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc), 1906 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc), 1907 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio), 1908 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio), 1909 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc), 1910 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio), 1911 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio), 1912 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd), 1913 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc), 1914 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc), 1915 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio), 1916 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd), 1917 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd), 1918 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio), 1919 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio), 1920 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc), 1921 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc), 1922 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc), 1923 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc), 1924 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio), 1925 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd), 1926 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc), 1927 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc), 1928 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc), 1929 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio), 1930 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd), 1931 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc), 1932 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio), 1933 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd), 1934 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc), 1935 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio), 1936 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd), 1937 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc), 1938 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio), 1939 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd), 1940 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc), 1941 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd), 1942 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd), 1943 SDHCI_PCI_DEVICE(INTEL, ICP_EMMC, intel_glk_emmc), 1944 SDHCI_PCI_DEVICE(INTEL, ICP_SD, intel_byt_sd), 1945 SDHCI_PCI_DEVICE(INTEL, EHL_EMMC, intel_glk_emmc), 1946 SDHCI_PCI_DEVICE(INTEL, EHL_SD, intel_byt_sd), 1947 SDHCI_PCI_DEVICE(INTEL, CML_EMMC, intel_glk_emmc), 1948 SDHCI_PCI_DEVICE(INTEL, CML_SD, intel_byt_sd), 1949 SDHCI_PCI_DEVICE(INTEL, CMLH_SD, intel_byt_sd), 1950 SDHCI_PCI_DEVICE(INTEL, JSL_EMMC, intel_glk_emmc), 1951 SDHCI_PCI_DEVICE(INTEL, JSL_SD, intel_byt_sd), 1952 SDHCI_PCI_DEVICE(INTEL, LKF_EMMC, intel_glk_emmc), 1953 SDHCI_PCI_DEVICE(INTEL, LKF_SD, intel_byt_sd), 1954 SDHCI_PCI_DEVICE(INTEL, ADL_EMMC, intel_glk_emmc), 1955 SDHCI_PCI_DEVICE(O2, 8120, o2), 1956 SDHCI_PCI_DEVICE(O2, 8220, o2), 1957 SDHCI_PCI_DEVICE(O2, 8221, o2), 1958 SDHCI_PCI_DEVICE(O2, 8320, o2), 1959 SDHCI_PCI_DEVICE(O2, 8321, o2), 1960 SDHCI_PCI_DEVICE(O2, FUJIN2, o2), 1961 SDHCI_PCI_DEVICE(O2, SDS0, o2), 1962 SDHCI_PCI_DEVICE(O2, SDS1, o2), 1963 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2), 1964 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), 1965 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan), 1966 SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps), 1967 SDHCI_PCI_DEVICE(GLI, 9750, gl9750), 1968 SDHCI_PCI_DEVICE(GLI, 9755, gl9755), 1969 SDHCI_PCI_DEVICE(GLI, 9763E, gl9763e), 1970 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), 1971 /* Generic SD host controller */ 1972 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, 1973 { /* end: all zeroes */ }, 1974 }; 1975 1976 MODULE_DEVICE_TABLE(pci, pci_ids); 1977 1978 /*****************************************************************************\ 1979 * * 1980 * SDHCI core callbacks * 1981 * * 1982 \*****************************************************************************/ 1983 1984 int sdhci_pci_enable_dma(struct sdhci_host *host) 1985 { 1986 struct sdhci_pci_slot *slot; 1987 struct pci_dev *pdev; 1988 1989 slot = sdhci_priv(host); 1990 pdev = slot->chip->pdev; 1991 1992 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1993 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1994 (host->flags & SDHCI_USE_SDMA)) { 1995 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1996 "doesn't fully claim to support it.\n"); 1997 } 1998 1999 pci_set_master(pdev); 2000 2001 return 0; 2002 } 2003 2004 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 2005 { 2006 struct sdhci_pci_slot *slot = sdhci_priv(host); 2007 int rst_n_gpio = slot->rst_n_gpio; 2008 2009 if (!gpio_is_valid(rst_n_gpio)) 2010 return; 2011 gpio_set_value_cansleep(rst_n_gpio, 0); 2012 /* For eMMC, minimum is 1us but give it 10us for good measure */ 2013 udelay(10); 2014 gpio_set_value_cansleep(rst_n_gpio, 1); 2015 /* For eMMC, minimum is 200us but give it 300us for good measure */ 2016 usleep_range(300, 1000); 2017 } 2018 2019 static void sdhci_pci_hw_reset(struct sdhci_host *host) 2020 { 2021 struct sdhci_pci_slot *slot = sdhci_priv(host); 2022 2023 if (slot->hw_reset) 2024 slot->hw_reset(host); 2025 } 2026 2027 static const struct sdhci_ops sdhci_pci_ops = { 2028 .set_clock = sdhci_set_clock, 2029 .enable_dma = sdhci_pci_enable_dma, 2030 .set_bus_width = sdhci_set_bus_width, 2031 .reset = sdhci_reset, 2032 .set_uhs_signaling = sdhci_set_uhs_signaling, 2033 .hw_reset = sdhci_pci_hw_reset, 2034 }; 2035 2036 /*****************************************************************************\ 2037 * * 2038 * Suspend/resume * 2039 * * 2040 \*****************************************************************************/ 2041 2042 #ifdef CONFIG_PM_SLEEP 2043 static int sdhci_pci_suspend(struct device *dev) 2044 { 2045 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2046 2047 if (!chip) 2048 return 0; 2049 2050 if (chip->fixes && chip->fixes->suspend) 2051 return chip->fixes->suspend(chip); 2052 2053 return sdhci_pci_suspend_host(chip); 2054 } 2055 2056 static int sdhci_pci_resume(struct device *dev) 2057 { 2058 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2059 2060 if (!chip) 2061 return 0; 2062 2063 if (chip->fixes && chip->fixes->resume) 2064 return chip->fixes->resume(chip); 2065 2066 return sdhci_pci_resume_host(chip); 2067 } 2068 #endif 2069 2070 #ifdef CONFIG_PM 2071 static int sdhci_pci_runtime_suspend(struct device *dev) 2072 { 2073 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2074 2075 if (!chip) 2076 return 0; 2077 2078 if (chip->fixes && chip->fixes->runtime_suspend) 2079 return chip->fixes->runtime_suspend(chip); 2080 2081 return sdhci_pci_runtime_suspend_host(chip); 2082 } 2083 2084 static int sdhci_pci_runtime_resume(struct device *dev) 2085 { 2086 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2087 2088 if (!chip) 2089 return 0; 2090 2091 if (chip->fixes && chip->fixes->runtime_resume) 2092 return chip->fixes->runtime_resume(chip); 2093 2094 return sdhci_pci_runtime_resume_host(chip); 2095 } 2096 #endif 2097 2098 static const struct dev_pm_ops sdhci_pci_pm_ops = { 2099 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 2100 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 2101 sdhci_pci_runtime_resume, NULL) 2102 }; 2103 2104 /*****************************************************************************\ 2105 * * 2106 * Device probing/removal * 2107 * * 2108 \*****************************************************************************/ 2109 2110 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 2111 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 2112 int slotno) 2113 { 2114 struct sdhci_pci_slot *slot; 2115 struct sdhci_host *host; 2116 int ret, bar = first_bar + slotno; 2117 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 2118 2119 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 2120 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 2121 return ERR_PTR(-ENODEV); 2122 } 2123 2124 if (pci_resource_len(pdev, bar) < 0x100) { 2125 dev_err(&pdev->dev, "Invalid iomem size. You may " 2126 "experience problems.\n"); 2127 } 2128 2129 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 2130 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 2131 return ERR_PTR(-ENODEV); 2132 } 2133 2134 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 2135 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 2136 return ERR_PTR(-ENODEV); 2137 } 2138 2139 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 2140 if (IS_ERR(host)) { 2141 dev_err(&pdev->dev, "cannot allocate host\n"); 2142 return ERR_CAST(host); 2143 } 2144 2145 slot = sdhci_priv(host); 2146 2147 slot->chip = chip; 2148 slot->host = host; 2149 slot->rst_n_gpio = -EINVAL; 2150 slot->cd_gpio = -EINVAL; 2151 slot->cd_idx = -1; 2152 2153 /* Retrieve platform data if there is any */ 2154 if (*sdhci_pci_get_data) 2155 slot->data = sdhci_pci_get_data(pdev, slotno); 2156 2157 if (slot->data) { 2158 if (slot->data->setup) { 2159 ret = slot->data->setup(slot->data); 2160 if (ret) { 2161 dev_err(&pdev->dev, "platform setup failed\n"); 2162 goto free; 2163 } 2164 } 2165 slot->rst_n_gpio = slot->data->rst_n_gpio; 2166 slot->cd_gpio = slot->data->cd_gpio; 2167 } 2168 2169 host->hw_name = "PCI"; 2170 host->ops = chip->fixes && chip->fixes->ops ? 2171 chip->fixes->ops : 2172 &sdhci_pci_ops; 2173 host->quirks = chip->quirks; 2174 host->quirks2 = chip->quirks2; 2175 2176 host->irq = pdev->irq; 2177 2178 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 2179 if (ret) { 2180 dev_err(&pdev->dev, "cannot request region\n"); 2181 goto cleanup; 2182 } 2183 2184 host->ioaddr = pcim_iomap_table(pdev)[bar]; 2185 2186 if (chip->fixes && chip->fixes->probe_slot) { 2187 ret = chip->fixes->probe_slot(slot); 2188 if (ret) 2189 goto cleanup; 2190 } 2191 2192 if (gpio_is_valid(slot->rst_n_gpio)) { 2193 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 2194 gpio_direction_output(slot->rst_n_gpio, 1); 2195 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 2196 slot->hw_reset = sdhci_pci_gpio_hw_reset; 2197 } else { 2198 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 2199 slot->rst_n_gpio = -EINVAL; 2200 } 2201 } 2202 2203 host->mmc->pm_caps = MMC_PM_KEEP_POWER; 2204 host->mmc->slotno = slotno; 2205 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 2206 2207 if (device_can_wakeup(&pdev->dev)) 2208 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ; 2209 2210 if (host->mmc->caps & MMC_CAP_CD_WAKE) 2211 device_init_wakeup(&pdev->dev, true); 2212 2213 if (slot->cd_idx >= 0) { 2214 ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx, 2215 slot->cd_override_level, 0); 2216 if (ret && ret != -EPROBE_DEFER) 2217 ret = mmc_gpiod_request_cd(host->mmc, NULL, 2218 slot->cd_idx, 2219 slot->cd_override_level, 2220 0); 2221 if (ret == -EPROBE_DEFER) 2222 goto remove; 2223 2224 if (ret) { 2225 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 2226 slot->cd_idx = -1; 2227 } 2228 } 2229 2230 if (chip->fixes && chip->fixes->add_host) 2231 ret = chip->fixes->add_host(slot); 2232 else 2233 ret = sdhci_add_host(host); 2234 if (ret) 2235 goto remove; 2236 2237 sdhci_pci_add_own_cd(slot); 2238 2239 /* 2240 * Check if the chip needs a separate GPIO for card detect to wake up 2241 * from runtime suspend. If it is not there, don't allow runtime PM. 2242 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 2243 */ 2244 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 2245 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 2246 chip->allow_runtime_pm = false; 2247 2248 return slot; 2249 2250 remove: 2251 if (chip->fixes && chip->fixes->remove_slot) 2252 chip->fixes->remove_slot(slot, 0); 2253 2254 cleanup: 2255 if (slot->data && slot->data->cleanup) 2256 slot->data->cleanup(slot->data); 2257 2258 free: 2259 sdhci_free_host(host); 2260 2261 return ERR_PTR(ret); 2262 } 2263 2264 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 2265 { 2266 int dead; 2267 u32 scratch; 2268 2269 sdhci_pci_remove_own_cd(slot); 2270 2271 dead = 0; 2272 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 2273 if (scratch == (u32)-1) 2274 dead = 1; 2275 2276 sdhci_remove_host(slot->host, dead); 2277 2278 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 2279 slot->chip->fixes->remove_slot(slot, dead); 2280 2281 if (slot->data && slot->data->cleanup) 2282 slot->data->cleanup(slot->data); 2283 2284 sdhci_free_host(slot->host); 2285 } 2286 2287 static void sdhci_pci_runtime_pm_allow(struct device *dev) 2288 { 2289 pm_suspend_ignore_children(dev, 1); 2290 pm_runtime_set_autosuspend_delay(dev, 50); 2291 pm_runtime_use_autosuspend(dev); 2292 pm_runtime_allow(dev); 2293 /* Stay active until mmc core scans for a card */ 2294 pm_runtime_put_noidle(dev); 2295 } 2296 2297 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 2298 { 2299 pm_runtime_forbid(dev); 2300 pm_runtime_get_noresume(dev); 2301 } 2302 2303 static int sdhci_pci_probe(struct pci_dev *pdev, 2304 const struct pci_device_id *ent) 2305 { 2306 struct sdhci_pci_chip *chip; 2307 struct sdhci_pci_slot *slot; 2308 2309 u8 slots, first_bar; 2310 int ret, i; 2311 2312 BUG_ON(pdev == NULL); 2313 BUG_ON(ent == NULL); 2314 2315 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 2316 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 2317 2318 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 2319 if (ret) 2320 return ret; 2321 2322 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 2323 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 2324 2325 BUG_ON(slots > MAX_SLOTS); 2326 2327 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 2328 if (ret) 2329 return ret; 2330 2331 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 2332 2333 if (first_bar > 5) { 2334 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 2335 return -ENODEV; 2336 } 2337 2338 ret = pcim_enable_device(pdev); 2339 if (ret) 2340 return ret; 2341 2342 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 2343 if (!chip) 2344 return -ENOMEM; 2345 2346 chip->pdev = pdev; 2347 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 2348 if (chip->fixes) { 2349 chip->quirks = chip->fixes->quirks; 2350 chip->quirks2 = chip->fixes->quirks2; 2351 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 2352 } 2353 chip->num_slots = slots; 2354 chip->pm_retune = true; 2355 chip->rpm_retune = true; 2356 2357 pci_set_drvdata(pdev, chip); 2358 2359 if (chip->fixes && chip->fixes->probe) { 2360 ret = chip->fixes->probe(chip); 2361 if (ret) 2362 return ret; 2363 } 2364 2365 slots = chip->num_slots; /* Quirk may have changed this */ 2366 2367 for (i = 0; i < slots; i++) { 2368 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 2369 if (IS_ERR(slot)) { 2370 for (i--; i >= 0; i--) 2371 sdhci_pci_remove_slot(chip->slots[i]); 2372 return PTR_ERR(slot); 2373 } 2374 2375 chip->slots[i] = slot; 2376 } 2377 2378 if (chip->allow_runtime_pm) 2379 sdhci_pci_runtime_pm_allow(&pdev->dev); 2380 2381 return 0; 2382 } 2383 2384 static void sdhci_pci_remove(struct pci_dev *pdev) 2385 { 2386 int i; 2387 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 2388 2389 if (chip->allow_runtime_pm) 2390 sdhci_pci_runtime_pm_forbid(&pdev->dev); 2391 2392 for (i = 0; i < chip->num_slots; i++) 2393 sdhci_pci_remove_slot(chip->slots[i]); 2394 } 2395 2396 static struct pci_driver sdhci_driver = { 2397 .name = "sdhci-pci", 2398 .id_table = pci_ids, 2399 .probe = sdhci_pci_probe, 2400 .remove = sdhci_pci_remove, 2401 .driver = { 2402 .pm = &sdhci_pci_pm_ops 2403 }, 2404 }; 2405 2406 module_pci_driver(sdhci_driver); 2407 2408 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 2409 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 2410 MODULE_LICENSE("GPL"); 2411