1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 2 * 3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 * 10 * Thanks to the following companies for their support: 11 * 12 * - JMicron (hardware and technical support) 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/highmem.h> 17 #include <linux/module.h> 18 #include <linux/pci.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/slab.h> 21 #include <linux/device.h> 22 #include <linux/mmc/host.h> 23 #include <linux/mmc/mmc.h> 24 #include <linux/scatterlist.h> 25 #include <linux/io.h> 26 #include <linux/gpio.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/mmc/slot-gpio.h> 29 #include <linux/mmc/sdhci-pci-data.h> 30 #include <linux/acpi.h> 31 32 #include "sdhci.h" 33 #include "sdhci-pci.h" 34 #include "sdhci-pci-o2micro.h" 35 36 static int sdhci_pci_enable_dma(struct sdhci_host *host); 37 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width); 38 static void sdhci_pci_hw_reset(struct sdhci_host *host); 39 40 #ifdef CONFIG_PM_SLEEP 41 static int __sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 42 { 43 int i, ret; 44 45 for (i = 0; i < chip->num_slots; i++) { 46 struct sdhci_pci_slot *slot = chip->slots[i]; 47 struct sdhci_host *host; 48 49 if (!slot) 50 continue; 51 52 host = slot->host; 53 54 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 55 mmc_retune_needed(host->mmc); 56 57 ret = sdhci_suspend_host(host); 58 if (ret) 59 goto err_pci_suspend; 60 61 if (host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ) 62 sdhci_enable_irq_wakeups(host); 63 } 64 65 return 0; 66 67 err_pci_suspend: 68 while (--i >= 0) 69 sdhci_resume_host(chip->slots[i]->host); 70 return ret; 71 } 72 73 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip) 74 { 75 mmc_pm_flag_t pm_flags = 0; 76 int i; 77 78 for (i = 0; i < chip->num_slots; i++) { 79 struct sdhci_pci_slot *slot = chip->slots[i]; 80 81 if (slot) 82 pm_flags |= slot->host->mmc->pm_flags; 83 } 84 85 return device_init_wakeup(&chip->pdev->dev, 86 (pm_flags & MMC_PM_KEEP_POWER) && 87 (pm_flags & MMC_PM_WAKE_SDIO_IRQ)); 88 } 89 90 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 91 { 92 int ret; 93 94 ret = __sdhci_pci_suspend_host(chip); 95 if (ret) 96 return ret; 97 98 sdhci_pci_init_wakeup(chip); 99 100 return 0; 101 } 102 103 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip) 104 { 105 struct sdhci_pci_slot *slot; 106 int i, ret; 107 108 for (i = 0; i < chip->num_slots; i++) { 109 slot = chip->slots[i]; 110 if (!slot) 111 continue; 112 113 ret = sdhci_resume_host(slot->host); 114 if (ret) 115 return ret; 116 } 117 118 return 0; 119 } 120 #endif 121 122 #ifdef CONFIG_PM 123 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip) 124 { 125 struct sdhci_pci_slot *slot; 126 struct sdhci_host *host; 127 int i, ret; 128 129 for (i = 0; i < chip->num_slots; i++) { 130 slot = chip->slots[i]; 131 if (!slot) 132 continue; 133 134 host = slot->host; 135 136 ret = sdhci_runtime_suspend_host(host); 137 if (ret) 138 goto err_pci_runtime_suspend; 139 140 if (chip->rpm_retune && 141 host->tuning_mode != SDHCI_TUNING_MODE_3) 142 mmc_retune_needed(host->mmc); 143 } 144 145 return 0; 146 147 err_pci_runtime_suspend: 148 while (--i >= 0) 149 sdhci_runtime_resume_host(chip->slots[i]->host); 150 return ret; 151 } 152 153 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip) 154 { 155 struct sdhci_pci_slot *slot; 156 int i, ret; 157 158 for (i = 0; i < chip->num_slots; i++) { 159 slot = chip->slots[i]; 160 if (!slot) 161 continue; 162 163 ret = sdhci_runtime_resume_host(slot->host); 164 if (ret) 165 return ret; 166 } 167 168 return 0; 169 } 170 #endif 171 172 /*****************************************************************************\ 173 * * 174 * Hardware specific quirk handling * 175 * * 176 \*****************************************************************************/ 177 178 static int ricoh_probe(struct sdhci_pci_chip *chip) 179 { 180 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 181 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 182 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 183 return 0; 184 } 185 186 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 187 { 188 slot->host->caps = 189 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 190 & SDHCI_TIMEOUT_CLK_MASK) | 191 192 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 193 & SDHCI_CLOCK_BASE_MASK) | 194 195 SDHCI_TIMEOUT_CLK_UNIT | 196 SDHCI_CAN_VDD_330 | 197 SDHCI_CAN_DO_HISPD | 198 SDHCI_CAN_DO_SDMA; 199 return 0; 200 } 201 202 #ifdef CONFIG_PM_SLEEP 203 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 204 { 205 /* Apply a delay to allow controller to settle */ 206 /* Otherwise it becomes confused if card state changed 207 during suspend */ 208 msleep(500); 209 return sdhci_pci_resume_host(chip); 210 } 211 #endif 212 213 static const struct sdhci_pci_fixes sdhci_ricoh = { 214 .probe = ricoh_probe, 215 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 216 SDHCI_QUIRK_FORCE_DMA | 217 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 218 }; 219 220 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 221 .probe_slot = ricoh_mmc_probe_slot, 222 #ifdef CONFIG_PM_SLEEP 223 .resume = ricoh_mmc_resume, 224 #endif 225 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 226 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 227 SDHCI_QUIRK_NO_CARD_NO_RESET | 228 SDHCI_QUIRK_MISSING_CAPS 229 }; 230 231 static const struct sdhci_pci_fixes sdhci_ene_712 = { 232 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 233 SDHCI_QUIRK_BROKEN_DMA, 234 }; 235 236 static const struct sdhci_pci_fixes sdhci_ene_714 = { 237 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 238 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 239 SDHCI_QUIRK_BROKEN_DMA, 240 }; 241 242 static const struct sdhci_pci_fixes sdhci_cafe = { 243 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 244 SDHCI_QUIRK_NO_BUSY_IRQ | 245 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 246 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 247 }; 248 249 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 250 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 251 }; 252 253 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 254 { 255 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 256 return 0; 257 } 258 259 /* 260 * ADMA operation is disabled for Moorestown platform due to 261 * hardware bugs. 262 */ 263 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 264 { 265 /* 266 * slots number is fixed here for MRST as SDIO3/5 are never used and 267 * have hardware bugs. 268 */ 269 chip->num_slots = 1; 270 return 0; 271 } 272 273 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 274 { 275 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 276 return 0; 277 } 278 279 #ifdef CONFIG_PM 280 281 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 282 { 283 struct sdhci_pci_slot *slot = dev_id; 284 struct sdhci_host *host = slot->host; 285 286 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 287 return IRQ_HANDLED; 288 } 289 290 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 291 { 292 int err, irq, gpio = slot->cd_gpio; 293 294 slot->cd_gpio = -EINVAL; 295 slot->cd_irq = -EINVAL; 296 297 if (!gpio_is_valid(gpio)) 298 return; 299 300 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 301 if (err < 0) 302 goto out; 303 304 err = gpio_direction_input(gpio); 305 if (err < 0) 306 goto out_free; 307 308 irq = gpio_to_irq(gpio); 309 if (irq < 0) 310 goto out_free; 311 312 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 313 IRQF_TRIGGER_FALLING, "sd_cd", slot); 314 if (err) 315 goto out_free; 316 317 slot->cd_gpio = gpio; 318 slot->cd_irq = irq; 319 320 return; 321 322 out_free: 323 devm_gpio_free(&slot->chip->pdev->dev, gpio); 324 out: 325 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 326 } 327 328 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 329 { 330 if (slot->cd_irq >= 0) 331 free_irq(slot->cd_irq, slot); 332 } 333 334 #else 335 336 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 337 { 338 } 339 340 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 341 { 342 } 343 344 #endif 345 346 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 347 { 348 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 349 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC | 350 MMC_CAP2_HC_ERASE_SZ; 351 return 0; 352 } 353 354 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 355 { 356 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 357 return 0; 358 } 359 360 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 361 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 362 .probe_slot = mrst_hc_probe_slot, 363 }; 364 365 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 366 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 367 .probe = mrst_hc_probe, 368 }; 369 370 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 371 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 372 .allow_runtime_pm = true, 373 .own_cd_for_runtime_pm = true, 374 }; 375 376 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 377 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 378 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 379 .allow_runtime_pm = true, 380 .probe_slot = mfd_sdio_probe_slot, 381 }; 382 383 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 384 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 385 .allow_runtime_pm = true, 386 .probe_slot = mfd_emmc_probe_slot, 387 }; 388 389 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 390 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 391 .probe_slot = pch_hc_probe_slot, 392 }; 393 394 enum { 395 INTEL_DSM_FNS = 0, 396 INTEL_DSM_DRV_STRENGTH = 9, 397 INTEL_DSM_D3_RETUNE = 10, 398 }; 399 400 struct intel_host { 401 u32 dsm_fns; 402 int drv_strength; 403 bool d3_retune; 404 }; 405 406 const u8 intel_dsm_uuid[] = { 407 0xA5, 0x3E, 0xC1, 0xF6, 0xCD, 0x65, 0x1F, 0x46, 408 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61, 409 }; 410 411 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 412 unsigned int fn, u32 *result) 413 { 414 union acpi_object *obj; 415 int err = 0; 416 417 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), intel_dsm_uuid, 0, fn, NULL); 418 if (!obj) 419 return -EOPNOTSUPP; 420 421 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { 422 err = -EINVAL; 423 goto out; 424 } 425 426 if (obj->buffer.length >= 4) 427 *result = *(u32 *)obj->buffer.pointer; 428 else if (obj->buffer.length >= 2) 429 *result = *(u16 *)obj->buffer.pointer; 430 else 431 *result = *(u8 *)obj->buffer.pointer; 432 out: 433 ACPI_FREE(obj); 434 435 return err; 436 } 437 438 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 439 unsigned int fn, u32 *result) 440 { 441 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 442 return -EOPNOTSUPP; 443 444 return __intel_dsm(intel_host, dev, fn, result); 445 } 446 447 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 448 struct mmc_host *mmc) 449 { 450 int err; 451 u32 val; 452 453 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 454 if (err) { 455 pr_debug("%s: DSM not supported, error %d\n", 456 mmc_hostname(mmc), err); 457 return; 458 } 459 460 pr_debug("%s: DSM function mask %#x\n", 461 mmc_hostname(mmc), intel_host->dsm_fns); 462 463 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 464 intel_host->drv_strength = err ? 0 : val; 465 466 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 467 intel_host->d3_retune = err ? true : !!val; 468 } 469 470 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 471 { 472 u8 reg; 473 474 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 475 reg |= 0x10; 476 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 477 /* For eMMC, minimum is 1us but give it 9us for good measure */ 478 udelay(9); 479 reg &= ~0x10; 480 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 481 /* For eMMC, minimum is 200us but give it 300us for good measure */ 482 usleep_range(300, 1000); 483 } 484 485 static int intel_select_drive_strength(struct mmc_card *card, 486 unsigned int max_dtr, int host_drv, 487 int card_drv, int *drv_type) 488 { 489 struct sdhci_host *host = mmc_priv(card->host); 490 struct sdhci_pci_slot *slot = sdhci_priv(host); 491 struct intel_host *intel_host = sdhci_pci_priv(slot); 492 493 return intel_host->drv_strength; 494 } 495 496 static int bxt_get_cd(struct mmc_host *mmc) 497 { 498 int gpio_cd = mmc_gpio_get_cd(mmc); 499 struct sdhci_host *host = mmc_priv(mmc); 500 unsigned long flags; 501 int ret = 0; 502 503 if (!gpio_cd) 504 return 0; 505 506 spin_lock_irqsave(&host->lock, flags); 507 508 if (host->flags & SDHCI_DEVICE_DEAD) 509 goto out; 510 511 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 512 out: 513 spin_unlock_irqrestore(&host->lock, flags); 514 515 return ret; 516 } 517 518 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 519 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 520 521 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 522 unsigned short vdd) 523 { 524 int cntr; 525 u8 reg; 526 527 sdhci_set_power(host, mode, vdd); 528 529 if (mode == MMC_POWER_OFF) 530 return; 531 532 /* 533 * Bus power might not enable after D3 -> D0 transition due to the 534 * present state not yet having propagated. Retry for up to 2ms. 535 */ 536 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 537 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 538 if (reg & SDHCI_POWER_ON) 539 break; 540 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 541 reg |= SDHCI_POWER_ON; 542 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 543 } 544 } 545 546 static const struct sdhci_ops sdhci_intel_byt_ops = { 547 .set_clock = sdhci_set_clock, 548 .set_power = sdhci_intel_set_power, 549 .enable_dma = sdhci_pci_enable_dma, 550 .set_bus_width = sdhci_pci_set_bus_width, 551 .reset = sdhci_reset, 552 .set_uhs_signaling = sdhci_set_uhs_signaling, 553 .hw_reset = sdhci_pci_hw_reset, 554 }; 555 556 static void byt_read_dsm(struct sdhci_pci_slot *slot) 557 { 558 struct intel_host *intel_host = sdhci_pci_priv(slot); 559 struct device *dev = &slot->chip->pdev->dev; 560 struct mmc_host *mmc = slot->host->mmc; 561 562 intel_dsm_init(intel_host, dev, mmc); 563 slot->chip->rpm_retune = intel_host->d3_retune; 564 } 565 566 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 567 { 568 byt_read_dsm(slot); 569 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 570 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 571 MMC_CAP_CMD_DURING_TFR | 572 MMC_CAP_WAIT_WHILE_BUSY; 573 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ; 574 slot->hw_reset = sdhci_pci_int_hw_reset; 575 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 576 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 577 slot->host->mmc_host_ops.select_drive_strength = 578 intel_select_drive_strength; 579 return 0; 580 } 581 582 #ifdef CONFIG_ACPI 583 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 584 { 585 acpi_status status; 586 unsigned long long max_freq; 587 588 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 589 "MXFQ", NULL, &max_freq); 590 if (ACPI_FAILURE(status)) { 591 dev_err(&slot->chip->pdev->dev, 592 "MXFQ not found in acpi table\n"); 593 return -EINVAL; 594 } 595 596 slot->host->mmc->f_max = max_freq * 1000000; 597 598 return 0; 599 } 600 #else 601 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 602 { 603 return 0; 604 } 605 #endif 606 607 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 608 { 609 int err; 610 611 byt_read_dsm(slot); 612 613 err = ni_set_max_freq(slot); 614 if (err) 615 return err; 616 617 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 618 MMC_CAP_WAIT_WHILE_BUSY; 619 return 0; 620 } 621 622 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 623 { 624 byt_read_dsm(slot); 625 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 626 MMC_CAP_WAIT_WHILE_BUSY; 627 return 0; 628 } 629 630 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 631 { 632 byt_read_dsm(slot); 633 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 634 slot->cd_idx = 0; 635 slot->cd_override_level = true; 636 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 637 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 638 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 639 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) { 640 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 641 slot->host->mmc->caps |= MMC_CAP_AGGRESSIVE_PM; 642 } 643 644 return 0; 645 } 646 647 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 648 .allow_runtime_pm = true, 649 .probe_slot = byt_emmc_probe_slot, 650 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 651 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 652 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 653 SDHCI_QUIRK2_STOP_WITH_TC, 654 .ops = &sdhci_intel_byt_ops, 655 .priv_size = sizeof(struct intel_host), 656 }; 657 658 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 659 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 660 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 661 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 662 .allow_runtime_pm = true, 663 .probe_slot = ni_byt_sdio_probe_slot, 664 .ops = &sdhci_intel_byt_ops, 665 .priv_size = sizeof(struct intel_host), 666 }; 667 668 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 669 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 670 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 671 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 672 .allow_runtime_pm = true, 673 .probe_slot = byt_sdio_probe_slot, 674 .ops = &sdhci_intel_byt_ops, 675 .priv_size = sizeof(struct intel_host), 676 }; 677 678 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 679 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 680 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 681 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 682 SDHCI_QUIRK2_STOP_WITH_TC, 683 .allow_runtime_pm = true, 684 .own_cd_for_runtime_pm = true, 685 .probe_slot = byt_sd_probe_slot, 686 .ops = &sdhci_intel_byt_ops, 687 .priv_size = sizeof(struct intel_host), 688 }; 689 690 /* Define Host controllers for Intel Merrifield platform */ 691 #define INTEL_MRFLD_EMMC_0 0 692 #define INTEL_MRFLD_EMMC_1 1 693 #define INTEL_MRFLD_SD 2 694 #define INTEL_MRFLD_SDIO 3 695 696 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 697 { 698 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 699 700 switch (func) { 701 case INTEL_MRFLD_EMMC_0: 702 case INTEL_MRFLD_EMMC_1: 703 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 704 MMC_CAP_8_BIT_DATA | 705 MMC_CAP_1_8V_DDR; 706 break; 707 case INTEL_MRFLD_SD: 708 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 709 break; 710 case INTEL_MRFLD_SDIO: 711 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 712 MMC_CAP_POWER_OFF_CARD; 713 break; 714 default: 715 return -ENODEV; 716 } 717 return 0; 718 } 719 720 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 721 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 722 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 723 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 724 .allow_runtime_pm = true, 725 .probe_slot = intel_mrfld_mmc_probe_slot, 726 }; 727 728 /* O2Micro extra registers */ 729 #define O2_SD_LOCK_WP 0xD3 730 #define O2_SD_MULTI_VCC3V 0xEE 731 #define O2_SD_CLKREQ 0xEC 732 #define O2_SD_CAPS 0xE0 733 #define O2_SD_ADMA1 0xE2 734 #define O2_SD_ADMA2 0xE7 735 #define O2_SD_INF_MOD 0xF1 736 737 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 738 { 739 u8 scratch; 740 int ret; 741 742 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 743 if (ret) 744 return ret; 745 746 /* 747 * Turn PMOS on [bit 0], set over current detection to 2.4 V 748 * [bit 1:2] and enable over current debouncing [bit 6]. 749 */ 750 if (on) 751 scratch |= 0x47; 752 else 753 scratch &= ~0x47; 754 755 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 756 } 757 758 static int jmicron_probe(struct sdhci_pci_chip *chip) 759 { 760 int ret; 761 u16 mmcdev = 0; 762 763 if (chip->pdev->revision == 0) { 764 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 765 SDHCI_QUIRK_32BIT_DMA_SIZE | 766 SDHCI_QUIRK_32BIT_ADMA_SIZE | 767 SDHCI_QUIRK_RESET_AFTER_REQUEST | 768 SDHCI_QUIRK_BROKEN_SMALL_PIO; 769 } 770 771 /* 772 * JMicron chips can have two interfaces to the same hardware 773 * in order to work around limitations in Microsoft's driver. 774 * We need to make sure we only bind to one of them. 775 * 776 * This code assumes two things: 777 * 778 * 1. The PCI code adds subfunctions in order. 779 * 780 * 2. The MMC interface has a lower subfunction number 781 * than the SD interface. 782 */ 783 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 784 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 785 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 786 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 787 788 if (mmcdev) { 789 struct pci_dev *sd_dev; 790 791 sd_dev = NULL; 792 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 793 mmcdev, sd_dev)) != NULL) { 794 if ((PCI_SLOT(chip->pdev->devfn) == 795 PCI_SLOT(sd_dev->devfn)) && 796 (chip->pdev->bus == sd_dev->bus)) 797 break; 798 } 799 800 if (sd_dev) { 801 pci_dev_put(sd_dev); 802 dev_info(&chip->pdev->dev, "Refusing to bind to " 803 "secondary interface.\n"); 804 return -ENODEV; 805 } 806 } 807 808 /* 809 * JMicron chips need a bit of a nudge to enable the power 810 * output pins. 811 */ 812 ret = jmicron_pmos(chip, 1); 813 if (ret) { 814 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 815 return ret; 816 } 817 818 /* quirk for unsable RO-detection on JM388 chips */ 819 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 820 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 821 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 822 823 return 0; 824 } 825 826 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 827 { 828 u8 scratch; 829 830 scratch = readb(host->ioaddr + 0xC0); 831 832 if (on) 833 scratch |= 0x01; 834 else 835 scratch &= ~0x01; 836 837 writeb(scratch, host->ioaddr + 0xC0); 838 } 839 840 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 841 { 842 if (slot->chip->pdev->revision == 0) { 843 u16 version; 844 845 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 846 version = (version & SDHCI_VENDOR_VER_MASK) >> 847 SDHCI_VENDOR_VER_SHIFT; 848 849 /* 850 * Older versions of the chip have lots of nasty glitches 851 * in the ADMA engine. It's best just to avoid it 852 * completely. 853 */ 854 if (version < 0xAC) 855 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 856 } 857 858 /* JM388 MMC doesn't support 1.8V while SD supports it */ 859 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 860 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 861 MMC_VDD_29_30 | MMC_VDD_30_31 | 862 MMC_VDD_165_195; /* allow 1.8V */ 863 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 864 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 865 } 866 867 /* 868 * The secondary interface requires a bit set to get the 869 * interrupts. 870 */ 871 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 872 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 873 jmicron_enable_mmc(slot->host, 1); 874 875 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 876 877 return 0; 878 } 879 880 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 881 { 882 if (dead) 883 return; 884 885 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 886 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 887 jmicron_enable_mmc(slot->host, 0); 888 } 889 890 #ifdef CONFIG_PM_SLEEP 891 static int jmicron_suspend(struct sdhci_pci_chip *chip) 892 { 893 int i, ret; 894 895 ret = __sdhci_pci_suspend_host(chip); 896 if (ret) 897 return ret; 898 899 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 900 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 901 for (i = 0; i < chip->num_slots; i++) 902 jmicron_enable_mmc(chip->slots[i]->host, 0); 903 } 904 905 sdhci_pci_init_wakeup(chip); 906 907 return 0; 908 } 909 910 static int jmicron_resume(struct sdhci_pci_chip *chip) 911 { 912 int ret, i; 913 914 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 915 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 916 for (i = 0; i < chip->num_slots; i++) 917 jmicron_enable_mmc(chip->slots[i]->host, 1); 918 } 919 920 ret = jmicron_pmos(chip, 1); 921 if (ret) { 922 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 923 return ret; 924 } 925 926 return sdhci_pci_resume_host(chip); 927 } 928 #endif 929 930 static const struct sdhci_pci_fixes sdhci_o2 = { 931 .probe = sdhci_pci_o2_probe, 932 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 933 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 934 .probe_slot = sdhci_pci_o2_probe_slot, 935 #ifdef CONFIG_PM_SLEEP 936 .resume = sdhci_pci_o2_resume, 937 #endif 938 }; 939 940 static const struct sdhci_pci_fixes sdhci_jmicron = { 941 .probe = jmicron_probe, 942 943 .probe_slot = jmicron_probe_slot, 944 .remove_slot = jmicron_remove_slot, 945 946 #ifdef CONFIG_PM_SLEEP 947 .suspend = jmicron_suspend, 948 .resume = jmicron_resume, 949 #endif 950 }; 951 952 /* SysKonnect CardBus2SDIO extra registers */ 953 #define SYSKT_CTRL 0x200 954 #define SYSKT_RDFIFO_STAT 0x204 955 #define SYSKT_WRFIFO_STAT 0x208 956 #define SYSKT_POWER_DATA 0x20c 957 #define SYSKT_POWER_330 0xef 958 #define SYSKT_POWER_300 0xf8 959 #define SYSKT_POWER_184 0xcc 960 #define SYSKT_POWER_CMD 0x20d 961 #define SYSKT_POWER_START (1 << 7) 962 #define SYSKT_POWER_STATUS 0x20e 963 #define SYSKT_POWER_STATUS_OK (1 << 0) 964 #define SYSKT_BOARD_REV 0x210 965 #define SYSKT_CHIP_REV 0x211 966 #define SYSKT_CONF_DATA 0x212 967 #define SYSKT_CONF_DATA_1V8 (1 << 2) 968 #define SYSKT_CONF_DATA_2V5 (1 << 1) 969 #define SYSKT_CONF_DATA_3V3 (1 << 0) 970 971 static int syskt_probe(struct sdhci_pci_chip *chip) 972 { 973 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 974 chip->pdev->class &= ~0x0000FF; 975 chip->pdev->class |= PCI_SDHCI_IFDMA; 976 } 977 return 0; 978 } 979 980 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 981 { 982 int tm, ps; 983 984 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 985 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 986 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 987 "board rev %d.%d, chip rev %d.%d\n", 988 board_rev >> 4, board_rev & 0xf, 989 chip_rev >> 4, chip_rev & 0xf); 990 if (chip_rev >= 0x20) 991 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 992 993 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 994 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 995 udelay(50); 996 tm = 10; /* Wait max 1 ms */ 997 do { 998 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 999 if (ps & SYSKT_POWER_STATUS_OK) 1000 break; 1001 udelay(100); 1002 } while (--tm); 1003 if (!tm) { 1004 dev_err(&slot->chip->pdev->dev, 1005 "power regulator never stabilized"); 1006 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 1007 return -ENODEV; 1008 } 1009 1010 return 0; 1011 } 1012 1013 static const struct sdhci_pci_fixes sdhci_syskt = { 1014 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 1015 .probe = syskt_probe, 1016 .probe_slot = syskt_probe_slot, 1017 }; 1018 1019 static int via_probe(struct sdhci_pci_chip *chip) 1020 { 1021 if (chip->pdev->revision == 0x10) 1022 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 1023 1024 return 0; 1025 } 1026 1027 static const struct sdhci_pci_fixes sdhci_via = { 1028 .probe = via_probe, 1029 }; 1030 1031 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 1032 { 1033 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 1034 return 0; 1035 } 1036 1037 static const struct sdhci_pci_fixes sdhci_rtsx = { 1038 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1039 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 1040 SDHCI_QUIRK2_BROKEN_DDR50, 1041 .probe_slot = rtsx_probe_slot, 1042 }; 1043 1044 /*AMD chipset generation*/ 1045 enum amd_chipset_gen { 1046 AMD_CHIPSET_BEFORE_ML, 1047 AMD_CHIPSET_CZ, 1048 AMD_CHIPSET_NL, 1049 AMD_CHIPSET_UNKNOWN, 1050 }; 1051 1052 /* AMD registers */ 1053 #define AMD_SD_AUTO_PATTERN 0xB8 1054 #define AMD_MSLEEP_DURATION 4 1055 #define AMD_SD_MISC_CONTROL 0xD0 1056 #define AMD_MAX_TUNE_VALUE 0x0B 1057 #define AMD_AUTO_TUNE_SEL 0x10800 1058 #define AMD_FIFO_PTR 0x30 1059 #define AMD_BIT_MASK 0x1F 1060 1061 static void amd_tuning_reset(struct sdhci_host *host) 1062 { 1063 unsigned int val; 1064 1065 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1066 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 1067 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1068 1069 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1070 val &= ~SDHCI_CTRL_EXEC_TUNING; 1071 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1072 } 1073 1074 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 1075 { 1076 unsigned int val; 1077 1078 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 1079 val &= ~AMD_BIT_MASK; 1080 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 1081 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 1082 } 1083 1084 static void amd_enable_manual_tuning(struct pci_dev *pdev) 1085 { 1086 unsigned int val; 1087 1088 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 1089 val |= AMD_FIFO_PTR; 1090 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 1091 } 1092 1093 static int amd_execute_tuning(struct sdhci_host *host, u32 opcode) 1094 { 1095 struct sdhci_pci_slot *slot = sdhci_priv(host); 1096 struct pci_dev *pdev = slot->chip->pdev; 1097 u8 valid_win = 0; 1098 u8 valid_win_max = 0; 1099 u8 valid_win_end = 0; 1100 u8 ctrl, tune_around; 1101 1102 amd_tuning_reset(host); 1103 1104 for (tune_around = 0; tune_around < 12; tune_around++) { 1105 amd_config_tuning_phase(pdev, tune_around); 1106 1107 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1108 valid_win = 0; 1109 msleep(AMD_MSLEEP_DURATION); 1110 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 1111 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 1112 } else if (++valid_win > valid_win_max) { 1113 valid_win_max = valid_win; 1114 valid_win_end = tune_around; 1115 } 1116 } 1117 1118 if (!valid_win_max) { 1119 dev_err(&pdev->dev, "no tuning point found\n"); 1120 return -EIO; 1121 } 1122 1123 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 1124 1125 amd_enable_manual_tuning(pdev); 1126 1127 host->mmc->retune_period = 0; 1128 1129 return 0; 1130 } 1131 1132 static int amd_probe(struct sdhci_pci_chip *chip) 1133 { 1134 struct pci_dev *smbus_dev; 1135 enum amd_chipset_gen gen; 1136 1137 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1138 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 1139 if (smbus_dev) { 1140 gen = AMD_CHIPSET_BEFORE_ML; 1141 } else { 1142 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1143 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1144 if (smbus_dev) { 1145 if (smbus_dev->revision < 0x51) 1146 gen = AMD_CHIPSET_CZ; 1147 else 1148 gen = AMD_CHIPSET_NL; 1149 } else { 1150 gen = AMD_CHIPSET_UNKNOWN; 1151 } 1152 } 1153 1154 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1155 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1156 1157 return 0; 1158 } 1159 1160 static const struct sdhci_ops amd_sdhci_pci_ops = { 1161 .set_clock = sdhci_set_clock, 1162 .enable_dma = sdhci_pci_enable_dma, 1163 .set_bus_width = sdhci_pci_set_bus_width, 1164 .reset = sdhci_reset, 1165 .set_uhs_signaling = sdhci_set_uhs_signaling, 1166 .platform_execute_tuning = amd_execute_tuning, 1167 }; 1168 1169 static const struct sdhci_pci_fixes sdhci_amd = { 1170 .probe = amd_probe, 1171 .ops = &amd_sdhci_pci_ops, 1172 }; 1173 1174 static const struct pci_device_id pci_ids[] = { 1175 { 1176 .vendor = PCI_VENDOR_ID_RICOH, 1177 .device = PCI_DEVICE_ID_RICOH_R5C822, 1178 .subvendor = PCI_ANY_ID, 1179 .subdevice = PCI_ANY_ID, 1180 .driver_data = (kernel_ulong_t)&sdhci_ricoh, 1181 }, 1182 1183 { 1184 .vendor = PCI_VENDOR_ID_RICOH, 1185 .device = 0x843, 1186 .subvendor = PCI_ANY_ID, 1187 .subdevice = PCI_ANY_ID, 1188 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 1189 }, 1190 1191 { 1192 .vendor = PCI_VENDOR_ID_RICOH, 1193 .device = 0xe822, 1194 .subvendor = PCI_ANY_ID, 1195 .subdevice = PCI_ANY_ID, 1196 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 1197 }, 1198 1199 { 1200 .vendor = PCI_VENDOR_ID_RICOH, 1201 .device = 0xe823, 1202 .subvendor = PCI_ANY_ID, 1203 .subdevice = PCI_ANY_ID, 1204 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 1205 }, 1206 1207 { 1208 .vendor = PCI_VENDOR_ID_ENE, 1209 .device = PCI_DEVICE_ID_ENE_CB712_SD, 1210 .subvendor = PCI_ANY_ID, 1211 .subdevice = PCI_ANY_ID, 1212 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 1213 }, 1214 1215 { 1216 .vendor = PCI_VENDOR_ID_ENE, 1217 .device = PCI_DEVICE_ID_ENE_CB712_SD_2, 1218 .subvendor = PCI_ANY_ID, 1219 .subdevice = PCI_ANY_ID, 1220 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 1221 }, 1222 1223 { 1224 .vendor = PCI_VENDOR_ID_ENE, 1225 .device = PCI_DEVICE_ID_ENE_CB714_SD, 1226 .subvendor = PCI_ANY_ID, 1227 .subdevice = PCI_ANY_ID, 1228 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 1229 }, 1230 1231 { 1232 .vendor = PCI_VENDOR_ID_ENE, 1233 .device = PCI_DEVICE_ID_ENE_CB714_SD_2, 1234 .subvendor = PCI_ANY_ID, 1235 .subdevice = PCI_ANY_ID, 1236 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 1237 }, 1238 1239 { 1240 .vendor = PCI_VENDOR_ID_MARVELL, 1241 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD, 1242 .subvendor = PCI_ANY_ID, 1243 .subdevice = PCI_ANY_ID, 1244 .driver_data = (kernel_ulong_t)&sdhci_cafe, 1245 }, 1246 1247 { 1248 .vendor = PCI_VENDOR_ID_JMICRON, 1249 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD, 1250 .subvendor = PCI_ANY_ID, 1251 .subdevice = PCI_ANY_ID, 1252 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1253 }, 1254 1255 { 1256 .vendor = PCI_VENDOR_ID_JMICRON, 1257 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC, 1258 .subvendor = PCI_ANY_ID, 1259 .subdevice = PCI_ANY_ID, 1260 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1261 }, 1262 1263 { 1264 .vendor = PCI_VENDOR_ID_JMICRON, 1265 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD, 1266 .subvendor = PCI_ANY_ID, 1267 .subdevice = PCI_ANY_ID, 1268 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1269 }, 1270 1271 { 1272 .vendor = PCI_VENDOR_ID_JMICRON, 1273 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD, 1274 .subvendor = PCI_ANY_ID, 1275 .subdevice = PCI_ANY_ID, 1276 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1277 }, 1278 1279 { 1280 .vendor = PCI_VENDOR_ID_SYSKONNECT, 1281 .device = 0x8000, 1282 .subvendor = PCI_ANY_ID, 1283 .subdevice = PCI_ANY_ID, 1284 .driver_data = (kernel_ulong_t)&sdhci_syskt, 1285 }, 1286 1287 { 1288 .vendor = PCI_VENDOR_ID_VIA, 1289 .device = 0x95d0, 1290 .subvendor = PCI_ANY_ID, 1291 .subdevice = PCI_ANY_ID, 1292 .driver_data = (kernel_ulong_t)&sdhci_via, 1293 }, 1294 1295 { 1296 .vendor = PCI_VENDOR_ID_REALTEK, 1297 .device = 0x5250, 1298 .subvendor = PCI_ANY_ID, 1299 .subdevice = PCI_ANY_ID, 1300 .driver_data = (kernel_ulong_t)&sdhci_rtsx, 1301 }, 1302 1303 { 1304 .vendor = PCI_VENDOR_ID_INTEL, 1305 .device = PCI_DEVICE_ID_INTEL_QRK_SD, 1306 .subvendor = PCI_ANY_ID, 1307 .subdevice = PCI_ANY_ID, 1308 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk, 1309 }, 1310 1311 { 1312 .vendor = PCI_VENDOR_ID_INTEL, 1313 .device = PCI_DEVICE_ID_INTEL_MRST_SD0, 1314 .subvendor = PCI_ANY_ID, 1315 .subdevice = PCI_ANY_ID, 1316 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0, 1317 }, 1318 1319 { 1320 .vendor = PCI_VENDOR_ID_INTEL, 1321 .device = PCI_DEVICE_ID_INTEL_MRST_SD1, 1322 .subvendor = PCI_ANY_ID, 1323 .subdevice = PCI_ANY_ID, 1324 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 1325 }, 1326 1327 { 1328 .vendor = PCI_VENDOR_ID_INTEL, 1329 .device = PCI_DEVICE_ID_INTEL_MRST_SD2, 1330 .subvendor = PCI_ANY_ID, 1331 .subdevice = PCI_ANY_ID, 1332 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 1333 }, 1334 1335 { 1336 .vendor = PCI_VENDOR_ID_INTEL, 1337 .device = PCI_DEVICE_ID_INTEL_MFD_SD, 1338 .subvendor = PCI_ANY_ID, 1339 .subdevice = PCI_ANY_ID, 1340 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1341 }, 1342 1343 { 1344 .vendor = PCI_VENDOR_ID_INTEL, 1345 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1, 1346 .subvendor = PCI_ANY_ID, 1347 .subdevice = PCI_ANY_ID, 1348 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1349 }, 1350 1351 { 1352 .vendor = PCI_VENDOR_ID_INTEL, 1353 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2, 1354 .subvendor = PCI_ANY_ID, 1355 .subdevice = PCI_ANY_ID, 1356 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1357 }, 1358 1359 { 1360 .vendor = PCI_VENDOR_ID_INTEL, 1361 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0, 1362 .subvendor = PCI_ANY_ID, 1363 .subdevice = PCI_ANY_ID, 1364 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1365 }, 1366 1367 { 1368 .vendor = PCI_VENDOR_ID_INTEL, 1369 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1, 1370 .subvendor = PCI_ANY_ID, 1371 .subdevice = PCI_ANY_ID, 1372 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1373 }, 1374 1375 { 1376 .vendor = PCI_VENDOR_ID_INTEL, 1377 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0, 1378 .subvendor = PCI_ANY_ID, 1379 .subdevice = PCI_ANY_ID, 1380 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1381 }, 1382 1383 { 1384 .vendor = PCI_VENDOR_ID_INTEL, 1385 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1, 1386 .subvendor = PCI_ANY_ID, 1387 .subdevice = PCI_ANY_ID, 1388 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1389 }, 1390 1391 { 1392 .vendor = PCI_VENDOR_ID_INTEL, 1393 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC, 1394 .subvendor = PCI_ANY_ID, 1395 .subdevice = PCI_ANY_ID, 1396 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1397 }, 1398 1399 { 1400 .vendor = PCI_VENDOR_ID_INTEL, 1401 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, 1402 .subvendor = PCI_VENDOR_ID_NI, 1403 .subdevice = 0x7884, 1404 .driver_data = (kernel_ulong_t)&sdhci_ni_byt_sdio, 1405 }, 1406 1407 { 1408 .vendor = PCI_VENDOR_ID_INTEL, 1409 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, 1410 .subvendor = PCI_ANY_ID, 1411 .subdevice = PCI_ANY_ID, 1412 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1413 }, 1414 1415 { 1416 .vendor = PCI_VENDOR_ID_INTEL, 1417 .device = PCI_DEVICE_ID_INTEL_BYT_SD, 1418 .subvendor = PCI_ANY_ID, 1419 .subdevice = PCI_ANY_ID, 1420 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1421 }, 1422 1423 { 1424 .vendor = PCI_VENDOR_ID_INTEL, 1425 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2, 1426 .subvendor = PCI_ANY_ID, 1427 .subdevice = PCI_ANY_ID, 1428 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1429 }, 1430 1431 { 1432 .vendor = PCI_VENDOR_ID_INTEL, 1433 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC, 1434 .subvendor = PCI_ANY_ID, 1435 .subdevice = PCI_ANY_ID, 1436 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1437 }, 1438 1439 { 1440 .vendor = PCI_VENDOR_ID_INTEL, 1441 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO, 1442 .subvendor = PCI_ANY_ID, 1443 .subdevice = PCI_ANY_ID, 1444 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1445 }, 1446 1447 { 1448 .vendor = PCI_VENDOR_ID_INTEL, 1449 .device = PCI_DEVICE_ID_INTEL_BSW_SD, 1450 .subvendor = PCI_ANY_ID, 1451 .subdevice = PCI_ANY_ID, 1452 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1453 }, 1454 1455 { 1456 .vendor = PCI_VENDOR_ID_INTEL, 1457 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0, 1458 .subvendor = PCI_ANY_ID, 1459 .subdevice = PCI_ANY_ID, 1460 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1461 }, 1462 1463 { 1464 .vendor = PCI_VENDOR_ID_INTEL, 1465 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1, 1466 .subvendor = PCI_ANY_ID, 1467 .subdevice = PCI_ANY_ID, 1468 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1469 }, 1470 1471 { 1472 .vendor = PCI_VENDOR_ID_INTEL, 1473 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2, 1474 .subvendor = PCI_ANY_ID, 1475 .subdevice = PCI_ANY_ID, 1476 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1477 }, 1478 1479 { 1480 .vendor = PCI_VENDOR_ID_INTEL, 1481 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0, 1482 .subvendor = PCI_ANY_ID, 1483 .subdevice = PCI_ANY_ID, 1484 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1485 }, 1486 1487 { 1488 .vendor = PCI_VENDOR_ID_INTEL, 1489 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1, 1490 .subvendor = PCI_ANY_ID, 1491 .subdevice = PCI_ANY_ID, 1492 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1493 }, 1494 1495 { 1496 .vendor = PCI_VENDOR_ID_INTEL, 1497 .device = PCI_DEVICE_ID_INTEL_MRFLD_MMC, 1498 .subvendor = PCI_ANY_ID, 1499 .subdevice = PCI_ANY_ID, 1500 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfld_mmc, 1501 }, 1502 1503 { 1504 .vendor = PCI_VENDOR_ID_INTEL, 1505 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC, 1506 .subvendor = PCI_ANY_ID, 1507 .subdevice = PCI_ANY_ID, 1508 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1509 }, 1510 1511 { 1512 .vendor = PCI_VENDOR_ID_INTEL, 1513 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO, 1514 .subvendor = PCI_ANY_ID, 1515 .subdevice = PCI_ANY_ID, 1516 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1517 }, 1518 1519 { 1520 .vendor = PCI_VENDOR_ID_INTEL, 1521 .device = PCI_DEVICE_ID_INTEL_SPT_SD, 1522 .subvendor = PCI_ANY_ID, 1523 .subdevice = PCI_ANY_ID, 1524 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1525 }, 1526 1527 { 1528 .vendor = PCI_VENDOR_ID_INTEL, 1529 .device = PCI_DEVICE_ID_INTEL_DNV_EMMC, 1530 .subvendor = PCI_ANY_ID, 1531 .subdevice = PCI_ANY_ID, 1532 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1533 }, 1534 1535 { 1536 .vendor = PCI_VENDOR_ID_INTEL, 1537 .device = PCI_DEVICE_ID_INTEL_BXT_EMMC, 1538 .subvendor = PCI_ANY_ID, 1539 .subdevice = PCI_ANY_ID, 1540 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1541 }, 1542 1543 { 1544 .vendor = PCI_VENDOR_ID_INTEL, 1545 .device = PCI_DEVICE_ID_INTEL_BXT_SDIO, 1546 .subvendor = PCI_ANY_ID, 1547 .subdevice = PCI_ANY_ID, 1548 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1549 }, 1550 1551 { 1552 .vendor = PCI_VENDOR_ID_INTEL, 1553 .device = PCI_DEVICE_ID_INTEL_BXT_SD, 1554 .subvendor = PCI_ANY_ID, 1555 .subdevice = PCI_ANY_ID, 1556 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1557 }, 1558 1559 { 1560 .vendor = PCI_VENDOR_ID_INTEL, 1561 .device = PCI_DEVICE_ID_INTEL_BXTM_EMMC, 1562 .subvendor = PCI_ANY_ID, 1563 .subdevice = PCI_ANY_ID, 1564 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1565 }, 1566 1567 { 1568 .vendor = PCI_VENDOR_ID_INTEL, 1569 .device = PCI_DEVICE_ID_INTEL_BXTM_SDIO, 1570 .subvendor = PCI_ANY_ID, 1571 .subdevice = PCI_ANY_ID, 1572 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1573 }, 1574 1575 { 1576 .vendor = PCI_VENDOR_ID_INTEL, 1577 .device = PCI_DEVICE_ID_INTEL_BXTM_SD, 1578 .subvendor = PCI_ANY_ID, 1579 .subdevice = PCI_ANY_ID, 1580 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1581 }, 1582 1583 { 1584 .vendor = PCI_VENDOR_ID_INTEL, 1585 .device = PCI_DEVICE_ID_INTEL_APL_EMMC, 1586 .subvendor = PCI_ANY_ID, 1587 .subdevice = PCI_ANY_ID, 1588 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1589 }, 1590 1591 { 1592 .vendor = PCI_VENDOR_ID_INTEL, 1593 .device = PCI_DEVICE_ID_INTEL_APL_SDIO, 1594 .subvendor = PCI_ANY_ID, 1595 .subdevice = PCI_ANY_ID, 1596 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1597 }, 1598 1599 { 1600 .vendor = PCI_VENDOR_ID_INTEL, 1601 .device = PCI_DEVICE_ID_INTEL_APL_SD, 1602 .subvendor = PCI_ANY_ID, 1603 .subdevice = PCI_ANY_ID, 1604 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1605 }, 1606 1607 { 1608 .vendor = PCI_VENDOR_ID_INTEL, 1609 .device = PCI_DEVICE_ID_INTEL_GLK_EMMC, 1610 .subvendor = PCI_ANY_ID, 1611 .subdevice = PCI_ANY_ID, 1612 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1613 }, 1614 1615 { 1616 .vendor = PCI_VENDOR_ID_INTEL, 1617 .device = PCI_DEVICE_ID_INTEL_GLK_SDIO, 1618 .subvendor = PCI_ANY_ID, 1619 .subdevice = PCI_ANY_ID, 1620 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1621 }, 1622 1623 { 1624 .vendor = PCI_VENDOR_ID_INTEL, 1625 .device = PCI_DEVICE_ID_INTEL_GLK_SD, 1626 .subvendor = PCI_ANY_ID, 1627 .subdevice = PCI_ANY_ID, 1628 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1629 }, 1630 1631 { 1632 .vendor = PCI_VENDOR_ID_O2, 1633 .device = PCI_DEVICE_ID_O2_8120, 1634 .subvendor = PCI_ANY_ID, 1635 .subdevice = PCI_ANY_ID, 1636 .driver_data = (kernel_ulong_t)&sdhci_o2, 1637 }, 1638 1639 { 1640 .vendor = PCI_VENDOR_ID_O2, 1641 .device = PCI_DEVICE_ID_O2_8220, 1642 .subvendor = PCI_ANY_ID, 1643 .subdevice = PCI_ANY_ID, 1644 .driver_data = (kernel_ulong_t)&sdhci_o2, 1645 }, 1646 1647 { 1648 .vendor = PCI_VENDOR_ID_O2, 1649 .device = PCI_DEVICE_ID_O2_8221, 1650 .subvendor = PCI_ANY_ID, 1651 .subdevice = PCI_ANY_ID, 1652 .driver_data = (kernel_ulong_t)&sdhci_o2, 1653 }, 1654 1655 { 1656 .vendor = PCI_VENDOR_ID_O2, 1657 .device = PCI_DEVICE_ID_O2_8320, 1658 .subvendor = PCI_ANY_ID, 1659 .subdevice = PCI_ANY_ID, 1660 .driver_data = (kernel_ulong_t)&sdhci_o2, 1661 }, 1662 1663 { 1664 .vendor = PCI_VENDOR_ID_O2, 1665 .device = PCI_DEVICE_ID_O2_8321, 1666 .subvendor = PCI_ANY_ID, 1667 .subdevice = PCI_ANY_ID, 1668 .driver_data = (kernel_ulong_t)&sdhci_o2, 1669 }, 1670 1671 { 1672 .vendor = PCI_VENDOR_ID_O2, 1673 .device = PCI_DEVICE_ID_O2_FUJIN2, 1674 .subvendor = PCI_ANY_ID, 1675 .subdevice = PCI_ANY_ID, 1676 .driver_data = (kernel_ulong_t)&sdhci_o2, 1677 }, 1678 1679 { 1680 .vendor = PCI_VENDOR_ID_O2, 1681 .device = PCI_DEVICE_ID_O2_SDS0, 1682 .subvendor = PCI_ANY_ID, 1683 .subdevice = PCI_ANY_ID, 1684 .driver_data = (kernel_ulong_t)&sdhci_o2, 1685 }, 1686 1687 { 1688 .vendor = PCI_VENDOR_ID_O2, 1689 .device = PCI_DEVICE_ID_O2_SDS1, 1690 .subvendor = PCI_ANY_ID, 1691 .subdevice = PCI_ANY_ID, 1692 .driver_data = (kernel_ulong_t)&sdhci_o2, 1693 }, 1694 1695 { 1696 .vendor = PCI_VENDOR_ID_O2, 1697 .device = PCI_DEVICE_ID_O2_SEABIRD0, 1698 .subvendor = PCI_ANY_ID, 1699 .subdevice = PCI_ANY_ID, 1700 .driver_data = (kernel_ulong_t)&sdhci_o2, 1701 }, 1702 1703 { 1704 .vendor = PCI_VENDOR_ID_O2, 1705 .device = PCI_DEVICE_ID_O2_SEABIRD1, 1706 .subvendor = PCI_ANY_ID, 1707 .subdevice = PCI_ANY_ID, 1708 .driver_data = (kernel_ulong_t)&sdhci_o2, 1709 }, 1710 { 1711 .vendor = PCI_VENDOR_ID_AMD, 1712 .device = PCI_ANY_ID, 1713 .class = PCI_CLASS_SYSTEM_SDHCI << 8, 1714 .class_mask = 0xFFFF00, 1715 .subvendor = PCI_ANY_ID, 1716 .subdevice = PCI_ANY_ID, 1717 .driver_data = (kernel_ulong_t)&sdhci_amd, 1718 }, 1719 { /* Generic SD host controller */ 1720 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) 1721 }, 1722 1723 { /* end: all zeroes */ }, 1724 }; 1725 1726 MODULE_DEVICE_TABLE(pci, pci_ids); 1727 1728 /*****************************************************************************\ 1729 * * 1730 * SDHCI core callbacks * 1731 * * 1732 \*****************************************************************************/ 1733 1734 static int sdhci_pci_enable_dma(struct sdhci_host *host) 1735 { 1736 struct sdhci_pci_slot *slot; 1737 struct pci_dev *pdev; 1738 1739 slot = sdhci_priv(host); 1740 pdev = slot->chip->pdev; 1741 1742 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1743 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1744 (host->flags & SDHCI_USE_SDMA)) { 1745 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1746 "doesn't fully claim to support it.\n"); 1747 } 1748 1749 pci_set_master(pdev); 1750 1751 return 0; 1752 } 1753 1754 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width) 1755 { 1756 u8 ctrl; 1757 1758 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1759 1760 switch (width) { 1761 case MMC_BUS_WIDTH_8: 1762 ctrl |= SDHCI_CTRL_8BITBUS; 1763 ctrl &= ~SDHCI_CTRL_4BITBUS; 1764 break; 1765 case MMC_BUS_WIDTH_4: 1766 ctrl |= SDHCI_CTRL_4BITBUS; 1767 ctrl &= ~SDHCI_CTRL_8BITBUS; 1768 break; 1769 default: 1770 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS); 1771 break; 1772 } 1773 1774 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1775 } 1776 1777 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1778 { 1779 struct sdhci_pci_slot *slot = sdhci_priv(host); 1780 int rst_n_gpio = slot->rst_n_gpio; 1781 1782 if (!gpio_is_valid(rst_n_gpio)) 1783 return; 1784 gpio_set_value_cansleep(rst_n_gpio, 0); 1785 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1786 udelay(10); 1787 gpio_set_value_cansleep(rst_n_gpio, 1); 1788 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1789 usleep_range(300, 1000); 1790 } 1791 1792 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1793 { 1794 struct sdhci_pci_slot *slot = sdhci_priv(host); 1795 1796 if (slot->hw_reset) 1797 slot->hw_reset(host); 1798 } 1799 1800 static const struct sdhci_ops sdhci_pci_ops = { 1801 .set_clock = sdhci_set_clock, 1802 .enable_dma = sdhci_pci_enable_dma, 1803 .set_bus_width = sdhci_pci_set_bus_width, 1804 .reset = sdhci_reset, 1805 .set_uhs_signaling = sdhci_set_uhs_signaling, 1806 .hw_reset = sdhci_pci_hw_reset, 1807 }; 1808 1809 /*****************************************************************************\ 1810 * * 1811 * Suspend/resume * 1812 * * 1813 \*****************************************************************************/ 1814 1815 #ifdef CONFIG_PM_SLEEP 1816 static int sdhci_pci_suspend(struct device *dev) 1817 { 1818 struct pci_dev *pdev = to_pci_dev(dev); 1819 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1820 1821 if (!chip) 1822 return 0; 1823 1824 if (chip->fixes && chip->fixes->suspend) 1825 return chip->fixes->suspend(chip); 1826 1827 return sdhci_pci_suspend_host(chip); 1828 } 1829 1830 static int sdhci_pci_resume(struct device *dev) 1831 { 1832 struct pci_dev *pdev = to_pci_dev(dev); 1833 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1834 1835 if (!chip) 1836 return 0; 1837 1838 if (chip->fixes && chip->fixes->resume) 1839 return chip->fixes->resume(chip); 1840 1841 return sdhci_pci_resume_host(chip); 1842 } 1843 #endif 1844 1845 #ifdef CONFIG_PM 1846 static int sdhci_pci_runtime_suspend(struct device *dev) 1847 { 1848 struct pci_dev *pdev = to_pci_dev(dev); 1849 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1850 1851 if (!chip) 1852 return 0; 1853 1854 if (chip->fixes && chip->fixes->runtime_suspend) 1855 return chip->fixes->runtime_suspend(chip); 1856 1857 return sdhci_pci_runtime_suspend_host(chip); 1858 } 1859 1860 static int sdhci_pci_runtime_resume(struct device *dev) 1861 { 1862 struct pci_dev *pdev = to_pci_dev(dev); 1863 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1864 1865 if (!chip) 1866 return 0; 1867 1868 if (chip->fixes && chip->fixes->runtime_resume) 1869 return chip->fixes->runtime_resume(chip); 1870 1871 return sdhci_pci_runtime_resume_host(chip); 1872 } 1873 #endif 1874 1875 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1876 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1877 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1878 sdhci_pci_runtime_resume, NULL) 1879 }; 1880 1881 /*****************************************************************************\ 1882 * * 1883 * Device probing/removal * 1884 * * 1885 \*****************************************************************************/ 1886 1887 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1888 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1889 int slotno) 1890 { 1891 struct sdhci_pci_slot *slot; 1892 struct sdhci_host *host; 1893 int ret, bar = first_bar + slotno; 1894 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 1895 1896 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1897 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1898 return ERR_PTR(-ENODEV); 1899 } 1900 1901 if (pci_resource_len(pdev, bar) < 0x100) { 1902 dev_err(&pdev->dev, "Invalid iomem size. You may " 1903 "experience problems.\n"); 1904 } 1905 1906 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1907 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1908 return ERR_PTR(-ENODEV); 1909 } 1910 1911 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1912 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1913 return ERR_PTR(-ENODEV); 1914 } 1915 1916 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 1917 if (IS_ERR(host)) { 1918 dev_err(&pdev->dev, "cannot allocate host\n"); 1919 return ERR_CAST(host); 1920 } 1921 1922 slot = sdhci_priv(host); 1923 1924 slot->chip = chip; 1925 slot->host = host; 1926 slot->rst_n_gpio = -EINVAL; 1927 slot->cd_gpio = -EINVAL; 1928 slot->cd_idx = -1; 1929 1930 /* Retrieve platform data if there is any */ 1931 if (*sdhci_pci_get_data) 1932 slot->data = sdhci_pci_get_data(pdev, slotno); 1933 1934 if (slot->data) { 1935 if (slot->data->setup) { 1936 ret = slot->data->setup(slot->data); 1937 if (ret) { 1938 dev_err(&pdev->dev, "platform setup failed\n"); 1939 goto free; 1940 } 1941 } 1942 slot->rst_n_gpio = slot->data->rst_n_gpio; 1943 slot->cd_gpio = slot->data->cd_gpio; 1944 } 1945 1946 host->hw_name = "PCI"; 1947 host->ops = chip->fixes && chip->fixes->ops ? 1948 chip->fixes->ops : 1949 &sdhci_pci_ops; 1950 host->quirks = chip->quirks; 1951 host->quirks2 = chip->quirks2; 1952 1953 host->irq = pdev->irq; 1954 1955 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1956 if (ret) { 1957 dev_err(&pdev->dev, "cannot request region\n"); 1958 goto cleanup; 1959 } 1960 1961 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1962 1963 if (chip->fixes && chip->fixes->probe_slot) { 1964 ret = chip->fixes->probe_slot(slot); 1965 if (ret) 1966 goto cleanup; 1967 } 1968 1969 if (gpio_is_valid(slot->rst_n_gpio)) { 1970 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1971 gpio_direction_output(slot->rst_n_gpio, 1); 1972 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1973 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1974 } else { 1975 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1976 slot->rst_n_gpio = -EINVAL; 1977 } 1978 } 1979 1980 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; 1981 host->mmc->slotno = slotno; 1982 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1983 1984 if (slot->cd_idx >= 0) { 1985 ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx, 1986 slot->cd_override_level, 0, NULL); 1987 if (ret == -EPROBE_DEFER) 1988 goto remove; 1989 1990 if (ret) { 1991 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 1992 slot->cd_idx = -1; 1993 } 1994 } 1995 1996 if (chip->fixes && chip->fixes->add_host) 1997 ret = chip->fixes->add_host(slot); 1998 else 1999 ret = sdhci_add_host(host); 2000 if (ret) 2001 goto remove; 2002 2003 sdhci_pci_add_own_cd(slot); 2004 2005 /* 2006 * Check if the chip needs a separate GPIO for card detect to wake up 2007 * from runtime suspend. If it is not there, don't allow runtime PM. 2008 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 2009 */ 2010 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 2011 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 2012 chip->allow_runtime_pm = false; 2013 2014 return slot; 2015 2016 remove: 2017 if (chip->fixes && chip->fixes->remove_slot) 2018 chip->fixes->remove_slot(slot, 0); 2019 2020 cleanup: 2021 if (slot->data && slot->data->cleanup) 2022 slot->data->cleanup(slot->data); 2023 2024 free: 2025 sdhci_free_host(host); 2026 2027 return ERR_PTR(ret); 2028 } 2029 2030 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 2031 { 2032 int dead; 2033 u32 scratch; 2034 2035 sdhci_pci_remove_own_cd(slot); 2036 2037 dead = 0; 2038 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 2039 if (scratch == (u32)-1) 2040 dead = 1; 2041 2042 sdhci_remove_host(slot->host, dead); 2043 2044 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 2045 slot->chip->fixes->remove_slot(slot, dead); 2046 2047 if (slot->data && slot->data->cleanup) 2048 slot->data->cleanup(slot->data); 2049 2050 sdhci_free_host(slot->host); 2051 } 2052 2053 static void sdhci_pci_runtime_pm_allow(struct device *dev) 2054 { 2055 pm_suspend_ignore_children(dev, 1); 2056 pm_runtime_set_autosuspend_delay(dev, 50); 2057 pm_runtime_use_autosuspend(dev); 2058 pm_runtime_allow(dev); 2059 /* Stay active until mmc core scans for a card */ 2060 pm_runtime_put_noidle(dev); 2061 } 2062 2063 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 2064 { 2065 pm_runtime_forbid(dev); 2066 pm_runtime_get_noresume(dev); 2067 } 2068 2069 static int sdhci_pci_probe(struct pci_dev *pdev, 2070 const struct pci_device_id *ent) 2071 { 2072 struct sdhci_pci_chip *chip; 2073 struct sdhci_pci_slot *slot; 2074 2075 u8 slots, first_bar; 2076 int ret, i; 2077 2078 BUG_ON(pdev == NULL); 2079 BUG_ON(ent == NULL); 2080 2081 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 2082 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 2083 2084 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 2085 if (ret) 2086 return ret; 2087 2088 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 2089 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 2090 if (slots == 0) 2091 return -ENODEV; 2092 2093 BUG_ON(slots > MAX_SLOTS); 2094 2095 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 2096 if (ret) 2097 return ret; 2098 2099 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 2100 2101 if (first_bar > 5) { 2102 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 2103 return -ENODEV; 2104 } 2105 2106 ret = pcim_enable_device(pdev); 2107 if (ret) 2108 return ret; 2109 2110 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 2111 if (!chip) 2112 return -ENOMEM; 2113 2114 chip->pdev = pdev; 2115 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 2116 if (chip->fixes) { 2117 chip->quirks = chip->fixes->quirks; 2118 chip->quirks2 = chip->fixes->quirks2; 2119 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 2120 } 2121 chip->num_slots = slots; 2122 chip->pm_retune = true; 2123 chip->rpm_retune = true; 2124 2125 pci_set_drvdata(pdev, chip); 2126 2127 if (chip->fixes && chip->fixes->probe) { 2128 ret = chip->fixes->probe(chip); 2129 if (ret) 2130 return ret; 2131 } 2132 2133 slots = chip->num_slots; /* Quirk may have changed this */ 2134 2135 for (i = 0; i < slots; i++) { 2136 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 2137 if (IS_ERR(slot)) { 2138 for (i--; i >= 0; i--) 2139 sdhci_pci_remove_slot(chip->slots[i]); 2140 return PTR_ERR(slot); 2141 } 2142 2143 chip->slots[i] = slot; 2144 } 2145 2146 if (chip->allow_runtime_pm) 2147 sdhci_pci_runtime_pm_allow(&pdev->dev); 2148 2149 return 0; 2150 } 2151 2152 static void sdhci_pci_remove(struct pci_dev *pdev) 2153 { 2154 int i; 2155 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 2156 2157 if (chip->allow_runtime_pm) 2158 sdhci_pci_runtime_pm_forbid(&pdev->dev); 2159 2160 for (i = 0; i < chip->num_slots; i++) 2161 sdhci_pci_remove_slot(chip->slots[i]); 2162 } 2163 2164 static struct pci_driver sdhci_driver = { 2165 .name = "sdhci-pci", 2166 .id_table = pci_ids, 2167 .probe = sdhci_pci_probe, 2168 .remove = sdhci_pci_remove, 2169 .driver = { 2170 .pm = &sdhci_pci_pm_ops 2171 }, 2172 }; 2173 2174 module_pci_driver(sdhci_driver); 2175 2176 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 2177 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 2178 MODULE_LICENSE("GPL"); 2179