1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 3 * 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 5 * 6 * Thanks to the following companies for their support: 7 * 8 * - JMicron (hardware and technical support) 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/string.h> 13 #include <linux/delay.h> 14 #include <linux/highmem.h> 15 #include <linux/module.h> 16 #include <linux/pci.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/slab.h> 19 #include <linux/device.h> 20 #include <linux/mmc/host.h> 21 #include <linux/mmc/mmc.h> 22 #include <linux/scatterlist.h> 23 #include <linux/io.h> 24 #include <linux/iopoll.h> 25 #include <linux/gpio.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/pm_qos.h> 28 #include <linux/debugfs.h> 29 #include <linux/mmc/slot-gpio.h> 30 #include <linux/mmc/sdhci-pci-data.h> 31 #include <linux/acpi.h> 32 #include <linux/dmi.h> 33 34 #ifdef CONFIG_X86 35 #include <asm/iosf_mbi.h> 36 #endif 37 38 #include "cqhci.h" 39 40 #include "sdhci.h" 41 #include "sdhci-pci.h" 42 43 static void sdhci_pci_hw_reset(struct sdhci_host *host); 44 45 #ifdef CONFIG_PM_SLEEP 46 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip) 47 { 48 mmc_pm_flag_t pm_flags = 0; 49 bool cap_cd_wake = false; 50 int i; 51 52 for (i = 0; i < chip->num_slots; i++) { 53 struct sdhci_pci_slot *slot = chip->slots[i]; 54 55 if (slot) { 56 pm_flags |= slot->host->mmc->pm_flags; 57 if (slot->host->mmc->caps & MMC_CAP_CD_WAKE) 58 cap_cd_wake = true; 59 } 60 } 61 62 if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ)) 63 return device_wakeup_enable(&chip->pdev->dev); 64 else if (!cap_cd_wake) 65 return device_wakeup_disable(&chip->pdev->dev); 66 67 return 0; 68 } 69 70 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 71 { 72 int i, ret; 73 74 sdhci_pci_init_wakeup(chip); 75 76 for (i = 0; i < chip->num_slots; i++) { 77 struct sdhci_pci_slot *slot = chip->slots[i]; 78 struct sdhci_host *host; 79 80 if (!slot) 81 continue; 82 83 host = slot->host; 84 85 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 86 mmc_retune_needed(host->mmc); 87 88 ret = sdhci_suspend_host(host); 89 if (ret) 90 goto err_pci_suspend; 91 92 if (device_may_wakeup(&chip->pdev->dev)) 93 mmc_gpio_set_cd_wake(host->mmc, true); 94 } 95 96 return 0; 97 98 err_pci_suspend: 99 while (--i >= 0) 100 sdhci_resume_host(chip->slots[i]->host); 101 return ret; 102 } 103 104 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip) 105 { 106 struct sdhci_pci_slot *slot; 107 int i, ret; 108 109 for (i = 0; i < chip->num_slots; i++) { 110 slot = chip->slots[i]; 111 if (!slot) 112 continue; 113 114 ret = sdhci_resume_host(slot->host); 115 if (ret) 116 return ret; 117 118 mmc_gpio_set_cd_wake(slot->host->mmc, false); 119 } 120 121 return 0; 122 } 123 124 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip) 125 { 126 int ret; 127 128 ret = cqhci_suspend(chip->slots[0]->host->mmc); 129 if (ret) 130 return ret; 131 132 return sdhci_pci_suspend_host(chip); 133 } 134 135 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip) 136 { 137 int ret; 138 139 ret = sdhci_pci_resume_host(chip); 140 if (ret) 141 return ret; 142 143 return cqhci_resume(chip->slots[0]->host->mmc); 144 } 145 #endif 146 147 #ifdef CONFIG_PM 148 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip) 149 { 150 struct sdhci_pci_slot *slot; 151 struct sdhci_host *host; 152 int i, ret; 153 154 for (i = 0; i < chip->num_slots; i++) { 155 slot = chip->slots[i]; 156 if (!slot) 157 continue; 158 159 host = slot->host; 160 161 ret = sdhci_runtime_suspend_host(host); 162 if (ret) 163 goto err_pci_runtime_suspend; 164 165 if (chip->rpm_retune && 166 host->tuning_mode != SDHCI_TUNING_MODE_3) 167 mmc_retune_needed(host->mmc); 168 } 169 170 return 0; 171 172 err_pci_runtime_suspend: 173 while (--i >= 0) 174 sdhci_runtime_resume_host(chip->slots[i]->host, 0); 175 return ret; 176 } 177 178 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip) 179 { 180 struct sdhci_pci_slot *slot; 181 int i, ret; 182 183 for (i = 0; i < chip->num_slots; i++) { 184 slot = chip->slots[i]; 185 if (!slot) 186 continue; 187 188 ret = sdhci_runtime_resume_host(slot->host, 0); 189 if (ret) 190 return ret; 191 } 192 193 return 0; 194 } 195 196 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip) 197 { 198 int ret; 199 200 ret = cqhci_suspend(chip->slots[0]->host->mmc); 201 if (ret) 202 return ret; 203 204 return sdhci_pci_runtime_suspend_host(chip); 205 } 206 207 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip) 208 { 209 int ret; 210 211 ret = sdhci_pci_runtime_resume_host(chip); 212 if (ret) 213 return ret; 214 215 return cqhci_resume(chip->slots[0]->host->mmc); 216 } 217 #endif 218 219 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask) 220 { 221 int cmd_error = 0; 222 int data_error = 0; 223 224 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 225 return intmask; 226 227 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 228 229 return 0; 230 } 231 232 static void sdhci_pci_dumpregs(struct mmc_host *mmc) 233 { 234 sdhci_dumpregs(mmc_priv(mmc)); 235 } 236 237 static void sdhci_cqhci_reset(struct sdhci_host *host, u8 mask) 238 { 239 if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) && 240 host->mmc->cqe_private) 241 cqhci_deactivate(host->mmc); 242 sdhci_reset(host, mask); 243 } 244 245 /*****************************************************************************\ 246 * * 247 * Hardware specific quirk handling * 248 * * 249 \*****************************************************************************/ 250 251 static int ricoh_probe(struct sdhci_pci_chip *chip) 252 { 253 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 254 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 255 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 256 return 0; 257 } 258 259 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 260 { 261 slot->host->caps = 262 FIELD_PREP(SDHCI_TIMEOUT_CLK_MASK, 0x21) | 263 FIELD_PREP(SDHCI_CLOCK_BASE_MASK, 0x21) | 264 SDHCI_TIMEOUT_CLK_UNIT | 265 SDHCI_CAN_VDD_330 | 266 SDHCI_CAN_DO_HISPD | 267 SDHCI_CAN_DO_SDMA; 268 return 0; 269 } 270 271 #ifdef CONFIG_PM_SLEEP 272 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 273 { 274 /* Apply a delay to allow controller to settle */ 275 /* Otherwise it becomes confused if card state changed 276 during suspend */ 277 msleep(500); 278 return sdhci_pci_resume_host(chip); 279 } 280 #endif 281 282 static const struct sdhci_pci_fixes sdhci_ricoh = { 283 .probe = ricoh_probe, 284 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 285 SDHCI_QUIRK_FORCE_DMA | 286 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 287 }; 288 289 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 290 .probe_slot = ricoh_mmc_probe_slot, 291 #ifdef CONFIG_PM_SLEEP 292 .resume = ricoh_mmc_resume, 293 #endif 294 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 295 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 296 SDHCI_QUIRK_NO_CARD_NO_RESET | 297 SDHCI_QUIRK_MISSING_CAPS 298 }; 299 300 static const struct sdhci_pci_fixes sdhci_ene_712 = { 301 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 302 SDHCI_QUIRK_BROKEN_DMA, 303 }; 304 305 static const struct sdhci_pci_fixes sdhci_ene_714 = { 306 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 307 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 308 SDHCI_QUIRK_BROKEN_DMA, 309 }; 310 311 static const struct sdhci_pci_fixes sdhci_cafe = { 312 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 313 SDHCI_QUIRK_NO_BUSY_IRQ | 314 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 315 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 316 }; 317 318 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 319 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 320 }; 321 322 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 323 { 324 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 325 return 0; 326 } 327 328 /* 329 * ADMA operation is disabled for Moorestown platform due to 330 * hardware bugs. 331 */ 332 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 333 { 334 /* 335 * slots number is fixed here for MRST as SDIO3/5 are never used and 336 * have hardware bugs. 337 */ 338 chip->num_slots = 1; 339 return 0; 340 } 341 342 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 343 { 344 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 345 return 0; 346 } 347 348 #ifdef CONFIG_PM 349 350 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 351 { 352 struct sdhci_pci_slot *slot = dev_id; 353 struct sdhci_host *host = slot->host; 354 355 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 356 return IRQ_HANDLED; 357 } 358 359 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 360 { 361 int err, irq, gpio = slot->cd_gpio; 362 363 slot->cd_gpio = -EINVAL; 364 slot->cd_irq = -EINVAL; 365 366 if (!gpio_is_valid(gpio)) 367 return; 368 369 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 370 if (err < 0) 371 goto out; 372 373 err = gpio_direction_input(gpio); 374 if (err < 0) 375 goto out_free; 376 377 irq = gpio_to_irq(gpio); 378 if (irq < 0) 379 goto out_free; 380 381 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 382 IRQF_TRIGGER_FALLING, "sd_cd", slot); 383 if (err) 384 goto out_free; 385 386 slot->cd_gpio = gpio; 387 slot->cd_irq = irq; 388 389 return; 390 391 out_free: 392 devm_gpio_free(&slot->chip->pdev->dev, gpio); 393 out: 394 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 395 } 396 397 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 398 { 399 if (slot->cd_irq >= 0) 400 free_irq(slot->cd_irq, slot); 401 } 402 403 #else 404 405 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 406 { 407 } 408 409 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 410 { 411 } 412 413 #endif 414 415 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 416 { 417 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 418 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC; 419 return 0; 420 } 421 422 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 423 { 424 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 425 return 0; 426 } 427 428 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 429 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 430 .probe_slot = mrst_hc_probe_slot, 431 }; 432 433 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 434 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 435 .probe = mrst_hc_probe, 436 }; 437 438 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 439 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 440 .allow_runtime_pm = true, 441 .own_cd_for_runtime_pm = true, 442 }; 443 444 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 445 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 446 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 447 .allow_runtime_pm = true, 448 .probe_slot = mfd_sdio_probe_slot, 449 }; 450 451 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 452 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 453 .allow_runtime_pm = true, 454 .probe_slot = mfd_emmc_probe_slot, 455 }; 456 457 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 458 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 459 .probe_slot = pch_hc_probe_slot, 460 }; 461 462 #ifdef CONFIG_X86 463 464 #define BYT_IOSF_SCCEP 0x63 465 #define BYT_IOSF_OCP_NETCTRL0 0x1078 466 #define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8) 467 468 static void byt_ocp_setting(struct pci_dev *pdev) 469 { 470 u32 val = 0; 471 472 if (pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC && 473 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SDIO && 474 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SD && 475 pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC2) 476 return; 477 478 if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0, 479 &val)) { 480 dev_err(&pdev->dev, "%s read error\n", __func__); 481 return; 482 } 483 484 if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE)) 485 return; 486 487 val &= ~BYT_IOSF_OCP_TIMEOUT_BASE; 488 489 if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0, 490 val)) { 491 dev_err(&pdev->dev, "%s write error\n", __func__); 492 return; 493 } 494 495 dev_dbg(&pdev->dev, "%s completed\n", __func__); 496 } 497 498 #else 499 500 static inline void byt_ocp_setting(struct pci_dev *pdev) 501 { 502 } 503 504 #endif 505 506 enum { 507 INTEL_DSM_FNS = 0, 508 INTEL_DSM_V18_SWITCH = 3, 509 INTEL_DSM_V33_SWITCH = 4, 510 INTEL_DSM_DRV_STRENGTH = 9, 511 INTEL_DSM_D3_RETUNE = 10, 512 }; 513 514 struct intel_host { 515 u32 dsm_fns; 516 int drv_strength; 517 bool d3_retune; 518 bool rpm_retune_ok; 519 u32 glk_rx_ctrl1; 520 u32 glk_tun_val; 521 u32 active_ltr; 522 u32 idle_ltr; 523 }; 524 525 static const guid_t intel_dsm_guid = 526 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F, 527 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61); 528 529 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 530 unsigned int fn, u32 *result) 531 { 532 union acpi_object *obj; 533 int err = 0; 534 size_t len; 535 536 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL); 537 if (!obj) 538 return -EOPNOTSUPP; 539 540 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { 541 err = -EINVAL; 542 goto out; 543 } 544 545 len = min_t(size_t, obj->buffer.length, 4); 546 547 *result = 0; 548 memcpy(result, obj->buffer.pointer, len); 549 out: 550 ACPI_FREE(obj); 551 552 return err; 553 } 554 555 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 556 unsigned int fn, u32 *result) 557 { 558 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 559 return -EOPNOTSUPP; 560 561 return __intel_dsm(intel_host, dev, fn, result); 562 } 563 564 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 565 struct mmc_host *mmc) 566 { 567 int err; 568 u32 val; 569 570 intel_host->d3_retune = true; 571 572 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 573 if (err) { 574 pr_debug("%s: DSM not supported, error %d\n", 575 mmc_hostname(mmc), err); 576 return; 577 } 578 579 pr_debug("%s: DSM function mask %#x\n", 580 mmc_hostname(mmc), intel_host->dsm_fns); 581 582 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 583 intel_host->drv_strength = err ? 0 : val; 584 585 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 586 intel_host->d3_retune = err ? true : !!val; 587 } 588 589 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 590 { 591 u8 reg; 592 593 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 594 reg |= 0x10; 595 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 596 /* For eMMC, minimum is 1us but give it 9us for good measure */ 597 udelay(9); 598 reg &= ~0x10; 599 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 600 /* For eMMC, minimum is 200us but give it 300us for good measure */ 601 usleep_range(300, 1000); 602 } 603 604 static int intel_select_drive_strength(struct mmc_card *card, 605 unsigned int max_dtr, int host_drv, 606 int card_drv, int *drv_type) 607 { 608 struct sdhci_host *host = mmc_priv(card->host); 609 struct sdhci_pci_slot *slot = sdhci_priv(host); 610 struct intel_host *intel_host = sdhci_pci_priv(slot); 611 612 if (!(mmc_driver_type_mask(intel_host->drv_strength) & card_drv)) 613 return 0; 614 615 return intel_host->drv_strength; 616 } 617 618 static int bxt_get_cd(struct mmc_host *mmc) 619 { 620 int gpio_cd = mmc_gpio_get_cd(mmc); 621 struct sdhci_host *host = mmc_priv(mmc); 622 unsigned long flags; 623 int ret = 0; 624 625 if (!gpio_cd) 626 return 0; 627 628 spin_lock_irqsave(&host->lock, flags); 629 630 if (host->flags & SDHCI_DEVICE_DEAD) 631 goto out; 632 633 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 634 out: 635 spin_unlock_irqrestore(&host->lock, flags); 636 637 return ret; 638 } 639 640 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 641 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 642 643 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 644 unsigned short vdd) 645 { 646 int cntr; 647 u8 reg; 648 649 sdhci_set_power(host, mode, vdd); 650 651 if (mode == MMC_POWER_OFF) 652 return; 653 654 /* 655 * Bus power might not enable after D3 -> D0 transition due to the 656 * present state not yet having propagated. Retry for up to 2ms. 657 */ 658 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 659 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 660 if (reg & SDHCI_POWER_ON) 661 break; 662 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 663 reg |= SDHCI_POWER_ON; 664 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 665 } 666 } 667 668 #define INTEL_HS400_ES_REG 0x78 669 #define INTEL_HS400_ES_BIT BIT(0) 670 671 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc, 672 struct mmc_ios *ios) 673 { 674 struct sdhci_host *host = mmc_priv(mmc); 675 u32 val; 676 677 val = sdhci_readl(host, INTEL_HS400_ES_REG); 678 if (ios->enhanced_strobe) 679 val |= INTEL_HS400_ES_BIT; 680 else 681 val &= ~INTEL_HS400_ES_BIT; 682 sdhci_writel(host, val, INTEL_HS400_ES_REG); 683 } 684 685 static int intel_start_signal_voltage_switch(struct mmc_host *mmc, 686 struct mmc_ios *ios) 687 { 688 struct device *dev = mmc_dev(mmc); 689 struct sdhci_host *host = mmc_priv(mmc); 690 struct sdhci_pci_slot *slot = sdhci_priv(host); 691 struct intel_host *intel_host = sdhci_pci_priv(slot); 692 unsigned int fn; 693 u32 result = 0; 694 int err; 695 696 err = sdhci_start_signal_voltage_switch(mmc, ios); 697 if (err) 698 return err; 699 700 switch (ios->signal_voltage) { 701 case MMC_SIGNAL_VOLTAGE_330: 702 fn = INTEL_DSM_V33_SWITCH; 703 break; 704 case MMC_SIGNAL_VOLTAGE_180: 705 fn = INTEL_DSM_V18_SWITCH; 706 break; 707 default: 708 return 0; 709 } 710 711 err = intel_dsm(intel_host, dev, fn, &result); 712 pr_debug("%s: %s DSM fn %u error %d result %u\n", 713 mmc_hostname(mmc), __func__, fn, err, result); 714 715 return 0; 716 } 717 718 static const struct sdhci_ops sdhci_intel_byt_ops = { 719 .set_clock = sdhci_set_clock, 720 .set_power = sdhci_intel_set_power, 721 .enable_dma = sdhci_pci_enable_dma, 722 .set_bus_width = sdhci_set_bus_width, 723 .reset = sdhci_reset, 724 .set_uhs_signaling = sdhci_set_uhs_signaling, 725 .hw_reset = sdhci_pci_hw_reset, 726 }; 727 728 static const struct sdhci_ops sdhci_intel_glk_ops = { 729 .set_clock = sdhci_set_clock, 730 .set_power = sdhci_intel_set_power, 731 .enable_dma = sdhci_pci_enable_dma, 732 .set_bus_width = sdhci_set_bus_width, 733 .reset = sdhci_cqhci_reset, 734 .set_uhs_signaling = sdhci_set_uhs_signaling, 735 .hw_reset = sdhci_pci_hw_reset, 736 .irq = sdhci_cqhci_irq, 737 }; 738 739 static void byt_read_dsm(struct sdhci_pci_slot *slot) 740 { 741 struct intel_host *intel_host = sdhci_pci_priv(slot); 742 struct device *dev = &slot->chip->pdev->dev; 743 struct mmc_host *mmc = slot->host->mmc; 744 745 intel_dsm_init(intel_host, dev, mmc); 746 slot->chip->rpm_retune = intel_host->d3_retune; 747 } 748 749 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode) 750 { 751 int err = sdhci_execute_tuning(mmc, opcode); 752 struct sdhci_host *host = mmc_priv(mmc); 753 754 if (err) 755 return err; 756 757 /* 758 * Tuning can leave the IP in an active state (Buffer Read Enable bit 759 * set) which prevents the entry to low power states (i.e. S0i3). Data 760 * reset will clear it. 761 */ 762 sdhci_reset(host, SDHCI_RESET_DATA); 763 764 return 0; 765 } 766 767 #define INTEL_ACTIVELTR 0x804 768 #define INTEL_IDLELTR 0x808 769 770 #define INTEL_LTR_REQ BIT(15) 771 #define INTEL_LTR_SCALE_MASK GENMASK(11, 10) 772 #define INTEL_LTR_SCALE_1US (2 << 10) 773 #define INTEL_LTR_SCALE_32US (3 << 10) 774 #define INTEL_LTR_VALUE_MASK GENMASK(9, 0) 775 776 static void intel_cache_ltr(struct sdhci_pci_slot *slot) 777 { 778 struct intel_host *intel_host = sdhci_pci_priv(slot); 779 struct sdhci_host *host = slot->host; 780 781 intel_host->active_ltr = readl(host->ioaddr + INTEL_ACTIVELTR); 782 intel_host->idle_ltr = readl(host->ioaddr + INTEL_IDLELTR); 783 } 784 785 static void intel_ltr_set(struct device *dev, s32 val) 786 { 787 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 788 struct sdhci_pci_slot *slot = chip->slots[0]; 789 struct intel_host *intel_host = sdhci_pci_priv(slot); 790 struct sdhci_host *host = slot->host; 791 u32 ltr; 792 793 pm_runtime_get_sync(dev); 794 795 /* 796 * Program latency tolerance (LTR) accordingly what has been asked 797 * by the PM QoS layer or disable it in case we were passed 798 * negative value or PM_QOS_LATENCY_ANY. 799 */ 800 ltr = readl(host->ioaddr + INTEL_ACTIVELTR); 801 802 if (val == PM_QOS_LATENCY_ANY || val < 0) { 803 ltr &= ~INTEL_LTR_REQ; 804 } else { 805 ltr |= INTEL_LTR_REQ; 806 ltr &= ~INTEL_LTR_SCALE_MASK; 807 ltr &= ~INTEL_LTR_VALUE_MASK; 808 809 if (val > INTEL_LTR_VALUE_MASK) { 810 val >>= 5; 811 if (val > INTEL_LTR_VALUE_MASK) 812 val = INTEL_LTR_VALUE_MASK; 813 ltr |= INTEL_LTR_SCALE_32US | val; 814 } else { 815 ltr |= INTEL_LTR_SCALE_1US | val; 816 } 817 } 818 819 if (ltr == intel_host->active_ltr) 820 goto out; 821 822 writel(ltr, host->ioaddr + INTEL_ACTIVELTR); 823 writel(ltr, host->ioaddr + INTEL_IDLELTR); 824 825 /* Cache the values into lpss structure */ 826 intel_cache_ltr(slot); 827 out: 828 pm_runtime_put_autosuspend(dev); 829 } 830 831 static bool intel_use_ltr(struct sdhci_pci_chip *chip) 832 { 833 switch (chip->pdev->device) { 834 case PCI_DEVICE_ID_INTEL_BYT_EMMC: 835 case PCI_DEVICE_ID_INTEL_BYT_EMMC2: 836 case PCI_DEVICE_ID_INTEL_BYT_SDIO: 837 case PCI_DEVICE_ID_INTEL_BYT_SD: 838 case PCI_DEVICE_ID_INTEL_BSW_EMMC: 839 case PCI_DEVICE_ID_INTEL_BSW_SDIO: 840 case PCI_DEVICE_ID_INTEL_BSW_SD: 841 return false; 842 default: 843 return true; 844 } 845 } 846 847 static void intel_ltr_expose(struct sdhci_pci_chip *chip) 848 { 849 struct device *dev = &chip->pdev->dev; 850 851 if (!intel_use_ltr(chip)) 852 return; 853 854 dev->power.set_latency_tolerance = intel_ltr_set; 855 dev_pm_qos_expose_latency_tolerance(dev); 856 } 857 858 static void intel_ltr_hide(struct sdhci_pci_chip *chip) 859 { 860 struct device *dev = &chip->pdev->dev; 861 862 if (!intel_use_ltr(chip)) 863 return; 864 865 dev_pm_qos_hide_latency_tolerance(dev); 866 dev->power.set_latency_tolerance = NULL; 867 } 868 869 static void byt_probe_slot(struct sdhci_pci_slot *slot) 870 { 871 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 872 struct device *dev = &slot->chip->pdev->dev; 873 struct mmc_host *mmc = slot->host->mmc; 874 875 byt_read_dsm(slot); 876 877 byt_ocp_setting(slot->chip->pdev); 878 879 ops->execute_tuning = intel_execute_tuning; 880 ops->start_signal_voltage_switch = intel_start_signal_voltage_switch; 881 882 device_property_read_u32(dev, "max-frequency", &mmc->f_max); 883 884 if (!mmc->slotno) { 885 slot->chip->slots[mmc->slotno] = slot; 886 intel_ltr_expose(slot->chip); 887 } 888 } 889 890 static void byt_add_debugfs(struct sdhci_pci_slot *slot) 891 { 892 struct intel_host *intel_host = sdhci_pci_priv(slot); 893 struct mmc_host *mmc = slot->host->mmc; 894 struct dentry *dir = mmc->debugfs_root; 895 896 if (!intel_use_ltr(slot->chip)) 897 return; 898 899 debugfs_create_x32("active_ltr", 0444, dir, &intel_host->active_ltr); 900 debugfs_create_x32("idle_ltr", 0444, dir, &intel_host->idle_ltr); 901 902 intel_cache_ltr(slot); 903 } 904 905 static int byt_add_host(struct sdhci_pci_slot *slot) 906 { 907 int ret = sdhci_add_host(slot->host); 908 909 if (!ret) 910 byt_add_debugfs(slot); 911 return ret; 912 } 913 914 static void byt_remove_slot(struct sdhci_pci_slot *slot, int dead) 915 { 916 struct mmc_host *mmc = slot->host->mmc; 917 918 if (!mmc->slotno) 919 intel_ltr_hide(slot->chip); 920 } 921 922 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 923 { 924 byt_probe_slot(slot); 925 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 926 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 927 MMC_CAP_CMD_DURING_TFR | 928 MMC_CAP_WAIT_WHILE_BUSY; 929 slot->hw_reset = sdhci_pci_int_hw_reset; 930 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 931 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 932 slot->host->mmc_host_ops.select_drive_strength = 933 intel_select_drive_strength; 934 return 0; 935 } 936 937 static bool glk_broken_cqhci(struct sdhci_pci_slot *slot) 938 { 939 return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 940 dmi_match(DMI_BIOS_VENDOR, "LENOVO"); 941 } 942 943 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot) 944 { 945 int ret = byt_emmc_probe_slot(slot); 946 947 if (!glk_broken_cqhci(slot)) 948 slot->host->mmc->caps2 |= MMC_CAP2_CQE; 949 950 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) { 951 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES, 952 slot->host->mmc_host_ops.hs400_enhanced_strobe = 953 intel_hs400_enhanced_strobe; 954 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; 955 } 956 957 return ret; 958 } 959 960 static const struct cqhci_host_ops glk_cqhci_ops = { 961 .enable = sdhci_cqe_enable, 962 .disable = sdhci_cqe_disable, 963 .dumpregs = sdhci_pci_dumpregs, 964 }; 965 966 static int glk_emmc_add_host(struct sdhci_pci_slot *slot) 967 { 968 struct device *dev = &slot->chip->pdev->dev; 969 struct sdhci_host *host = slot->host; 970 struct cqhci_host *cq_host; 971 bool dma64; 972 int ret; 973 974 ret = sdhci_setup_host(host); 975 if (ret) 976 return ret; 977 978 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); 979 if (!cq_host) { 980 ret = -ENOMEM; 981 goto cleanup; 982 } 983 984 cq_host->mmio = host->ioaddr + 0x200; 985 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 986 cq_host->ops = &glk_cqhci_ops; 987 988 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 989 if (dma64) 990 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 991 992 ret = cqhci_init(cq_host, host->mmc, dma64); 993 if (ret) 994 goto cleanup; 995 996 ret = __sdhci_add_host(host); 997 if (ret) 998 goto cleanup; 999 1000 byt_add_debugfs(slot); 1001 1002 return 0; 1003 1004 cleanup: 1005 sdhci_cleanup_host(host); 1006 return ret; 1007 } 1008 1009 #ifdef CONFIG_PM 1010 #define GLK_RX_CTRL1 0x834 1011 #define GLK_TUN_VAL 0x840 1012 #define GLK_PATH_PLL GENMASK(13, 8) 1013 #define GLK_DLY GENMASK(6, 0) 1014 /* Workaround firmware failing to restore the tuning value */ 1015 static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp) 1016 { 1017 struct sdhci_pci_slot *slot = chip->slots[0]; 1018 struct intel_host *intel_host = sdhci_pci_priv(slot); 1019 struct sdhci_host *host = slot->host; 1020 u32 glk_rx_ctrl1; 1021 u32 glk_tun_val; 1022 u32 dly; 1023 1024 if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc)) 1025 return; 1026 1027 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1); 1028 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL); 1029 1030 if (susp) { 1031 intel_host->glk_rx_ctrl1 = glk_rx_ctrl1; 1032 intel_host->glk_tun_val = glk_tun_val; 1033 return; 1034 } 1035 1036 if (!intel_host->glk_tun_val) 1037 return; 1038 1039 if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) { 1040 intel_host->rpm_retune_ok = true; 1041 return; 1042 } 1043 1044 dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) + 1045 (intel_host->glk_tun_val << 1)); 1046 if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1)) 1047 return; 1048 1049 glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly; 1050 sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1); 1051 1052 intel_host->rpm_retune_ok = true; 1053 chip->rpm_retune = true; 1054 mmc_retune_needed(host->mmc); 1055 pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc)); 1056 } 1057 1058 static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp) 1059 { 1060 if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 1061 !chip->rpm_retune) 1062 glk_rpm_retune_wa(chip, susp); 1063 } 1064 1065 static int glk_runtime_suspend(struct sdhci_pci_chip *chip) 1066 { 1067 glk_rpm_retune_chk(chip, true); 1068 1069 return sdhci_cqhci_runtime_suspend(chip); 1070 } 1071 1072 static int glk_runtime_resume(struct sdhci_pci_chip *chip) 1073 { 1074 glk_rpm_retune_chk(chip, false); 1075 1076 return sdhci_cqhci_runtime_resume(chip); 1077 } 1078 #endif 1079 1080 #ifdef CONFIG_ACPI 1081 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 1082 { 1083 acpi_status status; 1084 unsigned long long max_freq; 1085 1086 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 1087 "MXFQ", NULL, &max_freq); 1088 if (ACPI_FAILURE(status)) { 1089 dev_err(&slot->chip->pdev->dev, 1090 "MXFQ not found in acpi table\n"); 1091 return -EINVAL; 1092 } 1093 1094 slot->host->mmc->f_max = max_freq * 1000000; 1095 1096 return 0; 1097 } 1098 #else 1099 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 1100 { 1101 return 0; 1102 } 1103 #endif 1104 1105 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 1106 { 1107 int err; 1108 1109 byt_probe_slot(slot); 1110 1111 err = ni_set_max_freq(slot); 1112 if (err) 1113 return err; 1114 1115 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 1116 MMC_CAP_WAIT_WHILE_BUSY; 1117 return 0; 1118 } 1119 1120 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 1121 { 1122 byt_probe_slot(slot); 1123 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 1124 MMC_CAP_WAIT_WHILE_BUSY; 1125 return 0; 1126 } 1127 1128 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 1129 { 1130 byt_probe_slot(slot); 1131 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | 1132 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE; 1133 slot->cd_idx = 0; 1134 slot->cd_override_level = true; 1135 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 1136 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 1137 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 1138 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) 1139 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 1140 1141 if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI && 1142 slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3) 1143 slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V; 1144 1145 return 0; 1146 } 1147 1148 #ifdef CONFIG_PM_SLEEP 1149 1150 static int byt_resume(struct sdhci_pci_chip *chip) 1151 { 1152 byt_ocp_setting(chip->pdev); 1153 1154 return sdhci_pci_resume_host(chip); 1155 } 1156 1157 #endif 1158 1159 #ifdef CONFIG_PM 1160 1161 static int byt_runtime_resume(struct sdhci_pci_chip *chip) 1162 { 1163 byt_ocp_setting(chip->pdev); 1164 1165 return sdhci_pci_runtime_resume_host(chip); 1166 } 1167 1168 #endif 1169 1170 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 1171 #ifdef CONFIG_PM_SLEEP 1172 .resume = byt_resume, 1173 #endif 1174 #ifdef CONFIG_PM 1175 .runtime_resume = byt_runtime_resume, 1176 #endif 1177 .allow_runtime_pm = true, 1178 .probe_slot = byt_emmc_probe_slot, 1179 .add_host = byt_add_host, 1180 .remove_slot = byt_remove_slot, 1181 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1182 SDHCI_QUIRK_NO_LED, 1183 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1184 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1185 SDHCI_QUIRK2_STOP_WITH_TC, 1186 .ops = &sdhci_intel_byt_ops, 1187 .priv_size = sizeof(struct intel_host), 1188 }; 1189 1190 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = { 1191 .allow_runtime_pm = true, 1192 .probe_slot = glk_emmc_probe_slot, 1193 .add_host = glk_emmc_add_host, 1194 .remove_slot = byt_remove_slot, 1195 #ifdef CONFIG_PM_SLEEP 1196 .suspend = sdhci_cqhci_suspend, 1197 .resume = sdhci_cqhci_resume, 1198 #endif 1199 #ifdef CONFIG_PM 1200 .runtime_suspend = glk_runtime_suspend, 1201 .runtime_resume = glk_runtime_resume, 1202 #endif 1203 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1204 SDHCI_QUIRK_NO_LED, 1205 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1206 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1207 SDHCI_QUIRK2_STOP_WITH_TC, 1208 .ops = &sdhci_intel_glk_ops, 1209 .priv_size = sizeof(struct intel_host), 1210 }; 1211 1212 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 1213 #ifdef CONFIG_PM_SLEEP 1214 .resume = byt_resume, 1215 #endif 1216 #ifdef CONFIG_PM 1217 .runtime_resume = byt_runtime_resume, 1218 #endif 1219 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1220 SDHCI_QUIRK_NO_LED, 1221 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1222 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1223 .allow_runtime_pm = true, 1224 .probe_slot = ni_byt_sdio_probe_slot, 1225 .add_host = byt_add_host, 1226 .remove_slot = byt_remove_slot, 1227 .ops = &sdhci_intel_byt_ops, 1228 .priv_size = sizeof(struct intel_host), 1229 }; 1230 1231 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 1232 #ifdef CONFIG_PM_SLEEP 1233 .resume = byt_resume, 1234 #endif 1235 #ifdef CONFIG_PM 1236 .runtime_resume = byt_runtime_resume, 1237 #endif 1238 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1239 SDHCI_QUIRK_NO_LED, 1240 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1241 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1242 .allow_runtime_pm = true, 1243 .probe_slot = byt_sdio_probe_slot, 1244 .add_host = byt_add_host, 1245 .remove_slot = byt_remove_slot, 1246 .ops = &sdhci_intel_byt_ops, 1247 .priv_size = sizeof(struct intel_host), 1248 }; 1249 1250 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 1251 #ifdef CONFIG_PM_SLEEP 1252 .resume = byt_resume, 1253 #endif 1254 #ifdef CONFIG_PM 1255 .runtime_resume = byt_runtime_resume, 1256 #endif 1257 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1258 SDHCI_QUIRK_NO_LED, 1259 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 1260 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1261 SDHCI_QUIRK2_STOP_WITH_TC, 1262 .allow_runtime_pm = true, 1263 .own_cd_for_runtime_pm = true, 1264 .probe_slot = byt_sd_probe_slot, 1265 .add_host = byt_add_host, 1266 .remove_slot = byt_remove_slot, 1267 .ops = &sdhci_intel_byt_ops, 1268 .priv_size = sizeof(struct intel_host), 1269 }; 1270 1271 /* Define Host controllers for Intel Merrifield platform */ 1272 #define INTEL_MRFLD_EMMC_0 0 1273 #define INTEL_MRFLD_EMMC_1 1 1274 #define INTEL_MRFLD_SD 2 1275 #define INTEL_MRFLD_SDIO 3 1276 1277 #ifdef CONFIG_ACPI 1278 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) 1279 { 1280 struct acpi_device *device, *child; 1281 1282 device = ACPI_COMPANION(&slot->chip->pdev->dev); 1283 if (!device) 1284 return; 1285 1286 acpi_device_fix_up_power(device); 1287 list_for_each_entry(child, &device->children, node) 1288 if (child->status.present && child->status.enabled) 1289 acpi_device_fix_up_power(child); 1290 } 1291 #else 1292 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {} 1293 #endif 1294 1295 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 1296 { 1297 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 1298 1299 switch (func) { 1300 case INTEL_MRFLD_EMMC_0: 1301 case INTEL_MRFLD_EMMC_1: 1302 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1303 MMC_CAP_8_BIT_DATA | 1304 MMC_CAP_1_8V_DDR; 1305 break; 1306 case INTEL_MRFLD_SD: 1307 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1308 break; 1309 case INTEL_MRFLD_SDIO: 1310 /* Advertise 2.0v for compatibility with the SDIO card's OCR */ 1311 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195; 1312 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1313 MMC_CAP_POWER_OFF_CARD; 1314 break; 1315 default: 1316 return -ENODEV; 1317 } 1318 1319 intel_mrfld_mmc_fix_up_power_slot(slot); 1320 return 0; 1321 } 1322 1323 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 1324 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1325 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 1326 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1327 .allow_runtime_pm = true, 1328 .probe_slot = intel_mrfld_mmc_probe_slot, 1329 }; 1330 1331 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 1332 { 1333 u8 scratch; 1334 int ret; 1335 1336 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 1337 if (ret) 1338 return ret; 1339 1340 /* 1341 * Turn PMOS on [bit 0], set over current detection to 2.4 V 1342 * [bit 1:2] and enable over current debouncing [bit 6]. 1343 */ 1344 if (on) 1345 scratch |= 0x47; 1346 else 1347 scratch &= ~0x47; 1348 1349 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 1350 } 1351 1352 static int jmicron_probe(struct sdhci_pci_chip *chip) 1353 { 1354 int ret; 1355 u16 mmcdev = 0; 1356 1357 if (chip->pdev->revision == 0) { 1358 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 1359 SDHCI_QUIRK_32BIT_DMA_SIZE | 1360 SDHCI_QUIRK_32BIT_ADMA_SIZE | 1361 SDHCI_QUIRK_RESET_AFTER_REQUEST | 1362 SDHCI_QUIRK_BROKEN_SMALL_PIO; 1363 } 1364 1365 /* 1366 * JMicron chips can have two interfaces to the same hardware 1367 * in order to work around limitations in Microsoft's driver. 1368 * We need to make sure we only bind to one of them. 1369 * 1370 * This code assumes two things: 1371 * 1372 * 1. The PCI code adds subfunctions in order. 1373 * 1374 * 2. The MMC interface has a lower subfunction number 1375 * than the SD interface. 1376 */ 1377 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 1378 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 1379 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 1380 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 1381 1382 if (mmcdev) { 1383 struct pci_dev *sd_dev; 1384 1385 sd_dev = NULL; 1386 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 1387 mmcdev, sd_dev)) != NULL) { 1388 if ((PCI_SLOT(chip->pdev->devfn) == 1389 PCI_SLOT(sd_dev->devfn)) && 1390 (chip->pdev->bus == sd_dev->bus)) 1391 break; 1392 } 1393 1394 if (sd_dev) { 1395 pci_dev_put(sd_dev); 1396 dev_info(&chip->pdev->dev, "Refusing to bind to " 1397 "secondary interface.\n"); 1398 return -ENODEV; 1399 } 1400 } 1401 1402 /* 1403 * JMicron chips need a bit of a nudge to enable the power 1404 * output pins. 1405 */ 1406 ret = jmicron_pmos(chip, 1); 1407 if (ret) { 1408 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1409 return ret; 1410 } 1411 1412 /* quirk for unsable RO-detection on JM388 chips */ 1413 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 1414 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1415 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 1416 1417 return 0; 1418 } 1419 1420 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 1421 { 1422 u8 scratch; 1423 1424 scratch = readb(host->ioaddr + 0xC0); 1425 1426 if (on) 1427 scratch |= 0x01; 1428 else 1429 scratch &= ~0x01; 1430 1431 writeb(scratch, host->ioaddr + 0xC0); 1432 } 1433 1434 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 1435 { 1436 if (slot->chip->pdev->revision == 0) { 1437 u16 version; 1438 1439 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 1440 version = (version & SDHCI_VENDOR_VER_MASK) >> 1441 SDHCI_VENDOR_VER_SHIFT; 1442 1443 /* 1444 * Older versions of the chip have lots of nasty glitches 1445 * in the ADMA engine. It's best just to avoid it 1446 * completely. 1447 */ 1448 if (version < 0xAC) 1449 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 1450 } 1451 1452 /* JM388 MMC doesn't support 1.8V while SD supports it */ 1453 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1454 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 1455 MMC_VDD_29_30 | MMC_VDD_30_31 | 1456 MMC_VDD_165_195; /* allow 1.8V */ 1457 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 1458 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 1459 } 1460 1461 /* 1462 * The secondary interface requires a bit set to get the 1463 * interrupts. 1464 */ 1465 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1466 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1467 jmicron_enable_mmc(slot->host, 1); 1468 1469 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 1470 1471 return 0; 1472 } 1473 1474 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 1475 { 1476 if (dead) 1477 return; 1478 1479 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1480 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1481 jmicron_enable_mmc(slot->host, 0); 1482 } 1483 1484 #ifdef CONFIG_PM_SLEEP 1485 static int jmicron_suspend(struct sdhci_pci_chip *chip) 1486 { 1487 int i, ret; 1488 1489 ret = sdhci_pci_suspend_host(chip); 1490 if (ret) 1491 return ret; 1492 1493 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1494 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1495 for (i = 0; i < chip->num_slots; i++) 1496 jmicron_enable_mmc(chip->slots[i]->host, 0); 1497 } 1498 1499 return 0; 1500 } 1501 1502 static int jmicron_resume(struct sdhci_pci_chip *chip) 1503 { 1504 int ret, i; 1505 1506 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1507 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1508 for (i = 0; i < chip->num_slots; i++) 1509 jmicron_enable_mmc(chip->slots[i]->host, 1); 1510 } 1511 1512 ret = jmicron_pmos(chip, 1); 1513 if (ret) { 1514 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1515 return ret; 1516 } 1517 1518 return sdhci_pci_resume_host(chip); 1519 } 1520 #endif 1521 1522 static const struct sdhci_pci_fixes sdhci_jmicron = { 1523 .probe = jmicron_probe, 1524 1525 .probe_slot = jmicron_probe_slot, 1526 .remove_slot = jmicron_remove_slot, 1527 1528 #ifdef CONFIG_PM_SLEEP 1529 .suspend = jmicron_suspend, 1530 .resume = jmicron_resume, 1531 #endif 1532 }; 1533 1534 /* SysKonnect CardBus2SDIO extra registers */ 1535 #define SYSKT_CTRL 0x200 1536 #define SYSKT_RDFIFO_STAT 0x204 1537 #define SYSKT_WRFIFO_STAT 0x208 1538 #define SYSKT_POWER_DATA 0x20c 1539 #define SYSKT_POWER_330 0xef 1540 #define SYSKT_POWER_300 0xf8 1541 #define SYSKT_POWER_184 0xcc 1542 #define SYSKT_POWER_CMD 0x20d 1543 #define SYSKT_POWER_START (1 << 7) 1544 #define SYSKT_POWER_STATUS 0x20e 1545 #define SYSKT_POWER_STATUS_OK (1 << 0) 1546 #define SYSKT_BOARD_REV 0x210 1547 #define SYSKT_CHIP_REV 0x211 1548 #define SYSKT_CONF_DATA 0x212 1549 #define SYSKT_CONF_DATA_1V8 (1 << 2) 1550 #define SYSKT_CONF_DATA_2V5 (1 << 1) 1551 #define SYSKT_CONF_DATA_3V3 (1 << 0) 1552 1553 static int syskt_probe(struct sdhci_pci_chip *chip) 1554 { 1555 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1556 chip->pdev->class &= ~0x0000FF; 1557 chip->pdev->class |= PCI_SDHCI_IFDMA; 1558 } 1559 return 0; 1560 } 1561 1562 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 1563 { 1564 int tm, ps; 1565 1566 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 1567 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 1568 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 1569 "board rev %d.%d, chip rev %d.%d\n", 1570 board_rev >> 4, board_rev & 0xf, 1571 chip_rev >> 4, chip_rev & 0xf); 1572 if (chip_rev >= 0x20) 1573 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 1574 1575 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 1576 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 1577 udelay(50); 1578 tm = 10; /* Wait max 1 ms */ 1579 do { 1580 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 1581 if (ps & SYSKT_POWER_STATUS_OK) 1582 break; 1583 udelay(100); 1584 } while (--tm); 1585 if (!tm) { 1586 dev_err(&slot->chip->pdev->dev, 1587 "power regulator never stabilized"); 1588 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 1589 return -ENODEV; 1590 } 1591 1592 return 0; 1593 } 1594 1595 static const struct sdhci_pci_fixes sdhci_syskt = { 1596 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 1597 .probe = syskt_probe, 1598 .probe_slot = syskt_probe_slot, 1599 }; 1600 1601 static int via_probe(struct sdhci_pci_chip *chip) 1602 { 1603 if (chip->pdev->revision == 0x10) 1604 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 1605 1606 return 0; 1607 } 1608 1609 static const struct sdhci_pci_fixes sdhci_via = { 1610 .probe = via_probe, 1611 }; 1612 1613 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 1614 { 1615 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 1616 return 0; 1617 } 1618 1619 static const struct sdhci_pci_fixes sdhci_rtsx = { 1620 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1621 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 1622 SDHCI_QUIRK2_BROKEN_DDR50, 1623 .probe_slot = rtsx_probe_slot, 1624 }; 1625 1626 /*AMD chipset generation*/ 1627 enum amd_chipset_gen { 1628 AMD_CHIPSET_BEFORE_ML, 1629 AMD_CHIPSET_CZ, 1630 AMD_CHIPSET_NL, 1631 AMD_CHIPSET_UNKNOWN, 1632 }; 1633 1634 /* AMD registers */ 1635 #define AMD_SD_AUTO_PATTERN 0xB8 1636 #define AMD_MSLEEP_DURATION 4 1637 #define AMD_SD_MISC_CONTROL 0xD0 1638 #define AMD_MAX_TUNE_VALUE 0x0B 1639 #define AMD_AUTO_TUNE_SEL 0x10800 1640 #define AMD_FIFO_PTR 0x30 1641 #define AMD_BIT_MASK 0x1F 1642 1643 static void amd_tuning_reset(struct sdhci_host *host) 1644 { 1645 unsigned int val; 1646 1647 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1648 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 1649 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1650 1651 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1652 val &= ~SDHCI_CTRL_EXEC_TUNING; 1653 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1654 } 1655 1656 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 1657 { 1658 unsigned int val; 1659 1660 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 1661 val &= ~AMD_BIT_MASK; 1662 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 1663 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 1664 } 1665 1666 static void amd_enable_manual_tuning(struct pci_dev *pdev) 1667 { 1668 unsigned int val; 1669 1670 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 1671 val |= AMD_FIFO_PTR; 1672 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 1673 } 1674 1675 static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode) 1676 { 1677 struct sdhci_pci_slot *slot = sdhci_priv(host); 1678 struct pci_dev *pdev = slot->chip->pdev; 1679 u8 valid_win = 0; 1680 u8 valid_win_max = 0; 1681 u8 valid_win_end = 0; 1682 u8 ctrl, tune_around; 1683 1684 amd_tuning_reset(host); 1685 1686 for (tune_around = 0; tune_around < 12; tune_around++) { 1687 amd_config_tuning_phase(pdev, tune_around); 1688 1689 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1690 valid_win = 0; 1691 msleep(AMD_MSLEEP_DURATION); 1692 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 1693 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 1694 } else if (++valid_win > valid_win_max) { 1695 valid_win_max = valid_win; 1696 valid_win_end = tune_around; 1697 } 1698 } 1699 1700 if (!valid_win_max) { 1701 dev_err(&pdev->dev, "no tuning point found\n"); 1702 return -EIO; 1703 } 1704 1705 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 1706 1707 amd_enable_manual_tuning(pdev); 1708 1709 host->mmc->retune_period = 0; 1710 1711 return 0; 1712 } 1713 1714 static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode) 1715 { 1716 struct sdhci_host *host = mmc_priv(mmc); 1717 1718 /* AMD requires custom HS200 tuning */ 1719 if (host->timing == MMC_TIMING_MMC_HS200) 1720 return amd_execute_tuning_hs200(host, opcode); 1721 1722 /* Otherwise perform standard SDHCI tuning */ 1723 return sdhci_execute_tuning(mmc, opcode); 1724 } 1725 1726 static int amd_probe_slot(struct sdhci_pci_slot *slot) 1727 { 1728 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 1729 1730 ops->execute_tuning = amd_execute_tuning; 1731 1732 return 0; 1733 } 1734 1735 static int amd_probe(struct sdhci_pci_chip *chip) 1736 { 1737 struct pci_dev *smbus_dev; 1738 enum amd_chipset_gen gen; 1739 1740 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1741 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 1742 if (smbus_dev) { 1743 gen = AMD_CHIPSET_BEFORE_ML; 1744 } else { 1745 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1746 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1747 if (smbus_dev) { 1748 if (smbus_dev->revision < 0x51) 1749 gen = AMD_CHIPSET_CZ; 1750 else 1751 gen = AMD_CHIPSET_NL; 1752 } else { 1753 gen = AMD_CHIPSET_UNKNOWN; 1754 } 1755 } 1756 1757 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1758 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1759 1760 return 0; 1761 } 1762 1763 static u32 sdhci_read_present_state(struct sdhci_host *host) 1764 { 1765 return sdhci_readl(host, SDHCI_PRESENT_STATE); 1766 } 1767 1768 static void amd_sdhci_reset(struct sdhci_host *host, u8 mask) 1769 { 1770 struct sdhci_pci_slot *slot = sdhci_priv(host); 1771 struct pci_dev *pdev = slot->chip->pdev; 1772 u32 present_state; 1773 1774 /* 1775 * SDHC 0x7906 requires a hard reset to clear all internal state. 1776 * Otherwise it can get into a bad state where the DATA lines are always 1777 * read as zeros. 1778 */ 1779 if (pdev->device == 0x7906 && (mask & SDHCI_RESET_ALL)) { 1780 pci_clear_master(pdev); 1781 1782 pci_save_state(pdev); 1783 1784 pci_set_power_state(pdev, PCI_D3cold); 1785 pr_debug("%s: power_state=%u\n", mmc_hostname(host->mmc), 1786 pdev->current_state); 1787 pci_set_power_state(pdev, PCI_D0); 1788 1789 pci_restore_state(pdev); 1790 1791 /* 1792 * SDHCI_RESET_ALL says the card detect logic should not be 1793 * reset, but since we need to reset the entire controller 1794 * we should wait until the card detect logic has stabilized. 1795 * 1796 * This normally takes about 40ms. 1797 */ 1798 readx_poll_timeout( 1799 sdhci_read_present_state, 1800 host, 1801 present_state, 1802 present_state & SDHCI_CD_STABLE, 1803 10000, 1804 100000 1805 ); 1806 } 1807 1808 return sdhci_reset(host, mask); 1809 } 1810 1811 static const struct sdhci_ops amd_sdhci_pci_ops = { 1812 .set_clock = sdhci_set_clock, 1813 .enable_dma = sdhci_pci_enable_dma, 1814 .set_bus_width = sdhci_set_bus_width, 1815 .reset = amd_sdhci_reset, 1816 .set_uhs_signaling = sdhci_set_uhs_signaling, 1817 }; 1818 1819 static const struct sdhci_pci_fixes sdhci_amd = { 1820 .probe = amd_probe, 1821 .ops = &amd_sdhci_pci_ops, 1822 .probe_slot = amd_probe_slot, 1823 }; 1824 1825 static const struct pci_device_id pci_ids[] = { 1826 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh), 1827 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc), 1828 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc), 1829 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc), 1830 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712), 1831 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712), 1832 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714), 1833 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714), 1834 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe), 1835 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron), 1836 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron), 1837 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron), 1838 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron), 1839 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt), 1840 SDHCI_PCI_DEVICE(VIA, 95D0, via), 1841 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx), 1842 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk), 1843 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0), 1844 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2), 1845 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2), 1846 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd), 1847 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio), 1848 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio), 1849 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc), 1850 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc), 1851 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio), 1852 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio), 1853 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc), 1854 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio), 1855 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio), 1856 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd), 1857 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc), 1858 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc), 1859 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio), 1860 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd), 1861 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd), 1862 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio), 1863 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio), 1864 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc), 1865 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc), 1866 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc), 1867 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc), 1868 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio), 1869 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd), 1870 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc), 1871 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc), 1872 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc), 1873 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio), 1874 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd), 1875 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc), 1876 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio), 1877 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd), 1878 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc), 1879 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio), 1880 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd), 1881 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc), 1882 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio), 1883 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd), 1884 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc), 1885 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd), 1886 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd), 1887 SDHCI_PCI_DEVICE(INTEL, ICP_EMMC, intel_glk_emmc), 1888 SDHCI_PCI_DEVICE(INTEL, ICP_SD, intel_byt_sd), 1889 SDHCI_PCI_DEVICE(INTEL, EHL_EMMC, intel_glk_emmc), 1890 SDHCI_PCI_DEVICE(INTEL, EHL_SD, intel_byt_sd), 1891 SDHCI_PCI_DEVICE(INTEL, CML_EMMC, intel_glk_emmc), 1892 SDHCI_PCI_DEVICE(INTEL, CML_SD, intel_byt_sd), 1893 SDHCI_PCI_DEVICE(INTEL, CMLH_SD, intel_byt_sd), 1894 SDHCI_PCI_DEVICE(INTEL, JSL_EMMC, intel_glk_emmc), 1895 SDHCI_PCI_DEVICE(INTEL, JSL_SD, intel_byt_sd), 1896 SDHCI_PCI_DEVICE(O2, 8120, o2), 1897 SDHCI_PCI_DEVICE(O2, 8220, o2), 1898 SDHCI_PCI_DEVICE(O2, 8221, o2), 1899 SDHCI_PCI_DEVICE(O2, 8320, o2), 1900 SDHCI_PCI_DEVICE(O2, 8321, o2), 1901 SDHCI_PCI_DEVICE(O2, FUJIN2, o2), 1902 SDHCI_PCI_DEVICE(O2, SDS0, o2), 1903 SDHCI_PCI_DEVICE(O2, SDS1, o2), 1904 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2), 1905 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), 1906 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan), 1907 SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps), 1908 SDHCI_PCI_DEVICE(GLI, 9750, gl9750), 1909 SDHCI_PCI_DEVICE(GLI, 9755, gl9755), 1910 SDHCI_PCI_DEVICE(GLI, 9763E, gl9763e), 1911 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), 1912 /* Generic SD host controller */ 1913 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, 1914 { /* end: all zeroes */ }, 1915 }; 1916 1917 MODULE_DEVICE_TABLE(pci, pci_ids); 1918 1919 /*****************************************************************************\ 1920 * * 1921 * SDHCI core callbacks * 1922 * * 1923 \*****************************************************************************/ 1924 1925 int sdhci_pci_enable_dma(struct sdhci_host *host) 1926 { 1927 struct sdhci_pci_slot *slot; 1928 struct pci_dev *pdev; 1929 1930 slot = sdhci_priv(host); 1931 pdev = slot->chip->pdev; 1932 1933 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1934 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1935 (host->flags & SDHCI_USE_SDMA)) { 1936 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1937 "doesn't fully claim to support it.\n"); 1938 } 1939 1940 pci_set_master(pdev); 1941 1942 return 0; 1943 } 1944 1945 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1946 { 1947 struct sdhci_pci_slot *slot = sdhci_priv(host); 1948 int rst_n_gpio = slot->rst_n_gpio; 1949 1950 if (!gpio_is_valid(rst_n_gpio)) 1951 return; 1952 gpio_set_value_cansleep(rst_n_gpio, 0); 1953 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1954 udelay(10); 1955 gpio_set_value_cansleep(rst_n_gpio, 1); 1956 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1957 usleep_range(300, 1000); 1958 } 1959 1960 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1961 { 1962 struct sdhci_pci_slot *slot = sdhci_priv(host); 1963 1964 if (slot->hw_reset) 1965 slot->hw_reset(host); 1966 } 1967 1968 static const struct sdhci_ops sdhci_pci_ops = { 1969 .set_clock = sdhci_set_clock, 1970 .enable_dma = sdhci_pci_enable_dma, 1971 .set_bus_width = sdhci_set_bus_width, 1972 .reset = sdhci_reset, 1973 .set_uhs_signaling = sdhci_set_uhs_signaling, 1974 .hw_reset = sdhci_pci_hw_reset, 1975 }; 1976 1977 /*****************************************************************************\ 1978 * * 1979 * Suspend/resume * 1980 * * 1981 \*****************************************************************************/ 1982 1983 #ifdef CONFIG_PM_SLEEP 1984 static int sdhci_pci_suspend(struct device *dev) 1985 { 1986 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 1987 1988 if (!chip) 1989 return 0; 1990 1991 if (chip->fixes && chip->fixes->suspend) 1992 return chip->fixes->suspend(chip); 1993 1994 return sdhci_pci_suspend_host(chip); 1995 } 1996 1997 static int sdhci_pci_resume(struct device *dev) 1998 { 1999 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2000 2001 if (!chip) 2002 return 0; 2003 2004 if (chip->fixes && chip->fixes->resume) 2005 return chip->fixes->resume(chip); 2006 2007 return sdhci_pci_resume_host(chip); 2008 } 2009 #endif 2010 2011 #ifdef CONFIG_PM 2012 static int sdhci_pci_runtime_suspend(struct device *dev) 2013 { 2014 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2015 2016 if (!chip) 2017 return 0; 2018 2019 if (chip->fixes && chip->fixes->runtime_suspend) 2020 return chip->fixes->runtime_suspend(chip); 2021 2022 return sdhci_pci_runtime_suspend_host(chip); 2023 } 2024 2025 static int sdhci_pci_runtime_resume(struct device *dev) 2026 { 2027 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2028 2029 if (!chip) 2030 return 0; 2031 2032 if (chip->fixes && chip->fixes->runtime_resume) 2033 return chip->fixes->runtime_resume(chip); 2034 2035 return sdhci_pci_runtime_resume_host(chip); 2036 } 2037 #endif 2038 2039 static const struct dev_pm_ops sdhci_pci_pm_ops = { 2040 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 2041 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 2042 sdhci_pci_runtime_resume, NULL) 2043 }; 2044 2045 /*****************************************************************************\ 2046 * * 2047 * Device probing/removal * 2048 * * 2049 \*****************************************************************************/ 2050 2051 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 2052 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 2053 int slotno) 2054 { 2055 struct sdhci_pci_slot *slot; 2056 struct sdhci_host *host; 2057 int ret, bar = first_bar + slotno; 2058 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 2059 2060 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 2061 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 2062 return ERR_PTR(-ENODEV); 2063 } 2064 2065 if (pci_resource_len(pdev, bar) < 0x100) { 2066 dev_err(&pdev->dev, "Invalid iomem size. You may " 2067 "experience problems.\n"); 2068 } 2069 2070 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 2071 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 2072 return ERR_PTR(-ENODEV); 2073 } 2074 2075 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 2076 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 2077 return ERR_PTR(-ENODEV); 2078 } 2079 2080 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 2081 if (IS_ERR(host)) { 2082 dev_err(&pdev->dev, "cannot allocate host\n"); 2083 return ERR_CAST(host); 2084 } 2085 2086 slot = sdhci_priv(host); 2087 2088 slot->chip = chip; 2089 slot->host = host; 2090 slot->rst_n_gpio = -EINVAL; 2091 slot->cd_gpio = -EINVAL; 2092 slot->cd_idx = -1; 2093 2094 /* Retrieve platform data if there is any */ 2095 if (*sdhci_pci_get_data) 2096 slot->data = sdhci_pci_get_data(pdev, slotno); 2097 2098 if (slot->data) { 2099 if (slot->data->setup) { 2100 ret = slot->data->setup(slot->data); 2101 if (ret) { 2102 dev_err(&pdev->dev, "platform setup failed\n"); 2103 goto free; 2104 } 2105 } 2106 slot->rst_n_gpio = slot->data->rst_n_gpio; 2107 slot->cd_gpio = slot->data->cd_gpio; 2108 } 2109 2110 host->hw_name = "PCI"; 2111 host->ops = chip->fixes && chip->fixes->ops ? 2112 chip->fixes->ops : 2113 &sdhci_pci_ops; 2114 host->quirks = chip->quirks; 2115 host->quirks2 = chip->quirks2; 2116 2117 host->irq = pdev->irq; 2118 2119 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 2120 if (ret) { 2121 dev_err(&pdev->dev, "cannot request region\n"); 2122 goto cleanup; 2123 } 2124 2125 host->ioaddr = pcim_iomap_table(pdev)[bar]; 2126 2127 if (chip->fixes && chip->fixes->probe_slot) { 2128 ret = chip->fixes->probe_slot(slot); 2129 if (ret) 2130 goto cleanup; 2131 } 2132 2133 if (gpio_is_valid(slot->rst_n_gpio)) { 2134 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 2135 gpio_direction_output(slot->rst_n_gpio, 1); 2136 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 2137 slot->hw_reset = sdhci_pci_gpio_hw_reset; 2138 } else { 2139 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 2140 slot->rst_n_gpio = -EINVAL; 2141 } 2142 } 2143 2144 host->mmc->pm_caps = MMC_PM_KEEP_POWER; 2145 host->mmc->slotno = slotno; 2146 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 2147 2148 if (device_can_wakeup(&pdev->dev)) 2149 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ; 2150 2151 if (host->mmc->caps & MMC_CAP_CD_WAKE) 2152 device_init_wakeup(&pdev->dev, true); 2153 2154 if (slot->cd_idx >= 0) { 2155 ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx, 2156 slot->cd_override_level, 0); 2157 if (ret && ret != -EPROBE_DEFER) 2158 ret = mmc_gpiod_request_cd(host->mmc, NULL, 2159 slot->cd_idx, 2160 slot->cd_override_level, 2161 0); 2162 if (ret == -EPROBE_DEFER) 2163 goto remove; 2164 2165 if (ret) { 2166 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 2167 slot->cd_idx = -1; 2168 } 2169 } 2170 2171 if (chip->fixes && chip->fixes->add_host) 2172 ret = chip->fixes->add_host(slot); 2173 else 2174 ret = sdhci_add_host(host); 2175 if (ret) 2176 goto remove; 2177 2178 sdhci_pci_add_own_cd(slot); 2179 2180 /* 2181 * Check if the chip needs a separate GPIO for card detect to wake up 2182 * from runtime suspend. If it is not there, don't allow runtime PM. 2183 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 2184 */ 2185 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 2186 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 2187 chip->allow_runtime_pm = false; 2188 2189 return slot; 2190 2191 remove: 2192 if (chip->fixes && chip->fixes->remove_slot) 2193 chip->fixes->remove_slot(slot, 0); 2194 2195 cleanup: 2196 if (slot->data && slot->data->cleanup) 2197 slot->data->cleanup(slot->data); 2198 2199 free: 2200 sdhci_free_host(host); 2201 2202 return ERR_PTR(ret); 2203 } 2204 2205 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 2206 { 2207 int dead; 2208 u32 scratch; 2209 2210 sdhci_pci_remove_own_cd(slot); 2211 2212 dead = 0; 2213 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 2214 if (scratch == (u32)-1) 2215 dead = 1; 2216 2217 sdhci_remove_host(slot->host, dead); 2218 2219 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 2220 slot->chip->fixes->remove_slot(slot, dead); 2221 2222 if (slot->data && slot->data->cleanup) 2223 slot->data->cleanup(slot->data); 2224 2225 sdhci_free_host(slot->host); 2226 } 2227 2228 static void sdhci_pci_runtime_pm_allow(struct device *dev) 2229 { 2230 pm_suspend_ignore_children(dev, 1); 2231 pm_runtime_set_autosuspend_delay(dev, 50); 2232 pm_runtime_use_autosuspend(dev); 2233 pm_runtime_allow(dev); 2234 /* Stay active until mmc core scans for a card */ 2235 pm_runtime_put_noidle(dev); 2236 } 2237 2238 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 2239 { 2240 pm_runtime_forbid(dev); 2241 pm_runtime_get_noresume(dev); 2242 } 2243 2244 static int sdhci_pci_probe(struct pci_dev *pdev, 2245 const struct pci_device_id *ent) 2246 { 2247 struct sdhci_pci_chip *chip; 2248 struct sdhci_pci_slot *slot; 2249 2250 u8 slots, first_bar; 2251 int ret, i; 2252 2253 BUG_ON(pdev == NULL); 2254 BUG_ON(ent == NULL); 2255 2256 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 2257 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 2258 2259 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 2260 if (ret) 2261 return ret; 2262 2263 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 2264 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 2265 2266 BUG_ON(slots > MAX_SLOTS); 2267 2268 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 2269 if (ret) 2270 return ret; 2271 2272 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 2273 2274 if (first_bar > 5) { 2275 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 2276 return -ENODEV; 2277 } 2278 2279 ret = pcim_enable_device(pdev); 2280 if (ret) 2281 return ret; 2282 2283 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 2284 if (!chip) 2285 return -ENOMEM; 2286 2287 chip->pdev = pdev; 2288 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 2289 if (chip->fixes) { 2290 chip->quirks = chip->fixes->quirks; 2291 chip->quirks2 = chip->fixes->quirks2; 2292 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 2293 } 2294 chip->num_slots = slots; 2295 chip->pm_retune = true; 2296 chip->rpm_retune = true; 2297 2298 pci_set_drvdata(pdev, chip); 2299 2300 if (chip->fixes && chip->fixes->probe) { 2301 ret = chip->fixes->probe(chip); 2302 if (ret) 2303 return ret; 2304 } 2305 2306 slots = chip->num_slots; /* Quirk may have changed this */ 2307 2308 for (i = 0; i < slots; i++) { 2309 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 2310 if (IS_ERR(slot)) { 2311 for (i--; i >= 0; i--) 2312 sdhci_pci_remove_slot(chip->slots[i]); 2313 return PTR_ERR(slot); 2314 } 2315 2316 chip->slots[i] = slot; 2317 } 2318 2319 if (chip->allow_runtime_pm) 2320 sdhci_pci_runtime_pm_allow(&pdev->dev); 2321 2322 return 0; 2323 } 2324 2325 static void sdhci_pci_remove(struct pci_dev *pdev) 2326 { 2327 int i; 2328 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 2329 2330 if (chip->allow_runtime_pm) 2331 sdhci_pci_runtime_pm_forbid(&pdev->dev); 2332 2333 for (i = 0; i < chip->num_slots; i++) 2334 sdhci_pci_remove_slot(chip->slots[i]); 2335 } 2336 2337 static struct pci_driver sdhci_driver = { 2338 .name = "sdhci-pci", 2339 .id_table = pci_ids, 2340 .probe = sdhci_pci_probe, 2341 .remove = sdhci_pci_remove, 2342 .driver = { 2343 .pm = &sdhci_pci_pm_ops 2344 }, 2345 }; 2346 2347 module_pci_driver(sdhci_driver); 2348 2349 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 2350 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 2351 MODULE_LICENSE("GPL"); 2352