1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 2 * 3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 * 10 * Thanks to the following companies for their support: 11 * 12 * - JMicron (hardware and technical support) 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/highmem.h> 17 #include <linux/module.h> 18 #include <linux/pci.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/slab.h> 21 #include <linux/device.h> 22 #include <linux/mmc/host.h> 23 #include <linux/mmc/mmc.h> 24 #include <linux/scatterlist.h> 25 #include <linux/io.h> 26 #include <linux/gpio.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/mmc/slot-gpio.h> 29 #include <linux/mmc/sdhci-pci-data.h> 30 31 #include "sdhci.h" 32 #include "sdhci-pci.h" 33 #include "sdhci-pci-o2micro.h" 34 35 /*****************************************************************************\ 36 * * 37 * Hardware specific quirk handling * 38 * * 39 \*****************************************************************************/ 40 41 static int ricoh_probe(struct sdhci_pci_chip *chip) 42 { 43 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 44 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 45 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 46 return 0; 47 } 48 49 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 50 { 51 slot->host->caps = 52 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 53 & SDHCI_TIMEOUT_CLK_MASK) | 54 55 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 56 & SDHCI_CLOCK_BASE_MASK) | 57 58 SDHCI_TIMEOUT_CLK_UNIT | 59 SDHCI_CAN_VDD_330 | 60 SDHCI_CAN_DO_HISPD | 61 SDHCI_CAN_DO_SDMA; 62 return 0; 63 } 64 65 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 66 { 67 /* Apply a delay to allow controller to settle */ 68 /* Otherwise it becomes confused if card state changed 69 during suspend */ 70 msleep(500); 71 return 0; 72 } 73 74 static const struct sdhci_pci_fixes sdhci_ricoh = { 75 .probe = ricoh_probe, 76 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 77 SDHCI_QUIRK_FORCE_DMA | 78 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 79 }; 80 81 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 82 .probe_slot = ricoh_mmc_probe_slot, 83 .resume = ricoh_mmc_resume, 84 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 85 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 86 SDHCI_QUIRK_NO_CARD_NO_RESET | 87 SDHCI_QUIRK_MISSING_CAPS 88 }; 89 90 static const struct sdhci_pci_fixes sdhci_ene_712 = { 91 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 92 SDHCI_QUIRK_BROKEN_DMA, 93 }; 94 95 static const struct sdhci_pci_fixes sdhci_ene_714 = { 96 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 97 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 98 SDHCI_QUIRK_BROKEN_DMA, 99 }; 100 101 static const struct sdhci_pci_fixes sdhci_cafe = { 102 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 103 SDHCI_QUIRK_NO_BUSY_IRQ | 104 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 105 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 106 }; 107 108 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 109 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 110 }; 111 112 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 113 { 114 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 115 return 0; 116 } 117 118 /* 119 * ADMA operation is disabled for Moorestown platform due to 120 * hardware bugs. 121 */ 122 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 123 { 124 /* 125 * slots number is fixed here for MRST as SDIO3/5 are never used and 126 * have hardware bugs. 127 */ 128 chip->num_slots = 1; 129 return 0; 130 } 131 132 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 133 { 134 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 135 return 0; 136 } 137 138 #ifdef CONFIG_PM 139 140 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 141 { 142 struct sdhci_pci_slot *slot = dev_id; 143 struct sdhci_host *host = slot->host; 144 145 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 146 return IRQ_HANDLED; 147 } 148 149 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 150 { 151 int err, irq, gpio = slot->cd_gpio; 152 153 slot->cd_gpio = -EINVAL; 154 slot->cd_irq = -EINVAL; 155 156 if (!gpio_is_valid(gpio)) 157 return; 158 159 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 160 if (err < 0) 161 goto out; 162 163 err = gpio_direction_input(gpio); 164 if (err < 0) 165 goto out_free; 166 167 irq = gpio_to_irq(gpio); 168 if (irq < 0) 169 goto out_free; 170 171 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 172 IRQF_TRIGGER_FALLING, "sd_cd", slot); 173 if (err) 174 goto out_free; 175 176 slot->cd_gpio = gpio; 177 slot->cd_irq = irq; 178 179 return; 180 181 out_free: 182 devm_gpio_free(&slot->chip->pdev->dev, gpio); 183 out: 184 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 185 } 186 187 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 188 { 189 if (slot->cd_irq >= 0) 190 free_irq(slot->cd_irq, slot); 191 } 192 193 #else 194 195 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 196 { 197 } 198 199 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 200 { 201 } 202 203 #endif 204 205 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 206 { 207 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 208 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC | 209 MMC_CAP2_HC_ERASE_SZ; 210 return 0; 211 } 212 213 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 214 { 215 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 216 return 0; 217 } 218 219 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 220 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 221 .probe_slot = mrst_hc_probe_slot, 222 }; 223 224 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 225 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 226 .probe = mrst_hc_probe, 227 }; 228 229 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 230 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 231 .allow_runtime_pm = true, 232 .own_cd_for_runtime_pm = true, 233 }; 234 235 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 236 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 237 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 238 .allow_runtime_pm = true, 239 .probe_slot = mfd_sdio_probe_slot, 240 }; 241 242 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 243 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 244 .allow_runtime_pm = true, 245 .probe_slot = mfd_emmc_probe_slot, 246 }; 247 248 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 249 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 250 .probe_slot = pch_hc_probe_slot, 251 }; 252 253 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 254 { 255 u8 reg; 256 257 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 258 reg |= 0x10; 259 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 260 /* For eMMC, minimum is 1us but give it 9us for good measure */ 261 udelay(9); 262 reg &= ~0x10; 263 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 264 /* For eMMC, minimum is 200us but give it 300us for good measure */ 265 usleep_range(300, 1000); 266 } 267 268 static int spt_select_drive_strength(struct sdhci_host *host, 269 struct mmc_card *card, 270 unsigned int max_dtr, 271 int host_drv, int card_drv, int *drv_type) 272 { 273 int drive_strength; 274 275 if (sdhci_pci_spt_drive_strength > 0) 276 drive_strength = sdhci_pci_spt_drive_strength & 0xf; 277 else 278 drive_strength = 0; /* Default 50-ohm */ 279 280 if ((mmc_driver_type_mask(drive_strength) & card_drv) == 0) 281 drive_strength = 0; /* Default 50-ohm */ 282 283 return drive_strength; 284 } 285 286 /* Try to read the drive strength from the card */ 287 static void spt_read_drive_strength(struct sdhci_host *host) 288 { 289 u32 val, i, t; 290 u16 m; 291 292 if (sdhci_pci_spt_drive_strength) 293 return; 294 295 sdhci_pci_spt_drive_strength = -1; 296 297 m = sdhci_readw(host, SDHCI_HOST_CONTROL2) & 0x7; 298 if (m != 3 && m != 5) 299 return; 300 val = sdhci_readl(host, SDHCI_PRESENT_STATE); 301 if (val & 0x3) 302 return; 303 sdhci_writel(host, 0x007f0023, SDHCI_INT_ENABLE); 304 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 305 sdhci_writew(host, 0x10, SDHCI_TRANSFER_MODE); 306 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 307 sdhci_writew(host, 512, SDHCI_BLOCK_SIZE); 308 sdhci_writew(host, 1, SDHCI_BLOCK_COUNT); 309 sdhci_writel(host, 0, SDHCI_ARGUMENT); 310 sdhci_writew(host, 0x83b, SDHCI_COMMAND); 311 for (i = 0; i < 1000; i++) { 312 val = sdhci_readl(host, SDHCI_INT_STATUS); 313 if (val & 0xffff8000) 314 return; 315 if (val & 0x20) 316 break; 317 udelay(1); 318 } 319 val = sdhci_readl(host, SDHCI_PRESENT_STATE); 320 if (!(val & 0x800)) 321 return; 322 for (i = 0; i < 47; i++) 323 val = sdhci_readl(host, SDHCI_BUFFER); 324 t = val & 0xf00; 325 if (t != 0x200 && t != 0x300) 326 return; 327 328 sdhci_pci_spt_drive_strength = 0x10 | ((val >> 12) & 0xf); 329 } 330 331 static int bxt_get_cd(struct mmc_host *mmc) 332 { 333 int gpio_cd = mmc_gpio_get_cd(mmc); 334 struct sdhci_host *host = mmc_priv(mmc); 335 unsigned long flags; 336 int ret = 0; 337 338 if (!gpio_cd) 339 return 0; 340 341 spin_lock_irqsave(&host->lock, flags); 342 343 if (host->flags & SDHCI_DEVICE_DEAD) 344 goto out; 345 346 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 347 out: 348 spin_unlock_irqrestore(&host->lock, flags); 349 350 return ret; 351 } 352 353 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 354 { 355 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 356 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 357 MMC_CAP_WAIT_WHILE_BUSY; 358 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ; 359 slot->hw_reset = sdhci_pci_int_hw_reset; 360 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 361 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 362 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_SPT_EMMC) { 363 spt_read_drive_strength(slot->host); 364 slot->select_drive_strength = spt_select_drive_strength; 365 } 366 return 0; 367 } 368 369 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 370 { 371 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 372 MMC_CAP_WAIT_WHILE_BUSY; 373 return 0; 374 } 375 376 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 377 { 378 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 379 slot->cd_con_id = NULL; 380 slot->cd_idx = 0; 381 slot->cd_override_level = true; 382 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 383 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 384 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD) { 385 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 386 slot->host->mmc->caps |= MMC_CAP_AGGRESSIVE_PM; 387 } 388 389 return 0; 390 } 391 392 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 393 .allow_runtime_pm = true, 394 .probe_slot = byt_emmc_probe_slot, 395 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 396 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 397 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 398 SDHCI_QUIRK2_STOP_WITH_TC, 399 }; 400 401 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 402 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 403 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 404 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 405 .allow_runtime_pm = true, 406 .probe_slot = byt_sdio_probe_slot, 407 }; 408 409 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 410 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 411 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 412 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 413 SDHCI_QUIRK2_STOP_WITH_TC, 414 .allow_runtime_pm = true, 415 .own_cd_for_runtime_pm = true, 416 .probe_slot = byt_sd_probe_slot, 417 }; 418 419 /* Define Host controllers for Intel Merrifield platform */ 420 #define INTEL_MRFLD_EMMC_0 0 421 #define INTEL_MRFLD_EMMC_1 1 422 #define INTEL_MRFLD_SD 2 423 #define INTEL_MRFLD_SDIO 3 424 425 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 426 { 427 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 428 429 switch (func) { 430 case INTEL_MRFLD_EMMC_0: 431 case INTEL_MRFLD_EMMC_1: 432 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 433 MMC_CAP_8_BIT_DATA | 434 MMC_CAP_1_8V_DDR; 435 break; 436 case INTEL_MRFLD_SD: 437 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 438 break; 439 case INTEL_MRFLD_SDIO: 440 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 441 MMC_CAP_POWER_OFF_CARD; 442 break; 443 default: 444 return -ENODEV; 445 } 446 return 0; 447 } 448 449 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 450 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 451 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 452 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 453 .allow_runtime_pm = true, 454 .probe_slot = intel_mrfld_mmc_probe_slot, 455 }; 456 457 /* O2Micro extra registers */ 458 #define O2_SD_LOCK_WP 0xD3 459 #define O2_SD_MULTI_VCC3V 0xEE 460 #define O2_SD_CLKREQ 0xEC 461 #define O2_SD_CAPS 0xE0 462 #define O2_SD_ADMA1 0xE2 463 #define O2_SD_ADMA2 0xE7 464 #define O2_SD_INF_MOD 0xF1 465 466 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 467 { 468 u8 scratch; 469 int ret; 470 471 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 472 if (ret) 473 return ret; 474 475 /* 476 * Turn PMOS on [bit 0], set over current detection to 2.4 V 477 * [bit 1:2] and enable over current debouncing [bit 6]. 478 */ 479 if (on) 480 scratch |= 0x47; 481 else 482 scratch &= ~0x47; 483 484 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 485 } 486 487 static int jmicron_probe(struct sdhci_pci_chip *chip) 488 { 489 int ret; 490 u16 mmcdev = 0; 491 492 if (chip->pdev->revision == 0) { 493 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 494 SDHCI_QUIRK_32BIT_DMA_SIZE | 495 SDHCI_QUIRK_32BIT_ADMA_SIZE | 496 SDHCI_QUIRK_RESET_AFTER_REQUEST | 497 SDHCI_QUIRK_BROKEN_SMALL_PIO; 498 } 499 500 /* 501 * JMicron chips can have two interfaces to the same hardware 502 * in order to work around limitations in Microsoft's driver. 503 * We need to make sure we only bind to one of them. 504 * 505 * This code assumes two things: 506 * 507 * 1. The PCI code adds subfunctions in order. 508 * 509 * 2. The MMC interface has a lower subfunction number 510 * than the SD interface. 511 */ 512 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 513 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 514 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 515 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 516 517 if (mmcdev) { 518 struct pci_dev *sd_dev; 519 520 sd_dev = NULL; 521 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 522 mmcdev, sd_dev)) != NULL) { 523 if ((PCI_SLOT(chip->pdev->devfn) == 524 PCI_SLOT(sd_dev->devfn)) && 525 (chip->pdev->bus == sd_dev->bus)) 526 break; 527 } 528 529 if (sd_dev) { 530 pci_dev_put(sd_dev); 531 dev_info(&chip->pdev->dev, "Refusing to bind to " 532 "secondary interface.\n"); 533 return -ENODEV; 534 } 535 } 536 537 /* 538 * JMicron chips need a bit of a nudge to enable the power 539 * output pins. 540 */ 541 ret = jmicron_pmos(chip, 1); 542 if (ret) { 543 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 544 return ret; 545 } 546 547 /* quirk for unsable RO-detection on JM388 chips */ 548 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 549 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 550 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 551 552 return 0; 553 } 554 555 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 556 { 557 u8 scratch; 558 559 scratch = readb(host->ioaddr + 0xC0); 560 561 if (on) 562 scratch |= 0x01; 563 else 564 scratch &= ~0x01; 565 566 writeb(scratch, host->ioaddr + 0xC0); 567 } 568 569 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 570 { 571 if (slot->chip->pdev->revision == 0) { 572 u16 version; 573 574 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 575 version = (version & SDHCI_VENDOR_VER_MASK) >> 576 SDHCI_VENDOR_VER_SHIFT; 577 578 /* 579 * Older versions of the chip have lots of nasty glitches 580 * in the ADMA engine. It's best just to avoid it 581 * completely. 582 */ 583 if (version < 0xAC) 584 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 585 } 586 587 /* JM388 MMC doesn't support 1.8V while SD supports it */ 588 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 589 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 590 MMC_VDD_29_30 | MMC_VDD_30_31 | 591 MMC_VDD_165_195; /* allow 1.8V */ 592 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 593 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 594 } 595 596 /* 597 * The secondary interface requires a bit set to get the 598 * interrupts. 599 */ 600 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 601 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 602 jmicron_enable_mmc(slot->host, 1); 603 604 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 605 606 return 0; 607 } 608 609 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 610 { 611 if (dead) 612 return; 613 614 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 615 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 616 jmicron_enable_mmc(slot->host, 0); 617 } 618 619 static int jmicron_suspend(struct sdhci_pci_chip *chip) 620 { 621 int i; 622 623 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 624 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 625 for (i = 0; i < chip->num_slots; i++) 626 jmicron_enable_mmc(chip->slots[i]->host, 0); 627 } 628 629 return 0; 630 } 631 632 static int jmicron_resume(struct sdhci_pci_chip *chip) 633 { 634 int ret, i; 635 636 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 637 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 638 for (i = 0; i < chip->num_slots; i++) 639 jmicron_enable_mmc(chip->slots[i]->host, 1); 640 } 641 642 ret = jmicron_pmos(chip, 1); 643 if (ret) { 644 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 645 return ret; 646 } 647 648 return 0; 649 } 650 651 static const struct sdhci_pci_fixes sdhci_o2 = { 652 .probe = sdhci_pci_o2_probe, 653 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 654 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 655 .probe_slot = sdhci_pci_o2_probe_slot, 656 .resume = sdhci_pci_o2_resume, 657 }; 658 659 static const struct sdhci_pci_fixes sdhci_jmicron = { 660 .probe = jmicron_probe, 661 662 .probe_slot = jmicron_probe_slot, 663 .remove_slot = jmicron_remove_slot, 664 665 .suspend = jmicron_suspend, 666 .resume = jmicron_resume, 667 }; 668 669 /* SysKonnect CardBus2SDIO extra registers */ 670 #define SYSKT_CTRL 0x200 671 #define SYSKT_RDFIFO_STAT 0x204 672 #define SYSKT_WRFIFO_STAT 0x208 673 #define SYSKT_POWER_DATA 0x20c 674 #define SYSKT_POWER_330 0xef 675 #define SYSKT_POWER_300 0xf8 676 #define SYSKT_POWER_184 0xcc 677 #define SYSKT_POWER_CMD 0x20d 678 #define SYSKT_POWER_START (1 << 7) 679 #define SYSKT_POWER_STATUS 0x20e 680 #define SYSKT_POWER_STATUS_OK (1 << 0) 681 #define SYSKT_BOARD_REV 0x210 682 #define SYSKT_CHIP_REV 0x211 683 #define SYSKT_CONF_DATA 0x212 684 #define SYSKT_CONF_DATA_1V8 (1 << 2) 685 #define SYSKT_CONF_DATA_2V5 (1 << 1) 686 #define SYSKT_CONF_DATA_3V3 (1 << 0) 687 688 static int syskt_probe(struct sdhci_pci_chip *chip) 689 { 690 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 691 chip->pdev->class &= ~0x0000FF; 692 chip->pdev->class |= PCI_SDHCI_IFDMA; 693 } 694 return 0; 695 } 696 697 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 698 { 699 int tm, ps; 700 701 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 702 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 703 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 704 "board rev %d.%d, chip rev %d.%d\n", 705 board_rev >> 4, board_rev & 0xf, 706 chip_rev >> 4, chip_rev & 0xf); 707 if (chip_rev >= 0x20) 708 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 709 710 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 711 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 712 udelay(50); 713 tm = 10; /* Wait max 1 ms */ 714 do { 715 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 716 if (ps & SYSKT_POWER_STATUS_OK) 717 break; 718 udelay(100); 719 } while (--tm); 720 if (!tm) { 721 dev_err(&slot->chip->pdev->dev, 722 "power regulator never stabilized"); 723 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 724 return -ENODEV; 725 } 726 727 return 0; 728 } 729 730 static const struct sdhci_pci_fixes sdhci_syskt = { 731 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 732 .probe = syskt_probe, 733 .probe_slot = syskt_probe_slot, 734 }; 735 736 static int via_probe(struct sdhci_pci_chip *chip) 737 { 738 if (chip->pdev->revision == 0x10) 739 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 740 741 return 0; 742 } 743 744 static const struct sdhci_pci_fixes sdhci_via = { 745 .probe = via_probe, 746 }; 747 748 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 749 { 750 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 751 return 0; 752 } 753 754 static const struct sdhci_pci_fixes sdhci_rtsx = { 755 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 756 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 757 SDHCI_QUIRK2_BROKEN_DDR50, 758 .probe_slot = rtsx_probe_slot, 759 }; 760 761 /*AMD chipset generation*/ 762 enum amd_chipset_gen { 763 AMD_CHIPSET_BEFORE_ML, 764 AMD_CHIPSET_CZ, 765 AMD_CHIPSET_NL, 766 AMD_CHIPSET_UNKNOWN, 767 }; 768 769 static int amd_probe(struct sdhci_pci_chip *chip) 770 { 771 struct pci_dev *smbus_dev; 772 enum amd_chipset_gen gen; 773 774 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 775 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 776 if (smbus_dev) { 777 gen = AMD_CHIPSET_BEFORE_ML; 778 } else { 779 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 780 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 781 if (smbus_dev) { 782 if (smbus_dev->revision < 0x51) 783 gen = AMD_CHIPSET_CZ; 784 else 785 gen = AMD_CHIPSET_NL; 786 } else { 787 gen = AMD_CHIPSET_UNKNOWN; 788 } 789 } 790 791 if ((gen == AMD_CHIPSET_BEFORE_ML) || (gen == AMD_CHIPSET_CZ)) { 792 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 793 chip->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 794 } 795 796 return 0; 797 } 798 799 static const struct sdhci_pci_fixes sdhci_amd = { 800 .probe = amd_probe, 801 }; 802 803 static const struct pci_device_id pci_ids[] = { 804 { 805 .vendor = PCI_VENDOR_ID_RICOH, 806 .device = PCI_DEVICE_ID_RICOH_R5C822, 807 .subvendor = PCI_ANY_ID, 808 .subdevice = PCI_ANY_ID, 809 .driver_data = (kernel_ulong_t)&sdhci_ricoh, 810 }, 811 812 { 813 .vendor = PCI_VENDOR_ID_RICOH, 814 .device = 0x843, 815 .subvendor = PCI_ANY_ID, 816 .subdevice = PCI_ANY_ID, 817 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 818 }, 819 820 { 821 .vendor = PCI_VENDOR_ID_RICOH, 822 .device = 0xe822, 823 .subvendor = PCI_ANY_ID, 824 .subdevice = PCI_ANY_ID, 825 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 826 }, 827 828 { 829 .vendor = PCI_VENDOR_ID_RICOH, 830 .device = 0xe823, 831 .subvendor = PCI_ANY_ID, 832 .subdevice = PCI_ANY_ID, 833 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 834 }, 835 836 { 837 .vendor = PCI_VENDOR_ID_ENE, 838 .device = PCI_DEVICE_ID_ENE_CB712_SD, 839 .subvendor = PCI_ANY_ID, 840 .subdevice = PCI_ANY_ID, 841 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 842 }, 843 844 { 845 .vendor = PCI_VENDOR_ID_ENE, 846 .device = PCI_DEVICE_ID_ENE_CB712_SD_2, 847 .subvendor = PCI_ANY_ID, 848 .subdevice = PCI_ANY_ID, 849 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 850 }, 851 852 { 853 .vendor = PCI_VENDOR_ID_ENE, 854 .device = PCI_DEVICE_ID_ENE_CB714_SD, 855 .subvendor = PCI_ANY_ID, 856 .subdevice = PCI_ANY_ID, 857 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 858 }, 859 860 { 861 .vendor = PCI_VENDOR_ID_ENE, 862 .device = PCI_DEVICE_ID_ENE_CB714_SD_2, 863 .subvendor = PCI_ANY_ID, 864 .subdevice = PCI_ANY_ID, 865 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 866 }, 867 868 { 869 .vendor = PCI_VENDOR_ID_MARVELL, 870 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD, 871 .subvendor = PCI_ANY_ID, 872 .subdevice = PCI_ANY_ID, 873 .driver_data = (kernel_ulong_t)&sdhci_cafe, 874 }, 875 876 { 877 .vendor = PCI_VENDOR_ID_JMICRON, 878 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD, 879 .subvendor = PCI_ANY_ID, 880 .subdevice = PCI_ANY_ID, 881 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 882 }, 883 884 { 885 .vendor = PCI_VENDOR_ID_JMICRON, 886 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC, 887 .subvendor = PCI_ANY_ID, 888 .subdevice = PCI_ANY_ID, 889 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 890 }, 891 892 { 893 .vendor = PCI_VENDOR_ID_JMICRON, 894 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD, 895 .subvendor = PCI_ANY_ID, 896 .subdevice = PCI_ANY_ID, 897 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 898 }, 899 900 { 901 .vendor = PCI_VENDOR_ID_JMICRON, 902 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD, 903 .subvendor = PCI_ANY_ID, 904 .subdevice = PCI_ANY_ID, 905 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 906 }, 907 908 { 909 .vendor = PCI_VENDOR_ID_SYSKONNECT, 910 .device = 0x8000, 911 .subvendor = PCI_ANY_ID, 912 .subdevice = PCI_ANY_ID, 913 .driver_data = (kernel_ulong_t)&sdhci_syskt, 914 }, 915 916 { 917 .vendor = PCI_VENDOR_ID_VIA, 918 .device = 0x95d0, 919 .subvendor = PCI_ANY_ID, 920 .subdevice = PCI_ANY_ID, 921 .driver_data = (kernel_ulong_t)&sdhci_via, 922 }, 923 924 { 925 .vendor = PCI_VENDOR_ID_REALTEK, 926 .device = 0x5250, 927 .subvendor = PCI_ANY_ID, 928 .subdevice = PCI_ANY_ID, 929 .driver_data = (kernel_ulong_t)&sdhci_rtsx, 930 }, 931 932 { 933 .vendor = PCI_VENDOR_ID_INTEL, 934 .device = PCI_DEVICE_ID_INTEL_QRK_SD, 935 .subvendor = PCI_ANY_ID, 936 .subdevice = PCI_ANY_ID, 937 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk, 938 }, 939 940 { 941 .vendor = PCI_VENDOR_ID_INTEL, 942 .device = PCI_DEVICE_ID_INTEL_MRST_SD0, 943 .subvendor = PCI_ANY_ID, 944 .subdevice = PCI_ANY_ID, 945 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0, 946 }, 947 948 { 949 .vendor = PCI_VENDOR_ID_INTEL, 950 .device = PCI_DEVICE_ID_INTEL_MRST_SD1, 951 .subvendor = PCI_ANY_ID, 952 .subdevice = PCI_ANY_ID, 953 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 954 }, 955 956 { 957 .vendor = PCI_VENDOR_ID_INTEL, 958 .device = PCI_DEVICE_ID_INTEL_MRST_SD2, 959 .subvendor = PCI_ANY_ID, 960 .subdevice = PCI_ANY_ID, 961 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 962 }, 963 964 { 965 .vendor = PCI_VENDOR_ID_INTEL, 966 .device = PCI_DEVICE_ID_INTEL_MFD_SD, 967 .subvendor = PCI_ANY_ID, 968 .subdevice = PCI_ANY_ID, 969 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 970 }, 971 972 { 973 .vendor = PCI_VENDOR_ID_INTEL, 974 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1, 975 .subvendor = PCI_ANY_ID, 976 .subdevice = PCI_ANY_ID, 977 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 978 }, 979 980 { 981 .vendor = PCI_VENDOR_ID_INTEL, 982 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2, 983 .subvendor = PCI_ANY_ID, 984 .subdevice = PCI_ANY_ID, 985 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 986 }, 987 988 { 989 .vendor = PCI_VENDOR_ID_INTEL, 990 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0, 991 .subvendor = PCI_ANY_ID, 992 .subdevice = PCI_ANY_ID, 993 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 994 }, 995 996 { 997 .vendor = PCI_VENDOR_ID_INTEL, 998 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1, 999 .subvendor = PCI_ANY_ID, 1000 .subdevice = PCI_ANY_ID, 1001 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1002 }, 1003 1004 { 1005 .vendor = PCI_VENDOR_ID_INTEL, 1006 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0, 1007 .subvendor = PCI_ANY_ID, 1008 .subdevice = PCI_ANY_ID, 1009 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1010 }, 1011 1012 { 1013 .vendor = PCI_VENDOR_ID_INTEL, 1014 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1, 1015 .subvendor = PCI_ANY_ID, 1016 .subdevice = PCI_ANY_ID, 1017 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1018 }, 1019 1020 { 1021 .vendor = PCI_VENDOR_ID_INTEL, 1022 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC, 1023 .subvendor = PCI_ANY_ID, 1024 .subdevice = PCI_ANY_ID, 1025 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1026 }, 1027 1028 { 1029 .vendor = PCI_VENDOR_ID_INTEL, 1030 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, 1031 .subvendor = PCI_ANY_ID, 1032 .subdevice = PCI_ANY_ID, 1033 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1034 }, 1035 1036 { 1037 .vendor = PCI_VENDOR_ID_INTEL, 1038 .device = PCI_DEVICE_ID_INTEL_BYT_SD, 1039 .subvendor = PCI_ANY_ID, 1040 .subdevice = PCI_ANY_ID, 1041 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1042 }, 1043 1044 { 1045 .vendor = PCI_VENDOR_ID_INTEL, 1046 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2, 1047 .subvendor = PCI_ANY_ID, 1048 .subdevice = PCI_ANY_ID, 1049 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1050 }, 1051 1052 { 1053 .vendor = PCI_VENDOR_ID_INTEL, 1054 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC, 1055 .subvendor = PCI_ANY_ID, 1056 .subdevice = PCI_ANY_ID, 1057 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1058 }, 1059 1060 { 1061 .vendor = PCI_VENDOR_ID_INTEL, 1062 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO, 1063 .subvendor = PCI_ANY_ID, 1064 .subdevice = PCI_ANY_ID, 1065 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1066 }, 1067 1068 { 1069 .vendor = PCI_VENDOR_ID_INTEL, 1070 .device = PCI_DEVICE_ID_INTEL_BSW_SD, 1071 .subvendor = PCI_ANY_ID, 1072 .subdevice = PCI_ANY_ID, 1073 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1074 }, 1075 1076 { 1077 .vendor = PCI_VENDOR_ID_INTEL, 1078 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0, 1079 .subvendor = PCI_ANY_ID, 1080 .subdevice = PCI_ANY_ID, 1081 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1082 }, 1083 1084 { 1085 .vendor = PCI_VENDOR_ID_INTEL, 1086 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1, 1087 .subvendor = PCI_ANY_ID, 1088 .subdevice = PCI_ANY_ID, 1089 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1090 }, 1091 1092 { 1093 .vendor = PCI_VENDOR_ID_INTEL, 1094 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2, 1095 .subvendor = PCI_ANY_ID, 1096 .subdevice = PCI_ANY_ID, 1097 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1098 }, 1099 1100 { 1101 .vendor = PCI_VENDOR_ID_INTEL, 1102 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0, 1103 .subvendor = PCI_ANY_ID, 1104 .subdevice = PCI_ANY_ID, 1105 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1106 }, 1107 1108 { 1109 .vendor = PCI_VENDOR_ID_INTEL, 1110 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1, 1111 .subvendor = PCI_ANY_ID, 1112 .subdevice = PCI_ANY_ID, 1113 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1114 }, 1115 1116 { 1117 .vendor = PCI_VENDOR_ID_INTEL, 1118 .device = PCI_DEVICE_ID_INTEL_MRFLD_MMC, 1119 .subvendor = PCI_ANY_ID, 1120 .subdevice = PCI_ANY_ID, 1121 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfld_mmc, 1122 }, 1123 1124 { 1125 .vendor = PCI_VENDOR_ID_INTEL, 1126 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC, 1127 .subvendor = PCI_ANY_ID, 1128 .subdevice = PCI_ANY_ID, 1129 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1130 }, 1131 1132 { 1133 .vendor = PCI_VENDOR_ID_INTEL, 1134 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO, 1135 .subvendor = PCI_ANY_ID, 1136 .subdevice = PCI_ANY_ID, 1137 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1138 }, 1139 1140 { 1141 .vendor = PCI_VENDOR_ID_INTEL, 1142 .device = PCI_DEVICE_ID_INTEL_SPT_SD, 1143 .subvendor = PCI_ANY_ID, 1144 .subdevice = PCI_ANY_ID, 1145 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1146 }, 1147 1148 { 1149 .vendor = PCI_VENDOR_ID_INTEL, 1150 .device = PCI_DEVICE_ID_INTEL_DNV_EMMC, 1151 .subvendor = PCI_ANY_ID, 1152 .subdevice = PCI_ANY_ID, 1153 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1154 }, 1155 1156 { 1157 .vendor = PCI_VENDOR_ID_INTEL, 1158 .device = PCI_DEVICE_ID_INTEL_BXT_EMMC, 1159 .subvendor = PCI_ANY_ID, 1160 .subdevice = PCI_ANY_ID, 1161 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1162 }, 1163 1164 { 1165 .vendor = PCI_VENDOR_ID_INTEL, 1166 .device = PCI_DEVICE_ID_INTEL_BXT_SDIO, 1167 .subvendor = PCI_ANY_ID, 1168 .subdevice = PCI_ANY_ID, 1169 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1170 }, 1171 1172 { 1173 .vendor = PCI_VENDOR_ID_INTEL, 1174 .device = PCI_DEVICE_ID_INTEL_BXT_SD, 1175 .subvendor = PCI_ANY_ID, 1176 .subdevice = PCI_ANY_ID, 1177 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1178 }, 1179 1180 { 1181 .vendor = PCI_VENDOR_ID_INTEL, 1182 .device = PCI_DEVICE_ID_INTEL_BXTM_EMMC, 1183 .subvendor = PCI_ANY_ID, 1184 .subdevice = PCI_ANY_ID, 1185 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1186 }, 1187 1188 { 1189 .vendor = PCI_VENDOR_ID_INTEL, 1190 .device = PCI_DEVICE_ID_INTEL_BXTM_SDIO, 1191 .subvendor = PCI_ANY_ID, 1192 .subdevice = PCI_ANY_ID, 1193 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1194 }, 1195 1196 { 1197 .vendor = PCI_VENDOR_ID_INTEL, 1198 .device = PCI_DEVICE_ID_INTEL_BXTM_SD, 1199 .subvendor = PCI_ANY_ID, 1200 .subdevice = PCI_ANY_ID, 1201 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1202 }, 1203 1204 { 1205 .vendor = PCI_VENDOR_ID_INTEL, 1206 .device = PCI_DEVICE_ID_INTEL_APL_EMMC, 1207 .subvendor = PCI_ANY_ID, 1208 .subdevice = PCI_ANY_ID, 1209 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1210 }, 1211 1212 { 1213 .vendor = PCI_VENDOR_ID_INTEL, 1214 .device = PCI_DEVICE_ID_INTEL_APL_SDIO, 1215 .subvendor = PCI_ANY_ID, 1216 .subdevice = PCI_ANY_ID, 1217 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1218 }, 1219 1220 { 1221 .vendor = PCI_VENDOR_ID_INTEL, 1222 .device = PCI_DEVICE_ID_INTEL_APL_SD, 1223 .subvendor = PCI_ANY_ID, 1224 .subdevice = PCI_ANY_ID, 1225 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1226 }, 1227 1228 { 1229 .vendor = PCI_VENDOR_ID_O2, 1230 .device = PCI_DEVICE_ID_O2_8120, 1231 .subvendor = PCI_ANY_ID, 1232 .subdevice = PCI_ANY_ID, 1233 .driver_data = (kernel_ulong_t)&sdhci_o2, 1234 }, 1235 1236 { 1237 .vendor = PCI_VENDOR_ID_O2, 1238 .device = PCI_DEVICE_ID_O2_8220, 1239 .subvendor = PCI_ANY_ID, 1240 .subdevice = PCI_ANY_ID, 1241 .driver_data = (kernel_ulong_t)&sdhci_o2, 1242 }, 1243 1244 { 1245 .vendor = PCI_VENDOR_ID_O2, 1246 .device = PCI_DEVICE_ID_O2_8221, 1247 .subvendor = PCI_ANY_ID, 1248 .subdevice = PCI_ANY_ID, 1249 .driver_data = (kernel_ulong_t)&sdhci_o2, 1250 }, 1251 1252 { 1253 .vendor = PCI_VENDOR_ID_O2, 1254 .device = PCI_DEVICE_ID_O2_8320, 1255 .subvendor = PCI_ANY_ID, 1256 .subdevice = PCI_ANY_ID, 1257 .driver_data = (kernel_ulong_t)&sdhci_o2, 1258 }, 1259 1260 { 1261 .vendor = PCI_VENDOR_ID_O2, 1262 .device = PCI_DEVICE_ID_O2_8321, 1263 .subvendor = PCI_ANY_ID, 1264 .subdevice = PCI_ANY_ID, 1265 .driver_data = (kernel_ulong_t)&sdhci_o2, 1266 }, 1267 1268 { 1269 .vendor = PCI_VENDOR_ID_O2, 1270 .device = PCI_DEVICE_ID_O2_FUJIN2, 1271 .subvendor = PCI_ANY_ID, 1272 .subdevice = PCI_ANY_ID, 1273 .driver_data = (kernel_ulong_t)&sdhci_o2, 1274 }, 1275 1276 { 1277 .vendor = PCI_VENDOR_ID_O2, 1278 .device = PCI_DEVICE_ID_O2_SDS0, 1279 .subvendor = PCI_ANY_ID, 1280 .subdevice = PCI_ANY_ID, 1281 .driver_data = (kernel_ulong_t)&sdhci_o2, 1282 }, 1283 1284 { 1285 .vendor = PCI_VENDOR_ID_O2, 1286 .device = PCI_DEVICE_ID_O2_SDS1, 1287 .subvendor = PCI_ANY_ID, 1288 .subdevice = PCI_ANY_ID, 1289 .driver_data = (kernel_ulong_t)&sdhci_o2, 1290 }, 1291 1292 { 1293 .vendor = PCI_VENDOR_ID_O2, 1294 .device = PCI_DEVICE_ID_O2_SEABIRD0, 1295 .subvendor = PCI_ANY_ID, 1296 .subdevice = PCI_ANY_ID, 1297 .driver_data = (kernel_ulong_t)&sdhci_o2, 1298 }, 1299 1300 { 1301 .vendor = PCI_VENDOR_ID_O2, 1302 .device = PCI_DEVICE_ID_O2_SEABIRD1, 1303 .subvendor = PCI_ANY_ID, 1304 .subdevice = PCI_ANY_ID, 1305 .driver_data = (kernel_ulong_t)&sdhci_o2, 1306 }, 1307 { 1308 .vendor = PCI_VENDOR_ID_AMD, 1309 .device = PCI_ANY_ID, 1310 .class = PCI_CLASS_SYSTEM_SDHCI << 8, 1311 .class_mask = 0xFFFF00, 1312 .subvendor = PCI_ANY_ID, 1313 .subdevice = PCI_ANY_ID, 1314 .driver_data = (kernel_ulong_t)&sdhci_amd, 1315 }, 1316 { /* Generic SD host controller */ 1317 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) 1318 }, 1319 1320 { /* end: all zeroes */ }, 1321 }; 1322 1323 MODULE_DEVICE_TABLE(pci, pci_ids); 1324 1325 /*****************************************************************************\ 1326 * * 1327 * SDHCI core callbacks * 1328 * * 1329 \*****************************************************************************/ 1330 1331 static int sdhci_pci_enable_dma(struct sdhci_host *host) 1332 { 1333 struct sdhci_pci_slot *slot; 1334 struct pci_dev *pdev; 1335 1336 slot = sdhci_priv(host); 1337 pdev = slot->chip->pdev; 1338 1339 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1340 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1341 (host->flags & SDHCI_USE_SDMA)) { 1342 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1343 "doesn't fully claim to support it.\n"); 1344 } 1345 1346 pci_set_master(pdev); 1347 1348 return 0; 1349 } 1350 1351 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width) 1352 { 1353 u8 ctrl; 1354 1355 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1356 1357 switch (width) { 1358 case MMC_BUS_WIDTH_8: 1359 ctrl |= SDHCI_CTRL_8BITBUS; 1360 ctrl &= ~SDHCI_CTRL_4BITBUS; 1361 break; 1362 case MMC_BUS_WIDTH_4: 1363 ctrl |= SDHCI_CTRL_4BITBUS; 1364 ctrl &= ~SDHCI_CTRL_8BITBUS; 1365 break; 1366 default: 1367 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS); 1368 break; 1369 } 1370 1371 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1372 } 1373 1374 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1375 { 1376 struct sdhci_pci_slot *slot = sdhci_priv(host); 1377 int rst_n_gpio = slot->rst_n_gpio; 1378 1379 if (!gpio_is_valid(rst_n_gpio)) 1380 return; 1381 gpio_set_value_cansleep(rst_n_gpio, 0); 1382 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1383 udelay(10); 1384 gpio_set_value_cansleep(rst_n_gpio, 1); 1385 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1386 usleep_range(300, 1000); 1387 } 1388 1389 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1390 { 1391 struct sdhci_pci_slot *slot = sdhci_priv(host); 1392 1393 if (slot->hw_reset) 1394 slot->hw_reset(host); 1395 } 1396 1397 static int sdhci_pci_select_drive_strength(struct sdhci_host *host, 1398 struct mmc_card *card, 1399 unsigned int max_dtr, int host_drv, 1400 int card_drv, int *drv_type) 1401 { 1402 struct sdhci_pci_slot *slot = sdhci_priv(host); 1403 1404 if (!slot->select_drive_strength) 1405 return 0; 1406 1407 return slot->select_drive_strength(host, card, max_dtr, host_drv, 1408 card_drv, drv_type); 1409 } 1410 1411 static const struct sdhci_ops sdhci_pci_ops = { 1412 .set_clock = sdhci_set_clock, 1413 .enable_dma = sdhci_pci_enable_dma, 1414 .set_bus_width = sdhci_pci_set_bus_width, 1415 .reset = sdhci_reset, 1416 .set_uhs_signaling = sdhci_set_uhs_signaling, 1417 .hw_reset = sdhci_pci_hw_reset, 1418 .select_drive_strength = sdhci_pci_select_drive_strength, 1419 }; 1420 1421 /*****************************************************************************\ 1422 * * 1423 * Suspend/resume * 1424 * * 1425 \*****************************************************************************/ 1426 1427 #ifdef CONFIG_PM_SLEEP 1428 static int sdhci_pci_suspend(struct device *dev) 1429 { 1430 struct pci_dev *pdev = to_pci_dev(dev); 1431 struct sdhci_pci_chip *chip; 1432 struct sdhci_pci_slot *slot; 1433 mmc_pm_flag_t slot_pm_flags; 1434 mmc_pm_flag_t pm_flags = 0; 1435 int i, ret; 1436 1437 chip = pci_get_drvdata(pdev); 1438 if (!chip) 1439 return 0; 1440 1441 for (i = 0; i < chip->num_slots; i++) { 1442 slot = chip->slots[i]; 1443 if (!slot) 1444 continue; 1445 1446 ret = sdhci_suspend_host(slot->host); 1447 1448 if (ret) 1449 goto err_pci_suspend; 1450 1451 slot_pm_flags = slot->host->mmc->pm_flags; 1452 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1453 sdhci_enable_irq_wakeups(slot->host); 1454 1455 pm_flags |= slot_pm_flags; 1456 } 1457 1458 if (chip->fixes && chip->fixes->suspend) { 1459 ret = chip->fixes->suspend(chip); 1460 if (ret) 1461 goto err_pci_suspend; 1462 } 1463 1464 if (pm_flags & MMC_PM_KEEP_POWER) { 1465 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1466 device_init_wakeup(dev, true); 1467 else 1468 device_init_wakeup(dev, false); 1469 } else 1470 device_init_wakeup(dev, false); 1471 1472 return 0; 1473 1474 err_pci_suspend: 1475 while (--i >= 0) 1476 sdhci_resume_host(chip->slots[i]->host); 1477 return ret; 1478 } 1479 1480 static int sdhci_pci_resume(struct device *dev) 1481 { 1482 struct pci_dev *pdev = to_pci_dev(dev); 1483 struct sdhci_pci_chip *chip; 1484 struct sdhci_pci_slot *slot; 1485 int i, ret; 1486 1487 chip = pci_get_drvdata(pdev); 1488 if (!chip) 1489 return 0; 1490 1491 if (chip->fixes && chip->fixes->resume) { 1492 ret = chip->fixes->resume(chip); 1493 if (ret) 1494 return ret; 1495 } 1496 1497 for (i = 0; i < chip->num_slots; i++) { 1498 slot = chip->slots[i]; 1499 if (!slot) 1500 continue; 1501 1502 ret = sdhci_resume_host(slot->host); 1503 if (ret) 1504 return ret; 1505 } 1506 1507 return 0; 1508 } 1509 #endif 1510 1511 #ifdef CONFIG_PM 1512 static int sdhci_pci_runtime_suspend(struct device *dev) 1513 { 1514 struct pci_dev *pdev = to_pci_dev(dev); 1515 struct sdhci_pci_chip *chip; 1516 struct sdhci_pci_slot *slot; 1517 int i, ret; 1518 1519 chip = pci_get_drvdata(pdev); 1520 if (!chip) 1521 return 0; 1522 1523 for (i = 0; i < chip->num_slots; i++) { 1524 slot = chip->slots[i]; 1525 if (!slot) 1526 continue; 1527 1528 ret = sdhci_runtime_suspend_host(slot->host); 1529 1530 if (ret) 1531 goto err_pci_runtime_suspend; 1532 } 1533 1534 if (chip->fixes && chip->fixes->suspend) { 1535 ret = chip->fixes->suspend(chip); 1536 if (ret) 1537 goto err_pci_runtime_suspend; 1538 } 1539 1540 return 0; 1541 1542 err_pci_runtime_suspend: 1543 while (--i >= 0) 1544 sdhci_runtime_resume_host(chip->slots[i]->host); 1545 return ret; 1546 } 1547 1548 static int sdhci_pci_runtime_resume(struct device *dev) 1549 { 1550 struct pci_dev *pdev = to_pci_dev(dev); 1551 struct sdhci_pci_chip *chip; 1552 struct sdhci_pci_slot *slot; 1553 int i, ret; 1554 1555 chip = pci_get_drvdata(pdev); 1556 if (!chip) 1557 return 0; 1558 1559 if (chip->fixes && chip->fixes->resume) { 1560 ret = chip->fixes->resume(chip); 1561 if (ret) 1562 return ret; 1563 } 1564 1565 for (i = 0; i < chip->num_slots; i++) { 1566 slot = chip->slots[i]; 1567 if (!slot) 1568 continue; 1569 1570 ret = sdhci_runtime_resume_host(slot->host); 1571 if (ret) 1572 return ret; 1573 } 1574 1575 return 0; 1576 } 1577 #endif 1578 1579 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1580 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1581 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1582 sdhci_pci_runtime_resume, NULL) 1583 }; 1584 1585 /*****************************************************************************\ 1586 * * 1587 * Device probing/removal * 1588 * * 1589 \*****************************************************************************/ 1590 1591 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1592 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1593 int slotno) 1594 { 1595 struct sdhci_pci_slot *slot; 1596 struct sdhci_host *host; 1597 int ret, bar = first_bar + slotno; 1598 1599 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1600 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1601 return ERR_PTR(-ENODEV); 1602 } 1603 1604 if (pci_resource_len(pdev, bar) < 0x100) { 1605 dev_err(&pdev->dev, "Invalid iomem size. You may " 1606 "experience problems.\n"); 1607 } 1608 1609 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1610 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1611 return ERR_PTR(-ENODEV); 1612 } 1613 1614 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1615 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1616 return ERR_PTR(-ENODEV); 1617 } 1618 1619 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot)); 1620 if (IS_ERR(host)) { 1621 dev_err(&pdev->dev, "cannot allocate host\n"); 1622 return ERR_CAST(host); 1623 } 1624 1625 slot = sdhci_priv(host); 1626 1627 slot->chip = chip; 1628 slot->host = host; 1629 slot->rst_n_gpio = -EINVAL; 1630 slot->cd_gpio = -EINVAL; 1631 slot->cd_idx = -1; 1632 1633 /* Retrieve platform data if there is any */ 1634 if (*sdhci_pci_get_data) 1635 slot->data = sdhci_pci_get_data(pdev, slotno); 1636 1637 if (slot->data) { 1638 if (slot->data->setup) { 1639 ret = slot->data->setup(slot->data); 1640 if (ret) { 1641 dev_err(&pdev->dev, "platform setup failed\n"); 1642 goto free; 1643 } 1644 } 1645 slot->rst_n_gpio = slot->data->rst_n_gpio; 1646 slot->cd_gpio = slot->data->cd_gpio; 1647 } 1648 1649 host->hw_name = "PCI"; 1650 host->ops = &sdhci_pci_ops; 1651 host->quirks = chip->quirks; 1652 host->quirks2 = chip->quirks2; 1653 1654 host->irq = pdev->irq; 1655 1656 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1657 if (ret) { 1658 dev_err(&pdev->dev, "cannot request region\n"); 1659 goto cleanup; 1660 } 1661 1662 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1663 1664 if (chip->fixes && chip->fixes->probe_slot) { 1665 ret = chip->fixes->probe_slot(slot); 1666 if (ret) 1667 goto cleanup; 1668 } 1669 1670 if (gpio_is_valid(slot->rst_n_gpio)) { 1671 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1672 gpio_direction_output(slot->rst_n_gpio, 1); 1673 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1674 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1675 } else { 1676 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1677 slot->rst_n_gpio = -EINVAL; 1678 } 1679 } 1680 1681 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; 1682 host->mmc->slotno = slotno; 1683 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1684 1685 if (slot->cd_idx >= 0 && 1686 mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx, 1687 slot->cd_override_level, 0, NULL)) { 1688 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 1689 slot->cd_idx = -1; 1690 } 1691 1692 ret = sdhci_add_host(host); 1693 if (ret) 1694 goto remove; 1695 1696 sdhci_pci_add_own_cd(slot); 1697 1698 /* 1699 * Check if the chip needs a separate GPIO for card detect to wake up 1700 * from runtime suspend. If it is not there, don't allow runtime PM. 1701 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 1702 */ 1703 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 1704 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 1705 chip->allow_runtime_pm = false; 1706 1707 return slot; 1708 1709 remove: 1710 if (chip->fixes && chip->fixes->remove_slot) 1711 chip->fixes->remove_slot(slot, 0); 1712 1713 cleanup: 1714 if (slot->data && slot->data->cleanup) 1715 slot->data->cleanup(slot->data); 1716 1717 free: 1718 sdhci_free_host(host); 1719 1720 return ERR_PTR(ret); 1721 } 1722 1723 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 1724 { 1725 int dead; 1726 u32 scratch; 1727 1728 sdhci_pci_remove_own_cd(slot); 1729 1730 dead = 0; 1731 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 1732 if (scratch == (u32)-1) 1733 dead = 1; 1734 1735 sdhci_remove_host(slot->host, dead); 1736 1737 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 1738 slot->chip->fixes->remove_slot(slot, dead); 1739 1740 if (slot->data && slot->data->cleanup) 1741 slot->data->cleanup(slot->data); 1742 1743 sdhci_free_host(slot->host); 1744 } 1745 1746 static void sdhci_pci_runtime_pm_allow(struct device *dev) 1747 { 1748 pm_suspend_ignore_children(dev, 1); 1749 pm_runtime_set_autosuspend_delay(dev, 50); 1750 pm_runtime_use_autosuspend(dev); 1751 pm_runtime_allow(dev); 1752 /* Stay active until mmc core scans for a card */ 1753 pm_runtime_put_noidle(dev); 1754 } 1755 1756 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 1757 { 1758 pm_runtime_forbid(dev); 1759 pm_runtime_get_noresume(dev); 1760 } 1761 1762 static int sdhci_pci_probe(struct pci_dev *pdev, 1763 const struct pci_device_id *ent) 1764 { 1765 struct sdhci_pci_chip *chip; 1766 struct sdhci_pci_slot *slot; 1767 1768 u8 slots, first_bar; 1769 int ret, i; 1770 1771 BUG_ON(pdev == NULL); 1772 BUG_ON(ent == NULL); 1773 1774 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 1775 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 1776 1777 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 1778 if (ret) 1779 return ret; 1780 1781 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 1782 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 1783 if (slots == 0) 1784 return -ENODEV; 1785 1786 BUG_ON(slots > MAX_SLOTS); 1787 1788 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 1789 if (ret) 1790 return ret; 1791 1792 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 1793 1794 if (first_bar > 5) { 1795 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 1796 return -ENODEV; 1797 } 1798 1799 ret = pcim_enable_device(pdev); 1800 if (ret) 1801 return ret; 1802 1803 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 1804 if (!chip) 1805 return -ENOMEM; 1806 1807 chip->pdev = pdev; 1808 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 1809 if (chip->fixes) { 1810 chip->quirks = chip->fixes->quirks; 1811 chip->quirks2 = chip->fixes->quirks2; 1812 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 1813 } 1814 chip->num_slots = slots; 1815 1816 pci_set_drvdata(pdev, chip); 1817 1818 if (chip->fixes && chip->fixes->probe) { 1819 ret = chip->fixes->probe(chip); 1820 if (ret) 1821 return ret; 1822 } 1823 1824 slots = chip->num_slots; /* Quirk may have changed this */ 1825 1826 for (i = 0; i < slots; i++) { 1827 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 1828 if (IS_ERR(slot)) { 1829 for (i--; i >= 0; i--) 1830 sdhci_pci_remove_slot(chip->slots[i]); 1831 return PTR_ERR(slot); 1832 } 1833 1834 chip->slots[i] = slot; 1835 } 1836 1837 if (chip->allow_runtime_pm) 1838 sdhci_pci_runtime_pm_allow(&pdev->dev); 1839 1840 return 0; 1841 } 1842 1843 static void sdhci_pci_remove(struct pci_dev *pdev) 1844 { 1845 int i; 1846 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1847 1848 if (chip->allow_runtime_pm) 1849 sdhci_pci_runtime_pm_forbid(&pdev->dev); 1850 1851 for (i = 0; i < chip->num_slots; i++) 1852 sdhci_pci_remove_slot(chip->slots[i]); 1853 } 1854 1855 static struct pci_driver sdhci_driver = { 1856 .name = "sdhci-pci", 1857 .id_table = pci_ids, 1858 .probe = sdhci_pci_probe, 1859 .remove = sdhci_pci_remove, 1860 .driver = { 1861 .pm = &sdhci_pci_pm_ops 1862 }, 1863 }; 1864 1865 module_pci_driver(sdhci_driver); 1866 1867 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 1868 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 1869 MODULE_LICENSE("GPL"); 1870