1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 2 * 3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 * 10 * Thanks to the following companies for their support: 11 * 12 * - JMicron (hardware and technical support) 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/highmem.h> 17 #include <linux/module.h> 18 #include <linux/pci.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/slab.h> 21 #include <linux/device.h> 22 #include <linux/mmc/host.h> 23 #include <linux/mmc/mmc.h> 24 #include <linux/scatterlist.h> 25 #include <linux/io.h> 26 #include <linux/gpio.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/mmc/slot-gpio.h> 29 #include <linux/mmc/sdhci-pci-data.h> 30 31 #include "sdhci.h" 32 #include "sdhci-pci.h" 33 #include "sdhci-pci-o2micro.h" 34 35 static int sdhci_pci_enable_dma(struct sdhci_host *host); 36 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width); 37 static void sdhci_pci_hw_reset(struct sdhci_host *host); 38 static int sdhci_pci_select_drive_strength(struct sdhci_host *host, 39 struct mmc_card *card, 40 unsigned int max_dtr, int host_drv, 41 int card_drv, int *drv_type); 42 43 /*****************************************************************************\ 44 * * 45 * Hardware specific quirk handling * 46 * * 47 \*****************************************************************************/ 48 49 static int ricoh_probe(struct sdhci_pci_chip *chip) 50 { 51 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 52 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 53 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 54 return 0; 55 } 56 57 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 58 { 59 slot->host->caps = 60 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 61 & SDHCI_TIMEOUT_CLK_MASK) | 62 63 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 64 & SDHCI_CLOCK_BASE_MASK) | 65 66 SDHCI_TIMEOUT_CLK_UNIT | 67 SDHCI_CAN_VDD_330 | 68 SDHCI_CAN_DO_HISPD | 69 SDHCI_CAN_DO_SDMA; 70 return 0; 71 } 72 73 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 74 { 75 /* Apply a delay to allow controller to settle */ 76 /* Otherwise it becomes confused if card state changed 77 during suspend */ 78 msleep(500); 79 return 0; 80 } 81 82 static const struct sdhci_pci_fixes sdhci_ricoh = { 83 .probe = ricoh_probe, 84 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 85 SDHCI_QUIRK_FORCE_DMA | 86 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 87 }; 88 89 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 90 .probe_slot = ricoh_mmc_probe_slot, 91 .resume = ricoh_mmc_resume, 92 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 93 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 94 SDHCI_QUIRK_NO_CARD_NO_RESET | 95 SDHCI_QUIRK_MISSING_CAPS 96 }; 97 98 static const struct sdhci_pci_fixes sdhci_ene_712 = { 99 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 100 SDHCI_QUIRK_BROKEN_DMA, 101 }; 102 103 static const struct sdhci_pci_fixes sdhci_ene_714 = { 104 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 105 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 106 SDHCI_QUIRK_BROKEN_DMA, 107 }; 108 109 static const struct sdhci_pci_fixes sdhci_cafe = { 110 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 111 SDHCI_QUIRK_NO_BUSY_IRQ | 112 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 113 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 114 }; 115 116 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 117 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 118 }; 119 120 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 121 { 122 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 123 return 0; 124 } 125 126 /* 127 * ADMA operation is disabled for Moorestown platform due to 128 * hardware bugs. 129 */ 130 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 131 { 132 /* 133 * slots number is fixed here for MRST as SDIO3/5 are never used and 134 * have hardware bugs. 135 */ 136 chip->num_slots = 1; 137 return 0; 138 } 139 140 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 141 { 142 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 143 return 0; 144 } 145 146 #ifdef CONFIG_PM 147 148 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 149 { 150 struct sdhci_pci_slot *slot = dev_id; 151 struct sdhci_host *host = slot->host; 152 153 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 154 return IRQ_HANDLED; 155 } 156 157 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 158 { 159 int err, irq, gpio = slot->cd_gpio; 160 161 slot->cd_gpio = -EINVAL; 162 slot->cd_irq = -EINVAL; 163 164 if (!gpio_is_valid(gpio)) 165 return; 166 167 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 168 if (err < 0) 169 goto out; 170 171 err = gpio_direction_input(gpio); 172 if (err < 0) 173 goto out_free; 174 175 irq = gpio_to_irq(gpio); 176 if (irq < 0) 177 goto out_free; 178 179 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 180 IRQF_TRIGGER_FALLING, "sd_cd", slot); 181 if (err) 182 goto out_free; 183 184 slot->cd_gpio = gpio; 185 slot->cd_irq = irq; 186 187 return; 188 189 out_free: 190 devm_gpio_free(&slot->chip->pdev->dev, gpio); 191 out: 192 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 193 } 194 195 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 196 { 197 if (slot->cd_irq >= 0) 198 free_irq(slot->cd_irq, slot); 199 } 200 201 #else 202 203 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 204 { 205 } 206 207 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 208 { 209 } 210 211 #endif 212 213 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 214 { 215 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 216 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC | 217 MMC_CAP2_HC_ERASE_SZ; 218 return 0; 219 } 220 221 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 222 { 223 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 224 return 0; 225 } 226 227 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 228 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 229 .probe_slot = mrst_hc_probe_slot, 230 }; 231 232 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 233 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 234 .probe = mrst_hc_probe, 235 }; 236 237 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 238 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 239 .allow_runtime_pm = true, 240 .own_cd_for_runtime_pm = true, 241 }; 242 243 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 244 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 245 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 246 .allow_runtime_pm = true, 247 .probe_slot = mfd_sdio_probe_slot, 248 }; 249 250 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 251 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 252 .allow_runtime_pm = true, 253 .probe_slot = mfd_emmc_probe_slot, 254 }; 255 256 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 257 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 258 .probe_slot = pch_hc_probe_slot, 259 }; 260 261 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 262 { 263 u8 reg; 264 265 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 266 reg |= 0x10; 267 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 268 /* For eMMC, minimum is 1us but give it 9us for good measure */ 269 udelay(9); 270 reg &= ~0x10; 271 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 272 /* For eMMC, minimum is 200us but give it 300us for good measure */ 273 usleep_range(300, 1000); 274 } 275 276 static int spt_select_drive_strength(struct sdhci_host *host, 277 struct mmc_card *card, 278 unsigned int max_dtr, 279 int host_drv, int card_drv, int *drv_type) 280 { 281 int drive_strength; 282 283 if (sdhci_pci_spt_drive_strength > 0) 284 drive_strength = sdhci_pci_spt_drive_strength & 0xf; 285 else 286 drive_strength = 0; /* Default 50-ohm */ 287 288 if ((mmc_driver_type_mask(drive_strength) & card_drv) == 0) 289 drive_strength = 0; /* Default 50-ohm */ 290 291 return drive_strength; 292 } 293 294 /* Try to read the drive strength from the card */ 295 static void spt_read_drive_strength(struct sdhci_host *host) 296 { 297 u32 val, i, t; 298 u16 m; 299 300 if (sdhci_pci_spt_drive_strength) 301 return; 302 303 sdhci_pci_spt_drive_strength = -1; 304 305 m = sdhci_readw(host, SDHCI_HOST_CONTROL2) & 0x7; 306 if (m != 3 && m != 5) 307 return; 308 val = sdhci_readl(host, SDHCI_PRESENT_STATE); 309 if (val & 0x3) 310 return; 311 sdhci_writel(host, 0x007f0023, SDHCI_INT_ENABLE); 312 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 313 sdhci_writew(host, 0x10, SDHCI_TRANSFER_MODE); 314 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 315 sdhci_writew(host, 512, SDHCI_BLOCK_SIZE); 316 sdhci_writew(host, 1, SDHCI_BLOCK_COUNT); 317 sdhci_writel(host, 0, SDHCI_ARGUMENT); 318 sdhci_writew(host, 0x83b, SDHCI_COMMAND); 319 for (i = 0; i < 1000; i++) { 320 val = sdhci_readl(host, SDHCI_INT_STATUS); 321 if (val & 0xffff8000) 322 return; 323 if (val & 0x20) 324 break; 325 udelay(1); 326 } 327 val = sdhci_readl(host, SDHCI_PRESENT_STATE); 328 if (!(val & 0x800)) 329 return; 330 for (i = 0; i < 47; i++) 331 val = sdhci_readl(host, SDHCI_BUFFER); 332 t = val & 0xf00; 333 if (t != 0x200 && t != 0x300) 334 return; 335 336 sdhci_pci_spt_drive_strength = 0x10 | ((val >> 12) & 0xf); 337 } 338 339 static int bxt_get_cd(struct mmc_host *mmc) 340 { 341 int gpio_cd = mmc_gpio_get_cd(mmc); 342 struct sdhci_host *host = mmc_priv(mmc); 343 unsigned long flags; 344 int ret = 0; 345 346 if (!gpio_cd) 347 return 0; 348 349 spin_lock_irqsave(&host->lock, flags); 350 351 if (host->flags & SDHCI_DEVICE_DEAD) 352 goto out; 353 354 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 355 out: 356 spin_unlock_irqrestore(&host->lock, flags); 357 358 return ret; 359 } 360 361 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 362 { 363 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 364 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 365 MMC_CAP_CMD_DURING_TFR | 366 MMC_CAP_WAIT_WHILE_BUSY; 367 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ; 368 slot->hw_reset = sdhci_pci_int_hw_reset; 369 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 370 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 371 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_SPT_EMMC) { 372 spt_read_drive_strength(slot->host); 373 slot->select_drive_strength = spt_select_drive_strength; 374 } 375 return 0; 376 } 377 378 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 379 { 380 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 381 MMC_CAP_WAIT_WHILE_BUSY; 382 return 0; 383 } 384 385 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 386 { 387 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 388 MMC_CAP_WAIT_WHILE_BUSY; 389 return 0; 390 } 391 392 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 393 { 394 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 395 slot->cd_con_id = NULL; 396 slot->cd_idx = 0; 397 slot->cd_override_level = true; 398 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 399 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 400 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 401 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) { 402 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 403 slot->host->mmc->caps |= MMC_CAP_AGGRESSIVE_PM; 404 } 405 406 return 0; 407 } 408 409 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 410 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 411 412 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 413 unsigned short vdd) 414 { 415 int cntr; 416 u8 reg; 417 418 sdhci_set_power(host, mode, vdd); 419 420 if (mode == MMC_POWER_OFF) 421 return; 422 423 /* 424 * Bus power might not enable after D3 -> D0 transition due to the 425 * present state not yet having propagated. Retry for up to 2ms. 426 */ 427 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 428 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 429 if (reg & SDHCI_POWER_ON) 430 break; 431 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 432 reg |= SDHCI_POWER_ON; 433 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 434 } 435 } 436 437 static const struct sdhci_ops sdhci_intel_byt_ops = { 438 .set_clock = sdhci_set_clock, 439 .set_power = sdhci_intel_set_power, 440 .enable_dma = sdhci_pci_enable_dma, 441 .set_bus_width = sdhci_pci_set_bus_width, 442 .reset = sdhci_reset, 443 .set_uhs_signaling = sdhci_set_uhs_signaling, 444 .hw_reset = sdhci_pci_hw_reset, 445 .select_drive_strength = sdhci_pci_select_drive_strength, 446 }; 447 448 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 449 .allow_runtime_pm = true, 450 .probe_slot = byt_emmc_probe_slot, 451 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 452 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 453 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 454 SDHCI_QUIRK2_STOP_WITH_TC, 455 .ops = &sdhci_intel_byt_ops, 456 }; 457 458 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 459 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 460 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 461 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 462 .allow_runtime_pm = true, 463 .probe_slot = ni_byt_sdio_probe_slot, 464 .ops = &sdhci_intel_byt_ops, 465 }; 466 467 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 468 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 469 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 470 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 471 .allow_runtime_pm = true, 472 .probe_slot = byt_sdio_probe_slot, 473 .ops = &sdhci_intel_byt_ops, 474 }; 475 476 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 477 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 478 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 479 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 480 SDHCI_QUIRK2_STOP_WITH_TC, 481 .allow_runtime_pm = true, 482 .own_cd_for_runtime_pm = true, 483 .probe_slot = byt_sd_probe_slot, 484 .ops = &sdhci_intel_byt_ops, 485 }; 486 487 /* Define Host controllers for Intel Merrifield platform */ 488 #define INTEL_MRFLD_EMMC_0 0 489 #define INTEL_MRFLD_EMMC_1 1 490 #define INTEL_MRFLD_SD 2 491 #define INTEL_MRFLD_SDIO 3 492 493 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 494 { 495 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 496 497 switch (func) { 498 case INTEL_MRFLD_EMMC_0: 499 case INTEL_MRFLD_EMMC_1: 500 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 501 MMC_CAP_8_BIT_DATA | 502 MMC_CAP_1_8V_DDR; 503 break; 504 case INTEL_MRFLD_SD: 505 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 506 break; 507 case INTEL_MRFLD_SDIO: 508 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 509 MMC_CAP_POWER_OFF_CARD; 510 break; 511 default: 512 return -ENODEV; 513 } 514 return 0; 515 } 516 517 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 518 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 519 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 520 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 521 .allow_runtime_pm = true, 522 .probe_slot = intel_mrfld_mmc_probe_slot, 523 }; 524 525 /* O2Micro extra registers */ 526 #define O2_SD_LOCK_WP 0xD3 527 #define O2_SD_MULTI_VCC3V 0xEE 528 #define O2_SD_CLKREQ 0xEC 529 #define O2_SD_CAPS 0xE0 530 #define O2_SD_ADMA1 0xE2 531 #define O2_SD_ADMA2 0xE7 532 #define O2_SD_INF_MOD 0xF1 533 534 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 535 { 536 u8 scratch; 537 int ret; 538 539 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 540 if (ret) 541 return ret; 542 543 /* 544 * Turn PMOS on [bit 0], set over current detection to 2.4 V 545 * [bit 1:2] and enable over current debouncing [bit 6]. 546 */ 547 if (on) 548 scratch |= 0x47; 549 else 550 scratch &= ~0x47; 551 552 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 553 } 554 555 static int jmicron_probe(struct sdhci_pci_chip *chip) 556 { 557 int ret; 558 u16 mmcdev = 0; 559 560 if (chip->pdev->revision == 0) { 561 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 562 SDHCI_QUIRK_32BIT_DMA_SIZE | 563 SDHCI_QUIRK_32BIT_ADMA_SIZE | 564 SDHCI_QUIRK_RESET_AFTER_REQUEST | 565 SDHCI_QUIRK_BROKEN_SMALL_PIO; 566 } 567 568 /* 569 * JMicron chips can have two interfaces to the same hardware 570 * in order to work around limitations in Microsoft's driver. 571 * We need to make sure we only bind to one of them. 572 * 573 * This code assumes two things: 574 * 575 * 1. The PCI code adds subfunctions in order. 576 * 577 * 2. The MMC interface has a lower subfunction number 578 * than the SD interface. 579 */ 580 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 581 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 582 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 583 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 584 585 if (mmcdev) { 586 struct pci_dev *sd_dev; 587 588 sd_dev = NULL; 589 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 590 mmcdev, sd_dev)) != NULL) { 591 if ((PCI_SLOT(chip->pdev->devfn) == 592 PCI_SLOT(sd_dev->devfn)) && 593 (chip->pdev->bus == sd_dev->bus)) 594 break; 595 } 596 597 if (sd_dev) { 598 pci_dev_put(sd_dev); 599 dev_info(&chip->pdev->dev, "Refusing to bind to " 600 "secondary interface.\n"); 601 return -ENODEV; 602 } 603 } 604 605 /* 606 * JMicron chips need a bit of a nudge to enable the power 607 * output pins. 608 */ 609 ret = jmicron_pmos(chip, 1); 610 if (ret) { 611 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 612 return ret; 613 } 614 615 /* quirk for unsable RO-detection on JM388 chips */ 616 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 617 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 618 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 619 620 return 0; 621 } 622 623 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 624 { 625 u8 scratch; 626 627 scratch = readb(host->ioaddr + 0xC0); 628 629 if (on) 630 scratch |= 0x01; 631 else 632 scratch &= ~0x01; 633 634 writeb(scratch, host->ioaddr + 0xC0); 635 } 636 637 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 638 { 639 if (slot->chip->pdev->revision == 0) { 640 u16 version; 641 642 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 643 version = (version & SDHCI_VENDOR_VER_MASK) >> 644 SDHCI_VENDOR_VER_SHIFT; 645 646 /* 647 * Older versions of the chip have lots of nasty glitches 648 * in the ADMA engine. It's best just to avoid it 649 * completely. 650 */ 651 if (version < 0xAC) 652 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 653 } 654 655 /* JM388 MMC doesn't support 1.8V while SD supports it */ 656 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 657 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 658 MMC_VDD_29_30 | MMC_VDD_30_31 | 659 MMC_VDD_165_195; /* allow 1.8V */ 660 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 661 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 662 } 663 664 /* 665 * The secondary interface requires a bit set to get the 666 * interrupts. 667 */ 668 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 669 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 670 jmicron_enable_mmc(slot->host, 1); 671 672 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 673 674 return 0; 675 } 676 677 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 678 { 679 if (dead) 680 return; 681 682 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 683 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 684 jmicron_enable_mmc(slot->host, 0); 685 } 686 687 static int jmicron_suspend(struct sdhci_pci_chip *chip) 688 { 689 int i; 690 691 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 692 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 693 for (i = 0; i < chip->num_slots; i++) 694 jmicron_enable_mmc(chip->slots[i]->host, 0); 695 } 696 697 return 0; 698 } 699 700 static int jmicron_resume(struct sdhci_pci_chip *chip) 701 { 702 int ret, i; 703 704 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 705 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 706 for (i = 0; i < chip->num_slots; i++) 707 jmicron_enable_mmc(chip->slots[i]->host, 1); 708 } 709 710 ret = jmicron_pmos(chip, 1); 711 if (ret) { 712 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 713 return ret; 714 } 715 716 return 0; 717 } 718 719 static const struct sdhci_pci_fixes sdhci_o2 = { 720 .probe = sdhci_pci_o2_probe, 721 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 722 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 723 .probe_slot = sdhci_pci_o2_probe_slot, 724 .resume = sdhci_pci_o2_resume, 725 }; 726 727 static const struct sdhci_pci_fixes sdhci_jmicron = { 728 .probe = jmicron_probe, 729 730 .probe_slot = jmicron_probe_slot, 731 .remove_slot = jmicron_remove_slot, 732 733 .suspend = jmicron_suspend, 734 .resume = jmicron_resume, 735 }; 736 737 /* SysKonnect CardBus2SDIO extra registers */ 738 #define SYSKT_CTRL 0x200 739 #define SYSKT_RDFIFO_STAT 0x204 740 #define SYSKT_WRFIFO_STAT 0x208 741 #define SYSKT_POWER_DATA 0x20c 742 #define SYSKT_POWER_330 0xef 743 #define SYSKT_POWER_300 0xf8 744 #define SYSKT_POWER_184 0xcc 745 #define SYSKT_POWER_CMD 0x20d 746 #define SYSKT_POWER_START (1 << 7) 747 #define SYSKT_POWER_STATUS 0x20e 748 #define SYSKT_POWER_STATUS_OK (1 << 0) 749 #define SYSKT_BOARD_REV 0x210 750 #define SYSKT_CHIP_REV 0x211 751 #define SYSKT_CONF_DATA 0x212 752 #define SYSKT_CONF_DATA_1V8 (1 << 2) 753 #define SYSKT_CONF_DATA_2V5 (1 << 1) 754 #define SYSKT_CONF_DATA_3V3 (1 << 0) 755 756 static int syskt_probe(struct sdhci_pci_chip *chip) 757 { 758 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 759 chip->pdev->class &= ~0x0000FF; 760 chip->pdev->class |= PCI_SDHCI_IFDMA; 761 } 762 return 0; 763 } 764 765 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 766 { 767 int tm, ps; 768 769 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 770 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 771 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 772 "board rev %d.%d, chip rev %d.%d\n", 773 board_rev >> 4, board_rev & 0xf, 774 chip_rev >> 4, chip_rev & 0xf); 775 if (chip_rev >= 0x20) 776 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 777 778 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 779 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 780 udelay(50); 781 tm = 10; /* Wait max 1 ms */ 782 do { 783 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 784 if (ps & SYSKT_POWER_STATUS_OK) 785 break; 786 udelay(100); 787 } while (--tm); 788 if (!tm) { 789 dev_err(&slot->chip->pdev->dev, 790 "power regulator never stabilized"); 791 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 792 return -ENODEV; 793 } 794 795 return 0; 796 } 797 798 static const struct sdhci_pci_fixes sdhci_syskt = { 799 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 800 .probe = syskt_probe, 801 .probe_slot = syskt_probe_slot, 802 }; 803 804 static int via_probe(struct sdhci_pci_chip *chip) 805 { 806 if (chip->pdev->revision == 0x10) 807 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 808 809 return 0; 810 } 811 812 static const struct sdhci_pci_fixes sdhci_via = { 813 .probe = via_probe, 814 }; 815 816 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 817 { 818 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 819 return 0; 820 } 821 822 static const struct sdhci_pci_fixes sdhci_rtsx = { 823 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 824 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 825 SDHCI_QUIRK2_BROKEN_DDR50, 826 .probe_slot = rtsx_probe_slot, 827 }; 828 829 /*AMD chipset generation*/ 830 enum amd_chipset_gen { 831 AMD_CHIPSET_BEFORE_ML, 832 AMD_CHIPSET_CZ, 833 AMD_CHIPSET_NL, 834 AMD_CHIPSET_UNKNOWN, 835 }; 836 837 static int amd_probe(struct sdhci_pci_chip *chip) 838 { 839 struct pci_dev *smbus_dev; 840 enum amd_chipset_gen gen; 841 842 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 843 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 844 if (smbus_dev) { 845 gen = AMD_CHIPSET_BEFORE_ML; 846 } else { 847 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 848 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 849 if (smbus_dev) { 850 if (smbus_dev->revision < 0x51) 851 gen = AMD_CHIPSET_CZ; 852 else 853 gen = AMD_CHIPSET_NL; 854 } else { 855 gen = AMD_CHIPSET_UNKNOWN; 856 } 857 } 858 859 if ((gen == AMD_CHIPSET_BEFORE_ML) || (gen == AMD_CHIPSET_CZ)) { 860 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 861 chip->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 862 } 863 864 return 0; 865 } 866 867 static const struct sdhci_pci_fixes sdhci_amd = { 868 .probe = amd_probe, 869 }; 870 871 static const struct pci_device_id pci_ids[] = { 872 { 873 .vendor = PCI_VENDOR_ID_RICOH, 874 .device = PCI_DEVICE_ID_RICOH_R5C822, 875 .subvendor = PCI_ANY_ID, 876 .subdevice = PCI_ANY_ID, 877 .driver_data = (kernel_ulong_t)&sdhci_ricoh, 878 }, 879 880 { 881 .vendor = PCI_VENDOR_ID_RICOH, 882 .device = 0x843, 883 .subvendor = PCI_ANY_ID, 884 .subdevice = PCI_ANY_ID, 885 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 886 }, 887 888 { 889 .vendor = PCI_VENDOR_ID_RICOH, 890 .device = 0xe822, 891 .subvendor = PCI_ANY_ID, 892 .subdevice = PCI_ANY_ID, 893 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 894 }, 895 896 { 897 .vendor = PCI_VENDOR_ID_RICOH, 898 .device = 0xe823, 899 .subvendor = PCI_ANY_ID, 900 .subdevice = PCI_ANY_ID, 901 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 902 }, 903 904 { 905 .vendor = PCI_VENDOR_ID_ENE, 906 .device = PCI_DEVICE_ID_ENE_CB712_SD, 907 .subvendor = PCI_ANY_ID, 908 .subdevice = PCI_ANY_ID, 909 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 910 }, 911 912 { 913 .vendor = PCI_VENDOR_ID_ENE, 914 .device = PCI_DEVICE_ID_ENE_CB712_SD_2, 915 .subvendor = PCI_ANY_ID, 916 .subdevice = PCI_ANY_ID, 917 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 918 }, 919 920 { 921 .vendor = PCI_VENDOR_ID_ENE, 922 .device = PCI_DEVICE_ID_ENE_CB714_SD, 923 .subvendor = PCI_ANY_ID, 924 .subdevice = PCI_ANY_ID, 925 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 926 }, 927 928 { 929 .vendor = PCI_VENDOR_ID_ENE, 930 .device = PCI_DEVICE_ID_ENE_CB714_SD_2, 931 .subvendor = PCI_ANY_ID, 932 .subdevice = PCI_ANY_ID, 933 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 934 }, 935 936 { 937 .vendor = PCI_VENDOR_ID_MARVELL, 938 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD, 939 .subvendor = PCI_ANY_ID, 940 .subdevice = PCI_ANY_ID, 941 .driver_data = (kernel_ulong_t)&sdhci_cafe, 942 }, 943 944 { 945 .vendor = PCI_VENDOR_ID_JMICRON, 946 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD, 947 .subvendor = PCI_ANY_ID, 948 .subdevice = PCI_ANY_ID, 949 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 950 }, 951 952 { 953 .vendor = PCI_VENDOR_ID_JMICRON, 954 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC, 955 .subvendor = PCI_ANY_ID, 956 .subdevice = PCI_ANY_ID, 957 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 958 }, 959 960 { 961 .vendor = PCI_VENDOR_ID_JMICRON, 962 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD, 963 .subvendor = PCI_ANY_ID, 964 .subdevice = PCI_ANY_ID, 965 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 966 }, 967 968 { 969 .vendor = PCI_VENDOR_ID_JMICRON, 970 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD, 971 .subvendor = PCI_ANY_ID, 972 .subdevice = PCI_ANY_ID, 973 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 974 }, 975 976 { 977 .vendor = PCI_VENDOR_ID_SYSKONNECT, 978 .device = 0x8000, 979 .subvendor = PCI_ANY_ID, 980 .subdevice = PCI_ANY_ID, 981 .driver_data = (kernel_ulong_t)&sdhci_syskt, 982 }, 983 984 { 985 .vendor = PCI_VENDOR_ID_VIA, 986 .device = 0x95d0, 987 .subvendor = PCI_ANY_ID, 988 .subdevice = PCI_ANY_ID, 989 .driver_data = (kernel_ulong_t)&sdhci_via, 990 }, 991 992 { 993 .vendor = PCI_VENDOR_ID_REALTEK, 994 .device = 0x5250, 995 .subvendor = PCI_ANY_ID, 996 .subdevice = PCI_ANY_ID, 997 .driver_data = (kernel_ulong_t)&sdhci_rtsx, 998 }, 999 1000 { 1001 .vendor = PCI_VENDOR_ID_INTEL, 1002 .device = PCI_DEVICE_ID_INTEL_QRK_SD, 1003 .subvendor = PCI_ANY_ID, 1004 .subdevice = PCI_ANY_ID, 1005 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk, 1006 }, 1007 1008 { 1009 .vendor = PCI_VENDOR_ID_INTEL, 1010 .device = PCI_DEVICE_ID_INTEL_MRST_SD0, 1011 .subvendor = PCI_ANY_ID, 1012 .subdevice = PCI_ANY_ID, 1013 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0, 1014 }, 1015 1016 { 1017 .vendor = PCI_VENDOR_ID_INTEL, 1018 .device = PCI_DEVICE_ID_INTEL_MRST_SD1, 1019 .subvendor = PCI_ANY_ID, 1020 .subdevice = PCI_ANY_ID, 1021 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 1022 }, 1023 1024 { 1025 .vendor = PCI_VENDOR_ID_INTEL, 1026 .device = PCI_DEVICE_ID_INTEL_MRST_SD2, 1027 .subvendor = PCI_ANY_ID, 1028 .subdevice = PCI_ANY_ID, 1029 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 1030 }, 1031 1032 { 1033 .vendor = PCI_VENDOR_ID_INTEL, 1034 .device = PCI_DEVICE_ID_INTEL_MFD_SD, 1035 .subvendor = PCI_ANY_ID, 1036 .subdevice = PCI_ANY_ID, 1037 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1038 }, 1039 1040 { 1041 .vendor = PCI_VENDOR_ID_INTEL, 1042 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1, 1043 .subvendor = PCI_ANY_ID, 1044 .subdevice = PCI_ANY_ID, 1045 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1046 }, 1047 1048 { 1049 .vendor = PCI_VENDOR_ID_INTEL, 1050 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2, 1051 .subvendor = PCI_ANY_ID, 1052 .subdevice = PCI_ANY_ID, 1053 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1054 }, 1055 1056 { 1057 .vendor = PCI_VENDOR_ID_INTEL, 1058 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0, 1059 .subvendor = PCI_ANY_ID, 1060 .subdevice = PCI_ANY_ID, 1061 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1062 }, 1063 1064 { 1065 .vendor = PCI_VENDOR_ID_INTEL, 1066 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1, 1067 .subvendor = PCI_ANY_ID, 1068 .subdevice = PCI_ANY_ID, 1069 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1070 }, 1071 1072 { 1073 .vendor = PCI_VENDOR_ID_INTEL, 1074 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0, 1075 .subvendor = PCI_ANY_ID, 1076 .subdevice = PCI_ANY_ID, 1077 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1078 }, 1079 1080 { 1081 .vendor = PCI_VENDOR_ID_INTEL, 1082 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1, 1083 .subvendor = PCI_ANY_ID, 1084 .subdevice = PCI_ANY_ID, 1085 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1086 }, 1087 1088 { 1089 .vendor = PCI_VENDOR_ID_INTEL, 1090 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC, 1091 .subvendor = PCI_ANY_ID, 1092 .subdevice = PCI_ANY_ID, 1093 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1094 }, 1095 1096 { 1097 .vendor = PCI_VENDOR_ID_INTEL, 1098 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, 1099 .subvendor = PCI_VENDOR_ID_NI, 1100 .subdevice = 0x7884, 1101 .driver_data = (kernel_ulong_t)&sdhci_ni_byt_sdio, 1102 }, 1103 1104 { 1105 .vendor = PCI_VENDOR_ID_INTEL, 1106 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, 1107 .subvendor = PCI_ANY_ID, 1108 .subdevice = PCI_ANY_ID, 1109 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1110 }, 1111 1112 { 1113 .vendor = PCI_VENDOR_ID_INTEL, 1114 .device = PCI_DEVICE_ID_INTEL_BYT_SD, 1115 .subvendor = PCI_ANY_ID, 1116 .subdevice = PCI_ANY_ID, 1117 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1118 }, 1119 1120 { 1121 .vendor = PCI_VENDOR_ID_INTEL, 1122 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2, 1123 .subvendor = PCI_ANY_ID, 1124 .subdevice = PCI_ANY_ID, 1125 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1126 }, 1127 1128 { 1129 .vendor = PCI_VENDOR_ID_INTEL, 1130 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC, 1131 .subvendor = PCI_ANY_ID, 1132 .subdevice = PCI_ANY_ID, 1133 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1134 }, 1135 1136 { 1137 .vendor = PCI_VENDOR_ID_INTEL, 1138 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO, 1139 .subvendor = PCI_ANY_ID, 1140 .subdevice = PCI_ANY_ID, 1141 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1142 }, 1143 1144 { 1145 .vendor = PCI_VENDOR_ID_INTEL, 1146 .device = PCI_DEVICE_ID_INTEL_BSW_SD, 1147 .subvendor = PCI_ANY_ID, 1148 .subdevice = PCI_ANY_ID, 1149 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1150 }, 1151 1152 { 1153 .vendor = PCI_VENDOR_ID_INTEL, 1154 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0, 1155 .subvendor = PCI_ANY_ID, 1156 .subdevice = PCI_ANY_ID, 1157 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1158 }, 1159 1160 { 1161 .vendor = PCI_VENDOR_ID_INTEL, 1162 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1, 1163 .subvendor = PCI_ANY_ID, 1164 .subdevice = PCI_ANY_ID, 1165 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1166 }, 1167 1168 { 1169 .vendor = PCI_VENDOR_ID_INTEL, 1170 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2, 1171 .subvendor = PCI_ANY_ID, 1172 .subdevice = PCI_ANY_ID, 1173 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1174 }, 1175 1176 { 1177 .vendor = PCI_VENDOR_ID_INTEL, 1178 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0, 1179 .subvendor = PCI_ANY_ID, 1180 .subdevice = PCI_ANY_ID, 1181 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1182 }, 1183 1184 { 1185 .vendor = PCI_VENDOR_ID_INTEL, 1186 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1, 1187 .subvendor = PCI_ANY_ID, 1188 .subdevice = PCI_ANY_ID, 1189 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1190 }, 1191 1192 { 1193 .vendor = PCI_VENDOR_ID_INTEL, 1194 .device = PCI_DEVICE_ID_INTEL_MRFLD_MMC, 1195 .subvendor = PCI_ANY_ID, 1196 .subdevice = PCI_ANY_ID, 1197 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfld_mmc, 1198 }, 1199 1200 { 1201 .vendor = PCI_VENDOR_ID_INTEL, 1202 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC, 1203 .subvendor = PCI_ANY_ID, 1204 .subdevice = PCI_ANY_ID, 1205 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1206 }, 1207 1208 { 1209 .vendor = PCI_VENDOR_ID_INTEL, 1210 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO, 1211 .subvendor = PCI_ANY_ID, 1212 .subdevice = PCI_ANY_ID, 1213 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1214 }, 1215 1216 { 1217 .vendor = PCI_VENDOR_ID_INTEL, 1218 .device = PCI_DEVICE_ID_INTEL_SPT_SD, 1219 .subvendor = PCI_ANY_ID, 1220 .subdevice = PCI_ANY_ID, 1221 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1222 }, 1223 1224 { 1225 .vendor = PCI_VENDOR_ID_INTEL, 1226 .device = PCI_DEVICE_ID_INTEL_DNV_EMMC, 1227 .subvendor = PCI_ANY_ID, 1228 .subdevice = PCI_ANY_ID, 1229 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1230 }, 1231 1232 { 1233 .vendor = PCI_VENDOR_ID_INTEL, 1234 .device = PCI_DEVICE_ID_INTEL_BXT_EMMC, 1235 .subvendor = PCI_ANY_ID, 1236 .subdevice = PCI_ANY_ID, 1237 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1238 }, 1239 1240 { 1241 .vendor = PCI_VENDOR_ID_INTEL, 1242 .device = PCI_DEVICE_ID_INTEL_BXT_SDIO, 1243 .subvendor = PCI_ANY_ID, 1244 .subdevice = PCI_ANY_ID, 1245 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1246 }, 1247 1248 { 1249 .vendor = PCI_VENDOR_ID_INTEL, 1250 .device = PCI_DEVICE_ID_INTEL_BXT_SD, 1251 .subvendor = PCI_ANY_ID, 1252 .subdevice = PCI_ANY_ID, 1253 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1254 }, 1255 1256 { 1257 .vendor = PCI_VENDOR_ID_INTEL, 1258 .device = PCI_DEVICE_ID_INTEL_BXTM_EMMC, 1259 .subvendor = PCI_ANY_ID, 1260 .subdevice = PCI_ANY_ID, 1261 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1262 }, 1263 1264 { 1265 .vendor = PCI_VENDOR_ID_INTEL, 1266 .device = PCI_DEVICE_ID_INTEL_BXTM_SDIO, 1267 .subvendor = PCI_ANY_ID, 1268 .subdevice = PCI_ANY_ID, 1269 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1270 }, 1271 1272 { 1273 .vendor = PCI_VENDOR_ID_INTEL, 1274 .device = PCI_DEVICE_ID_INTEL_BXTM_SD, 1275 .subvendor = PCI_ANY_ID, 1276 .subdevice = PCI_ANY_ID, 1277 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1278 }, 1279 1280 { 1281 .vendor = PCI_VENDOR_ID_INTEL, 1282 .device = PCI_DEVICE_ID_INTEL_APL_EMMC, 1283 .subvendor = PCI_ANY_ID, 1284 .subdevice = PCI_ANY_ID, 1285 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1286 }, 1287 1288 { 1289 .vendor = PCI_VENDOR_ID_INTEL, 1290 .device = PCI_DEVICE_ID_INTEL_APL_SDIO, 1291 .subvendor = PCI_ANY_ID, 1292 .subdevice = PCI_ANY_ID, 1293 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1294 }, 1295 1296 { 1297 .vendor = PCI_VENDOR_ID_INTEL, 1298 .device = PCI_DEVICE_ID_INTEL_APL_SD, 1299 .subvendor = PCI_ANY_ID, 1300 .subdevice = PCI_ANY_ID, 1301 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1302 }, 1303 1304 { 1305 .vendor = PCI_VENDOR_ID_INTEL, 1306 .device = PCI_DEVICE_ID_INTEL_GLK_EMMC, 1307 .subvendor = PCI_ANY_ID, 1308 .subdevice = PCI_ANY_ID, 1309 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1310 }, 1311 1312 { 1313 .vendor = PCI_VENDOR_ID_INTEL, 1314 .device = PCI_DEVICE_ID_INTEL_GLK_SDIO, 1315 .subvendor = PCI_ANY_ID, 1316 .subdevice = PCI_ANY_ID, 1317 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1318 }, 1319 1320 { 1321 .vendor = PCI_VENDOR_ID_INTEL, 1322 .device = PCI_DEVICE_ID_INTEL_GLK_SD, 1323 .subvendor = PCI_ANY_ID, 1324 .subdevice = PCI_ANY_ID, 1325 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1326 }, 1327 1328 { 1329 .vendor = PCI_VENDOR_ID_O2, 1330 .device = PCI_DEVICE_ID_O2_8120, 1331 .subvendor = PCI_ANY_ID, 1332 .subdevice = PCI_ANY_ID, 1333 .driver_data = (kernel_ulong_t)&sdhci_o2, 1334 }, 1335 1336 { 1337 .vendor = PCI_VENDOR_ID_O2, 1338 .device = PCI_DEVICE_ID_O2_8220, 1339 .subvendor = PCI_ANY_ID, 1340 .subdevice = PCI_ANY_ID, 1341 .driver_data = (kernel_ulong_t)&sdhci_o2, 1342 }, 1343 1344 { 1345 .vendor = PCI_VENDOR_ID_O2, 1346 .device = PCI_DEVICE_ID_O2_8221, 1347 .subvendor = PCI_ANY_ID, 1348 .subdevice = PCI_ANY_ID, 1349 .driver_data = (kernel_ulong_t)&sdhci_o2, 1350 }, 1351 1352 { 1353 .vendor = PCI_VENDOR_ID_O2, 1354 .device = PCI_DEVICE_ID_O2_8320, 1355 .subvendor = PCI_ANY_ID, 1356 .subdevice = PCI_ANY_ID, 1357 .driver_data = (kernel_ulong_t)&sdhci_o2, 1358 }, 1359 1360 { 1361 .vendor = PCI_VENDOR_ID_O2, 1362 .device = PCI_DEVICE_ID_O2_8321, 1363 .subvendor = PCI_ANY_ID, 1364 .subdevice = PCI_ANY_ID, 1365 .driver_data = (kernel_ulong_t)&sdhci_o2, 1366 }, 1367 1368 { 1369 .vendor = PCI_VENDOR_ID_O2, 1370 .device = PCI_DEVICE_ID_O2_FUJIN2, 1371 .subvendor = PCI_ANY_ID, 1372 .subdevice = PCI_ANY_ID, 1373 .driver_data = (kernel_ulong_t)&sdhci_o2, 1374 }, 1375 1376 { 1377 .vendor = PCI_VENDOR_ID_O2, 1378 .device = PCI_DEVICE_ID_O2_SDS0, 1379 .subvendor = PCI_ANY_ID, 1380 .subdevice = PCI_ANY_ID, 1381 .driver_data = (kernel_ulong_t)&sdhci_o2, 1382 }, 1383 1384 { 1385 .vendor = PCI_VENDOR_ID_O2, 1386 .device = PCI_DEVICE_ID_O2_SDS1, 1387 .subvendor = PCI_ANY_ID, 1388 .subdevice = PCI_ANY_ID, 1389 .driver_data = (kernel_ulong_t)&sdhci_o2, 1390 }, 1391 1392 { 1393 .vendor = PCI_VENDOR_ID_O2, 1394 .device = PCI_DEVICE_ID_O2_SEABIRD0, 1395 .subvendor = PCI_ANY_ID, 1396 .subdevice = PCI_ANY_ID, 1397 .driver_data = (kernel_ulong_t)&sdhci_o2, 1398 }, 1399 1400 { 1401 .vendor = PCI_VENDOR_ID_O2, 1402 .device = PCI_DEVICE_ID_O2_SEABIRD1, 1403 .subvendor = PCI_ANY_ID, 1404 .subdevice = PCI_ANY_ID, 1405 .driver_data = (kernel_ulong_t)&sdhci_o2, 1406 }, 1407 { 1408 .vendor = PCI_VENDOR_ID_AMD, 1409 .device = PCI_ANY_ID, 1410 .class = PCI_CLASS_SYSTEM_SDHCI << 8, 1411 .class_mask = 0xFFFF00, 1412 .subvendor = PCI_ANY_ID, 1413 .subdevice = PCI_ANY_ID, 1414 .driver_data = (kernel_ulong_t)&sdhci_amd, 1415 }, 1416 { /* Generic SD host controller */ 1417 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) 1418 }, 1419 1420 { /* end: all zeroes */ }, 1421 }; 1422 1423 MODULE_DEVICE_TABLE(pci, pci_ids); 1424 1425 /*****************************************************************************\ 1426 * * 1427 * SDHCI core callbacks * 1428 * * 1429 \*****************************************************************************/ 1430 1431 static int sdhci_pci_enable_dma(struct sdhci_host *host) 1432 { 1433 struct sdhci_pci_slot *slot; 1434 struct pci_dev *pdev; 1435 1436 slot = sdhci_priv(host); 1437 pdev = slot->chip->pdev; 1438 1439 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1440 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1441 (host->flags & SDHCI_USE_SDMA)) { 1442 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1443 "doesn't fully claim to support it.\n"); 1444 } 1445 1446 pci_set_master(pdev); 1447 1448 return 0; 1449 } 1450 1451 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width) 1452 { 1453 u8 ctrl; 1454 1455 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1456 1457 switch (width) { 1458 case MMC_BUS_WIDTH_8: 1459 ctrl |= SDHCI_CTRL_8BITBUS; 1460 ctrl &= ~SDHCI_CTRL_4BITBUS; 1461 break; 1462 case MMC_BUS_WIDTH_4: 1463 ctrl |= SDHCI_CTRL_4BITBUS; 1464 ctrl &= ~SDHCI_CTRL_8BITBUS; 1465 break; 1466 default: 1467 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS); 1468 break; 1469 } 1470 1471 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1472 } 1473 1474 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1475 { 1476 struct sdhci_pci_slot *slot = sdhci_priv(host); 1477 int rst_n_gpio = slot->rst_n_gpio; 1478 1479 if (!gpio_is_valid(rst_n_gpio)) 1480 return; 1481 gpio_set_value_cansleep(rst_n_gpio, 0); 1482 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1483 udelay(10); 1484 gpio_set_value_cansleep(rst_n_gpio, 1); 1485 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1486 usleep_range(300, 1000); 1487 } 1488 1489 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1490 { 1491 struct sdhci_pci_slot *slot = sdhci_priv(host); 1492 1493 if (slot->hw_reset) 1494 slot->hw_reset(host); 1495 } 1496 1497 static int sdhci_pci_select_drive_strength(struct sdhci_host *host, 1498 struct mmc_card *card, 1499 unsigned int max_dtr, int host_drv, 1500 int card_drv, int *drv_type) 1501 { 1502 struct sdhci_pci_slot *slot = sdhci_priv(host); 1503 1504 if (!slot->select_drive_strength) 1505 return 0; 1506 1507 return slot->select_drive_strength(host, card, max_dtr, host_drv, 1508 card_drv, drv_type); 1509 } 1510 1511 static const struct sdhci_ops sdhci_pci_ops = { 1512 .set_clock = sdhci_set_clock, 1513 .enable_dma = sdhci_pci_enable_dma, 1514 .set_bus_width = sdhci_pci_set_bus_width, 1515 .reset = sdhci_reset, 1516 .set_uhs_signaling = sdhci_set_uhs_signaling, 1517 .hw_reset = sdhci_pci_hw_reset, 1518 .select_drive_strength = sdhci_pci_select_drive_strength, 1519 }; 1520 1521 /*****************************************************************************\ 1522 * * 1523 * Suspend/resume * 1524 * * 1525 \*****************************************************************************/ 1526 1527 #ifdef CONFIG_PM_SLEEP 1528 static int sdhci_pci_suspend(struct device *dev) 1529 { 1530 struct pci_dev *pdev = to_pci_dev(dev); 1531 struct sdhci_pci_chip *chip; 1532 struct sdhci_pci_slot *slot; 1533 mmc_pm_flag_t slot_pm_flags; 1534 mmc_pm_flag_t pm_flags = 0; 1535 int i, ret; 1536 1537 chip = pci_get_drvdata(pdev); 1538 if (!chip) 1539 return 0; 1540 1541 for (i = 0; i < chip->num_slots; i++) { 1542 slot = chip->slots[i]; 1543 if (!slot) 1544 continue; 1545 1546 ret = sdhci_suspend_host(slot->host); 1547 1548 if (ret) 1549 goto err_pci_suspend; 1550 1551 slot_pm_flags = slot->host->mmc->pm_flags; 1552 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1553 sdhci_enable_irq_wakeups(slot->host); 1554 1555 pm_flags |= slot_pm_flags; 1556 } 1557 1558 if (chip->fixes && chip->fixes->suspend) { 1559 ret = chip->fixes->suspend(chip); 1560 if (ret) 1561 goto err_pci_suspend; 1562 } 1563 1564 if (pm_flags & MMC_PM_KEEP_POWER) { 1565 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1566 device_init_wakeup(dev, true); 1567 else 1568 device_init_wakeup(dev, false); 1569 } else 1570 device_init_wakeup(dev, false); 1571 1572 return 0; 1573 1574 err_pci_suspend: 1575 while (--i >= 0) 1576 sdhci_resume_host(chip->slots[i]->host); 1577 return ret; 1578 } 1579 1580 static int sdhci_pci_resume(struct device *dev) 1581 { 1582 struct pci_dev *pdev = to_pci_dev(dev); 1583 struct sdhci_pci_chip *chip; 1584 struct sdhci_pci_slot *slot; 1585 int i, ret; 1586 1587 chip = pci_get_drvdata(pdev); 1588 if (!chip) 1589 return 0; 1590 1591 if (chip->fixes && chip->fixes->resume) { 1592 ret = chip->fixes->resume(chip); 1593 if (ret) 1594 return ret; 1595 } 1596 1597 for (i = 0; i < chip->num_slots; i++) { 1598 slot = chip->slots[i]; 1599 if (!slot) 1600 continue; 1601 1602 ret = sdhci_resume_host(slot->host); 1603 if (ret) 1604 return ret; 1605 } 1606 1607 return 0; 1608 } 1609 #endif 1610 1611 #ifdef CONFIG_PM 1612 static int sdhci_pci_runtime_suspend(struct device *dev) 1613 { 1614 struct pci_dev *pdev = to_pci_dev(dev); 1615 struct sdhci_pci_chip *chip; 1616 struct sdhci_pci_slot *slot; 1617 int i, ret; 1618 1619 chip = pci_get_drvdata(pdev); 1620 if (!chip) 1621 return 0; 1622 1623 for (i = 0; i < chip->num_slots; i++) { 1624 slot = chip->slots[i]; 1625 if (!slot) 1626 continue; 1627 1628 ret = sdhci_runtime_suspend_host(slot->host); 1629 1630 if (ret) 1631 goto err_pci_runtime_suspend; 1632 } 1633 1634 if (chip->fixes && chip->fixes->suspend) { 1635 ret = chip->fixes->suspend(chip); 1636 if (ret) 1637 goto err_pci_runtime_suspend; 1638 } 1639 1640 return 0; 1641 1642 err_pci_runtime_suspend: 1643 while (--i >= 0) 1644 sdhci_runtime_resume_host(chip->slots[i]->host); 1645 return ret; 1646 } 1647 1648 static int sdhci_pci_runtime_resume(struct device *dev) 1649 { 1650 struct pci_dev *pdev = to_pci_dev(dev); 1651 struct sdhci_pci_chip *chip; 1652 struct sdhci_pci_slot *slot; 1653 int i, ret; 1654 1655 chip = pci_get_drvdata(pdev); 1656 if (!chip) 1657 return 0; 1658 1659 if (chip->fixes && chip->fixes->resume) { 1660 ret = chip->fixes->resume(chip); 1661 if (ret) 1662 return ret; 1663 } 1664 1665 for (i = 0; i < chip->num_slots; i++) { 1666 slot = chip->slots[i]; 1667 if (!slot) 1668 continue; 1669 1670 ret = sdhci_runtime_resume_host(slot->host); 1671 if (ret) 1672 return ret; 1673 } 1674 1675 return 0; 1676 } 1677 #endif 1678 1679 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1680 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1681 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1682 sdhci_pci_runtime_resume, NULL) 1683 }; 1684 1685 /*****************************************************************************\ 1686 * * 1687 * Device probing/removal * 1688 * * 1689 \*****************************************************************************/ 1690 1691 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1692 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1693 int slotno) 1694 { 1695 struct sdhci_pci_slot *slot; 1696 struct sdhci_host *host; 1697 int ret, bar = first_bar + slotno; 1698 1699 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1700 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1701 return ERR_PTR(-ENODEV); 1702 } 1703 1704 if (pci_resource_len(pdev, bar) < 0x100) { 1705 dev_err(&pdev->dev, "Invalid iomem size. You may " 1706 "experience problems.\n"); 1707 } 1708 1709 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1710 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1711 return ERR_PTR(-ENODEV); 1712 } 1713 1714 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1715 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1716 return ERR_PTR(-ENODEV); 1717 } 1718 1719 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot)); 1720 if (IS_ERR(host)) { 1721 dev_err(&pdev->dev, "cannot allocate host\n"); 1722 return ERR_CAST(host); 1723 } 1724 1725 slot = sdhci_priv(host); 1726 1727 slot->chip = chip; 1728 slot->host = host; 1729 slot->rst_n_gpio = -EINVAL; 1730 slot->cd_gpio = -EINVAL; 1731 slot->cd_idx = -1; 1732 1733 /* Retrieve platform data if there is any */ 1734 if (*sdhci_pci_get_data) 1735 slot->data = sdhci_pci_get_data(pdev, slotno); 1736 1737 if (slot->data) { 1738 if (slot->data->setup) { 1739 ret = slot->data->setup(slot->data); 1740 if (ret) { 1741 dev_err(&pdev->dev, "platform setup failed\n"); 1742 goto free; 1743 } 1744 } 1745 slot->rst_n_gpio = slot->data->rst_n_gpio; 1746 slot->cd_gpio = slot->data->cd_gpio; 1747 } 1748 1749 host->hw_name = "PCI"; 1750 host->ops = chip->fixes && chip->fixes->ops ? 1751 chip->fixes->ops : 1752 &sdhci_pci_ops; 1753 host->quirks = chip->quirks; 1754 host->quirks2 = chip->quirks2; 1755 1756 host->irq = pdev->irq; 1757 1758 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1759 if (ret) { 1760 dev_err(&pdev->dev, "cannot request region\n"); 1761 goto cleanup; 1762 } 1763 1764 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1765 1766 if (chip->fixes && chip->fixes->probe_slot) { 1767 ret = chip->fixes->probe_slot(slot); 1768 if (ret) 1769 goto cleanup; 1770 } 1771 1772 if (gpio_is_valid(slot->rst_n_gpio)) { 1773 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1774 gpio_direction_output(slot->rst_n_gpio, 1); 1775 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1776 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1777 } else { 1778 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1779 slot->rst_n_gpio = -EINVAL; 1780 } 1781 } 1782 1783 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; 1784 host->mmc->slotno = slotno; 1785 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1786 1787 if (slot->cd_idx >= 0) { 1788 ret = mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx, 1789 slot->cd_override_level, 0, NULL); 1790 if (ret == -EPROBE_DEFER) 1791 goto remove; 1792 1793 if (ret) { 1794 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 1795 slot->cd_idx = -1; 1796 } 1797 } 1798 1799 ret = sdhci_add_host(host); 1800 if (ret) 1801 goto remove; 1802 1803 sdhci_pci_add_own_cd(slot); 1804 1805 /* 1806 * Check if the chip needs a separate GPIO for card detect to wake up 1807 * from runtime suspend. If it is not there, don't allow runtime PM. 1808 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 1809 */ 1810 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 1811 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 1812 chip->allow_runtime_pm = false; 1813 1814 return slot; 1815 1816 remove: 1817 if (chip->fixes && chip->fixes->remove_slot) 1818 chip->fixes->remove_slot(slot, 0); 1819 1820 cleanup: 1821 if (slot->data && slot->data->cleanup) 1822 slot->data->cleanup(slot->data); 1823 1824 free: 1825 sdhci_free_host(host); 1826 1827 return ERR_PTR(ret); 1828 } 1829 1830 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 1831 { 1832 int dead; 1833 u32 scratch; 1834 1835 sdhci_pci_remove_own_cd(slot); 1836 1837 dead = 0; 1838 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 1839 if (scratch == (u32)-1) 1840 dead = 1; 1841 1842 sdhci_remove_host(slot->host, dead); 1843 1844 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 1845 slot->chip->fixes->remove_slot(slot, dead); 1846 1847 if (slot->data && slot->data->cleanup) 1848 slot->data->cleanup(slot->data); 1849 1850 sdhci_free_host(slot->host); 1851 } 1852 1853 static void sdhci_pci_runtime_pm_allow(struct device *dev) 1854 { 1855 pm_suspend_ignore_children(dev, 1); 1856 pm_runtime_set_autosuspend_delay(dev, 50); 1857 pm_runtime_use_autosuspend(dev); 1858 pm_runtime_allow(dev); 1859 /* Stay active until mmc core scans for a card */ 1860 pm_runtime_put_noidle(dev); 1861 } 1862 1863 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 1864 { 1865 pm_runtime_forbid(dev); 1866 pm_runtime_get_noresume(dev); 1867 } 1868 1869 static int sdhci_pci_probe(struct pci_dev *pdev, 1870 const struct pci_device_id *ent) 1871 { 1872 struct sdhci_pci_chip *chip; 1873 struct sdhci_pci_slot *slot; 1874 1875 u8 slots, first_bar; 1876 int ret, i; 1877 1878 BUG_ON(pdev == NULL); 1879 BUG_ON(ent == NULL); 1880 1881 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 1882 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 1883 1884 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 1885 if (ret) 1886 return ret; 1887 1888 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 1889 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 1890 if (slots == 0) 1891 return -ENODEV; 1892 1893 BUG_ON(slots > MAX_SLOTS); 1894 1895 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 1896 if (ret) 1897 return ret; 1898 1899 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 1900 1901 if (first_bar > 5) { 1902 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 1903 return -ENODEV; 1904 } 1905 1906 ret = pcim_enable_device(pdev); 1907 if (ret) 1908 return ret; 1909 1910 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 1911 if (!chip) 1912 return -ENOMEM; 1913 1914 chip->pdev = pdev; 1915 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 1916 if (chip->fixes) { 1917 chip->quirks = chip->fixes->quirks; 1918 chip->quirks2 = chip->fixes->quirks2; 1919 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 1920 } 1921 chip->num_slots = slots; 1922 1923 pci_set_drvdata(pdev, chip); 1924 1925 if (chip->fixes && chip->fixes->probe) { 1926 ret = chip->fixes->probe(chip); 1927 if (ret) 1928 return ret; 1929 } 1930 1931 slots = chip->num_slots; /* Quirk may have changed this */ 1932 1933 for (i = 0; i < slots; i++) { 1934 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 1935 if (IS_ERR(slot)) { 1936 for (i--; i >= 0; i--) 1937 sdhci_pci_remove_slot(chip->slots[i]); 1938 return PTR_ERR(slot); 1939 } 1940 1941 chip->slots[i] = slot; 1942 } 1943 1944 if (chip->allow_runtime_pm) 1945 sdhci_pci_runtime_pm_allow(&pdev->dev); 1946 1947 return 0; 1948 } 1949 1950 static void sdhci_pci_remove(struct pci_dev *pdev) 1951 { 1952 int i; 1953 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1954 1955 if (chip->allow_runtime_pm) 1956 sdhci_pci_runtime_pm_forbid(&pdev->dev); 1957 1958 for (i = 0; i < chip->num_slots; i++) 1959 sdhci_pci_remove_slot(chip->slots[i]); 1960 } 1961 1962 static struct pci_driver sdhci_driver = { 1963 .name = "sdhci-pci", 1964 .id_table = pci_ids, 1965 .probe = sdhci_pci_probe, 1966 .remove = sdhci_pci_remove, 1967 .driver = { 1968 .pm = &sdhci_pci_pm_ops 1969 }, 1970 }; 1971 1972 module_pci_driver(sdhci_driver); 1973 1974 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 1975 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 1976 MODULE_LICENSE("GPL"); 1977