1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 3 * 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 5 * 6 * Thanks to the following companies for their support: 7 * 8 * - JMicron (hardware and technical support) 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/string.h> 13 #include <linux/delay.h> 14 #include <linux/highmem.h> 15 #include <linux/module.h> 16 #include <linux/pci.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/slab.h> 19 #include <linux/device.h> 20 #include <linux/mmc/host.h> 21 #include <linux/mmc/mmc.h> 22 #include <linux/scatterlist.h> 23 #include <linux/io.h> 24 #include <linux/iopoll.h> 25 #include <linux/gpio.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/pm_qos.h> 28 #include <linux/debugfs.h> 29 #include <linux/mmc/slot-gpio.h> 30 #include <linux/mmc/sdhci-pci-data.h> 31 #include <linux/acpi.h> 32 #include <linux/dmi.h> 33 34 #ifdef CONFIG_X86 35 #include <asm/iosf_mbi.h> 36 #endif 37 38 #include "cqhci.h" 39 40 #include "sdhci.h" 41 #include "sdhci-pci.h" 42 43 static void sdhci_pci_hw_reset(struct sdhci_host *host); 44 45 #ifdef CONFIG_PM_SLEEP 46 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip) 47 { 48 mmc_pm_flag_t pm_flags = 0; 49 bool cap_cd_wake = false; 50 int i; 51 52 for (i = 0; i < chip->num_slots; i++) { 53 struct sdhci_pci_slot *slot = chip->slots[i]; 54 55 if (slot) { 56 pm_flags |= slot->host->mmc->pm_flags; 57 if (slot->host->mmc->caps & MMC_CAP_CD_WAKE) 58 cap_cd_wake = true; 59 } 60 } 61 62 if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ)) 63 return device_wakeup_enable(&chip->pdev->dev); 64 else if (!cap_cd_wake) 65 return device_wakeup_disable(&chip->pdev->dev); 66 67 return 0; 68 } 69 70 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 71 { 72 int i, ret; 73 74 sdhci_pci_init_wakeup(chip); 75 76 for (i = 0; i < chip->num_slots; i++) { 77 struct sdhci_pci_slot *slot = chip->slots[i]; 78 struct sdhci_host *host; 79 80 if (!slot) 81 continue; 82 83 host = slot->host; 84 85 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 86 mmc_retune_needed(host->mmc); 87 88 ret = sdhci_suspend_host(host); 89 if (ret) 90 goto err_pci_suspend; 91 92 if (device_may_wakeup(&chip->pdev->dev)) 93 mmc_gpio_set_cd_wake(host->mmc, true); 94 } 95 96 return 0; 97 98 err_pci_suspend: 99 while (--i >= 0) 100 sdhci_resume_host(chip->slots[i]->host); 101 return ret; 102 } 103 104 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip) 105 { 106 struct sdhci_pci_slot *slot; 107 int i, ret; 108 109 for (i = 0; i < chip->num_slots; i++) { 110 slot = chip->slots[i]; 111 if (!slot) 112 continue; 113 114 ret = sdhci_resume_host(slot->host); 115 if (ret) 116 return ret; 117 118 mmc_gpio_set_cd_wake(slot->host->mmc, false); 119 } 120 121 return 0; 122 } 123 124 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip) 125 { 126 int ret; 127 128 ret = cqhci_suspend(chip->slots[0]->host->mmc); 129 if (ret) 130 return ret; 131 132 return sdhci_pci_suspend_host(chip); 133 } 134 135 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip) 136 { 137 int ret; 138 139 ret = sdhci_pci_resume_host(chip); 140 if (ret) 141 return ret; 142 143 return cqhci_resume(chip->slots[0]->host->mmc); 144 } 145 #endif 146 147 #ifdef CONFIG_PM 148 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip) 149 { 150 struct sdhci_pci_slot *slot; 151 struct sdhci_host *host; 152 int i, ret; 153 154 for (i = 0; i < chip->num_slots; i++) { 155 slot = chip->slots[i]; 156 if (!slot) 157 continue; 158 159 host = slot->host; 160 161 ret = sdhci_runtime_suspend_host(host); 162 if (ret) 163 goto err_pci_runtime_suspend; 164 165 if (chip->rpm_retune && 166 host->tuning_mode != SDHCI_TUNING_MODE_3) 167 mmc_retune_needed(host->mmc); 168 } 169 170 return 0; 171 172 err_pci_runtime_suspend: 173 while (--i >= 0) 174 sdhci_runtime_resume_host(chip->slots[i]->host, 0); 175 return ret; 176 } 177 178 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip) 179 { 180 struct sdhci_pci_slot *slot; 181 int i, ret; 182 183 for (i = 0; i < chip->num_slots; i++) { 184 slot = chip->slots[i]; 185 if (!slot) 186 continue; 187 188 ret = sdhci_runtime_resume_host(slot->host, 0); 189 if (ret) 190 return ret; 191 } 192 193 return 0; 194 } 195 196 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip) 197 { 198 int ret; 199 200 ret = cqhci_suspend(chip->slots[0]->host->mmc); 201 if (ret) 202 return ret; 203 204 return sdhci_pci_runtime_suspend_host(chip); 205 } 206 207 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip) 208 { 209 int ret; 210 211 ret = sdhci_pci_runtime_resume_host(chip); 212 if (ret) 213 return ret; 214 215 return cqhci_resume(chip->slots[0]->host->mmc); 216 } 217 #endif 218 219 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask) 220 { 221 int cmd_error = 0; 222 int data_error = 0; 223 224 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 225 return intmask; 226 227 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 228 229 return 0; 230 } 231 232 static void sdhci_pci_dumpregs(struct mmc_host *mmc) 233 { 234 sdhci_dumpregs(mmc_priv(mmc)); 235 } 236 237 static void sdhci_cqhci_reset(struct sdhci_host *host, u8 mask) 238 { 239 if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) && 240 host->mmc->cqe_private) 241 cqhci_deactivate(host->mmc); 242 sdhci_reset(host, mask); 243 } 244 245 /*****************************************************************************\ 246 * * 247 * Hardware specific quirk handling * 248 * * 249 \*****************************************************************************/ 250 251 static int ricoh_probe(struct sdhci_pci_chip *chip) 252 { 253 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 254 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 255 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 256 return 0; 257 } 258 259 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 260 { 261 slot->host->caps = 262 FIELD_PREP(SDHCI_TIMEOUT_CLK_MASK, 0x21) | 263 FIELD_PREP(SDHCI_CLOCK_BASE_MASK, 0x21) | 264 SDHCI_TIMEOUT_CLK_UNIT | 265 SDHCI_CAN_VDD_330 | 266 SDHCI_CAN_DO_HISPD | 267 SDHCI_CAN_DO_SDMA; 268 return 0; 269 } 270 271 #ifdef CONFIG_PM_SLEEP 272 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 273 { 274 /* Apply a delay to allow controller to settle */ 275 /* Otherwise it becomes confused if card state changed 276 during suspend */ 277 msleep(500); 278 return sdhci_pci_resume_host(chip); 279 } 280 #endif 281 282 static const struct sdhci_pci_fixes sdhci_ricoh = { 283 .probe = ricoh_probe, 284 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 285 SDHCI_QUIRK_FORCE_DMA | 286 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 287 }; 288 289 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 290 .probe_slot = ricoh_mmc_probe_slot, 291 #ifdef CONFIG_PM_SLEEP 292 .resume = ricoh_mmc_resume, 293 #endif 294 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 295 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 296 SDHCI_QUIRK_NO_CARD_NO_RESET | 297 SDHCI_QUIRK_MISSING_CAPS 298 }; 299 300 static const struct sdhci_pci_fixes sdhci_ene_712 = { 301 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 302 SDHCI_QUIRK_BROKEN_DMA, 303 }; 304 305 static const struct sdhci_pci_fixes sdhci_ene_714 = { 306 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 307 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 308 SDHCI_QUIRK_BROKEN_DMA, 309 }; 310 311 static const struct sdhci_pci_fixes sdhci_cafe = { 312 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 313 SDHCI_QUIRK_NO_BUSY_IRQ | 314 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 315 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 316 }; 317 318 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 319 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 320 }; 321 322 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 323 { 324 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 325 return 0; 326 } 327 328 /* 329 * ADMA operation is disabled for Moorestown platform due to 330 * hardware bugs. 331 */ 332 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 333 { 334 /* 335 * slots number is fixed here for MRST as SDIO3/5 are never used and 336 * have hardware bugs. 337 */ 338 chip->num_slots = 1; 339 return 0; 340 } 341 342 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 343 { 344 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 345 return 0; 346 } 347 348 #ifdef CONFIG_PM 349 350 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 351 { 352 struct sdhci_pci_slot *slot = dev_id; 353 struct sdhci_host *host = slot->host; 354 355 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 356 return IRQ_HANDLED; 357 } 358 359 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 360 { 361 int err, irq, gpio = slot->cd_gpio; 362 363 slot->cd_gpio = -EINVAL; 364 slot->cd_irq = -EINVAL; 365 366 if (!gpio_is_valid(gpio)) 367 return; 368 369 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 370 if (err < 0) 371 goto out; 372 373 err = gpio_direction_input(gpio); 374 if (err < 0) 375 goto out_free; 376 377 irq = gpio_to_irq(gpio); 378 if (irq < 0) 379 goto out_free; 380 381 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 382 IRQF_TRIGGER_FALLING, "sd_cd", slot); 383 if (err) 384 goto out_free; 385 386 slot->cd_gpio = gpio; 387 slot->cd_irq = irq; 388 389 return; 390 391 out_free: 392 devm_gpio_free(&slot->chip->pdev->dev, gpio); 393 out: 394 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 395 } 396 397 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 398 { 399 if (slot->cd_irq >= 0) 400 free_irq(slot->cd_irq, slot); 401 } 402 403 #else 404 405 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 406 { 407 } 408 409 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 410 { 411 } 412 413 #endif 414 415 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 416 { 417 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 418 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC; 419 return 0; 420 } 421 422 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 423 { 424 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 425 return 0; 426 } 427 428 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 429 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 430 .probe_slot = mrst_hc_probe_slot, 431 }; 432 433 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 434 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 435 .probe = mrst_hc_probe, 436 }; 437 438 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 439 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 440 .allow_runtime_pm = true, 441 .own_cd_for_runtime_pm = true, 442 }; 443 444 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 445 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 446 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 447 .allow_runtime_pm = true, 448 .probe_slot = mfd_sdio_probe_slot, 449 }; 450 451 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 452 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 453 .allow_runtime_pm = true, 454 .probe_slot = mfd_emmc_probe_slot, 455 }; 456 457 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 458 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 459 .probe_slot = pch_hc_probe_slot, 460 }; 461 462 #ifdef CONFIG_X86 463 464 #define BYT_IOSF_SCCEP 0x63 465 #define BYT_IOSF_OCP_NETCTRL0 0x1078 466 #define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8) 467 468 static void byt_ocp_setting(struct pci_dev *pdev) 469 { 470 u32 val = 0; 471 472 if (pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC && 473 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SDIO && 474 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SD && 475 pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC2) 476 return; 477 478 if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0, 479 &val)) { 480 dev_err(&pdev->dev, "%s read error\n", __func__); 481 return; 482 } 483 484 if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE)) 485 return; 486 487 val &= ~BYT_IOSF_OCP_TIMEOUT_BASE; 488 489 if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0, 490 val)) { 491 dev_err(&pdev->dev, "%s write error\n", __func__); 492 return; 493 } 494 495 dev_dbg(&pdev->dev, "%s completed\n", __func__); 496 } 497 498 #else 499 500 static inline void byt_ocp_setting(struct pci_dev *pdev) 501 { 502 } 503 504 #endif 505 506 enum { 507 INTEL_DSM_FNS = 0, 508 INTEL_DSM_V18_SWITCH = 3, 509 INTEL_DSM_V33_SWITCH = 4, 510 INTEL_DSM_DRV_STRENGTH = 9, 511 INTEL_DSM_D3_RETUNE = 10, 512 }; 513 514 struct intel_host { 515 u32 dsm_fns; 516 int drv_strength; 517 bool d3_retune; 518 bool rpm_retune_ok; 519 bool needs_pwr_off; 520 u32 glk_rx_ctrl1; 521 u32 glk_tun_val; 522 u32 active_ltr; 523 u32 idle_ltr; 524 }; 525 526 static const guid_t intel_dsm_guid = 527 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F, 528 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61); 529 530 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 531 unsigned int fn, u32 *result) 532 { 533 union acpi_object *obj; 534 int err = 0; 535 size_t len; 536 537 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL); 538 if (!obj) 539 return -EOPNOTSUPP; 540 541 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { 542 err = -EINVAL; 543 goto out; 544 } 545 546 len = min_t(size_t, obj->buffer.length, 4); 547 548 *result = 0; 549 memcpy(result, obj->buffer.pointer, len); 550 out: 551 ACPI_FREE(obj); 552 553 return err; 554 } 555 556 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 557 unsigned int fn, u32 *result) 558 { 559 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 560 return -EOPNOTSUPP; 561 562 return __intel_dsm(intel_host, dev, fn, result); 563 } 564 565 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 566 struct mmc_host *mmc) 567 { 568 int err; 569 u32 val; 570 571 intel_host->d3_retune = true; 572 573 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 574 if (err) { 575 pr_debug("%s: DSM not supported, error %d\n", 576 mmc_hostname(mmc), err); 577 return; 578 } 579 580 pr_debug("%s: DSM function mask %#x\n", 581 mmc_hostname(mmc), intel_host->dsm_fns); 582 583 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 584 intel_host->drv_strength = err ? 0 : val; 585 586 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 587 intel_host->d3_retune = err ? true : !!val; 588 } 589 590 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 591 { 592 u8 reg; 593 594 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 595 reg |= 0x10; 596 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 597 /* For eMMC, minimum is 1us but give it 9us for good measure */ 598 udelay(9); 599 reg &= ~0x10; 600 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 601 /* For eMMC, minimum is 200us but give it 300us for good measure */ 602 usleep_range(300, 1000); 603 } 604 605 static int intel_select_drive_strength(struct mmc_card *card, 606 unsigned int max_dtr, int host_drv, 607 int card_drv, int *drv_type) 608 { 609 struct sdhci_host *host = mmc_priv(card->host); 610 struct sdhci_pci_slot *slot = sdhci_priv(host); 611 struct intel_host *intel_host = sdhci_pci_priv(slot); 612 613 if (!(mmc_driver_type_mask(intel_host->drv_strength) & card_drv)) 614 return 0; 615 616 return intel_host->drv_strength; 617 } 618 619 static int bxt_get_cd(struct mmc_host *mmc) 620 { 621 int gpio_cd = mmc_gpio_get_cd(mmc); 622 struct sdhci_host *host = mmc_priv(mmc); 623 unsigned long flags; 624 int ret = 0; 625 626 if (!gpio_cd) 627 return 0; 628 629 spin_lock_irqsave(&host->lock, flags); 630 631 if (host->flags & SDHCI_DEVICE_DEAD) 632 goto out; 633 634 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 635 out: 636 spin_unlock_irqrestore(&host->lock, flags); 637 638 return ret; 639 } 640 641 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 642 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 643 644 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 645 unsigned short vdd) 646 { 647 struct sdhci_pci_slot *slot = sdhci_priv(host); 648 struct intel_host *intel_host = sdhci_pci_priv(slot); 649 int cntr; 650 u8 reg; 651 652 /* 653 * Bus power may control card power, but a full reset still may not 654 * reset the power, whereas a direct write to SDHCI_POWER_CONTROL can. 655 * That might be needed to initialize correctly, if the card was left 656 * powered on previously. 657 */ 658 if (intel_host->needs_pwr_off) { 659 intel_host->needs_pwr_off = false; 660 if (mode != MMC_POWER_OFF) { 661 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 662 usleep_range(10000, 12500); 663 } 664 } 665 666 sdhci_set_power(host, mode, vdd); 667 668 if (mode == MMC_POWER_OFF) 669 return; 670 671 /* 672 * Bus power might not enable after D3 -> D0 transition due to the 673 * present state not yet having propagated. Retry for up to 2ms. 674 */ 675 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 676 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 677 if (reg & SDHCI_POWER_ON) 678 break; 679 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 680 reg |= SDHCI_POWER_ON; 681 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 682 } 683 } 684 685 static void sdhci_intel_set_uhs_signaling(struct sdhci_host *host, 686 unsigned int timing) 687 { 688 /* Set UHS timing to SDR25 for High Speed mode */ 689 if (timing == MMC_TIMING_MMC_HS || timing == MMC_TIMING_SD_HS) 690 timing = MMC_TIMING_UHS_SDR25; 691 sdhci_set_uhs_signaling(host, timing); 692 } 693 694 #define INTEL_HS400_ES_REG 0x78 695 #define INTEL_HS400_ES_BIT BIT(0) 696 697 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc, 698 struct mmc_ios *ios) 699 { 700 struct sdhci_host *host = mmc_priv(mmc); 701 u32 val; 702 703 val = sdhci_readl(host, INTEL_HS400_ES_REG); 704 if (ios->enhanced_strobe) 705 val |= INTEL_HS400_ES_BIT; 706 else 707 val &= ~INTEL_HS400_ES_BIT; 708 sdhci_writel(host, val, INTEL_HS400_ES_REG); 709 } 710 711 static int intel_start_signal_voltage_switch(struct mmc_host *mmc, 712 struct mmc_ios *ios) 713 { 714 struct device *dev = mmc_dev(mmc); 715 struct sdhci_host *host = mmc_priv(mmc); 716 struct sdhci_pci_slot *slot = sdhci_priv(host); 717 struct intel_host *intel_host = sdhci_pci_priv(slot); 718 unsigned int fn; 719 u32 result = 0; 720 int err; 721 722 err = sdhci_start_signal_voltage_switch(mmc, ios); 723 if (err) 724 return err; 725 726 switch (ios->signal_voltage) { 727 case MMC_SIGNAL_VOLTAGE_330: 728 fn = INTEL_DSM_V33_SWITCH; 729 break; 730 case MMC_SIGNAL_VOLTAGE_180: 731 fn = INTEL_DSM_V18_SWITCH; 732 break; 733 default: 734 return 0; 735 } 736 737 err = intel_dsm(intel_host, dev, fn, &result); 738 pr_debug("%s: %s DSM fn %u error %d result %u\n", 739 mmc_hostname(mmc), __func__, fn, err, result); 740 741 return 0; 742 } 743 744 static const struct sdhci_ops sdhci_intel_byt_ops = { 745 .set_clock = sdhci_set_clock, 746 .set_power = sdhci_intel_set_power, 747 .enable_dma = sdhci_pci_enable_dma, 748 .set_bus_width = sdhci_set_bus_width, 749 .reset = sdhci_reset, 750 .set_uhs_signaling = sdhci_intel_set_uhs_signaling, 751 .hw_reset = sdhci_pci_hw_reset, 752 }; 753 754 static const struct sdhci_ops sdhci_intel_glk_ops = { 755 .set_clock = sdhci_set_clock, 756 .set_power = sdhci_intel_set_power, 757 .enable_dma = sdhci_pci_enable_dma, 758 .set_bus_width = sdhci_set_bus_width, 759 .reset = sdhci_cqhci_reset, 760 .set_uhs_signaling = sdhci_intel_set_uhs_signaling, 761 .hw_reset = sdhci_pci_hw_reset, 762 .irq = sdhci_cqhci_irq, 763 }; 764 765 static void byt_read_dsm(struct sdhci_pci_slot *slot) 766 { 767 struct intel_host *intel_host = sdhci_pci_priv(slot); 768 struct device *dev = &slot->chip->pdev->dev; 769 struct mmc_host *mmc = slot->host->mmc; 770 771 intel_dsm_init(intel_host, dev, mmc); 772 slot->chip->rpm_retune = intel_host->d3_retune; 773 } 774 775 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode) 776 { 777 int err = sdhci_execute_tuning(mmc, opcode); 778 struct sdhci_host *host = mmc_priv(mmc); 779 780 if (err) 781 return err; 782 783 /* 784 * Tuning can leave the IP in an active state (Buffer Read Enable bit 785 * set) which prevents the entry to low power states (i.e. S0i3). Data 786 * reset will clear it. 787 */ 788 sdhci_reset(host, SDHCI_RESET_DATA); 789 790 return 0; 791 } 792 793 #define INTEL_ACTIVELTR 0x804 794 #define INTEL_IDLELTR 0x808 795 796 #define INTEL_LTR_REQ BIT(15) 797 #define INTEL_LTR_SCALE_MASK GENMASK(11, 10) 798 #define INTEL_LTR_SCALE_1US (2 << 10) 799 #define INTEL_LTR_SCALE_32US (3 << 10) 800 #define INTEL_LTR_VALUE_MASK GENMASK(9, 0) 801 802 static void intel_cache_ltr(struct sdhci_pci_slot *slot) 803 { 804 struct intel_host *intel_host = sdhci_pci_priv(slot); 805 struct sdhci_host *host = slot->host; 806 807 intel_host->active_ltr = readl(host->ioaddr + INTEL_ACTIVELTR); 808 intel_host->idle_ltr = readl(host->ioaddr + INTEL_IDLELTR); 809 } 810 811 static void intel_ltr_set(struct device *dev, s32 val) 812 { 813 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 814 struct sdhci_pci_slot *slot = chip->slots[0]; 815 struct intel_host *intel_host = sdhci_pci_priv(slot); 816 struct sdhci_host *host = slot->host; 817 u32 ltr; 818 819 pm_runtime_get_sync(dev); 820 821 /* 822 * Program latency tolerance (LTR) accordingly what has been asked 823 * by the PM QoS layer or disable it in case we were passed 824 * negative value or PM_QOS_LATENCY_ANY. 825 */ 826 ltr = readl(host->ioaddr + INTEL_ACTIVELTR); 827 828 if (val == PM_QOS_LATENCY_ANY || val < 0) { 829 ltr &= ~INTEL_LTR_REQ; 830 } else { 831 ltr |= INTEL_LTR_REQ; 832 ltr &= ~INTEL_LTR_SCALE_MASK; 833 ltr &= ~INTEL_LTR_VALUE_MASK; 834 835 if (val > INTEL_LTR_VALUE_MASK) { 836 val >>= 5; 837 if (val > INTEL_LTR_VALUE_MASK) 838 val = INTEL_LTR_VALUE_MASK; 839 ltr |= INTEL_LTR_SCALE_32US | val; 840 } else { 841 ltr |= INTEL_LTR_SCALE_1US | val; 842 } 843 } 844 845 if (ltr == intel_host->active_ltr) 846 goto out; 847 848 writel(ltr, host->ioaddr + INTEL_ACTIVELTR); 849 writel(ltr, host->ioaddr + INTEL_IDLELTR); 850 851 /* Cache the values into lpss structure */ 852 intel_cache_ltr(slot); 853 out: 854 pm_runtime_put_autosuspend(dev); 855 } 856 857 static bool intel_use_ltr(struct sdhci_pci_chip *chip) 858 { 859 switch (chip->pdev->device) { 860 case PCI_DEVICE_ID_INTEL_BYT_EMMC: 861 case PCI_DEVICE_ID_INTEL_BYT_EMMC2: 862 case PCI_DEVICE_ID_INTEL_BYT_SDIO: 863 case PCI_DEVICE_ID_INTEL_BYT_SD: 864 case PCI_DEVICE_ID_INTEL_BSW_EMMC: 865 case PCI_DEVICE_ID_INTEL_BSW_SDIO: 866 case PCI_DEVICE_ID_INTEL_BSW_SD: 867 return false; 868 default: 869 return true; 870 } 871 } 872 873 static void intel_ltr_expose(struct sdhci_pci_chip *chip) 874 { 875 struct device *dev = &chip->pdev->dev; 876 877 if (!intel_use_ltr(chip)) 878 return; 879 880 dev->power.set_latency_tolerance = intel_ltr_set; 881 dev_pm_qos_expose_latency_tolerance(dev); 882 } 883 884 static void intel_ltr_hide(struct sdhci_pci_chip *chip) 885 { 886 struct device *dev = &chip->pdev->dev; 887 888 if (!intel_use_ltr(chip)) 889 return; 890 891 dev_pm_qos_hide_latency_tolerance(dev); 892 dev->power.set_latency_tolerance = NULL; 893 } 894 895 static void byt_probe_slot(struct sdhci_pci_slot *slot) 896 { 897 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 898 struct device *dev = &slot->chip->pdev->dev; 899 struct mmc_host *mmc = slot->host->mmc; 900 901 byt_read_dsm(slot); 902 903 byt_ocp_setting(slot->chip->pdev); 904 905 ops->execute_tuning = intel_execute_tuning; 906 ops->start_signal_voltage_switch = intel_start_signal_voltage_switch; 907 908 device_property_read_u32(dev, "max-frequency", &mmc->f_max); 909 910 if (!mmc->slotno) { 911 slot->chip->slots[mmc->slotno] = slot; 912 intel_ltr_expose(slot->chip); 913 } 914 } 915 916 static void byt_add_debugfs(struct sdhci_pci_slot *slot) 917 { 918 struct intel_host *intel_host = sdhci_pci_priv(slot); 919 struct mmc_host *mmc = slot->host->mmc; 920 struct dentry *dir = mmc->debugfs_root; 921 922 if (!intel_use_ltr(slot->chip)) 923 return; 924 925 debugfs_create_x32("active_ltr", 0444, dir, &intel_host->active_ltr); 926 debugfs_create_x32("idle_ltr", 0444, dir, &intel_host->idle_ltr); 927 928 intel_cache_ltr(slot); 929 } 930 931 static int byt_add_host(struct sdhci_pci_slot *slot) 932 { 933 int ret = sdhci_add_host(slot->host); 934 935 if (!ret) 936 byt_add_debugfs(slot); 937 return ret; 938 } 939 940 static void byt_remove_slot(struct sdhci_pci_slot *slot, int dead) 941 { 942 struct mmc_host *mmc = slot->host->mmc; 943 944 if (!mmc->slotno) 945 intel_ltr_hide(slot->chip); 946 } 947 948 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 949 { 950 byt_probe_slot(slot); 951 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 952 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 953 MMC_CAP_CMD_DURING_TFR | 954 MMC_CAP_WAIT_WHILE_BUSY; 955 slot->hw_reset = sdhci_pci_int_hw_reset; 956 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 957 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 958 slot->host->mmc_host_ops.select_drive_strength = 959 intel_select_drive_strength; 960 return 0; 961 } 962 963 static bool glk_broken_cqhci(struct sdhci_pci_slot *slot) 964 { 965 return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 966 (dmi_match(DMI_BIOS_VENDOR, "LENOVO") || 967 dmi_match(DMI_SYS_VENDOR, "IRBIS")); 968 } 969 970 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot) 971 { 972 int ret = byt_emmc_probe_slot(slot); 973 974 if (!glk_broken_cqhci(slot)) 975 slot->host->mmc->caps2 |= MMC_CAP2_CQE; 976 977 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) { 978 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES; 979 slot->host->mmc_host_ops.hs400_enhanced_strobe = 980 intel_hs400_enhanced_strobe; 981 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; 982 } 983 984 return ret; 985 } 986 987 static const struct cqhci_host_ops glk_cqhci_ops = { 988 .enable = sdhci_cqe_enable, 989 .disable = sdhci_cqe_disable, 990 .dumpregs = sdhci_pci_dumpregs, 991 }; 992 993 static int glk_emmc_add_host(struct sdhci_pci_slot *slot) 994 { 995 struct device *dev = &slot->chip->pdev->dev; 996 struct sdhci_host *host = slot->host; 997 struct cqhci_host *cq_host; 998 bool dma64; 999 int ret; 1000 1001 ret = sdhci_setup_host(host); 1002 if (ret) 1003 return ret; 1004 1005 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); 1006 if (!cq_host) { 1007 ret = -ENOMEM; 1008 goto cleanup; 1009 } 1010 1011 cq_host->mmio = host->ioaddr + 0x200; 1012 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 1013 cq_host->ops = &glk_cqhci_ops; 1014 1015 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 1016 if (dma64) 1017 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 1018 1019 ret = cqhci_init(cq_host, host->mmc, dma64); 1020 if (ret) 1021 goto cleanup; 1022 1023 ret = __sdhci_add_host(host); 1024 if (ret) 1025 goto cleanup; 1026 1027 byt_add_debugfs(slot); 1028 1029 return 0; 1030 1031 cleanup: 1032 sdhci_cleanup_host(host); 1033 return ret; 1034 } 1035 1036 #ifdef CONFIG_PM 1037 #define GLK_RX_CTRL1 0x834 1038 #define GLK_TUN_VAL 0x840 1039 #define GLK_PATH_PLL GENMASK(13, 8) 1040 #define GLK_DLY GENMASK(6, 0) 1041 /* Workaround firmware failing to restore the tuning value */ 1042 static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp) 1043 { 1044 struct sdhci_pci_slot *slot = chip->slots[0]; 1045 struct intel_host *intel_host = sdhci_pci_priv(slot); 1046 struct sdhci_host *host = slot->host; 1047 u32 glk_rx_ctrl1; 1048 u32 glk_tun_val; 1049 u32 dly; 1050 1051 if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc)) 1052 return; 1053 1054 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1); 1055 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL); 1056 1057 if (susp) { 1058 intel_host->glk_rx_ctrl1 = glk_rx_ctrl1; 1059 intel_host->glk_tun_val = glk_tun_val; 1060 return; 1061 } 1062 1063 if (!intel_host->glk_tun_val) 1064 return; 1065 1066 if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) { 1067 intel_host->rpm_retune_ok = true; 1068 return; 1069 } 1070 1071 dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) + 1072 (intel_host->glk_tun_val << 1)); 1073 if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1)) 1074 return; 1075 1076 glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly; 1077 sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1); 1078 1079 intel_host->rpm_retune_ok = true; 1080 chip->rpm_retune = true; 1081 mmc_retune_needed(host->mmc); 1082 pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc)); 1083 } 1084 1085 static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp) 1086 { 1087 if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 1088 !chip->rpm_retune) 1089 glk_rpm_retune_wa(chip, susp); 1090 } 1091 1092 static int glk_runtime_suspend(struct sdhci_pci_chip *chip) 1093 { 1094 glk_rpm_retune_chk(chip, true); 1095 1096 return sdhci_cqhci_runtime_suspend(chip); 1097 } 1098 1099 static int glk_runtime_resume(struct sdhci_pci_chip *chip) 1100 { 1101 glk_rpm_retune_chk(chip, false); 1102 1103 return sdhci_cqhci_runtime_resume(chip); 1104 } 1105 #endif 1106 1107 #ifdef CONFIG_ACPI 1108 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 1109 { 1110 acpi_status status; 1111 unsigned long long max_freq; 1112 1113 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 1114 "MXFQ", NULL, &max_freq); 1115 if (ACPI_FAILURE(status)) { 1116 dev_err(&slot->chip->pdev->dev, 1117 "MXFQ not found in acpi table\n"); 1118 return -EINVAL; 1119 } 1120 1121 slot->host->mmc->f_max = max_freq * 1000000; 1122 1123 return 0; 1124 } 1125 #else 1126 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 1127 { 1128 return 0; 1129 } 1130 #endif 1131 1132 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 1133 { 1134 int err; 1135 1136 byt_probe_slot(slot); 1137 1138 err = ni_set_max_freq(slot); 1139 if (err) 1140 return err; 1141 1142 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 1143 MMC_CAP_WAIT_WHILE_BUSY; 1144 return 0; 1145 } 1146 1147 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 1148 { 1149 byt_probe_slot(slot); 1150 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 1151 MMC_CAP_WAIT_WHILE_BUSY; 1152 return 0; 1153 } 1154 1155 static void byt_needs_pwr_off(struct sdhci_pci_slot *slot) 1156 { 1157 struct intel_host *intel_host = sdhci_pci_priv(slot); 1158 u8 reg = sdhci_readb(slot->host, SDHCI_POWER_CONTROL); 1159 1160 intel_host->needs_pwr_off = reg & SDHCI_POWER_ON; 1161 } 1162 1163 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 1164 { 1165 byt_probe_slot(slot); 1166 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | 1167 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE; 1168 slot->cd_idx = 0; 1169 slot->cd_override_level = true; 1170 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 1171 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 1172 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 1173 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) 1174 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 1175 1176 if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI && 1177 slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3) 1178 slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V; 1179 1180 byt_needs_pwr_off(slot); 1181 1182 return 0; 1183 } 1184 1185 #ifdef CONFIG_PM_SLEEP 1186 1187 static int byt_resume(struct sdhci_pci_chip *chip) 1188 { 1189 byt_ocp_setting(chip->pdev); 1190 1191 return sdhci_pci_resume_host(chip); 1192 } 1193 1194 #endif 1195 1196 #ifdef CONFIG_PM 1197 1198 static int byt_runtime_resume(struct sdhci_pci_chip *chip) 1199 { 1200 byt_ocp_setting(chip->pdev); 1201 1202 return sdhci_pci_runtime_resume_host(chip); 1203 } 1204 1205 #endif 1206 1207 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 1208 #ifdef CONFIG_PM_SLEEP 1209 .resume = byt_resume, 1210 #endif 1211 #ifdef CONFIG_PM 1212 .runtime_resume = byt_runtime_resume, 1213 #endif 1214 .allow_runtime_pm = true, 1215 .probe_slot = byt_emmc_probe_slot, 1216 .add_host = byt_add_host, 1217 .remove_slot = byt_remove_slot, 1218 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1219 SDHCI_QUIRK_NO_LED, 1220 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1221 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1222 SDHCI_QUIRK2_STOP_WITH_TC, 1223 .ops = &sdhci_intel_byt_ops, 1224 .priv_size = sizeof(struct intel_host), 1225 }; 1226 1227 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = { 1228 .allow_runtime_pm = true, 1229 .probe_slot = glk_emmc_probe_slot, 1230 .add_host = glk_emmc_add_host, 1231 .remove_slot = byt_remove_slot, 1232 #ifdef CONFIG_PM_SLEEP 1233 .suspend = sdhci_cqhci_suspend, 1234 .resume = sdhci_cqhci_resume, 1235 #endif 1236 #ifdef CONFIG_PM 1237 .runtime_suspend = glk_runtime_suspend, 1238 .runtime_resume = glk_runtime_resume, 1239 #endif 1240 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1241 SDHCI_QUIRK_NO_LED, 1242 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1243 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1244 SDHCI_QUIRK2_STOP_WITH_TC, 1245 .ops = &sdhci_intel_glk_ops, 1246 .priv_size = sizeof(struct intel_host), 1247 }; 1248 1249 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 1250 #ifdef CONFIG_PM_SLEEP 1251 .resume = byt_resume, 1252 #endif 1253 #ifdef CONFIG_PM 1254 .runtime_resume = byt_runtime_resume, 1255 #endif 1256 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1257 SDHCI_QUIRK_NO_LED, 1258 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1259 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1260 .allow_runtime_pm = true, 1261 .probe_slot = ni_byt_sdio_probe_slot, 1262 .add_host = byt_add_host, 1263 .remove_slot = byt_remove_slot, 1264 .ops = &sdhci_intel_byt_ops, 1265 .priv_size = sizeof(struct intel_host), 1266 }; 1267 1268 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 1269 #ifdef CONFIG_PM_SLEEP 1270 .resume = byt_resume, 1271 #endif 1272 #ifdef CONFIG_PM 1273 .runtime_resume = byt_runtime_resume, 1274 #endif 1275 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1276 SDHCI_QUIRK_NO_LED, 1277 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1278 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1279 .allow_runtime_pm = true, 1280 .probe_slot = byt_sdio_probe_slot, 1281 .add_host = byt_add_host, 1282 .remove_slot = byt_remove_slot, 1283 .ops = &sdhci_intel_byt_ops, 1284 .priv_size = sizeof(struct intel_host), 1285 }; 1286 1287 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 1288 #ifdef CONFIG_PM_SLEEP 1289 .resume = byt_resume, 1290 #endif 1291 #ifdef CONFIG_PM 1292 .runtime_resume = byt_runtime_resume, 1293 #endif 1294 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1295 SDHCI_QUIRK_NO_LED, 1296 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 1297 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1298 SDHCI_QUIRK2_STOP_WITH_TC, 1299 .allow_runtime_pm = true, 1300 .own_cd_for_runtime_pm = true, 1301 .probe_slot = byt_sd_probe_slot, 1302 .add_host = byt_add_host, 1303 .remove_slot = byt_remove_slot, 1304 .ops = &sdhci_intel_byt_ops, 1305 .priv_size = sizeof(struct intel_host), 1306 }; 1307 1308 /* Define Host controllers for Intel Merrifield platform */ 1309 #define INTEL_MRFLD_EMMC_0 0 1310 #define INTEL_MRFLD_EMMC_1 1 1311 #define INTEL_MRFLD_SD 2 1312 #define INTEL_MRFLD_SDIO 3 1313 1314 #ifdef CONFIG_ACPI 1315 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) 1316 { 1317 struct acpi_device *device, *child; 1318 1319 device = ACPI_COMPANION(&slot->chip->pdev->dev); 1320 if (!device) 1321 return; 1322 1323 acpi_device_fix_up_power(device); 1324 list_for_each_entry(child, &device->children, node) 1325 if (child->status.present && child->status.enabled) 1326 acpi_device_fix_up_power(child); 1327 } 1328 #else 1329 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {} 1330 #endif 1331 1332 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 1333 { 1334 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 1335 1336 switch (func) { 1337 case INTEL_MRFLD_EMMC_0: 1338 case INTEL_MRFLD_EMMC_1: 1339 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1340 MMC_CAP_8_BIT_DATA | 1341 MMC_CAP_1_8V_DDR; 1342 break; 1343 case INTEL_MRFLD_SD: 1344 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1345 break; 1346 case INTEL_MRFLD_SDIO: 1347 /* Advertise 2.0v for compatibility with the SDIO card's OCR */ 1348 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195; 1349 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1350 MMC_CAP_POWER_OFF_CARD; 1351 break; 1352 default: 1353 return -ENODEV; 1354 } 1355 1356 intel_mrfld_mmc_fix_up_power_slot(slot); 1357 return 0; 1358 } 1359 1360 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 1361 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1362 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 1363 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1364 .allow_runtime_pm = true, 1365 .probe_slot = intel_mrfld_mmc_probe_slot, 1366 }; 1367 1368 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 1369 { 1370 u8 scratch; 1371 int ret; 1372 1373 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 1374 if (ret) 1375 return ret; 1376 1377 /* 1378 * Turn PMOS on [bit 0], set over current detection to 2.4 V 1379 * [bit 1:2] and enable over current debouncing [bit 6]. 1380 */ 1381 if (on) 1382 scratch |= 0x47; 1383 else 1384 scratch &= ~0x47; 1385 1386 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 1387 } 1388 1389 static int jmicron_probe(struct sdhci_pci_chip *chip) 1390 { 1391 int ret; 1392 u16 mmcdev = 0; 1393 1394 if (chip->pdev->revision == 0) { 1395 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 1396 SDHCI_QUIRK_32BIT_DMA_SIZE | 1397 SDHCI_QUIRK_32BIT_ADMA_SIZE | 1398 SDHCI_QUIRK_RESET_AFTER_REQUEST | 1399 SDHCI_QUIRK_BROKEN_SMALL_PIO; 1400 } 1401 1402 /* 1403 * JMicron chips can have two interfaces to the same hardware 1404 * in order to work around limitations in Microsoft's driver. 1405 * We need to make sure we only bind to one of them. 1406 * 1407 * This code assumes two things: 1408 * 1409 * 1. The PCI code adds subfunctions in order. 1410 * 1411 * 2. The MMC interface has a lower subfunction number 1412 * than the SD interface. 1413 */ 1414 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 1415 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 1416 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 1417 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 1418 1419 if (mmcdev) { 1420 struct pci_dev *sd_dev; 1421 1422 sd_dev = NULL; 1423 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 1424 mmcdev, sd_dev)) != NULL) { 1425 if ((PCI_SLOT(chip->pdev->devfn) == 1426 PCI_SLOT(sd_dev->devfn)) && 1427 (chip->pdev->bus == sd_dev->bus)) 1428 break; 1429 } 1430 1431 if (sd_dev) { 1432 pci_dev_put(sd_dev); 1433 dev_info(&chip->pdev->dev, "Refusing to bind to " 1434 "secondary interface.\n"); 1435 return -ENODEV; 1436 } 1437 } 1438 1439 /* 1440 * JMicron chips need a bit of a nudge to enable the power 1441 * output pins. 1442 */ 1443 ret = jmicron_pmos(chip, 1); 1444 if (ret) { 1445 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1446 return ret; 1447 } 1448 1449 /* quirk for unsable RO-detection on JM388 chips */ 1450 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 1451 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1452 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 1453 1454 return 0; 1455 } 1456 1457 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 1458 { 1459 u8 scratch; 1460 1461 scratch = readb(host->ioaddr + 0xC0); 1462 1463 if (on) 1464 scratch |= 0x01; 1465 else 1466 scratch &= ~0x01; 1467 1468 writeb(scratch, host->ioaddr + 0xC0); 1469 } 1470 1471 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 1472 { 1473 if (slot->chip->pdev->revision == 0) { 1474 u16 version; 1475 1476 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 1477 version = (version & SDHCI_VENDOR_VER_MASK) >> 1478 SDHCI_VENDOR_VER_SHIFT; 1479 1480 /* 1481 * Older versions of the chip have lots of nasty glitches 1482 * in the ADMA engine. It's best just to avoid it 1483 * completely. 1484 */ 1485 if (version < 0xAC) 1486 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 1487 } 1488 1489 /* JM388 MMC doesn't support 1.8V while SD supports it */ 1490 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1491 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 1492 MMC_VDD_29_30 | MMC_VDD_30_31 | 1493 MMC_VDD_165_195; /* allow 1.8V */ 1494 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 1495 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 1496 } 1497 1498 /* 1499 * The secondary interface requires a bit set to get the 1500 * interrupts. 1501 */ 1502 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1503 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1504 jmicron_enable_mmc(slot->host, 1); 1505 1506 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 1507 1508 return 0; 1509 } 1510 1511 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 1512 { 1513 if (dead) 1514 return; 1515 1516 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1517 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1518 jmicron_enable_mmc(slot->host, 0); 1519 } 1520 1521 #ifdef CONFIG_PM_SLEEP 1522 static int jmicron_suspend(struct sdhci_pci_chip *chip) 1523 { 1524 int i, ret; 1525 1526 ret = sdhci_pci_suspend_host(chip); 1527 if (ret) 1528 return ret; 1529 1530 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1531 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1532 for (i = 0; i < chip->num_slots; i++) 1533 jmicron_enable_mmc(chip->slots[i]->host, 0); 1534 } 1535 1536 return 0; 1537 } 1538 1539 static int jmicron_resume(struct sdhci_pci_chip *chip) 1540 { 1541 int ret, i; 1542 1543 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1544 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1545 for (i = 0; i < chip->num_slots; i++) 1546 jmicron_enable_mmc(chip->slots[i]->host, 1); 1547 } 1548 1549 ret = jmicron_pmos(chip, 1); 1550 if (ret) { 1551 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1552 return ret; 1553 } 1554 1555 return sdhci_pci_resume_host(chip); 1556 } 1557 #endif 1558 1559 static const struct sdhci_pci_fixes sdhci_jmicron = { 1560 .probe = jmicron_probe, 1561 1562 .probe_slot = jmicron_probe_slot, 1563 .remove_slot = jmicron_remove_slot, 1564 1565 #ifdef CONFIG_PM_SLEEP 1566 .suspend = jmicron_suspend, 1567 .resume = jmicron_resume, 1568 #endif 1569 }; 1570 1571 /* SysKonnect CardBus2SDIO extra registers */ 1572 #define SYSKT_CTRL 0x200 1573 #define SYSKT_RDFIFO_STAT 0x204 1574 #define SYSKT_WRFIFO_STAT 0x208 1575 #define SYSKT_POWER_DATA 0x20c 1576 #define SYSKT_POWER_330 0xef 1577 #define SYSKT_POWER_300 0xf8 1578 #define SYSKT_POWER_184 0xcc 1579 #define SYSKT_POWER_CMD 0x20d 1580 #define SYSKT_POWER_START (1 << 7) 1581 #define SYSKT_POWER_STATUS 0x20e 1582 #define SYSKT_POWER_STATUS_OK (1 << 0) 1583 #define SYSKT_BOARD_REV 0x210 1584 #define SYSKT_CHIP_REV 0x211 1585 #define SYSKT_CONF_DATA 0x212 1586 #define SYSKT_CONF_DATA_1V8 (1 << 2) 1587 #define SYSKT_CONF_DATA_2V5 (1 << 1) 1588 #define SYSKT_CONF_DATA_3V3 (1 << 0) 1589 1590 static int syskt_probe(struct sdhci_pci_chip *chip) 1591 { 1592 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1593 chip->pdev->class &= ~0x0000FF; 1594 chip->pdev->class |= PCI_SDHCI_IFDMA; 1595 } 1596 return 0; 1597 } 1598 1599 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 1600 { 1601 int tm, ps; 1602 1603 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 1604 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 1605 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 1606 "board rev %d.%d, chip rev %d.%d\n", 1607 board_rev >> 4, board_rev & 0xf, 1608 chip_rev >> 4, chip_rev & 0xf); 1609 if (chip_rev >= 0x20) 1610 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 1611 1612 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 1613 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 1614 udelay(50); 1615 tm = 10; /* Wait max 1 ms */ 1616 do { 1617 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 1618 if (ps & SYSKT_POWER_STATUS_OK) 1619 break; 1620 udelay(100); 1621 } while (--tm); 1622 if (!tm) { 1623 dev_err(&slot->chip->pdev->dev, 1624 "power regulator never stabilized"); 1625 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 1626 return -ENODEV; 1627 } 1628 1629 return 0; 1630 } 1631 1632 static const struct sdhci_pci_fixes sdhci_syskt = { 1633 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 1634 .probe = syskt_probe, 1635 .probe_slot = syskt_probe_slot, 1636 }; 1637 1638 static int via_probe(struct sdhci_pci_chip *chip) 1639 { 1640 if (chip->pdev->revision == 0x10) 1641 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 1642 1643 return 0; 1644 } 1645 1646 static const struct sdhci_pci_fixes sdhci_via = { 1647 .probe = via_probe, 1648 }; 1649 1650 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 1651 { 1652 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 1653 return 0; 1654 } 1655 1656 static const struct sdhci_pci_fixes sdhci_rtsx = { 1657 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1658 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 1659 SDHCI_QUIRK2_BROKEN_DDR50, 1660 .probe_slot = rtsx_probe_slot, 1661 }; 1662 1663 /*AMD chipset generation*/ 1664 enum amd_chipset_gen { 1665 AMD_CHIPSET_BEFORE_ML, 1666 AMD_CHIPSET_CZ, 1667 AMD_CHIPSET_NL, 1668 AMD_CHIPSET_UNKNOWN, 1669 }; 1670 1671 /* AMD registers */ 1672 #define AMD_SD_AUTO_PATTERN 0xB8 1673 #define AMD_MSLEEP_DURATION 4 1674 #define AMD_SD_MISC_CONTROL 0xD0 1675 #define AMD_MAX_TUNE_VALUE 0x0B 1676 #define AMD_AUTO_TUNE_SEL 0x10800 1677 #define AMD_FIFO_PTR 0x30 1678 #define AMD_BIT_MASK 0x1F 1679 1680 static void amd_tuning_reset(struct sdhci_host *host) 1681 { 1682 unsigned int val; 1683 1684 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1685 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 1686 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1687 1688 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1689 val &= ~SDHCI_CTRL_EXEC_TUNING; 1690 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1691 } 1692 1693 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 1694 { 1695 unsigned int val; 1696 1697 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 1698 val &= ~AMD_BIT_MASK; 1699 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 1700 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 1701 } 1702 1703 static void amd_enable_manual_tuning(struct pci_dev *pdev) 1704 { 1705 unsigned int val; 1706 1707 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 1708 val |= AMD_FIFO_PTR; 1709 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 1710 } 1711 1712 static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode) 1713 { 1714 struct sdhci_pci_slot *slot = sdhci_priv(host); 1715 struct pci_dev *pdev = slot->chip->pdev; 1716 u8 valid_win = 0; 1717 u8 valid_win_max = 0; 1718 u8 valid_win_end = 0; 1719 u8 ctrl, tune_around; 1720 1721 amd_tuning_reset(host); 1722 1723 for (tune_around = 0; tune_around < 12; tune_around++) { 1724 amd_config_tuning_phase(pdev, tune_around); 1725 1726 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1727 valid_win = 0; 1728 msleep(AMD_MSLEEP_DURATION); 1729 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 1730 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 1731 } else if (++valid_win > valid_win_max) { 1732 valid_win_max = valid_win; 1733 valid_win_end = tune_around; 1734 } 1735 } 1736 1737 if (!valid_win_max) { 1738 dev_err(&pdev->dev, "no tuning point found\n"); 1739 return -EIO; 1740 } 1741 1742 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 1743 1744 amd_enable_manual_tuning(pdev); 1745 1746 host->mmc->retune_period = 0; 1747 1748 return 0; 1749 } 1750 1751 static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode) 1752 { 1753 struct sdhci_host *host = mmc_priv(mmc); 1754 1755 /* AMD requires custom HS200 tuning */ 1756 if (host->timing == MMC_TIMING_MMC_HS200) 1757 return amd_execute_tuning_hs200(host, opcode); 1758 1759 /* Otherwise perform standard SDHCI tuning */ 1760 return sdhci_execute_tuning(mmc, opcode); 1761 } 1762 1763 static int amd_probe_slot(struct sdhci_pci_slot *slot) 1764 { 1765 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 1766 1767 ops->execute_tuning = amd_execute_tuning; 1768 1769 return 0; 1770 } 1771 1772 static int amd_probe(struct sdhci_pci_chip *chip) 1773 { 1774 struct pci_dev *smbus_dev; 1775 enum amd_chipset_gen gen; 1776 1777 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1778 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 1779 if (smbus_dev) { 1780 gen = AMD_CHIPSET_BEFORE_ML; 1781 } else { 1782 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1783 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1784 if (smbus_dev) { 1785 if (smbus_dev->revision < 0x51) 1786 gen = AMD_CHIPSET_CZ; 1787 else 1788 gen = AMD_CHIPSET_NL; 1789 } else { 1790 gen = AMD_CHIPSET_UNKNOWN; 1791 } 1792 } 1793 1794 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1795 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1796 1797 return 0; 1798 } 1799 1800 static u32 sdhci_read_present_state(struct sdhci_host *host) 1801 { 1802 return sdhci_readl(host, SDHCI_PRESENT_STATE); 1803 } 1804 1805 static void amd_sdhci_reset(struct sdhci_host *host, u8 mask) 1806 { 1807 struct sdhci_pci_slot *slot = sdhci_priv(host); 1808 struct pci_dev *pdev = slot->chip->pdev; 1809 u32 present_state; 1810 1811 /* 1812 * SDHC 0x7906 requires a hard reset to clear all internal state. 1813 * Otherwise it can get into a bad state where the DATA lines are always 1814 * read as zeros. 1815 */ 1816 if (pdev->device == 0x7906 && (mask & SDHCI_RESET_ALL)) { 1817 pci_clear_master(pdev); 1818 1819 pci_save_state(pdev); 1820 1821 pci_set_power_state(pdev, PCI_D3cold); 1822 pr_debug("%s: power_state=%u\n", mmc_hostname(host->mmc), 1823 pdev->current_state); 1824 pci_set_power_state(pdev, PCI_D0); 1825 1826 pci_restore_state(pdev); 1827 1828 /* 1829 * SDHCI_RESET_ALL says the card detect logic should not be 1830 * reset, but since we need to reset the entire controller 1831 * we should wait until the card detect logic has stabilized. 1832 * 1833 * This normally takes about 40ms. 1834 */ 1835 readx_poll_timeout( 1836 sdhci_read_present_state, 1837 host, 1838 present_state, 1839 present_state & SDHCI_CD_STABLE, 1840 10000, 1841 100000 1842 ); 1843 } 1844 1845 return sdhci_reset(host, mask); 1846 } 1847 1848 static const struct sdhci_ops amd_sdhci_pci_ops = { 1849 .set_clock = sdhci_set_clock, 1850 .enable_dma = sdhci_pci_enable_dma, 1851 .set_bus_width = sdhci_set_bus_width, 1852 .reset = amd_sdhci_reset, 1853 .set_uhs_signaling = sdhci_set_uhs_signaling, 1854 }; 1855 1856 static const struct sdhci_pci_fixes sdhci_amd = { 1857 .probe = amd_probe, 1858 .ops = &amd_sdhci_pci_ops, 1859 .probe_slot = amd_probe_slot, 1860 }; 1861 1862 static const struct pci_device_id pci_ids[] = { 1863 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh), 1864 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc), 1865 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc), 1866 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc), 1867 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712), 1868 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712), 1869 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714), 1870 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714), 1871 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe), 1872 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron), 1873 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron), 1874 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron), 1875 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron), 1876 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt), 1877 SDHCI_PCI_DEVICE(VIA, 95D0, via), 1878 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx), 1879 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk), 1880 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0), 1881 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2), 1882 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2), 1883 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd), 1884 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio), 1885 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio), 1886 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc), 1887 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc), 1888 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio), 1889 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio), 1890 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc), 1891 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio), 1892 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio), 1893 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd), 1894 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc), 1895 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc), 1896 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio), 1897 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd), 1898 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd), 1899 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio), 1900 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio), 1901 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc), 1902 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc), 1903 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc), 1904 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc), 1905 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio), 1906 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd), 1907 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc), 1908 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc), 1909 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc), 1910 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio), 1911 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd), 1912 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc), 1913 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio), 1914 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd), 1915 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc), 1916 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio), 1917 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd), 1918 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc), 1919 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio), 1920 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd), 1921 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc), 1922 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd), 1923 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd), 1924 SDHCI_PCI_DEVICE(INTEL, ICP_EMMC, intel_glk_emmc), 1925 SDHCI_PCI_DEVICE(INTEL, ICP_SD, intel_byt_sd), 1926 SDHCI_PCI_DEVICE(INTEL, EHL_EMMC, intel_glk_emmc), 1927 SDHCI_PCI_DEVICE(INTEL, EHL_SD, intel_byt_sd), 1928 SDHCI_PCI_DEVICE(INTEL, CML_EMMC, intel_glk_emmc), 1929 SDHCI_PCI_DEVICE(INTEL, CML_SD, intel_byt_sd), 1930 SDHCI_PCI_DEVICE(INTEL, CMLH_SD, intel_byt_sd), 1931 SDHCI_PCI_DEVICE(INTEL, JSL_EMMC, intel_glk_emmc), 1932 SDHCI_PCI_DEVICE(INTEL, JSL_SD, intel_byt_sd), 1933 SDHCI_PCI_DEVICE(INTEL, LKF_EMMC, intel_glk_emmc), 1934 SDHCI_PCI_DEVICE(INTEL, LKF_SD, intel_byt_sd), 1935 SDHCI_PCI_DEVICE(O2, 8120, o2), 1936 SDHCI_PCI_DEVICE(O2, 8220, o2), 1937 SDHCI_PCI_DEVICE(O2, 8221, o2), 1938 SDHCI_PCI_DEVICE(O2, 8320, o2), 1939 SDHCI_PCI_DEVICE(O2, 8321, o2), 1940 SDHCI_PCI_DEVICE(O2, FUJIN2, o2), 1941 SDHCI_PCI_DEVICE(O2, SDS0, o2), 1942 SDHCI_PCI_DEVICE(O2, SDS1, o2), 1943 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2), 1944 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), 1945 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan), 1946 SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps), 1947 SDHCI_PCI_DEVICE(GLI, 9750, gl9750), 1948 SDHCI_PCI_DEVICE(GLI, 9755, gl9755), 1949 SDHCI_PCI_DEVICE(GLI, 9763E, gl9763e), 1950 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), 1951 /* Generic SD host controller */ 1952 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, 1953 { /* end: all zeroes */ }, 1954 }; 1955 1956 MODULE_DEVICE_TABLE(pci, pci_ids); 1957 1958 /*****************************************************************************\ 1959 * * 1960 * SDHCI core callbacks * 1961 * * 1962 \*****************************************************************************/ 1963 1964 int sdhci_pci_enable_dma(struct sdhci_host *host) 1965 { 1966 struct sdhci_pci_slot *slot; 1967 struct pci_dev *pdev; 1968 1969 slot = sdhci_priv(host); 1970 pdev = slot->chip->pdev; 1971 1972 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1973 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1974 (host->flags & SDHCI_USE_SDMA)) { 1975 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1976 "doesn't fully claim to support it.\n"); 1977 } 1978 1979 pci_set_master(pdev); 1980 1981 return 0; 1982 } 1983 1984 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1985 { 1986 struct sdhci_pci_slot *slot = sdhci_priv(host); 1987 int rst_n_gpio = slot->rst_n_gpio; 1988 1989 if (!gpio_is_valid(rst_n_gpio)) 1990 return; 1991 gpio_set_value_cansleep(rst_n_gpio, 0); 1992 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1993 udelay(10); 1994 gpio_set_value_cansleep(rst_n_gpio, 1); 1995 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1996 usleep_range(300, 1000); 1997 } 1998 1999 static void sdhci_pci_hw_reset(struct sdhci_host *host) 2000 { 2001 struct sdhci_pci_slot *slot = sdhci_priv(host); 2002 2003 if (slot->hw_reset) 2004 slot->hw_reset(host); 2005 } 2006 2007 static const struct sdhci_ops sdhci_pci_ops = { 2008 .set_clock = sdhci_set_clock, 2009 .enable_dma = sdhci_pci_enable_dma, 2010 .set_bus_width = sdhci_set_bus_width, 2011 .reset = sdhci_reset, 2012 .set_uhs_signaling = sdhci_set_uhs_signaling, 2013 .hw_reset = sdhci_pci_hw_reset, 2014 }; 2015 2016 /*****************************************************************************\ 2017 * * 2018 * Suspend/resume * 2019 * * 2020 \*****************************************************************************/ 2021 2022 #ifdef CONFIG_PM_SLEEP 2023 static int sdhci_pci_suspend(struct device *dev) 2024 { 2025 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2026 2027 if (!chip) 2028 return 0; 2029 2030 if (chip->fixes && chip->fixes->suspend) 2031 return chip->fixes->suspend(chip); 2032 2033 return sdhci_pci_suspend_host(chip); 2034 } 2035 2036 static int sdhci_pci_resume(struct device *dev) 2037 { 2038 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2039 2040 if (!chip) 2041 return 0; 2042 2043 if (chip->fixes && chip->fixes->resume) 2044 return chip->fixes->resume(chip); 2045 2046 return sdhci_pci_resume_host(chip); 2047 } 2048 #endif 2049 2050 #ifdef CONFIG_PM 2051 static int sdhci_pci_runtime_suspend(struct device *dev) 2052 { 2053 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2054 2055 if (!chip) 2056 return 0; 2057 2058 if (chip->fixes && chip->fixes->runtime_suspend) 2059 return chip->fixes->runtime_suspend(chip); 2060 2061 return sdhci_pci_runtime_suspend_host(chip); 2062 } 2063 2064 static int sdhci_pci_runtime_resume(struct device *dev) 2065 { 2066 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2067 2068 if (!chip) 2069 return 0; 2070 2071 if (chip->fixes && chip->fixes->runtime_resume) 2072 return chip->fixes->runtime_resume(chip); 2073 2074 return sdhci_pci_runtime_resume_host(chip); 2075 } 2076 #endif 2077 2078 static const struct dev_pm_ops sdhci_pci_pm_ops = { 2079 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 2080 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 2081 sdhci_pci_runtime_resume, NULL) 2082 }; 2083 2084 /*****************************************************************************\ 2085 * * 2086 * Device probing/removal * 2087 * * 2088 \*****************************************************************************/ 2089 2090 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 2091 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 2092 int slotno) 2093 { 2094 struct sdhci_pci_slot *slot; 2095 struct sdhci_host *host; 2096 int ret, bar = first_bar + slotno; 2097 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 2098 2099 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 2100 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 2101 return ERR_PTR(-ENODEV); 2102 } 2103 2104 if (pci_resource_len(pdev, bar) < 0x100) { 2105 dev_err(&pdev->dev, "Invalid iomem size. You may " 2106 "experience problems.\n"); 2107 } 2108 2109 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 2110 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 2111 return ERR_PTR(-ENODEV); 2112 } 2113 2114 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 2115 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 2116 return ERR_PTR(-ENODEV); 2117 } 2118 2119 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 2120 if (IS_ERR(host)) { 2121 dev_err(&pdev->dev, "cannot allocate host\n"); 2122 return ERR_CAST(host); 2123 } 2124 2125 slot = sdhci_priv(host); 2126 2127 slot->chip = chip; 2128 slot->host = host; 2129 slot->rst_n_gpio = -EINVAL; 2130 slot->cd_gpio = -EINVAL; 2131 slot->cd_idx = -1; 2132 2133 /* Retrieve platform data if there is any */ 2134 if (*sdhci_pci_get_data) 2135 slot->data = sdhci_pci_get_data(pdev, slotno); 2136 2137 if (slot->data) { 2138 if (slot->data->setup) { 2139 ret = slot->data->setup(slot->data); 2140 if (ret) { 2141 dev_err(&pdev->dev, "platform setup failed\n"); 2142 goto free; 2143 } 2144 } 2145 slot->rst_n_gpio = slot->data->rst_n_gpio; 2146 slot->cd_gpio = slot->data->cd_gpio; 2147 } 2148 2149 host->hw_name = "PCI"; 2150 host->ops = chip->fixes && chip->fixes->ops ? 2151 chip->fixes->ops : 2152 &sdhci_pci_ops; 2153 host->quirks = chip->quirks; 2154 host->quirks2 = chip->quirks2; 2155 2156 host->irq = pdev->irq; 2157 2158 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 2159 if (ret) { 2160 dev_err(&pdev->dev, "cannot request region\n"); 2161 goto cleanup; 2162 } 2163 2164 host->ioaddr = pcim_iomap_table(pdev)[bar]; 2165 2166 if (chip->fixes && chip->fixes->probe_slot) { 2167 ret = chip->fixes->probe_slot(slot); 2168 if (ret) 2169 goto cleanup; 2170 } 2171 2172 if (gpio_is_valid(slot->rst_n_gpio)) { 2173 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 2174 gpio_direction_output(slot->rst_n_gpio, 1); 2175 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 2176 slot->hw_reset = sdhci_pci_gpio_hw_reset; 2177 } else { 2178 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 2179 slot->rst_n_gpio = -EINVAL; 2180 } 2181 } 2182 2183 host->mmc->pm_caps = MMC_PM_KEEP_POWER; 2184 host->mmc->slotno = slotno; 2185 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 2186 2187 if (device_can_wakeup(&pdev->dev)) 2188 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ; 2189 2190 if (host->mmc->caps & MMC_CAP_CD_WAKE) 2191 device_init_wakeup(&pdev->dev, true); 2192 2193 if (slot->cd_idx >= 0) { 2194 ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx, 2195 slot->cd_override_level, 0); 2196 if (ret && ret != -EPROBE_DEFER) 2197 ret = mmc_gpiod_request_cd(host->mmc, NULL, 2198 slot->cd_idx, 2199 slot->cd_override_level, 2200 0); 2201 if (ret == -EPROBE_DEFER) 2202 goto remove; 2203 2204 if (ret) { 2205 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 2206 slot->cd_idx = -1; 2207 } 2208 } 2209 2210 if (chip->fixes && chip->fixes->add_host) 2211 ret = chip->fixes->add_host(slot); 2212 else 2213 ret = sdhci_add_host(host); 2214 if (ret) 2215 goto remove; 2216 2217 sdhci_pci_add_own_cd(slot); 2218 2219 /* 2220 * Check if the chip needs a separate GPIO for card detect to wake up 2221 * from runtime suspend. If it is not there, don't allow runtime PM. 2222 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 2223 */ 2224 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 2225 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 2226 chip->allow_runtime_pm = false; 2227 2228 return slot; 2229 2230 remove: 2231 if (chip->fixes && chip->fixes->remove_slot) 2232 chip->fixes->remove_slot(slot, 0); 2233 2234 cleanup: 2235 if (slot->data && slot->data->cleanup) 2236 slot->data->cleanup(slot->data); 2237 2238 free: 2239 sdhci_free_host(host); 2240 2241 return ERR_PTR(ret); 2242 } 2243 2244 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 2245 { 2246 int dead; 2247 u32 scratch; 2248 2249 sdhci_pci_remove_own_cd(slot); 2250 2251 dead = 0; 2252 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 2253 if (scratch == (u32)-1) 2254 dead = 1; 2255 2256 sdhci_remove_host(slot->host, dead); 2257 2258 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 2259 slot->chip->fixes->remove_slot(slot, dead); 2260 2261 if (slot->data && slot->data->cleanup) 2262 slot->data->cleanup(slot->data); 2263 2264 sdhci_free_host(slot->host); 2265 } 2266 2267 static void sdhci_pci_runtime_pm_allow(struct device *dev) 2268 { 2269 pm_suspend_ignore_children(dev, 1); 2270 pm_runtime_set_autosuspend_delay(dev, 50); 2271 pm_runtime_use_autosuspend(dev); 2272 pm_runtime_allow(dev); 2273 /* Stay active until mmc core scans for a card */ 2274 pm_runtime_put_noidle(dev); 2275 } 2276 2277 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 2278 { 2279 pm_runtime_forbid(dev); 2280 pm_runtime_get_noresume(dev); 2281 } 2282 2283 static int sdhci_pci_probe(struct pci_dev *pdev, 2284 const struct pci_device_id *ent) 2285 { 2286 struct sdhci_pci_chip *chip; 2287 struct sdhci_pci_slot *slot; 2288 2289 u8 slots, first_bar; 2290 int ret, i; 2291 2292 BUG_ON(pdev == NULL); 2293 BUG_ON(ent == NULL); 2294 2295 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 2296 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 2297 2298 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 2299 if (ret) 2300 return ret; 2301 2302 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 2303 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 2304 2305 BUG_ON(slots > MAX_SLOTS); 2306 2307 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 2308 if (ret) 2309 return ret; 2310 2311 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 2312 2313 if (first_bar > 5) { 2314 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 2315 return -ENODEV; 2316 } 2317 2318 ret = pcim_enable_device(pdev); 2319 if (ret) 2320 return ret; 2321 2322 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 2323 if (!chip) 2324 return -ENOMEM; 2325 2326 chip->pdev = pdev; 2327 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 2328 if (chip->fixes) { 2329 chip->quirks = chip->fixes->quirks; 2330 chip->quirks2 = chip->fixes->quirks2; 2331 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 2332 } 2333 chip->num_slots = slots; 2334 chip->pm_retune = true; 2335 chip->rpm_retune = true; 2336 2337 pci_set_drvdata(pdev, chip); 2338 2339 if (chip->fixes && chip->fixes->probe) { 2340 ret = chip->fixes->probe(chip); 2341 if (ret) 2342 return ret; 2343 } 2344 2345 slots = chip->num_slots; /* Quirk may have changed this */ 2346 2347 for (i = 0; i < slots; i++) { 2348 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 2349 if (IS_ERR(slot)) { 2350 for (i--; i >= 0; i--) 2351 sdhci_pci_remove_slot(chip->slots[i]); 2352 return PTR_ERR(slot); 2353 } 2354 2355 chip->slots[i] = slot; 2356 } 2357 2358 if (chip->allow_runtime_pm) 2359 sdhci_pci_runtime_pm_allow(&pdev->dev); 2360 2361 return 0; 2362 } 2363 2364 static void sdhci_pci_remove(struct pci_dev *pdev) 2365 { 2366 int i; 2367 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 2368 2369 if (chip->allow_runtime_pm) 2370 sdhci_pci_runtime_pm_forbid(&pdev->dev); 2371 2372 for (i = 0; i < chip->num_slots; i++) 2373 sdhci_pci_remove_slot(chip->slots[i]); 2374 } 2375 2376 static struct pci_driver sdhci_driver = { 2377 .name = "sdhci-pci", 2378 .id_table = pci_ids, 2379 .probe = sdhci_pci_probe, 2380 .remove = sdhci_pci_remove, 2381 .driver = { 2382 .pm = &sdhci_pci_pm_ops 2383 }, 2384 }; 2385 2386 module_pci_driver(sdhci_driver); 2387 2388 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 2389 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 2390 MODULE_LICENSE("GPL"); 2391