1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 2 * 3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 * 10 * Thanks to the following companies for their support: 11 * 12 * - JMicron (hardware and technical support) 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/highmem.h> 17 #include <linux/module.h> 18 #include <linux/pci.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/slab.h> 21 #include <linux/device.h> 22 #include <linux/mmc/host.h> 23 #include <linux/mmc/mmc.h> 24 #include <linux/scatterlist.h> 25 #include <linux/io.h> 26 #include <linux/gpio.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/mmc/slot-gpio.h> 29 #include <linux/mmc/sdhci-pci-data.h> 30 31 #include "sdhci.h" 32 #include "sdhci-pci.h" 33 #include "sdhci-pci-o2micro.h" 34 35 /*****************************************************************************\ 36 * * 37 * Hardware specific quirk handling * 38 * * 39 \*****************************************************************************/ 40 41 static int ricoh_probe(struct sdhci_pci_chip *chip) 42 { 43 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 44 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 45 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 46 return 0; 47 } 48 49 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 50 { 51 slot->host->caps = 52 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 53 & SDHCI_TIMEOUT_CLK_MASK) | 54 55 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 56 & SDHCI_CLOCK_BASE_MASK) | 57 58 SDHCI_TIMEOUT_CLK_UNIT | 59 SDHCI_CAN_VDD_330 | 60 SDHCI_CAN_DO_HISPD | 61 SDHCI_CAN_DO_SDMA; 62 return 0; 63 } 64 65 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 66 { 67 /* Apply a delay to allow controller to settle */ 68 /* Otherwise it becomes confused if card state changed 69 during suspend */ 70 msleep(500); 71 return 0; 72 } 73 74 static const struct sdhci_pci_fixes sdhci_ricoh = { 75 .probe = ricoh_probe, 76 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 77 SDHCI_QUIRK_FORCE_DMA | 78 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 79 }; 80 81 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 82 .probe_slot = ricoh_mmc_probe_slot, 83 .resume = ricoh_mmc_resume, 84 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 85 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 86 SDHCI_QUIRK_NO_CARD_NO_RESET | 87 SDHCI_QUIRK_MISSING_CAPS 88 }; 89 90 static const struct sdhci_pci_fixes sdhci_ene_712 = { 91 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 92 SDHCI_QUIRK_BROKEN_DMA, 93 }; 94 95 static const struct sdhci_pci_fixes sdhci_ene_714 = { 96 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 97 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 98 SDHCI_QUIRK_BROKEN_DMA, 99 }; 100 101 static const struct sdhci_pci_fixes sdhci_cafe = { 102 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 103 SDHCI_QUIRK_NO_BUSY_IRQ | 104 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 105 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 106 }; 107 108 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 109 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 110 }; 111 112 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 113 { 114 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 115 return 0; 116 } 117 118 /* 119 * ADMA operation is disabled for Moorestown platform due to 120 * hardware bugs. 121 */ 122 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 123 { 124 /* 125 * slots number is fixed here for MRST as SDIO3/5 are never used and 126 * have hardware bugs. 127 */ 128 chip->num_slots = 1; 129 return 0; 130 } 131 132 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 133 { 134 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 135 return 0; 136 } 137 138 #ifdef CONFIG_PM 139 140 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 141 { 142 struct sdhci_pci_slot *slot = dev_id; 143 struct sdhci_host *host = slot->host; 144 145 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 146 return IRQ_HANDLED; 147 } 148 149 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 150 { 151 int err, irq, gpio = slot->cd_gpio; 152 153 slot->cd_gpio = -EINVAL; 154 slot->cd_irq = -EINVAL; 155 156 if (!gpio_is_valid(gpio)) 157 return; 158 159 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 160 if (err < 0) 161 goto out; 162 163 err = gpio_direction_input(gpio); 164 if (err < 0) 165 goto out_free; 166 167 irq = gpio_to_irq(gpio); 168 if (irq < 0) 169 goto out_free; 170 171 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 172 IRQF_TRIGGER_FALLING, "sd_cd", slot); 173 if (err) 174 goto out_free; 175 176 slot->cd_gpio = gpio; 177 slot->cd_irq = irq; 178 179 return; 180 181 out_free: 182 devm_gpio_free(&slot->chip->pdev->dev, gpio); 183 out: 184 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 185 } 186 187 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 188 { 189 if (slot->cd_irq >= 0) 190 free_irq(slot->cd_irq, slot); 191 } 192 193 #else 194 195 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 196 { 197 } 198 199 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 200 { 201 } 202 203 #endif 204 205 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 206 { 207 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 208 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC | 209 MMC_CAP2_HC_ERASE_SZ; 210 return 0; 211 } 212 213 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 214 { 215 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 216 return 0; 217 } 218 219 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 220 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 221 .probe_slot = mrst_hc_probe_slot, 222 }; 223 224 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 225 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 226 .probe = mrst_hc_probe, 227 }; 228 229 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 230 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 231 .allow_runtime_pm = true, 232 .own_cd_for_runtime_pm = true, 233 }; 234 235 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 236 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 237 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 238 .allow_runtime_pm = true, 239 .probe_slot = mfd_sdio_probe_slot, 240 }; 241 242 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 243 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 244 .allow_runtime_pm = true, 245 .probe_slot = mfd_emmc_probe_slot, 246 }; 247 248 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 249 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 250 .probe_slot = pch_hc_probe_slot, 251 }; 252 253 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 254 { 255 u8 reg; 256 257 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 258 reg |= 0x10; 259 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 260 /* For eMMC, minimum is 1us but give it 9us for good measure */ 261 udelay(9); 262 reg &= ~0x10; 263 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 264 /* For eMMC, minimum is 200us but give it 300us for good measure */ 265 usleep_range(300, 1000); 266 } 267 268 static int spt_select_drive_strength(struct sdhci_host *host, 269 struct mmc_card *card, 270 unsigned int max_dtr, 271 int host_drv, int card_drv, int *drv_type) 272 { 273 int drive_strength; 274 275 if (sdhci_pci_spt_drive_strength > 0) 276 drive_strength = sdhci_pci_spt_drive_strength & 0xf; 277 else 278 drive_strength = 0; /* Default 50-ohm */ 279 280 if ((mmc_driver_type_mask(drive_strength) & card_drv) == 0) 281 drive_strength = 0; /* Default 50-ohm */ 282 283 return drive_strength; 284 } 285 286 /* Try to read the drive strength from the card */ 287 static void spt_read_drive_strength(struct sdhci_host *host) 288 { 289 u32 val, i, t; 290 u16 m; 291 292 if (sdhci_pci_spt_drive_strength) 293 return; 294 295 sdhci_pci_spt_drive_strength = -1; 296 297 m = sdhci_readw(host, SDHCI_HOST_CONTROL2) & 0x7; 298 if (m != 3 && m != 5) 299 return; 300 val = sdhci_readl(host, SDHCI_PRESENT_STATE); 301 if (val & 0x3) 302 return; 303 sdhci_writel(host, 0x007f0023, SDHCI_INT_ENABLE); 304 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 305 sdhci_writew(host, 0x10, SDHCI_TRANSFER_MODE); 306 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 307 sdhci_writew(host, 512, SDHCI_BLOCK_SIZE); 308 sdhci_writew(host, 1, SDHCI_BLOCK_COUNT); 309 sdhci_writel(host, 0, SDHCI_ARGUMENT); 310 sdhci_writew(host, 0x83b, SDHCI_COMMAND); 311 for (i = 0; i < 1000; i++) { 312 val = sdhci_readl(host, SDHCI_INT_STATUS); 313 if (val & 0xffff8000) 314 return; 315 if (val & 0x20) 316 break; 317 udelay(1); 318 } 319 val = sdhci_readl(host, SDHCI_PRESENT_STATE); 320 if (!(val & 0x800)) 321 return; 322 for (i = 0; i < 47; i++) 323 val = sdhci_readl(host, SDHCI_BUFFER); 324 t = val & 0xf00; 325 if (t != 0x200 && t != 0x300) 326 return; 327 328 sdhci_pci_spt_drive_strength = 0x10 | ((val >> 12) & 0xf); 329 } 330 331 static int bxt_get_cd(struct mmc_host *mmc) 332 { 333 int gpio_cd = mmc_gpio_get_cd(mmc); 334 struct sdhci_host *host = mmc_priv(mmc); 335 unsigned long flags; 336 int ret = 0; 337 338 if (!gpio_cd) 339 return 0; 340 341 spin_lock_irqsave(&host->lock, flags); 342 343 if (host->flags & SDHCI_DEVICE_DEAD) 344 goto out; 345 346 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 347 out: 348 spin_unlock_irqrestore(&host->lock, flags); 349 350 return ret; 351 } 352 353 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 354 { 355 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 356 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 357 MMC_CAP_WAIT_WHILE_BUSY; 358 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ; 359 slot->hw_reset = sdhci_pci_int_hw_reset; 360 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 361 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 362 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_SPT_EMMC) { 363 spt_read_drive_strength(slot->host); 364 slot->select_drive_strength = spt_select_drive_strength; 365 } 366 return 0; 367 } 368 369 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 370 { 371 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 372 MMC_CAP_WAIT_WHILE_BUSY; 373 return 0; 374 } 375 376 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 377 { 378 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 379 slot->cd_con_id = NULL; 380 slot->cd_idx = 0; 381 slot->cd_override_level = true; 382 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 383 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 384 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD) { 385 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 386 slot->host->mmc->caps |= MMC_CAP_AGGRESSIVE_PM; 387 } 388 389 return 0; 390 } 391 392 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 393 .allow_runtime_pm = true, 394 .probe_slot = byt_emmc_probe_slot, 395 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 396 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 397 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 398 SDHCI_QUIRK2_STOP_WITH_TC, 399 }; 400 401 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 402 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 403 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 404 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 405 .allow_runtime_pm = true, 406 .probe_slot = byt_sdio_probe_slot, 407 }; 408 409 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 410 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 411 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 412 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 413 SDHCI_QUIRK2_STOP_WITH_TC, 414 .allow_runtime_pm = true, 415 .own_cd_for_runtime_pm = true, 416 .probe_slot = byt_sd_probe_slot, 417 }; 418 419 /* Define Host controllers for Intel Merrifield platform */ 420 #define INTEL_MRFLD_EMMC_0 0 421 #define INTEL_MRFLD_EMMC_1 1 422 423 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 424 { 425 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 426 427 switch (func) { 428 case INTEL_MRFLD_EMMC_0: 429 case INTEL_MRFLD_EMMC_1: 430 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 431 MMC_CAP_8_BIT_DATA | 432 MMC_CAP_1_8V_DDR; 433 break; 434 default: 435 /* SD support is not ready yet */ 436 return -ENODEV; 437 } 438 return 0; 439 } 440 441 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 442 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 443 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 444 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 445 .allow_runtime_pm = true, 446 .probe_slot = intel_mrfld_mmc_probe_slot, 447 }; 448 449 /* O2Micro extra registers */ 450 #define O2_SD_LOCK_WP 0xD3 451 #define O2_SD_MULTI_VCC3V 0xEE 452 #define O2_SD_CLKREQ 0xEC 453 #define O2_SD_CAPS 0xE0 454 #define O2_SD_ADMA1 0xE2 455 #define O2_SD_ADMA2 0xE7 456 #define O2_SD_INF_MOD 0xF1 457 458 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 459 { 460 u8 scratch; 461 int ret; 462 463 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 464 if (ret) 465 return ret; 466 467 /* 468 * Turn PMOS on [bit 0], set over current detection to 2.4 V 469 * [bit 1:2] and enable over current debouncing [bit 6]. 470 */ 471 if (on) 472 scratch |= 0x47; 473 else 474 scratch &= ~0x47; 475 476 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 477 } 478 479 static int jmicron_probe(struct sdhci_pci_chip *chip) 480 { 481 int ret; 482 u16 mmcdev = 0; 483 484 if (chip->pdev->revision == 0) { 485 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 486 SDHCI_QUIRK_32BIT_DMA_SIZE | 487 SDHCI_QUIRK_32BIT_ADMA_SIZE | 488 SDHCI_QUIRK_RESET_AFTER_REQUEST | 489 SDHCI_QUIRK_BROKEN_SMALL_PIO; 490 } 491 492 /* 493 * JMicron chips can have two interfaces to the same hardware 494 * in order to work around limitations in Microsoft's driver. 495 * We need to make sure we only bind to one of them. 496 * 497 * This code assumes two things: 498 * 499 * 1. The PCI code adds subfunctions in order. 500 * 501 * 2. The MMC interface has a lower subfunction number 502 * than the SD interface. 503 */ 504 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 505 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 506 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 507 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 508 509 if (mmcdev) { 510 struct pci_dev *sd_dev; 511 512 sd_dev = NULL; 513 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 514 mmcdev, sd_dev)) != NULL) { 515 if ((PCI_SLOT(chip->pdev->devfn) == 516 PCI_SLOT(sd_dev->devfn)) && 517 (chip->pdev->bus == sd_dev->bus)) 518 break; 519 } 520 521 if (sd_dev) { 522 pci_dev_put(sd_dev); 523 dev_info(&chip->pdev->dev, "Refusing to bind to " 524 "secondary interface.\n"); 525 return -ENODEV; 526 } 527 } 528 529 /* 530 * JMicron chips need a bit of a nudge to enable the power 531 * output pins. 532 */ 533 ret = jmicron_pmos(chip, 1); 534 if (ret) { 535 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 536 return ret; 537 } 538 539 /* quirk for unsable RO-detection on JM388 chips */ 540 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 541 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 542 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 543 544 return 0; 545 } 546 547 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 548 { 549 u8 scratch; 550 551 scratch = readb(host->ioaddr + 0xC0); 552 553 if (on) 554 scratch |= 0x01; 555 else 556 scratch &= ~0x01; 557 558 writeb(scratch, host->ioaddr + 0xC0); 559 } 560 561 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 562 { 563 if (slot->chip->pdev->revision == 0) { 564 u16 version; 565 566 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 567 version = (version & SDHCI_VENDOR_VER_MASK) >> 568 SDHCI_VENDOR_VER_SHIFT; 569 570 /* 571 * Older versions of the chip have lots of nasty glitches 572 * in the ADMA engine. It's best just to avoid it 573 * completely. 574 */ 575 if (version < 0xAC) 576 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 577 } 578 579 /* JM388 MMC doesn't support 1.8V while SD supports it */ 580 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 581 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 582 MMC_VDD_29_30 | MMC_VDD_30_31 | 583 MMC_VDD_165_195; /* allow 1.8V */ 584 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 585 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 586 } 587 588 /* 589 * The secondary interface requires a bit set to get the 590 * interrupts. 591 */ 592 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 593 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 594 jmicron_enable_mmc(slot->host, 1); 595 596 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 597 598 return 0; 599 } 600 601 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 602 { 603 if (dead) 604 return; 605 606 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 607 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 608 jmicron_enable_mmc(slot->host, 0); 609 } 610 611 static int jmicron_suspend(struct sdhci_pci_chip *chip) 612 { 613 int i; 614 615 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 616 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 617 for (i = 0; i < chip->num_slots; i++) 618 jmicron_enable_mmc(chip->slots[i]->host, 0); 619 } 620 621 return 0; 622 } 623 624 static int jmicron_resume(struct sdhci_pci_chip *chip) 625 { 626 int ret, i; 627 628 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 629 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 630 for (i = 0; i < chip->num_slots; i++) 631 jmicron_enable_mmc(chip->slots[i]->host, 1); 632 } 633 634 ret = jmicron_pmos(chip, 1); 635 if (ret) { 636 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 637 return ret; 638 } 639 640 return 0; 641 } 642 643 static const struct sdhci_pci_fixes sdhci_o2 = { 644 .probe = sdhci_pci_o2_probe, 645 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 646 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 647 .probe_slot = sdhci_pci_o2_probe_slot, 648 .resume = sdhci_pci_o2_resume, 649 }; 650 651 static const struct sdhci_pci_fixes sdhci_jmicron = { 652 .probe = jmicron_probe, 653 654 .probe_slot = jmicron_probe_slot, 655 .remove_slot = jmicron_remove_slot, 656 657 .suspend = jmicron_suspend, 658 .resume = jmicron_resume, 659 }; 660 661 /* SysKonnect CardBus2SDIO extra registers */ 662 #define SYSKT_CTRL 0x200 663 #define SYSKT_RDFIFO_STAT 0x204 664 #define SYSKT_WRFIFO_STAT 0x208 665 #define SYSKT_POWER_DATA 0x20c 666 #define SYSKT_POWER_330 0xef 667 #define SYSKT_POWER_300 0xf8 668 #define SYSKT_POWER_184 0xcc 669 #define SYSKT_POWER_CMD 0x20d 670 #define SYSKT_POWER_START (1 << 7) 671 #define SYSKT_POWER_STATUS 0x20e 672 #define SYSKT_POWER_STATUS_OK (1 << 0) 673 #define SYSKT_BOARD_REV 0x210 674 #define SYSKT_CHIP_REV 0x211 675 #define SYSKT_CONF_DATA 0x212 676 #define SYSKT_CONF_DATA_1V8 (1 << 2) 677 #define SYSKT_CONF_DATA_2V5 (1 << 1) 678 #define SYSKT_CONF_DATA_3V3 (1 << 0) 679 680 static int syskt_probe(struct sdhci_pci_chip *chip) 681 { 682 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 683 chip->pdev->class &= ~0x0000FF; 684 chip->pdev->class |= PCI_SDHCI_IFDMA; 685 } 686 return 0; 687 } 688 689 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 690 { 691 int tm, ps; 692 693 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 694 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 695 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 696 "board rev %d.%d, chip rev %d.%d\n", 697 board_rev >> 4, board_rev & 0xf, 698 chip_rev >> 4, chip_rev & 0xf); 699 if (chip_rev >= 0x20) 700 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 701 702 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 703 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 704 udelay(50); 705 tm = 10; /* Wait max 1 ms */ 706 do { 707 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 708 if (ps & SYSKT_POWER_STATUS_OK) 709 break; 710 udelay(100); 711 } while (--tm); 712 if (!tm) { 713 dev_err(&slot->chip->pdev->dev, 714 "power regulator never stabilized"); 715 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 716 return -ENODEV; 717 } 718 719 return 0; 720 } 721 722 static const struct sdhci_pci_fixes sdhci_syskt = { 723 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 724 .probe = syskt_probe, 725 .probe_slot = syskt_probe_slot, 726 }; 727 728 static int via_probe(struct sdhci_pci_chip *chip) 729 { 730 if (chip->pdev->revision == 0x10) 731 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 732 733 return 0; 734 } 735 736 static const struct sdhci_pci_fixes sdhci_via = { 737 .probe = via_probe, 738 }; 739 740 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 741 { 742 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 743 return 0; 744 } 745 746 static const struct sdhci_pci_fixes sdhci_rtsx = { 747 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 748 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 749 SDHCI_QUIRK2_BROKEN_DDR50, 750 .probe_slot = rtsx_probe_slot, 751 }; 752 753 /*AMD chipset generation*/ 754 enum amd_chipset_gen { 755 AMD_CHIPSET_BEFORE_ML, 756 AMD_CHIPSET_CZ, 757 AMD_CHIPSET_NL, 758 AMD_CHIPSET_UNKNOWN, 759 }; 760 761 static int amd_probe(struct sdhci_pci_chip *chip) 762 { 763 struct pci_dev *smbus_dev; 764 enum amd_chipset_gen gen; 765 766 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 767 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 768 if (smbus_dev) { 769 gen = AMD_CHIPSET_BEFORE_ML; 770 } else { 771 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 772 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 773 if (smbus_dev) { 774 if (smbus_dev->revision < 0x51) 775 gen = AMD_CHIPSET_CZ; 776 else 777 gen = AMD_CHIPSET_NL; 778 } else { 779 gen = AMD_CHIPSET_UNKNOWN; 780 } 781 } 782 783 if ((gen == AMD_CHIPSET_BEFORE_ML) || (gen == AMD_CHIPSET_CZ)) { 784 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 785 chip->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 786 } 787 788 return 0; 789 } 790 791 static const struct sdhci_pci_fixes sdhci_amd = { 792 .probe = amd_probe, 793 }; 794 795 static const struct pci_device_id pci_ids[] = { 796 { 797 .vendor = PCI_VENDOR_ID_RICOH, 798 .device = PCI_DEVICE_ID_RICOH_R5C822, 799 .subvendor = PCI_ANY_ID, 800 .subdevice = PCI_ANY_ID, 801 .driver_data = (kernel_ulong_t)&sdhci_ricoh, 802 }, 803 804 { 805 .vendor = PCI_VENDOR_ID_RICOH, 806 .device = 0x843, 807 .subvendor = PCI_ANY_ID, 808 .subdevice = PCI_ANY_ID, 809 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 810 }, 811 812 { 813 .vendor = PCI_VENDOR_ID_RICOH, 814 .device = 0xe822, 815 .subvendor = PCI_ANY_ID, 816 .subdevice = PCI_ANY_ID, 817 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 818 }, 819 820 { 821 .vendor = PCI_VENDOR_ID_RICOH, 822 .device = 0xe823, 823 .subvendor = PCI_ANY_ID, 824 .subdevice = PCI_ANY_ID, 825 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 826 }, 827 828 { 829 .vendor = PCI_VENDOR_ID_ENE, 830 .device = PCI_DEVICE_ID_ENE_CB712_SD, 831 .subvendor = PCI_ANY_ID, 832 .subdevice = PCI_ANY_ID, 833 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 834 }, 835 836 { 837 .vendor = PCI_VENDOR_ID_ENE, 838 .device = PCI_DEVICE_ID_ENE_CB712_SD_2, 839 .subvendor = PCI_ANY_ID, 840 .subdevice = PCI_ANY_ID, 841 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 842 }, 843 844 { 845 .vendor = PCI_VENDOR_ID_ENE, 846 .device = PCI_DEVICE_ID_ENE_CB714_SD, 847 .subvendor = PCI_ANY_ID, 848 .subdevice = PCI_ANY_ID, 849 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 850 }, 851 852 { 853 .vendor = PCI_VENDOR_ID_ENE, 854 .device = PCI_DEVICE_ID_ENE_CB714_SD_2, 855 .subvendor = PCI_ANY_ID, 856 .subdevice = PCI_ANY_ID, 857 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 858 }, 859 860 { 861 .vendor = PCI_VENDOR_ID_MARVELL, 862 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD, 863 .subvendor = PCI_ANY_ID, 864 .subdevice = PCI_ANY_ID, 865 .driver_data = (kernel_ulong_t)&sdhci_cafe, 866 }, 867 868 { 869 .vendor = PCI_VENDOR_ID_JMICRON, 870 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD, 871 .subvendor = PCI_ANY_ID, 872 .subdevice = PCI_ANY_ID, 873 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 874 }, 875 876 { 877 .vendor = PCI_VENDOR_ID_JMICRON, 878 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC, 879 .subvendor = PCI_ANY_ID, 880 .subdevice = PCI_ANY_ID, 881 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 882 }, 883 884 { 885 .vendor = PCI_VENDOR_ID_JMICRON, 886 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD, 887 .subvendor = PCI_ANY_ID, 888 .subdevice = PCI_ANY_ID, 889 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 890 }, 891 892 { 893 .vendor = PCI_VENDOR_ID_JMICRON, 894 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD, 895 .subvendor = PCI_ANY_ID, 896 .subdevice = PCI_ANY_ID, 897 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 898 }, 899 900 { 901 .vendor = PCI_VENDOR_ID_SYSKONNECT, 902 .device = 0x8000, 903 .subvendor = PCI_ANY_ID, 904 .subdevice = PCI_ANY_ID, 905 .driver_data = (kernel_ulong_t)&sdhci_syskt, 906 }, 907 908 { 909 .vendor = PCI_VENDOR_ID_VIA, 910 .device = 0x95d0, 911 .subvendor = PCI_ANY_ID, 912 .subdevice = PCI_ANY_ID, 913 .driver_data = (kernel_ulong_t)&sdhci_via, 914 }, 915 916 { 917 .vendor = PCI_VENDOR_ID_REALTEK, 918 .device = 0x5250, 919 .subvendor = PCI_ANY_ID, 920 .subdevice = PCI_ANY_ID, 921 .driver_data = (kernel_ulong_t)&sdhci_rtsx, 922 }, 923 924 { 925 .vendor = PCI_VENDOR_ID_INTEL, 926 .device = PCI_DEVICE_ID_INTEL_QRK_SD, 927 .subvendor = PCI_ANY_ID, 928 .subdevice = PCI_ANY_ID, 929 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk, 930 }, 931 932 { 933 .vendor = PCI_VENDOR_ID_INTEL, 934 .device = PCI_DEVICE_ID_INTEL_MRST_SD0, 935 .subvendor = PCI_ANY_ID, 936 .subdevice = PCI_ANY_ID, 937 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0, 938 }, 939 940 { 941 .vendor = PCI_VENDOR_ID_INTEL, 942 .device = PCI_DEVICE_ID_INTEL_MRST_SD1, 943 .subvendor = PCI_ANY_ID, 944 .subdevice = PCI_ANY_ID, 945 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 946 }, 947 948 { 949 .vendor = PCI_VENDOR_ID_INTEL, 950 .device = PCI_DEVICE_ID_INTEL_MRST_SD2, 951 .subvendor = PCI_ANY_ID, 952 .subdevice = PCI_ANY_ID, 953 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 954 }, 955 956 { 957 .vendor = PCI_VENDOR_ID_INTEL, 958 .device = PCI_DEVICE_ID_INTEL_MFD_SD, 959 .subvendor = PCI_ANY_ID, 960 .subdevice = PCI_ANY_ID, 961 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 962 }, 963 964 { 965 .vendor = PCI_VENDOR_ID_INTEL, 966 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1, 967 .subvendor = PCI_ANY_ID, 968 .subdevice = PCI_ANY_ID, 969 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 970 }, 971 972 { 973 .vendor = PCI_VENDOR_ID_INTEL, 974 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2, 975 .subvendor = PCI_ANY_ID, 976 .subdevice = PCI_ANY_ID, 977 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 978 }, 979 980 { 981 .vendor = PCI_VENDOR_ID_INTEL, 982 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0, 983 .subvendor = PCI_ANY_ID, 984 .subdevice = PCI_ANY_ID, 985 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 986 }, 987 988 { 989 .vendor = PCI_VENDOR_ID_INTEL, 990 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1, 991 .subvendor = PCI_ANY_ID, 992 .subdevice = PCI_ANY_ID, 993 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 994 }, 995 996 { 997 .vendor = PCI_VENDOR_ID_INTEL, 998 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0, 999 .subvendor = PCI_ANY_ID, 1000 .subdevice = PCI_ANY_ID, 1001 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1002 }, 1003 1004 { 1005 .vendor = PCI_VENDOR_ID_INTEL, 1006 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1, 1007 .subvendor = PCI_ANY_ID, 1008 .subdevice = PCI_ANY_ID, 1009 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1010 }, 1011 1012 { 1013 .vendor = PCI_VENDOR_ID_INTEL, 1014 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC, 1015 .subvendor = PCI_ANY_ID, 1016 .subdevice = PCI_ANY_ID, 1017 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1018 }, 1019 1020 { 1021 .vendor = PCI_VENDOR_ID_INTEL, 1022 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, 1023 .subvendor = PCI_ANY_ID, 1024 .subdevice = PCI_ANY_ID, 1025 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1026 }, 1027 1028 { 1029 .vendor = PCI_VENDOR_ID_INTEL, 1030 .device = PCI_DEVICE_ID_INTEL_BYT_SD, 1031 .subvendor = PCI_ANY_ID, 1032 .subdevice = PCI_ANY_ID, 1033 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1034 }, 1035 1036 { 1037 .vendor = PCI_VENDOR_ID_INTEL, 1038 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2, 1039 .subvendor = PCI_ANY_ID, 1040 .subdevice = PCI_ANY_ID, 1041 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1042 }, 1043 1044 { 1045 .vendor = PCI_VENDOR_ID_INTEL, 1046 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC, 1047 .subvendor = PCI_ANY_ID, 1048 .subdevice = PCI_ANY_ID, 1049 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1050 }, 1051 1052 { 1053 .vendor = PCI_VENDOR_ID_INTEL, 1054 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO, 1055 .subvendor = PCI_ANY_ID, 1056 .subdevice = PCI_ANY_ID, 1057 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1058 }, 1059 1060 { 1061 .vendor = PCI_VENDOR_ID_INTEL, 1062 .device = PCI_DEVICE_ID_INTEL_BSW_SD, 1063 .subvendor = PCI_ANY_ID, 1064 .subdevice = PCI_ANY_ID, 1065 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1066 }, 1067 1068 { 1069 .vendor = PCI_VENDOR_ID_INTEL, 1070 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0, 1071 .subvendor = PCI_ANY_ID, 1072 .subdevice = PCI_ANY_ID, 1073 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1074 }, 1075 1076 { 1077 .vendor = PCI_VENDOR_ID_INTEL, 1078 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1, 1079 .subvendor = PCI_ANY_ID, 1080 .subdevice = PCI_ANY_ID, 1081 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1082 }, 1083 1084 { 1085 .vendor = PCI_VENDOR_ID_INTEL, 1086 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2, 1087 .subvendor = PCI_ANY_ID, 1088 .subdevice = PCI_ANY_ID, 1089 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1090 }, 1091 1092 { 1093 .vendor = PCI_VENDOR_ID_INTEL, 1094 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0, 1095 .subvendor = PCI_ANY_ID, 1096 .subdevice = PCI_ANY_ID, 1097 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1098 }, 1099 1100 { 1101 .vendor = PCI_VENDOR_ID_INTEL, 1102 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1, 1103 .subvendor = PCI_ANY_ID, 1104 .subdevice = PCI_ANY_ID, 1105 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1106 }, 1107 1108 { 1109 .vendor = PCI_VENDOR_ID_INTEL, 1110 .device = PCI_DEVICE_ID_INTEL_MRFLD_MMC, 1111 .subvendor = PCI_ANY_ID, 1112 .subdevice = PCI_ANY_ID, 1113 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfld_mmc, 1114 }, 1115 1116 { 1117 .vendor = PCI_VENDOR_ID_INTEL, 1118 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC, 1119 .subvendor = PCI_ANY_ID, 1120 .subdevice = PCI_ANY_ID, 1121 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1122 }, 1123 1124 { 1125 .vendor = PCI_VENDOR_ID_INTEL, 1126 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO, 1127 .subvendor = PCI_ANY_ID, 1128 .subdevice = PCI_ANY_ID, 1129 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1130 }, 1131 1132 { 1133 .vendor = PCI_VENDOR_ID_INTEL, 1134 .device = PCI_DEVICE_ID_INTEL_SPT_SD, 1135 .subvendor = PCI_ANY_ID, 1136 .subdevice = PCI_ANY_ID, 1137 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1138 }, 1139 1140 { 1141 .vendor = PCI_VENDOR_ID_INTEL, 1142 .device = PCI_DEVICE_ID_INTEL_DNV_EMMC, 1143 .subvendor = PCI_ANY_ID, 1144 .subdevice = PCI_ANY_ID, 1145 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1146 }, 1147 1148 { 1149 .vendor = PCI_VENDOR_ID_INTEL, 1150 .device = PCI_DEVICE_ID_INTEL_BXT_EMMC, 1151 .subvendor = PCI_ANY_ID, 1152 .subdevice = PCI_ANY_ID, 1153 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1154 }, 1155 1156 { 1157 .vendor = PCI_VENDOR_ID_INTEL, 1158 .device = PCI_DEVICE_ID_INTEL_BXT_SDIO, 1159 .subvendor = PCI_ANY_ID, 1160 .subdevice = PCI_ANY_ID, 1161 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1162 }, 1163 1164 { 1165 .vendor = PCI_VENDOR_ID_INTEL, 1166 .device = PCI_DEVICE_ID_INTEL_BXT_SD, 1167 .subvendor = PCI_ANY_ID, 1168 .subdevice = PCI_ANY_ID, 1169 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1170 }, 1171 1172 { 1173 .vendor = PCI_VENDOR_ID_INTEL, 1174 .device = PCI_DEVICE_ID_INTEL_BXTM_EMMC, 1175 .subvendor = PCI_ANY_ID, 1176 .subdevice = PCI_ANY_ID, 1177 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1178 }, 1179 1180 { 1181 .vendor = PCI_VENDOR_ID_INTEL, 1182 .device = PCI_DEVICE_ID_INTEL_BXTM_SDIO, 1183 .subvendor = PCI_ANY_ID, 1184 .subdevice = PCI_ANY_ID, 1185 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1186 }, 1187 1188 { 1189 .vendor = PCI_VENDOR_ID_INTEL, 1190 .device = PCI_DEVICE_ID_INTEL_BXTM_SD, 1191 .subvendor = PCI_ANY_ID, 1192 .subdevice = PCI_ANY_ID, 1193 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1194 }, 1195 1196 { 1197 .vendor = PCI_VENDOR_ID_INTEL, 1198 .device = PCI_DEVICE_ID_INTEL_APL_EMMC, 1199 .subvendor = PCI_ANY_ID, 1200 .subdevice = PCI_ANY_ID, 1201 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1202 }, 1203 1204 { 1205 .vendor = PCI_VENDOR_ID_INTEL, 1206 .device = PCI_DEVICE_ID_INTEL_APL_SDIO, 1207 .subvendor = PCI_ANY_ID, 1208 .subdevice = PCI_ANY_ID, 1209 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1210 }, 1211 1212 { 1213 .vendor = PCI_VENDOR_ID_INTEL, 1214 .device = PCI_DEVICE_ID_INTEL_APL_SD, 1215 .subvendor = PCI_ANY_ID, 1216 .subdevice = PCI_ANY_ID, 1217 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1218 }, 1219 1220 { 1221 .vendor = PCI_VENDOR_ID_O2, 1222 .device = PCI_DEVICE_ID_O2_8120, 1223 .subvendor = PCI_ANY_ID, 1224 .subdevice = PCI_ANY_ID, 1225 .driver_data = (kernel_ulong_t)&sdhci_o2, 1226 }, 1227 1228 { 1229 .vendor = PCI_VENDOR_ID_O2, 1230 .device = PCI_DEVICE_ID_O2_8220, 1231 .subvendor = PCI_ANY_ID, 1232 .subdevice = PCI_ANY_ID, 1233 .driver_data = (kernel_ulong_t)&sdhci_o2, 1234 }, 1235 1236 { 1237 .vendor = PCI_VENDOR_ID_O2, 1238 .device = PCI_DEVICE_ID_O2_8221, 1239 .subvendor = PCI_ANY_ID, 1240 .subdevice = PCI_ANY_ID, 1241 .driver_data = (kernel_ulong_t)&sdhci_o2, 1242 }, 1243 1244 { 1245 .vendor = PCI_VENDOR_ID_O2, 1246 .device = PCI_DEVICE_ID_O2_8320, 1247 .subvendor = PCI_ANY_ID, 1248 .subdevice = PCI_ANY_ID, 1249 .driver_data = (kernel_ulong_t)&sdhci_o2, 1250 }, 1251 1252 { 1253 .vendor = PCI_VENDOR_ID_O2, 1254 .device = PCI_DEVICE_ID_O2_8321, 1255 .subvendor = PCI_ANY_ID, 1256 .subdevice = PCI_ANY_ID, 1257 .driver_data = (kernel_ulong_t)&sdhci_o2, 1258 }, 1259 1260 { 1261 .vendor = PCI_VENDOR_ID_O2, 1262 .device = PCI_DEVICE_ID_O2_FUJIN2, 1263 .subvendor = PCI_ANY_ID, 1264 .subdevice = PCI_ANY_ID, 1265 .driver_data = (kernel_ulong_t)&sdhci_o2, 1266 }, 1267 1268 { 1269 .vendor = PCI_VENDOR_ID_O2, 1270 .device = PCI_DEVICE_ID_O2_SDS0, 1271 .subvendor = PCI_ANY_ID, 1272 .subdevice = PCI_ANY_ID, 1273 .driver_data = (kernel_ulong_t)&sdhci_o2, 1274 }, 1275 1276 { 1277 .vendor = PCI_VENDOR_ID_O2, 1278 .device = PCI_DEVICE_ID_O2_SDS1, 1279 .subvendor = PCI_ANY_ID, 1280 .subdevice = PCI_ANY_ID, 1281 .driver_data = (kernel_ulong_t)&sdhci_o2, 1282 }, 1283 1284 { 1285 .vendor = PCI_VENDOR_ID_O2, 1286 .device = PCI_DEVICE_ID_O2_SEABIRD0, 1287 .subvendor = PCI_ANY_ID, 1288 .subdevice = PCI_ANY_ID, 1289 .driver_data = (kernel_ulong_t)&sdhci_o2, 1290 }, 1291 1292 { 1293 .vendor = PCI_VENDOR_ID_O2, 1294 .device = PCI_DEVICE_ID_O2_SEABIRD1, 1295 .subvendor = PCI_ANY_ID, 1296 .subdevice = PCI_ANY_ID, 1297 .driver_data = (kernel_ulong_t)&sdhci_o2, 1298 }, 1299 { 1300 .vendor = PCI_VENDOR_ID_AMD, 1301 .device = PCI_ANY_ID, 1302 .class = PCI_CLASS_SYSTEM_SDHCI << 8, 1303 .class_mask = 0xFFFF00, 1304 .subvendor = PCI_ANY_ID, 1305 .subdevice = PCI_ANY_ID, 1306 .driver_data = (kernel_ulong_t)&sdhci_amd, 1307 }, 1308 { /* Generic SD host controller */ 1309 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) 1310 }, 1311 1312 { /* end: all zeroes */ }, 1313 }; 1314 1315 MODULE_DEVICE_TABLE(pci, pci_ids); 1316 1317 /*****************************************************************************\ 1318 * * 1319 * SDHCI core callbacks * 1320 * * 1321 \*****************************************************************************/ 1322 1323 static int sdhci_pci_enable_dma(struct sdhci_host *host) 1324 { 1325 struct sdhci_pci_slot *slot; 1326 struct pci_dev *pdev; 1327 1328 slot = sdhci_priv(host); 1329 pdev = slot->chip->pdev; 1330 1331 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1332 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1333 (host->flags & SDHCI_USE_SDMA)) { 1334 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1335 "doesn't fully claim to support it.\n"); 1336 } 1337 1338 pci_set_master(pdev); 1339 1340 return 0; 1341 } 1342 1343 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width) 1344 { 1345 u8 ctrl; 1346 1347 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1348 1349 switch (width) { 1350 case MMC_BUS_WIDTH_8: 1351 ctrl |= SDHCI_CTRL_8BITBUS; 1352 ctrl &= ~SDHCI_CTRL_4BITBUS; 1353 break; 1354 case MMC_BUS_WIDTH_4: 1355 ctrl |= SDHCI_CTRL_4BITBUS; 1356 ctrl &= ~SDHCI_CTRL_8BITBUS; 1357 break; 1358 default: 1359 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS); 1360 break; 1361 } 1362 1363 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1364 } 1365 1366 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1367 { 1368 struct sdhci_pci_slot *slot = sdhci_priv(host); 1369 int rst_n_gpio = slot->rst_n_gpio; 1370 1371 if (!gpio_is_valid(rst_n_gpio)) 1372 return; 1373 gpio_set_value_cansleep(rst_n_gpio, 0); 1374 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1375 udelay(10); 1376 gpio_set_value_cansleep(rst_n_gpio, 1); 1377 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1378 usleep_range(300, 1000); 1379 } 1380 1381 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1382 { 1383 struct sdhci_pci_slot *slot = sdhci_priv(host); 1384 1385 if (slot->hw_reset) 1386 slot->hw_reset(host); 1387 } 1388 1389 static int sdhci_pci_select_drive_strength(struct sdhci_host *host, 1390 struct mmc_card *card, 1391 unsigned int max_dtr, int host_drv, 1392 int card_drv, int *drv_type) 1393 { 1394 struct sdhci_pci_slot *slot = sdhci_priv(host); 1395 1396 if (!slot->select_drive_strength) 1397 return 0; 1398 1399 return slot->select_drive_strength(host, card, max_dtr, host_drv, 1400 card_drv, drv_type); 1401 } 1402 1403 static const struct sdhci_ops sdhci_pci_ops = { 1404 .set_clock = sdhci_set_clock, 1405 .enable_dma = sdhci_pci_enable_dma, 1406 .set_bus_width = sdhci_pci_set_bus_width, 1407 .reset = sdhci_reset, 1408 .set_uhs_signaling = sdhci_set_uhs_signaling, 1409 .hw_reset = sdhci_pci_hw_reset, 1410 .select_drive_strength = sdhci_pci_select_drive_strength, 1411 }; 1412 1413 /*****************************************************************************\ 1414 * * 1415 * Suspend/resume * 1416 * * 1417 \*****************************************************************************/ 1418 1419 #ifdef CONFIG_PM_SLEEP 1420 static int sdhci_pci_suspend(struct device *dev) 1421 { 1422 struct pci_dev *pdev = to_pci_dev(dev); 1423 struct sdhci_pci_chip *chip; 1424 struct sdhci_pci_slot *slot; 1425 mmc_pm_flag_t slot_pm_flags; 1426 mmc_pm_flag_t pm_flags = 0; 1427 int i, ret; 1428 1429 chip = pci_get_drvdata(pdev); 1430 if (!chip) 1431 return 0; 1432 1433 for (i = 0; i < chip->num_slots; i++) { 1434 slot = chip->slots[i]; 1435 if (!slot) 1436 continue; 1437 1438 ret = sdhci_suspend_host(slot->host); 1439 1440 if (ret) 1441 goto err_pci_suspend; 1442 1443 slot_pm_flags = slot->host->mmc->pm_flags; 1444 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1445 sdhci_enable_irq_wakeups(slot->host); 1446 1447 pm_flags |= slot_pm_flags; 1448 } 1449 1450 if (chip->fixes && chip->fixes->suspend) { 1451 ret = chip->fixes->suspend(chip); 1452 if (ret) 1453 goto err_pci_suspend; 1454 } 1455 1456 if (pm_flags & MMC_PM_KEEP_POWER) { 1457 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1458 device_init_wakeup(dev, true); 1459 else 1460 device_init_wakeup(dev, false); 1461 } else 1462 device_init_wakeup(dev, false); 1463 1464 return 0; 1465 1466 err_pci_suspend: 1467 while (--i >= 0) 1468 sdhci_resume_host(chip->slots[i]->host); 1469 return ret; 1470 } 1471 1472 static int sdhci_pci_resume(struct device *dev) 1473 { 1474 struct pci_dev *pdev = to_pci_dev(dev); 1475 struct sdhci_pci_chip *chip; 1476 struct sdhci_pci_slot *slot; 1477 int i, ret; 1478 1479 chip = pci_get_drvdata(pdev); 1480 if (!chip) 1481 return 0; 1482 1483 if (chip->fixes && chip->fixes->resume) { 1484 ret = chip->fixes->resume(chip); 1485 if (ret) 1486 return ret; 1487 } 1488 1489 for (i = 0; i < chip->num_slots; i++) { 1490 slot = chip->slots[i]; 1491 if (!slot) 1492 continue; 1493 1494 ret = sdhci_resume_host(slot->host); 1495 if (ret) 1496 return ret; 1497 } 1498 1499 return 0; 1500 } 1501 #endif 1502 1503 #ifdef CONFIG_PM 1504 static int sdhci_pci_runtime_suspend(struct device *dev) 1505 { 1506 struct pci_dev *pdev = to_pci_dev(dev); 1507 struct sdhci_pci_chip *chip; 1508 struct sdhci_pci_slot *slot; 1509 int i, ret; 1510 1511 chip = pci_get_drvdata(pdev); 1512 if (!chip) 1513 return 0; 1514 1515 for (i = 0; i < chip->num_slots; i++) { 1516 slot = chip->slots[i]; 1517 if (!slot) 1518 continue; 1519 1520 ret = sdhci_runtime_suspend_host(slot->host); 1521 1522 if (ret) 1523 goto err_pci_runtime_suspend; 1524 } 1525 1526 if (chip->fixes && chip->fixes->suspend) { 1527 ret = chip->fixes->suspend(chip); 1528 if (ret) 1529 goto err_pci_runtime_suspend; 1530 } 1531 1532 return 0; 1533 1534 err_pci_runtime_suspend: 1535 while (--i >= 0) 1536 sdhci_runtime_resume_host(chip->slots[i]->host); 1537 return ret; 1538 } 1539 1540 static int sdhci_pci_runtime_resume(struct device *dev) 1541 { 1542 struct pci_dev *pdev = to_pci_dev(dev); 1543 struct sdhci_pci_chip *chip; 1544 struct sdhci_pci_slot *slot; 1545 int i, ret; 1546 1547 chip = pci_get_drvdata(pdev); 1548 if (!chip) 1549 return 0; 1550 1551 if (chip->fixes && chip->fixes->resume) { 1552 ret = chip->fixes->resume(chip); 1553 if (ret) 1554 return ret; 1555 } 1556 1557 for (i = 0; i < chip->num_slots; i++) { 1558 slot = chip->slots[i]; 1559 if (!slot) 1560 continue; 1561 1562 ret = sdhci_runtime_resume_host(slot->host); 1563 if (ret) 1564 return ret; 1565 } 1566 1567 return 0; 1568 } 1569 #endif 1570 1571 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1572 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1573 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1574 sdhci_pci_runtime_resume, NULL) 1575 }; 1576 1577 /*****************************************************************************\ 1578 * * 1579 * Device probing/removal * 1580 * * 1581 \*****************************************************************************/ 1582 1583 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1584 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1585 int slotno) 1586 { 1587 struct sdhci_pci_slot *slot; 1588 struct sdhci_host *host; 1589 int ret, bar = first_bar + slotno; 1590 1591 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1592 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1593 return ERR_PTR(-ENODEV); 1594 } 1595 1596 if (pci_resource_len(pdev, bar) < 0x100) { 1597 dev_err(&pdev->dev, "Invalid iomem size. You may " 1598 "experience problems.\n"); 1599 } 1600 1601 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1602 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1603 return ERR_PTR(-ENODEV); 1604 } 1605 1606 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1607 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1608 return ERR_PTR(-ENODEV); 1609 } 1610 1611 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot)); 1612 if (IS_ERR(host)) { 1613 dev_err(&pdev->dev, "cannot allocate host\n"); 1614 return ERR_CAST(host); 1615 } 1616 1617 slot = sdhci_priv(host); 1618 1619 slot->chip = chip; 1620 slot->host = host; 1621 slot->rst_n_gpio = -EINVAL; 1622 slot->cd_gpio = -EINVAL; 1623 slot->cd_idx = -1; 1624 1625 /* Retrieve platform data if there is any */ 1626 if (*sdhci_pci_get_data) 1627 slot->data = sdhci_pci_get_data(pdev, slotno); 1628 1629 if (slot->data) { 1630 if (slot->data->setup) { 1631 ret = slot->data->setup(slot->data); 1632 if (ret) { 1633 dev_err(&pdev->dev, "platform setup failed\n"); 1634 goto free; 1635 } 1636 } 1637 slot->rst_n_gpio = slot->data->rst_n_gpio; 1638 slot->cd_gpio = slot->data->cd_gpio; 1639 } 1640 1641 host->hw_name = "PCI"; 1642 host->ops = &sdhci_pci_ops; 1643 host->quirks = chip->quirks; 1644 host->quirks2 = chip->quirks2; 1645 1646 host->irq = pdev->irq; 1647 1648 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1649 if (ret) { 1650 dev_err(&pdev->dev, "cannot request region\n"); 1651 goto cleanup; 1652 } 1653 1654 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1655 1656 if (chip->fixes && chip->fixes->probe_slot) { 1657 ret = chip->fixes->probe_slot(slot); 1658 if (ret) 1659 goto cleanup; 1660 } 1661 1662 if (gpio_is_valid(slot->rst_n_gpio)) { 1663 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1664 gpio_direction_output(slot->rst_n_gpio, 1); 1665 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1666 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1667 } else { 1668 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1669 slot->rst_n_gpio = -EINVAL; 1670 } 1671 } 1672 1673 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; 1674 host->mmc->slotno = slotno; 1675 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1676 1677 if (slot->cd_idx >= 0 && 1678 mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx, 1679 slot->cd_override_level, 0, NULL)) { 1680 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 1681 slot->cd_idx = -1; 1682 } 1683 1684 ret = sdhci_add_host(host); 1685 if (ret) 1686 goto remove; 1687 1688 sdhci_pci_add_own_cd(slot); 1689 1690 /* 1691 * Check if the chip needs a separate GPIO for card detect to wake up 1692 * from runtime suspend. If it is not there, don't allow runtime PM. 1693 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 1694 */ 1695 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 1696 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 1697 chip->allow_runtime_pm = false; 1698 1699 return slot; 1700 1701 remove: 1702 if (chip->fixes && chip->fixes->remove_slot) 1703 chip->fixes->remove_slot(slot, 0); 1704 1705 cleanup: 1706 if (slot->data && slot->data->cleanup) 1707 slot->data->cleanup(slot->data); 1708 1709 free: 1710 sdhci_free_host(host); 1711 1712 return ERR_PTR(ret); 1713 } 1714 1715 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 1716 { 1717 int dead; 1718 u32 scratch; 1719 1720 sdhci_pci_remove_own_cd(slot); 1721 1722 dead = 0; 1723 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 1724 if (scratch == (u32)-1) 1725 dead = 1; 1726 1727 sdhci_remove_host(slot->host, dead); 1728 1729 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 1730 slot->chip->fixes->remove_slot(slot, dead); 1731 1732 if (slot->data && slot->data->cleanup) 1733 slot->data->cleanup(slot->data); 1734 1735 sdhci_free_host(slot->host); 1736 } 1737 1738 static void sdhci_pci_runtime_pm_allow(struct device *dev) 1739 { 1740 pm_suspend_ignore_children(dev, 1); 1741 pm_runtime_set_autosuspend_delay(dev, 50); 1742 pm_runtime_use_autosuspend(dev); 1743 pm_runtime_allow(dev); 1744 /* Stay active until mmc core scans for a card */ 1745 pm_runtime_put_noidle(dev); 1746 } 1747 1748 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 1749 { 1750 pm_runtime_forbid(dev); 1751 pm_runtime_get_noresume(dev); 1752 } 1753 1754 static int sdhci_pci_probe(struct pci_dev *pdev, 1755 const struct pci_device_id *ent) 1756 { 1757 struct sdhci_pci_chip *chip; 1758 struct sdhci_pci_slot *slot; 1759 1760 u8 slots, first_bar; 1761 int ret, i; 1762 1763 BUG_ON(pdev == NULL); 1764 BUG_ON(ent == NULL); 1765 1766 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 1767 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 1768 1769 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 1770 if (ret) 1771 return ret; 1772 1773 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 1774 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 1775 if (slots == 0) 1776 return -ENODEV; 1777 1778 BUG_ON(slots > MAX_SLOTS); 1779 1780 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 1781 if (ret) 1782 return ret; 1783 1784 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 1785 1786 if (first_bar > 5) { 1787 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 1788 return -ENODEV; 1789 } 1790 1791 ret = pcim_enable_device(pdev); 1792 if (ret) 1793 return ret; 1794 1795 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 1796 if (!chip) 1797 return -ENOMEM; 1798 1799 chip->pdev = pdev; 1800 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 1801 if (chip->fixes) { 1802 chip->quirks = chip->fixes->quirks; 1803 chip->quirks2 = chip->fixes->quirks2; 1804 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 1805 } 1806 chip->num_slots = slots; 1807 1808 pci_set_drvdata(pdev, chip); 1809 1810 if (chip->fixes && chip->fixes->probe) { 1811 ret = chip->fixes->probe(chip); 1812 if (ret) 1813 return ret; 1814 } 1815 1816 slots = chip->num_slots; /* Quirk may have changed this */ 1817 1818 for (i = 0; i < slots; i++) { 1819 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 1820 if (IS_ERR(slot)) { 1821 for (i--; i >= 0; i--) 1822 sdhci_pci_remove_slot(chip->slots[i]); 1823 return PTR_ERR(slot); 1824 } 1825 1826 chip->slots[i] = slot; 1827 } 1828 1829 if (chip->allow_runtime_pm) 1830 sdhci_pci_runtime_pm_allow(&pdev->dev); 1831 1832 return 0; 1833 } 1834 1835 static void sdhci_pci_remove(struct pci_dev *pdev) 1836 { 1837 int i; 1838 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1839 1840 if (chip->allow_runtime_pm) 1841 sdhci_pci_runtime_pm_forbid(&pdev->dev); 1842 1843 for (i = 0; i < chip->num_slots; i++) 1844 sdhci_pci_remove_slot(chip->slots[i]); 1845 } 1846 1847 static struct pci_driver sdhci_driver = { 1848 .name = "sdhci-pci", 1849 .id_table = pci_ids, 1850 .probe = sdhci_pci_probe, 1851 .remove = sdhci_pci_remove, 1852 .driver = { 1853 .pm = &sdhci_pci_pm_ops 1854 }, 1855 }; 1856 1857 module_pci_driver(sdhci_driver); 1858 1859 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 1860 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 1861 MODULE_LICENSE("GPL"); 1862