1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 2 * 3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 * 10 * Thanks to the following companies for their support: 11 * 12 * - JMicron (hardware and technical support) 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/highmem.h> 17 #include <linux/module.h> 18 #include <linux/pci.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/slab.h> 21 #include <linux/device.h> 22 #include <linux/mmc/host.h> 23 #include <linux/mmc/mmc.h> 24 #include <linux/scatterlist.h> 25 #include <linux/io.h> 26 #include <linux/gpio.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/mmc/slot-gpio.h> 29 #include <linux/mmc/sdhci-pci-data.h> 30 #include <linux/acpi.h> 31 32 #include "sdhci.h" 33 #include "sdhci-pci.h" 34 #include "sdhci-pci-o2micro.h" 35 36 static int sdhci_pci_enable_dma(struct sdhci_host *host); 37 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width); 38 static void sdhci_pci_hw_reset(struct sdhci_host *host); 39 40 /*****************************************************************************\ 41 * * 42 * Hardware specific quirk handling * 43 * * 44 \*****************************************************************************/ 45 46 static int ricoh_probe(struct sdhci_pci_chip *chip) 47 { 48 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 49 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 50 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 51 return 0; 52 } 53 54 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 55 { 56 slot->host->caps = 57 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 58 & SDHCI_TIMEOUT_CLK_MASK) | 59 60 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 61 & SDHCI_CLOCK_BASE_MASK) | 62 63 SDHCI_TIMEOUT_CLK_UNIT | 64 SDHCI_CAN_VDD_330 | 65 SDHCI_CAN_DO_HISPD | 66 SDHCI_CAN_DO_SDMA; 67 return 0; 68 } 69 70 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 71 { 72 /* Apply a delay to allow controller to settle */ 73 /* Otherwise it becomes confused if card state changed 74 during suspend */ 75 msleep(500); 76 return 0; 77 } 78 79 static const struct sdhci_pci_fixes sdhci_ricoh = { 80 .probe = ricoh_probe, 81 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 82 SDHCI_QUIRK_FORCE_DMA | 83 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 84 }; 85 86 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 87 .probe_slot = ricoh_mmc_probe_slot, 88 .resume = ricoh_mmc_resume, 89 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 90 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 91 SDHCI_QUIRK_NO_CARD_NO_RESET | 92 SDHCI_QUIRK_MISSING_CAPS 93 }; 94 95 static const struct sdhci_pci_fixes sdhci_ene_712 = { 96 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 97 SDHCI_QUIRK_BROKEN_DMA, 98 }; 99 100 static const struct sdhci_pci_fixes sdhci_ene_714 = { 101 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 102 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 103 SDHCI_QUIRK_BROKEN_DMA, 104 }; 105 106 static const struct sdhci_pci_fixes sdhci_cafe = { 107 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 108 SDHCI_QUIRK_NO_BUSY_IRQ | 109 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 110 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 111 }; 112 113 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 114 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 115 }; 116 117 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 118 { 119 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 120 return 0; 121 } 122 123 /* 124 * ADMA operation is disabled for Moorestown platform due to 125 * hardware bugs. 126 */ 127 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 128 { 129 /* 130 * slots number is fixed here for MRST as SDIO3/5 are never used and 131 * have hardware bugs. 132 */ 133 chip->num_slots = 1; 134 return 0; 135 } 136 137 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 138 { 139 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 140 return 0; 141 } 142 143 #ifdef CONFIG_PM 144 145 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 146 { 147 struct sdhci_pci_slot *slot = dev_id; 148 struct sdhci_host *host = slot->host; 149 150 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 151 return IRQ_HANDLED; 152 } 153 154 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 155 { 156 int err, irq, gpio = slot->cd_gpio; 157 158 slot->cd_gpio = -EINVAL; 159 slot->cd_irq = -EINVAL; 160 161 if (!gpio_is_valid(gpio)) 162 return; 163 164 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 165 if (err < 0) 166 goto out; 167 168 err = gpio_direction_input(gpio); 169 if (err < 0) 170 goto out_free; 171 172 irq = gpio_to_irq(gpio); 173 if (irq < 0) 174 goto out_free; 175 176 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 177 IRQF_TRIGGER_FALLING, "sd_cd", slot); 178 if (err) 179 goto out_free; 180 181 slot->cd_gpio = gpio; 182 slot->cd_irq = irq; 183 184 return; 185 186 out_free: 187 devm_gpio_free(&slot->chip->pdev->dev, gpio); 188 out: 189 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 190 } 191 192 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 193 { 194 if (slot->cd_irq >= 0) 195 free_irq(slot->cd_irq, slot); 196 } 197 198 #else 199 200 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 201 { 202 } 203 204 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 205 { 206 } 207 208 #endif 209 210 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 211 { 212 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 213 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC | 214 MMC_CAP2_HC_ERASE_SZ; 215 return 0; 216 } 217 218 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 219 { 220 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 221 return 0; 222 } 223 224 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 225 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 226 .probe_slot = mrst_hc_probe_slot, 227 }; 228 229 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 230 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 231 .probe = mrst_hc_probe, 232 }; 233 234 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 235 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 236 .allow_runtime_pm = true, 237 .own_cd_for_runtime_pm = true, 238 }; 239 240 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 241 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 242 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 243 .allow_runtime_pm = true, 244 .probe_slot = mfd_sdio_probe_slot, 245 }; 246 247 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 248 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 249 .allow_runtime_pm = true, 250 .probe_slot = mfd_emmc_probe_slot, 251 }; 252 253 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 254 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 255 .probe_slot = pch_hc_probe_slot, 256 }; 257 258 enum { 259 INTEL_DSM_FNS = 0, 260 INTEL_DSM_DRV_STRENGTH = 9, 261 INTEL_DSM_D3_RETUNE = 10, 262 }; 263 264 struct intel_host { 265 u32 dsm_fns; 266 int drv_strength; 267 bool d3_retune; 268 }; 269 270 const u8 intel_dsm_uuid[] = { 271 0xA5, 0x3E, 0xC1, 0xF6, 0xCD, 0x65, 0x1F, 0x46, 272 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61, 273 }; 274 275 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 276 unsigned int fn, u32 *result) 277 { 278 union acpi_object *obj; 279 int err = 0; 280 281 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), intel_dsm_uuid, 0, fn, NULL); 282 if (!obj) 283 return -EOPNOTSUPP; 284 285 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { 286 err = -EINVAL; 287 goto out; 288 } 289 290 if (obj->buffer.length >= 4) 291 *result = *(u32 *)obj->buffer.pointer; 292 else if (obj->buffer.length >= 2) 293 *result = *(u16 *)obj->buffer.pointer; 294 else 295 *result = *(u8 *)obj->buffer.pointer; 296 out: 297 ACPI_FREE(obj); 298 299 return err; 300 } 301 302 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 303 unsigned int fn, u32 *result) 304 { 305 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 306 return -EOPNOTSUPP; 307 308 return __intel_dsm(intel_host, dev, fn, result); 309 } 310 311 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 312 struct mmc_host *mmc) 313 { 314 int err; 315 u32 val; 316 317 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 318 if (err) { 319 pr_debug("%s: DSM not supported, error %d\n", 320 mmc_hostname(mmc), err); 321 return; 322 } 323 324 pr_debug("%s: DSM function mask %#x\n", 325 mmc_hostname(mmc), intel_host->dsm_fns); 326 327 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 328 intel_host->drv_strength = err ? 0 : val; 329 330 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 331 intel_host->d3_retune = err ? true : !!val; 332 } 333 334 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 335 { 336 u8 reg; 337 338 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 339 reg |= 0x10; 340 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 341 /* For eMMC, minimum is 1us but give it 9us for good measure */ 342 udelay(9); 343 reg &= ~0x10; 344 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 345 /* For eMMC, minimum is 200us but give it 300us for good measure */ 346 usleep_range(300, 1000); 347 } 348 349 static int intel_select_drive_strength(struct mmc_card *card, 350 unsigned int max_dtr, int host_drv, 351 int card_drv, int *drv_type) 352 { 353 struct sdhci_host *host = mmc_priv(card->host); 354 struct sdhci_pci_slot *slot = sdhci_priv(host); 355 struct intel_host *intel_host = sdhci_pci_priv(slot); 356 357 return intel_host->drv_strength; 358 } 359 360 static int bxt_get_cd(struct mmc_host *mmc) 361 { 362 int gpio_cd = mmc_gpio_get_cd(mmc); 363 struct sdhci_host *host = mmc_priv(mmc); 364 unsigned long flags; 365 int ret = 0; 366 367 if (!gpio_cd) 368 return 0; 369 370 spin_lock_irqsave(&host->lock, flags); 371 372 if (host->flags & SDHCI_DEVICE_DEAD) 373 goto out; 374 375 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 376 out: 377 spin_unlock_irqrestore(&host->lock, flags); 378 379 return ret; 380 } 381 382 static void byt_read_dsm(struct sdhci_pci_slot *slot) 383 { 384 struct intel_host *intel_host = sdhci_pci_priv(slot); 385 struct device *dev = &slot->chip->pdev->dev; 386 struct mmc_host *mmc = slot->host->mmc; 387 388 intel_dsm_init(intel_host, dev, mmc); 389 slot->chip->rpm_retune = intel_host->d3_retune; 390 } 391 392 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 393 { 394 byt_read_dsm(slot); 395 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 396 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 397 MMC_CAP_CMD_DURING_TFR | 398 MMC_CAP_WAIT_WHILE_BUSY; 399 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ; 400 slot->hw_reset = sdhci_pci_int_hw_reset; 401 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 402 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 403 slot->host->mmc_host_ops.select_drive_strength = 404 intel_select_drive_strength; 405 return 0; 406 } 407 408 #ifdef CONFIG_ACPI 409 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 410 { 411 acpi_status status; 412 unsigned long long max_freq; 413 414 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 415 "MXFQ", NULL, &max_freq); 416 if (ACPI_FAILURE(status)) { 417 dev_err(&slot->chip->pdev->dev, 418 "MXFQ not found in acpi table\n"); 419 return -EINVAL; 420 } 421 422 slot->host->mmc->f_max = max_freq * 1000000; 423 424 return 0; 425 } 426 #else 427 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 428 { 429 return 0; 430 } 431 #endif 432 433 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 434 { 435 int err; 436 437 byt_read_dsm(slot); 438 439 err = ni_set_max_freq(slot); 440 if (err) 441 return err; 442 443 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 444 MMC_CAP_WAIT_WHILE_BUSY; 445 return 0; 446 } 447 448 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 449 { 450 byt_read_dsm(slot); 451 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 452 MMC_CAP_WAIT_WHILE_BUSY; 453 return 0; 454 } 455 456 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 457 { 458 byt_read_dsm(slot); 459 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 460 slot->cd_idx = 0; 461 slot->cd_override_level = true; 462 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 463 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 464 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 465 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) { 466 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 467 slot->host->mmc->caps |= MMC_CAP_AGGRESSIVE_PM; 468 } 469 470 return 0; 471 } 472 473 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 474 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 475 476 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 477 unsigned short vdd) 478 { 479 int cntr; 480 u8 reg; 481 482 sdhci_set_power(host, mode, vdd); 483 484 if (mode == MMC_POWER_OFF) 485 return; 486 487 spin_unlock_irq(&host->lock); 488 489 /* 490 * Bus power might not enable after D3 -> D0 transition due to the 491 * present state not yet having propagated. Retry for up to 2ms. 492 */ 493 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 494 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 495 if (reg & SDHCI_POWER_ON) 496 break; 497 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 498 reg |= SDHCI_POWER_ON; 499 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 500 } 501 502 spin_lock_irq(&host->lock); 503 } 504 505 static const struct sdhci_ops sdhci_intel_byt_ops = { 506 .set_clock = sdhci_set_clock, 507 .set_power = sdhci_intel_set_power, 508 .enable_dma = sdhci_pci_enable_dma, 509 .set_bus_width = sdhci_pci_set_bus_width, 510 .reset = sdhci_reset, 511 .set_uhs_signaling = sdhci_set_uhs_signaling, 512 .hw_reset = sdhci_pci_hw_reset, 513 }; 514 515 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 516 .allow_runtime_pm = true, 517 .probe_slot = byt_emmc_probe_slot, 518 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 519 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 520 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 521 SDHCI_QUIRK2_STOP_WITH_TC, 522 .ops = &sdhci_intel_byt_ops, 523 .priv_size = sizeof(struct intel_host), 524 }; 525 526 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 527 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 528 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 529 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 530 .allow_runtime_pm = true, 531 .probe_slot = ni_byt_sdio_probe_slot, 532 .ops = &sdhci_intel_byt_ops, 533 .priv_size = sizeof(struct intel_host), 534 }; 535 536 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 537 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 538 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 539 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 540 .allow_runtime_pm = true, 541 .probe_slot = byt_sdio_probe_slot, 542 .ops = &sdhci_intel_byt_ops, 543 .priv_size = sizeof(struct intel_host), 544 }; 545 546 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 547 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 548 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 549 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 550 SDHCI_QUIRK2_STOP_WITH_TC, 551 .allow_runtime_pm = true, 552 .own_cd_for_runtime_pm = true, 553 .probe_slot = byt_sd_probe_slot, 554 .ops = &sdhci_intel_byt_ops, 555 .priv_size = sizeof(struct intel_host), 556 }; 557 558 /* Define Host controllers for Intel Merrifield platform */ 559 #define INTEL_MRFLD_EMMC_0 0 560 #define INTEL_MRFLD_EMMC_1 1 561 #define INTEL_MRFLD_SD 2 562 #define INTEL_MRFLD_SDIO 3 563 564 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 565 { 566 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 567 568 switch (func) { 569 case INTEL_MRFLD_EMMC_0: 570 case INTEL_MRFLD_EMMC_1: 571 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 572 MMC_CAP_8_BIT_DATA | 573 MMC_CAP_1_8V_DDR; 574 break; 575 case INTEL_MRFLD_SD: 576 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 577 break; 578 case INTEL_MRFLD_SDIO: 579 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 580 MMC_CAP_POWER_OFF_CARD; 581 break; 582 default: 583 return -ENODEV; 584 } 585 return 0; 586 } 587 588 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 589 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 590 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 591 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 592 .allow_runtime_pm = true, 593 .probe_slot = intel_mrfld_mmc_probe_slot, 594 }; 595 596 /* O2Micro extra registers */ 597 #define O2_SD_LOCK_WP 0xD3 598 #define O2_SD_MULTI_VCC3V 0xEE 599 #define O2_SD_CLKREQ 0xEC 600 #define O2_SD_CAPS 0xE0 601 #define O2_SD_ADMA1 0xE2 602 #define O2_SD_ADMA2 0xE7 603 #define O2_SD_INF_MOD 0xF1 604 605 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 606 { 607 u8 scratch; 608 int ret; 609 610 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 611 if (ret) 612 return ret; 613 614 /* 615 * Turn PMOS on [bit 0], set over current detection to 2.4 V 616 * [bit 1:2] and enable over current debouncing [bit 6]. 617 */ 618 if (on) 619 scratch |= 0x47; 620 else 621 scratch &= ~0x47; 622 623 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 624 } 625 626 static int jmicron_probe(struct sdhci_pci_chip *chip) 627 { 628 int ret; 629 u16 mmcdev = 0; 630 631 if (chip->pdev->revision == 0) { 632 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 633 SDHCI_QUIRK_32BIT_DMA_SIZE | 634 SDHCI_QUIRK_32BIT_ADMA_SIZE | 635 SDHCI_QUIRK_RESET_AFTER_REQUEST | 636 SDHCI_QUIRK_BROKEN_SMALL_PIO; 637 } 638 639 /* 640 * JMicron chips can have two interfaces to the same hardware 641 * in order to work around limitations in Microsoft's driver. 642 * We need to make sure we only bind to one of them. 643 * 644 * This code assumes two things: 645 * 646 * 1. The PCI code adds subfunctions in order. 647 * 648 * 2. The MMC interface has a lower subfunction number 649 * than the SD interface. 650 */ 651 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 652 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 653 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 654 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 655 656 if (mmcdev) { 657 struct pci_dev *sd_dev; 658 659 sd_dev = NULL; 660 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 661 mmcdev, sd_dev)) != NULL) { 662 if ((PCI_SLOT(chip->pdev->devfn) == 663 PCI_SLOT(sd_dev->devfn)) && 664 (chip->pdev->bus == sd_dev->bus)) 665 break; 666 } 667 668 if (sd_dev) { 669 pci_dev_put(sd_dev); 670 dev_info(&chip->pdev->dev, "Refusing to bind to " 671 "secondary interface.\n"); 672 return -ENODEV; 673 } 674 } 675 676 /* 677 * JMicron chips need a bit of a nudge to enable the power 678 * output pins. 679 */ 680 ret = jmicron_pmos(chip, 1); 681 if (ret) { 682 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 683 return ret; 684 } 685 686 /* quirk for unsable RO-detection on JM388 chips */ 687 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 688 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 689 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 690 691 return 0; 692 } 693 694 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 695 { 696 u8 scratch; 697 698 scratch = readb(host->ioaddr + 0xC0); 699 700 if (on) 701 scratch |= 0x01; 702 else 703 scratch &= ~0x01; 704 705 writeb(scratch, host->ioaddr + 0xC0); 706 } 707 708 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 709 { 710 if (slot->chip->pdev->revision == 0) { 711 u16 version; 712 713 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 714 version = (version & SDHCI_VENDOR_VER_MASK) >> 715 SDHCI_VENDOR_VER_SHIFT; 716 717 /* 718 * Older versions of the chip have lots of nasty glitches 719 * in the ADMA engine. It's best just to avoid it 720 * completely. 721 */ 722 if (version < 0xAC) 723 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 724 } 725 726 /* JM388 MMC doesn't support 1.8V while SD supports it */ 727 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 728 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 729 MMC_VDD_29_30 | MMC_VDD_30_31 | 730 MMC_VDD_165_195; /* allow 1.8V */ 731 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 732 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 733 } 734 735 /* 736 * The secondary interface requires a bit set to get the 737 * interrupts. 738 */ 739 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 740 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 741 jmicron_enable_mmc(slot->host, 1); 742 743 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 744 745 return 0; 746 } 747 748 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 749 { 750 if (dead) 751 return; 752 753 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 754 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 755 jmicron_enable_mmc(slot->host, 0); 756 } 757 758 static int jmicron_suspend(struct sdhci_pci_chip *chip) 759 { 760 int i; 761 762 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 763 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 764 for (i = 0; i < chip->num_slots; i++) 765 jmicron_enable_mmc(chip->slots[i]->host, 0); 766 } 767 768 return 0; 769 } 770 771 static int jmicron_resume(struct sdhci_pci_chip *chip) 772 { 773 int ret, i; 774 775 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 776 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 777 for (i = 0; i < chip->num_slots; i++) 778 jmicron_enable_mmc(chip->slots[i]->host, 1); 779 } 780 781 ret = jmicron_pmos(chip, 1); 782 if (ret) { 783 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 784 return ret; 785 } 786 787 return 0; 788 } 789 790 static const struct sdhci_pci_fixes sdhci_o2 = { 791 .probe = sdhci_pci_o2_probe, 792 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 793 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 794 .probe_slot = sdhci_pci_o2_probe_slot, 795 .resume = sdhci_pci_o2_resume, 796 }; 797 798 static const struct sdhci_pci_fixes sdhci_jmicron = { 799 .probe = jmicron_probe, 800 801 .probe_slot = jmicron_probe_slot, 802 .remove_slot = jmicron_remove_slot, 803 804 .suspend = jmicron_suspend, 805 .resume = jmicron_resume, 806 }; 807 808 /* SysKonnect CardBus2SDIO extra registers */ 809 #define SYSKT_CTRL 0x200 810 #define SYSKT_RDFIFO_STAT 0x204 811 #define SYSKT_WRFIFO_STAT 0x208 812 #define SYSKT_POWER_DATA 0x20c 813 #define SYSKT_POWER_330 0xef 814 #define SYSKT_POWER_300 0xf8 815 #define SYSKT_POWER_184 0xcc 816 #define SYSKT_POWER_CMD 0x20d 817 #define SYSKT_POWER_START (1 << 7) 818 #define SYSKT_POWER_STATUS 0x20e 819 #define SYSKT_POWER_STATUS_OK (1 << 0) 820 #define SYSKT_BOARD_REV 0x210 821 #define SYSKT_CHIP_REV 0x211 822 #define SYSKT_CONF_DATA 0x212 823 #define SYSKT_CONF_DATA_1V8 (1 << 2) 824 #define SYSKT_CONF_DATA_2V5 (1 << 1) 825 #define SYSKT_CONF_DATA_3V3 (1 << 0) 826 827 static int syskt_probe(struct sdhci_pci_chip *chip) 828 { 829 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 830 chip->pdev->class &= ~0x0000FF; 831 chip->pdev->class |= PCI_SDHCI_IFDMA; 832 } 833 return 0; 834 } 835 836 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 837 { 838 int tm, ps; 839 840 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 841 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 842 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 843 "board rev %d.%d, chip rev %d.%d\n", 844 board_rev >> 4, board_rev & 0xf, 845 chip_rev >> 4, chip_rev & 0xf); 846 if (chip_rev >= 0x20) 847 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 848 849 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 850 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 851 udelay(50); 852 tm = 10; /* Wait max 1 ms */ 853 do { 854 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 855 if (ps & SYSKT_POWER_STATUS_OK) 856 break; 857 udelay(100); 858 } while (--tm); 859 if (!tm) { 860 dev_err(&slot->chip->pdev->dev, 861 "power regulator never stabilized"); 862 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 863 return -ENODEV; 864 } 865 866 return 0; 867 } 868 869 static const struct sdhci_pci_fixes sdhci_syskt = { 870 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 871 .probe = syskt_probe, 872 .probe_slot = syskt_probe_slot, 873 }; 874 875 static int via_probe(struct sdhci_pci_chip *chip) 876 { 877 if (chip->pdev->revision == 0x10) 878 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 879 880 return 0; 881 } 882 883 static const struct sdhci_pci_fixes sdhci_via = { 884 .probe = via_probe, 885 }; 886 887 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 888 { 889 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 890 return 0; 891 } 892 893 static const struct sdhci_pci_fixes sdhci_rtsx = { 894 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 895 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 896 SDHCI_QUIRK2_BROKEN_DDR50, 897 .probe_slot = rtsx_probe_slot, 898 }; 899 900 /*AMD chipset generation*/ 901 enum amd_chipset_gen { 902 AMD_CHIPSET_BEFORE_ML, 903 AMD_CHIPSET_CZ, 904 AMD_CHIPSET_NL, 905 AMD_CHIPSET_UNKNOWN, 906 }; 907 908 /* AMD registers */ 909 #define AMD_SD_AUTO_PATTERN 0xB8 910 #define AMD_MSLEEP_DURATION 4 911 #define AMD_SD_MISC_CONTROL 0xD0 912 #define AMD_MAX_TUNE_VALUE 0x0B 913 #define AMD_AUTO_TUNE_SEL 0x10800 914 #define AMD_FIFO_PTR 0x30 915 #define AMD_BIT_MASK 0x1F 916 917 static void amd_tuning_reset(struct sdhci_host *host) 918 { 919 unsigned int val; 920 921 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 922 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 923 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 924 925 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 926 val &= ~SDHCI_CTRL_EXEC_TUNING; 927 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 928 } 929 930 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 931 { 932 unsigned int val; 933 934 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 935 val &= ~AMD_BIT_MASK; 936 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 937 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 938 } 939 940 static void amd_enable_manual_tuning(struct pci_dev *pdev) 941 { 942 unsigned int val; 943 944 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 945 val |= AMD_FIFO_PTR; 946 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 947 } 948 949 static int amd_execute_tuning(struct sdhci_host *host, u32 opcode) 950 { 951 struct sdhci_pci_slot *slot = sdhci_priv(host); 952 struct pci_dev *pdev = slot->chip->pdev; 953 u8 valid_win = 0; 954 u8 valid_win_max = 0; 955 u8 valid_win_end = 0; 956 u8 ctrl, tune_around; 957 958 amd_tuning_reset(host); 959 960 for (tune_around = 0; tune_around < 12; tune_around++) { 961 amd_config_tuning_phase(pdev, tune_around); 962 963 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 964 valid_win = 0; 965 msleep(AMD_MSLEEP_DURATION); 966 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 967 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 968 } else if (++valid_win > valid_win_max) { 969 valid_win_max = valid_win; 970 valid_win_end = tune_around; 971 } 972 } 973 974 if (!valid_win_max) { 975 dev_err(&pdev->dev, "no tuning point found\n"); 976 return -EIO; 977 } 978 979 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 980 981 amd_enable_manual_tuning(pdev); 982 983 host->mmc->retune_period = 0; 984 985 return 0; 986 } 987 988 static int amd_probe(struct sdhci_pci_chip *chip) 989 { 990 struct pci_dev *smbus_dev; 991 enum amd_chipset_gen gen; 992 993 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 994 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 995 if (smbus_dev) { 996 gen = AMD_CHIPSET_BEFORE_ML; 997 } else { 998 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 999 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1000 if (smbus_dev) { 1001 if (smbus_dev->revision < 0x51) 1002 gen = AMD_CHIPSET_CZ; 1003 else 1004 gen = AMD_CHIPSET_NL; 1005 } else { 1006 gen = AMD_CHIPSET_UNKNOWN; 1007 } 1008 } 1009 1010 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1011 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1012 1013 return 0; 1014 } 1015 1016 static const struct sdhci_ops amd_sdhci_pci_ops = { 1017 .set_clock = sdhci_set_clock, 1018 .enable_dma = sdhci_pci_enable_dma, 1019 .set_bus_width = sdhci_pci_set_bus_width, 1020 .reset = sdhci_reset, 1021 .set_uhs_signaling = sdhci_set_uhs_signaling, 1022 .platform_execute_tuning = amd_execute_tuning, 1023 }; 1024 1025 static const struct sdhci_pci_fixes sdhci_amd = { 1026 .probe = amd_probe, 1027 .ops = &amd_sdhci_pci_ops, 1028 }; 1029 1030 static const struct pci_device_id pci_ids[] = { 1031 { 1032 .vendor = PCI_VENDOR_ID_RICOH, 1033 .device = PCI_DEVICE_ID_RICOH_R5C822, 1034 .subvendor = PCI_ANY_ID, 1035 .subdevice = PCI_ANY_ID, 1036 .driver_data = (kernel_ulong_t)&sdhci_ricoh, 1037 }, 1038 1039 { 1040 .vendor = PCI_VENDOR_ID_RICOH, 1041 .device = 0x843, 1042 .subvendor = PCI_ANY_ID, 1043 .subdevice = PCI_ANY_ID, 1044 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 1045 }, 1046 1047 { 1048 .vendor = PCI_VENDOR_ID_RICOH, 1049 .device = 0xe822, 1050 .subvendor = PCI_ANY_ID, 1051 .subdevice = PCI_ANY_ID, 1052 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 1053 }, 1054 1055 { 1056 .vendor = PCI_VENDOR_ID_RICOH, 1057 .device = 0xe823, 1058 .subvendor = PCI_ANY_ID, 1059 .subdevice = PCI_ANY_ID, 1060 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, 1061 }, 1062 1063 { 1064 .vendor = PCI_VENDOR_ID_ENE, 1065 .device = PCI_DEVICE_ID_ENE_CB712_SD, 1066 .subvendor = PCI_ANY_ID, 1067 .subdevice = PCI_ANY_ID, 1068 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 1069 }, 1070 1071 { 1072 .vendor = PCI_VENDOR_ID_ENE, 1073 .device = PCI_DEVICE_ID_ENE_CB712_SD_2, 1074 .subvendor = PCI_ANY_ID, 1075 .subdevice = PCI_ANY_ID, 1076 .driver_data = (kernel_ulong_t)&sdhci_ene_712, 1077 }, 1078 1079 { 1080 .vendor = PCI_VENDOR_ID_ENE, 1081 .device = PCI_DEVICE_ID_ENE_CB714_SD, 1082 .subvendor = PCI_ANY_ID, 1083 .subdevice = PCI_ANY_ID, 1084 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 1085 }, 1086 1087 { 1088 .vendor = PCI_VENDOR_ID_ENE, 1089 .device = PCI_DEVICE_ID_ENE_CB714_SD_2, 1090 .subvendor = PCI_ANY_ID, 1091 .subdevice = PCI_ANY_ID, 1092 .driver_data = (kernel_ulong_t)&sdhci_ene_714, 1093 }, 1094 1095 { 1096 .vendor = PCI_VENDOR_ID_MARVELL, 1097 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD, 1098 .subvendor = PCI_ANY_ID, 1099 .subdevice = PCI_ANY_ID, 1100 .driver_data = (kernel_ulong_t)&sdhci_cafe, 1101 }, 1102 1103 { 1104 .vendor = PCI_VENDOR_ID_JMICRON, 1105 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD, 1106 .subvendor = PCI_ANY_ID, 1107 .subdevice = PCI_ANY_ID, 1108 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1109 }, 1110 1111 { 1112 .vendor = PCI_VENDOR_ID_JMICRON, 1113 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC, 1114 .subvendor = PCI_ANY_ID, 1115 .subdevice = PCI_ANY_ID, 1116 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1117 }, 1118 1119 { 1120 .vendor = PCI_VENDOR_ID_JMICRON, 1121 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD, 1122 .subvendor = PCI_ANY_ID, 1123 .subdevice = PCI_ANY_ID, 1124 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1125 }, 1126 1127 { 1128 .vendor = PCI_VENDOR_ID_JMICRON, 1129 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD, 1130 .subvendor = PCI_ANY_ID, 1131 .subdevice = PCI_ANY_ID, 1132 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 1133 }, 1134 1135 { 1136 .vendor = PCI_VENDOR_ID_SYSKONNECT, 1137 .device = 0x8000, 1138 .subvendor = PCI_ANY_ID, 1139 .subdevice = PCI_ANY_ID, 1140 .driver_data = (kernel_ulong_t)&sdhci_syskt, 1141 }, 1142 1143 { 1144 .vendor = PCI_VENDOR_ID_VIA, 1145 .device = 0x95d0, 1146 .subvendor = PCI_ANY_ID, 1147 .subdevice = PCI_ANY_ID, 1148 .driver_data = (kernel_ulong_t)&sdhci_via, 1149 }, 1150 1151 { 1152 .vendor = PCI_VENDOR_ID_REALTEK, 1153 .device = 0x5250, 1154 .subvendor = PCI_ANY_ID, 1155 .subdevice = PCI_ANY_ID, 1156 .driver_data = (kernel_ulong_t)&sdhci_rtsx, 1157 }, 1158 1159 { 1160 .vendor = PCI_VENDOR_ID_INTEL, 1161 .device = PCI_DEVICE_ID_INTEL_QRK_SD, 1162 .subvendor = PCI_ANY_ID, 1163 .subdevice = PCI_ANY_ID, 1164 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk, 1165 }, 1166 1167 { 1168 .vendor = PCI_VENDOR_ID_INTEL, 1169 .device = PCI_DEVICE_ID_INTEL_MRST_SD0, 1170 .subvendor = PCI_ANY_ID, 1171 .subdevice = PCI_ANY_ID, 1172 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0, 1173 }, 1174 1175 { 1176 .vendor = PCI_VENDOR_ID_INTEL, 1177 .device = PCI_DEVICE_ID_INTEL_MRST_SD1, 1178 .subvendor = PCI_ANY_ID, 1179 .subdevice = PCI_ANY_ID, 1180 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 1181 }, 1182 1183 { 1184 .vendor = PCI_VENDOR_ID_INTEL, 1185 .device = PCI_DEVICE_ID_INTEL_MRST_SD2, 1186 .subvendor = PCI_ANY_ID, 1187 .subdevice = PCI_ANY_ID, 1188 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, 1189 }, 1190 1191 { 1192 .vendor = PCI_VENDOR_ID_INTEL, 1193 .device = PCI_DEVICE_ID_INTEL_MFD_SD, 1194 .subvendor = PCI_ANY_ID, 1195 .subdevice = PCI_ANY_ID, 1196 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1197 }, 1198 1199 { 1200 .vendor = PCI_VENDOR_ID_INTEL, 1201 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1, 1202 .subvendor = PCI_ANY_ID, 1203 .subdevice = PCI_ANY_ID, 1204 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1205 }, 1206 1207 { 1208 .vendor = PCI_VENDOR_ID_INTEL, 1209 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2, 1210 .subvendor = PCI_ANY_ID, 1211 .subdevice = PCI_ANY_ID, 1212 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1213 }, 1214 1215 { 1216 .vendor = PCI_VENDOR_ID_INTEL, 1217 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0, 1218 .subvendor = PCI_ANY_ID, 1219 .subdevice = PCI_ANY_ID, 1220 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1221 }, 1222 1223 { 1224 .vendor = PCI_VENDOR_ID_INTEL, 1225 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1, 1226 .subvendor = PCI_ANY_ID, 1227 .subdevice = PCI_ANY_ID, 1228 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1229 }, 1230 1231 { 1232 .vendor = PCI_VENDOR_ID_INTEL, 1233 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0, 1234 .subvendor = PCI_ANY_ID, 1235 .subdevice = PCI_ANY_ID, 1236 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1237 }, 1238 1239 { 1240 .vendor = PCI_VENDOR_ID_INTEL, 1241 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1, 1242 .subvendor = PCI_ANY_ID, 1243 .subdevice = PCI_ANY_ID, 1244 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, 1245 }, 1246 1247 { 1248 .vendor = PCI_VENDOR_ID_INTEL, 1249 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC, 1250 .subvendor = PCI_ANY_ID, 1251 .subdevice = PCI_ANY_ID, 1252 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1253 }, 1254 1255 { 1256 .vendor = PCI_VENDOR_ID_INTEL, 1257 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, 1258 .subvendor = PCI_VENDOR_ID_NI, 1259 .subdevice = 0x7884, 1260 .driver_data = (kernel_ulong_t)&sdhci_ni_byt_sdio, 1261 }, 1262 1263 { 1264 .vendor = PCI_VENDOR_ID_INTEL, 1265 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, 1266 .subvendor = PCI_ANY_ID, 1267 .subdevice = PCI_ANY_ID, 1268 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1269 }, 1270 1271 { 1272 .vendor = PCI_VENDOR_ID_INTEL, 1273 .device = PCI_DEVICE_ID_INTEL_BYT_SD, 1274 .subvendor = PCI_ANY_ID, 1275 .subdevice = PCI_ANY_ID, 1276 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1277 }, 1278 1279 { 1280 .vendor = PCI_VENDOR_ID_INTEL, 1281 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2, 1282 .subvendor = PCI_ANY_ID, 1283 .subdevice = PCI_ANY_ID, 1284 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1285 }, 1286 1287 { 1288 .vendor = PCI_VENDOR_ID_INTEL, 1289 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC, 1290 .subvendor = PCI_ANY_ID, 1291 .subdevice = PCI_ANY_ID, 1292 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1293 }, 1294 1295 { 1296 .vendor = PCI_VENDOR_ID_INTEL, 1297 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO, 1298 .subvendor = PCI_ANY_ID, 1299 .subdevice = PCI_ANY_ID, 1300 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1301 }, 1302 1303 { 1304 .vendor = PCI_VENDOR_ID_INTEL, 1305 .device = PCI_DEVICE_ID_INTEL_BSW_SD, 1306 .subvendor = PCI_ANY_ID, 1307 .subdevice = PCI_ANY_ID, 1308 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1309 }, 1310 1311 { 1312 .vendor = PCI_VENDOR_ID_INTEL, 1313 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0, 1314 .subvendor = PCI_ANY_ID, 1315 .subdevice = PCI_ANY_ID, 1316 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, 1317 }, 1318 1319 { 1320 .vendor = PCI_VENDOR_ID_INTEL, 1321 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1, 1322 .subvendor = PCI_ANY_ID, 1323 .subdevice = PCI_ANY_ID, 1324 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1325 }, 1326 1327 { 1328 .vendor = PCI_VENDOR_ID_INTEL, 1329 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2, 1330 .subvendor = PCI_ANY_ID, 1331 .subdevice = PCI_ANY_ID, 1332 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, 1333 }, 1334 1335 { 1336 .vendor = PCI_VENDOR_ID_INTEL, 1337 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0, 1338 .subvendor = PCI_ANY_ID, 1339 .subdevice = PCI_ANY_ID, 1340 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1341 }, 1342 1343 { 1344 .vendor = PCI_VENDOR_ID_INTEL, 1345 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1, 1346 .subvendor = PCI_ANY_ID, 1347 .subdevice = PCI_ANY_ID, 1348 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, 1349 }, 1350 1351 { 1352 .vendor = PCI_VENDOR_ID_INTEL, 1353 .device = PCI_DEVICE_ID_INTEL_MRFLD_MMC, 1354 .subvendor = PCI_ANY_ID, 1355 .subdevice = PCI_ANY_ID, 1356 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfld_mmc, 1357 }, 1358 1359 { 1360 .vendor = PCI_VENDOR_ID_INTEL, 1361 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC, 1362 .subvendor = PCI_ANY_ID, 1363 .subdevice = PCI_ANY_ID, 1364 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1365 }, 1366 1367 { 1368 .vendor = PCI_VENDOR_ID_INTEL, 1369 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO, 1370 .subvendor = PCI_ANY_ID, 1371 .subdevice = PCI_ANY_ID, 1372 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1373 }, 1374 1375 { 1376 .vendor = PCI_VENDOR_ID_INTEL, 1377 .device = PCI_DEVICE_ID_INTEL_SPT_SD, 1378 .subvendor = PCI_ANY_ID, 1379 .subdevice = PCI_ANY_ID, 1380 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1381 }, 1382 1383 { 1384 .vendor = PCI_VENDOR_ID_INTEL, 1385 .device = PCI_DEVICE_ID_INTEL_DNV_EMMC, 1386 .subvendor = PCI_ANY_ID, 1387 .subdevice = PCI_ANY_ID, 1388 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1389 }, 1390 1391 { 1392 .vendor = PCI_VENDOR_ID_INTEL, 1393 .device = PCI_DEVICE_ID_INTEL_BXT_EMMC, 1394 .subvendor = PCI_ANY_ID, 1395 .subdevice = PCI_ANY_ID, 1396 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1397 }, 1398 1399 { 1400 .vendor = PCI_VENDOR_ID_INTEL, 1401 .device = PCI_DEVICE_ID_INTEL_BXT_SDIO, 1402 .subvendor = PCI_ANY_ID, 1403 .subdevice = PCI_ANY_ID, 1404 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1405 }, 1406 1407 { 1408 .vendor = PCI_VENDOR_ID_INTEL, 1409 .device = PCI_DEVICE_ID_INTEL_BXT_SD, 1410 .subvendor = PCI_ANY_ID, 1411 .subdevice = PCI_ANY_ID, 1412 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1413 }, 1414 1415 { 1416 .vendor = PCI_VENDOR_ID_INTEL, 1417 .device = PCI_DEVICE_ID_INTEL_BXTM_EMMC, 1418 .subvendor = PCI_ANY_ID, 1419 .subdevice = PCI_ANY_ID, 1420 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1421 }, 1422 1423 { 1424 .vendor = PCI_VENDOR_ID_INTEL, 1425 .device = PCI_DEVICE_ID_INTEL_BXTM_SDIO, 1426 .subvendor = PCI_ANY_ID, 1427 .subdevice = PCI_ANY_ID, 1428 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1429 }, 1430 1431 { 1432 .vendor = PCI_VENDOR_ID_INTEL, 1433 .device = PCI_DEVICE_ID_INTEL_BXTM_SD, 1434 .subvendor = PCI_ANY_ID, 1435 .subdevice = PCI_ANY_ID, 1436 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1437 }, 1438 1439 { 1440 .vendor = PCI_VENDOR_ID_INTEL, 1441 .device = PCI_DEVICE_ID_INTEL_APL_EMMC, 1442 .subvendor = PCI_ANY_ID, 1443 .subdevice = PCI_ANY_ID, 1444 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1445 }, 1446 1447 { 1448 .vendor = PCI_VENDOR_ID_INTEL, 1449 .device = PCI_DEVICE_ID_INTEL_APL_SDIO, 1450 .subvendor = PCI_ANY_ID, 1451 .subdevice = PCI_ANY_ID, 1452 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1453 }, 1454 1455 { 1456 .vendor = PCI_VENDOR_ID_INTEL, 1457 .device = PCI_DEVICE_ID_INTEL_APL_SD, 1458 .subvendor = PCI_ANY_ID, 1459 .subdevice = PCI_ANY_ID, 1460 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1461 }, 1462 1463 { 1464 .vendor = PCI_VENDOR_ID_INTEL, 1465 .device = PCI_DEVICE_ID_INTEL_GLK_EMMC, 1466 .subvendor = PCI_ANY_ID, 1467 .subdevice = PCI_ANY_ID, 1468 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, 1469 }, 1470 1471 { 1472 .vendor = PCI_VENDOR_ID_INTEL, 1473 .device = PCI_DEVICE_ID_INTEL_GLK_SDIO, 1474 .subvendor = PCI_ANY_ID, 1475 .subdevice = PCI_ANY_ID, 1476 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, 1477 }, 1478 1479 { 1480 .vendor = PCI_VENDOR_ID_INTEL, 1481 .device = PCI_DEVICE_ID_INTEL_GLK_SD, 1482 .subvendor = PCI_ANY_ID, 1483 .subdevice = PCI_ANY_ID, 1484 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, 1485 }, 1486 1487 { 1488 .vendor = PCI_VENDOR_ID_O2, 1489 .device = PCI_DEVICE_ID_O2_8120, 1490 .subvendor = PCI_ANY_ID, 1491 .subdevice = PCI_ANY_ID, 1492 .driver_data = (kernel_ulong_t)&sdhci_o2, 1493 }, 1494 1495 { 1496 .vendor = PCI_VENDOR_ID_O2, 1497 .device = PCI_DEVICE_ID_O2_8220, 1498 .subvendor = PCI_ANY_ID, 1499 .subdevice = PCI_ANY_ID, 1500 .driver_data = (kernel_ulong_t)&sdhci_o2, 1501 }, 1502 1503 { 1504 .vendor = PCI_VENDOR_ID_O2, 1505 .device = PCI_DEVICE_ID_O2_8221, 1506 .subvendor = PCI_ANY_ID, 1507 .subdevice = PCI_ANY_ID, 1508 .driver_data = (kernel_ulong_t)&sdhci_o2, 1509 }, 1510 1511 { 1512 .vendor = PCI_VENDOR_ID_O2, 1513 .device = PCI_DEVICE_ID_O2_8320, 1514 .subvendor = PCI_ANY_ID, 1515 .subdevice = PCI_ANY_ID, 1516 .driver_data = (kernel_ulong_t)&sdhci_o2, 1517 }, 1518 1519 { 1520 .vendor = PCI_VENDOR_ID_O2, 1521 .device = PCI_DEVICE_ID_O2_8321, 1522 .subvendor = PCI_ANY_ID, 1523 .subdevice = PCI_ANY_ID, 1524 .driver_data = (kernel_ulong_t)&sdhci_o2, 1525 }, 1526 1527 { 1528 .vendor = PCI_VENDOR_ID_O2, 1529 .device = PCI_DEVICE_ID_O2_FUJIN2, 1530 .subvendor = PCI_ANY_ID, 1531 .subdevice = PCI_ANY_ID, 1532 .driver_data = (kernel_ulong_t)&sdhci_o2, 1533 }, 1534 1535 { 1536 .vendor = PCI_VENDOR_ID_O2, 1537 .device = PCI_DEVICE_ID_O2_SDS0, 1538 .subvendor = PCI_ANY_ID, 1539 .subdevice = PCI_ANY_ID, 1540 .driver_data = (kernel_ulong_t)&sdhci_o2, 1541 }, 1542 1543 { 1544 .vendor = PCI_VENDOR_ID_O2, 1545 .device = PCI_DEVICE_ID_O2_SDS1, 1546 .subvendor = PCI_ANY_ID, 1547 .subdevice = PCI_ANY_ID, 1548 .driver_data = (kernel_ulong_t)&sdhci_o2, 1549 }, 1550 1551 { 1552 .vendor = PCI_VENDOR_ID_O2, 1553 .device = PCI_DEVICE_ID_O2_SEABIRD0, 1554 .subvendor = PCI_ANY_ID, 1555 .subdevice = PCI_ANY_ID, 1556 .driver_data = (kernel_ulong_t)&sdhci_o2, 1557 }, 1558 1559 { 1560 .vendor = PCI_VENDOR_ID_O2, 1561 .device = PCI_DEVICE_ID_O2_SEABIRD1, 1562 .subvendor = PCI_ANY_ID, 1563 .subdevice = PCI_ANY_ID, 1564 .driver_data = (kernel_ulong_t)&sdhci_o2, 1565 }, 1566 { 1567 .vendor = PCI_VENDOR_ID_AMD, 1568 .device = PCI_ANY_ID, 1569 .class = PCI_CLASS_SYSTEM_SDHCI << 8, 1570 .class_mask = 0xFFFF00, 1571 .subvendor = PCI_ANY_ID, 1572 .subdevice = PCI_ANY_ID, 1573 .driver_data = (kernel_ulong_t)&sdhci_amd, 1574 }, 1575 { /* Generic SD host controller */ 1576 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) 1577 }, 1578 1579 { /* end: all zeroes */ }, 1580 }; 1581 1582 MODULE_DEVICE_TABLE(pci, pci_ids); 1583 1584 /*****************************************************************************\ 1585 * * 1586 * SDHCI core callbacks * 1587 * * 1588 \*****************************************************************************/ 1589 1590 static int sdhci_pci_enable_dma(struct sdhci_host *host) 1591 { 1592 struct sdhci_pci_slot *slot; 1593 struct pci_dev *pdev; 1594 1595 slot = sdhci_priv(host); 1596 pdev = slot->chip->pdev; 1597 1598 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1599 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1600 (host->flags & SDHCI_USE_SDMA)) { 1601 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1602 "doesn't fully claim to support it.\n"); 1603 } 1604 1605 pci_set_master(pdev); 1606 1607 return 0; 1608 } 1609 1610 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width) 1611 { 1612 u8 ctrl; 1613 1614 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1615 1616 switch (width) { 1617 case MMC_BUS_WIDTH_8: 1618 ctrl |= SDHCI_CTRL_8BITBUS; 1619 ctrl &= ~SDHCI_CTRL_4BITBUS; 1620 break; 1621 case MMC_BUS_WIDTH_4: 1622 ctrl |= SDHCI_CTRL_4BITBUS; 1623 ctrl &= ~SDHCI_CTRL_8BITBUS; 1624 break; 1625 default: 1626 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS); 1627 break; 1628 } 1629 1630 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1631 } 1632 1633 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1634 { 1635 struct sdhci_pci_slot *slot = sdhci_priv(host); 1636 int rst_n_gpio = slot->rst_n_gpio; 1637 1638 if (!gpio_is_valid(rst_n_gpio)) 1639 return; 1640 gpio_set_value_cansleep(rst_n_gpio, 0); 1641 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1642 udelay(10); 1643 gpio_set_value_cansleep(rst_n_gpio, 1); 1644 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1645 usleep_range(300, 1000); 1646 } 1647 1648 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1649 { 1650 struct sdhci_pci_slot *slot = sdhci_priv(host); 1651 1652 if (slot->hw_reset) 1653 slot->hw_reset(host); 1654 } 1655 1656 static const struct sdhci_ops sdhci_pci_ops = { 1657 .set_clock = sdhci_set_clock, 1658 .enable_dma = sdhci_pci_enable_dma, 1659 .set_bus_width = sdhci_pci_set_bus_width, 1660 .reset = sdhci_reset, 1661 .set_uhs_signaling = sdhci_set_uhs_signaling, 1662 .hw_reset = sdhci_pci_hw_reset, 1663 }; 1664 1665 /*****************************************************************************\ 1666 * * 1667 * Suspend/resume * 1668 * * 1669 \*****************************************************************************/ 1670 1671 #ifdef CONFIG_PM_SLEEP 1672 static int sdhci_pci_suspend(struct device *dev) 1673 { 1674 struct pci_dev *pdev = to_pci_dev(dev); 1675 struct sdhci_pci_chip *chip; 1676 struct sdhci_pci_slot *slot; 1677 struct sdhci_host *host; 1678 mmc_pm_flag_t slot_pm_flags; 1679 mmc_pm_flag_t pm_flags = 0; 1680 int i, ret; 1681 1682 chip = pci_get_drvdata(pdev); 1683 if (!chip) 1684 return 0; 1685 1686 for (i = 0; i < chip->num_slots; i++) { 1687 slot = chip->slots[i]; 1688 if (!slot) 1689 continue; 1690 1691 host = slot->host; 1692 1693 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 1694 mmc_retune_needed(host->mmc); 1695 1696 ret = sdhci_suspend_host(host); 1697 1698 if (ret) 1699 goto err_pci_suspend; 1700 1701 slot_pm_flags = host->mmc->pm_flags; 1702 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1703 sdhci_enable_irq_wakeups(host); 1704 1705 pm_flags |= slot_pm_flags; 1706 } 1707 1708 if (chip->fixes && chip->fixes->suspend) { 1709 ret = chip->fixes->suspend(chip); 1710 if (ret) 1711 goto err_pci_suspend; 1712 } 1713 1714 if (pm_flags & MMC_PM_KEEP_POWER) { 1715 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) 1716 device_init_wakeup(dev, true); 1717 else 1718 device_init_wakeup(dev, false); 1719 } else 1720 device_init_wakeup(dev, false); 1721 1722 return 0; 1723 1724 err_pci_suspend: 1725 while (--i >= 0) 1726 sdhci_resume_host(chip->slots[i]->host); 1727 return ret; 1728 } 1729 1730 static int sdhci_pci_resume(struct device *dev) 1731 { 1732 struct pci_dev *pdev = to_pci_dev(dev); 1733 struct sdhci_pci_chip *chip; 1734 struct sdhci_pci_slot *slot; 1735 int i, ret; 1736 1737 chip = pci_get_drvdata(pdev); 1738 if (!chip) 1739 return 0; 1740 1741 if (chip->fixes && chip->fixes->resume) { 1742 ret = chip->fixes->resume(chip); 1743 if (ret) 1744 return ret; 1745 } 1746 1747 for (i = 0; i < chip->num_slots; i++) { 1748 slot = chip->slots[i]; 1749 if (!slot) 1750 continue; 1751 1752 ret = sdhci_resume_host(slot->host); 1753 if (ret) 1754 return ret; 1755 } 1756 1757 return 0; 1758 } 1759 #endif 1760 1761 #ifdef CONFIG_PM 1762 static int sdhci_pci_runtime_suspend(struct device *dev) 1763 { 1764 struct pci_dev *pdev = to_pci_dev(dev); 1765 struct sdhci_pci_chip *chip; 1766 struct sdhci_pci_slot *slot; 1767 struct sdhci_host *host; 1768 int i, ret; 1769 1770 chip = pci_get_drvdata(pdev); 1771 if (!chip) 1772 return 0; 1773 1774 for (i = 0; i < chip->num_slots; i++) { 1775 slot = chip->slots[i]; 1776 if (!slot) 1777 continue; 1778 1779 host = slot->host; 1780 1781 ret = sdhci_runtime_suspend_host(host); 1782 if (ret) 1783 goto err_pci_runtime_suspend; 1784 1785 if (chip->rpm_retune && 1786 host->tuning_mode != SDHCI_TUNING_MODE_3) 1787 mmc_retune_needed(host->mmc); 1788 } 1789 1790 if (chip->fixes && chip->fixes->suspend) { 1791 ret = chip->fixes->suspend(chip); 1792 if (ret) 1793 goto err_pci_runtime_suspend; 1794 } 1795 1796 return 0; 1797 1798 err_pci_runtime_suspend: 1799 while (--i >= 0) 1800 sdhci_runtime_resume_host(chip->slots[i]->host); 1801 return ret; 1802 } 1803 1804 static int sdhci_pci_runtime_resume(struct device *dev) 1805 { 1806 struct pci_dev *pdev = to_pci_dev(dev); 1807 struct sdhci_pci_chip *chip; 1808 struct sdhci_pci_slot *slot; 1809 int i, ret; 1810 1811 chip = pci_get_drvdata(pdev); 1812 if (!chip) 1813 return 0; 1814 1815 if (chip->fixes && chip->fixes->resume) { 1816 ret = chip->fixes->resume(chip); 1817 if (ret) 1818 return ret; 1819 } 1820 1821 for (i = 0; i < chip->num_slots; i++) { 1822 slot = chip->slots[i]; 1823 if (!slot) 1824 continue; 1825 1826 ret = sdhci_runtime_resume_host(slot->host); 1827 if (ret) 1828 return ret; 1829 } 1830 1831 return 0; 1832 } 1833 #endif 1834 1835 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1836 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1837 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1838 sdhci_pci_runtime_resume, NULL) 1839 }; 1840 1841 /*****************************************************************************\ 1842 * * 1843 * Device probing/removal * 1844 * * 1845 \*****************************************************************************/ 1846 1847 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1848 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1849 int slotno) 1850 { 1851 struct sdhci_pci_slot *slot; 1852 struct sdhci_host *host; 1853 int ret, bar = first_bar + slotno; 1854 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 1855 1856 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1857 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1858 return ERR_PTR(-ENODEV); 1859 } 1860 1861 if (pci_resource_len(pdev, bar) < 0x100) { 1862 dev_err(&pdev->dev, "Invalid iomem size. You may " 1863 "experience problems.\n"); 1864 } 1865 1866 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1867 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1868 return ERR_PTR(-ENODEV); 1869 } 1870 1871 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1872 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1873 return ERR_PTR(-ENODEV); 1874 } 1875 1876 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 1877 if (IS_ERR(host)) { 1878 dev_err(&pdev->dev, "cannot allocate host\n"); 1879 return ERR_CAST(host); 1880 } 1881 1882 slot = sdhci_priv(host); 1883 1884 slot->chip = chip; 1885 slot->host = host; 1886 slot->rst_n_gpio = -EINVAL; 1887 slot->cd_gpio = -EINVAL; 1888 slot->cd_idx = -1; 1889 1890 /* Retrieve platform data if there is any */ 1891 if (*sdhci_pci_get_data) 1892 slot->data = sdhci_pci_get_data(pdev, slotno); 1893 1894 if (slot->data) { 1895 if (slot->data->setup) { 1896 ret = slot->data->setup(slot->data); 1897 if (ret) { 1898 dev_err(&pdev->dev, "platform setup failed\n"); 1899 goto free; 1900 } 1901 } 1902 slot->rst_n_gpio = slot->data->rst_n_gpio; 1903 slot->cd_gpio = slot->data->cd_gpio; 1904 } 1905 1906 host->hw_name = "PCI"; 1907 host->ops = chip->fixes && chip->fixes->ops ? 1908 chip->fixes->ops : 1909 &sdhci_pci_ops; 1910 host->quirks = chip->quirks; 1911 host->quirks2 = chip->quirks2; 1912 1913 host->irq = pdev->irq; 1914 1915 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1916 if (ret) { 1917 dev_err(&pdev->dev, "cannot request region\n"); 1918 goto cleanup; 1919 } 1920 1921 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1922 1923 if (chip->fixes && chip->fixes->probe_slot) { 1924 ret = chip->fixes->probe_slot(slot); 1925 if (ret) 1926 goto cleanup; 1927 } 1928 1929 if (gpio_is_valid(slot->rst_n_gpio)) { 1930 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1931 gpio_direction_output(slot->rst_n_gpio, 1); 1932 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1933 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1934 } else { 1935 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1936 slot->rst_n_gpio = -EINVAL; 1937 } 1938 } 1939 1940 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; 1941 host->mmc->slotno = slotno; 1942 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1943 1944 if (slot->cd_idx >= 0) { 1945 ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx, 1946 slot->cd_override_level, 0, NULL); 1947 if (ret == -EPROBE_DEFER) 1948 goto remove; 1949 1950 if (ret) { 1951 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 1952 slot->cd_idx = -1; 1953 } 1954 } 1955 1956 ret = sdhci_add_host(host); 1957 if (ret) 1958 goto remove; 1959 1960 sdhci_pci_add_own_cd(slot); 1961 1962 /* 1963 * Check if the chip needs a separate GPIO for card detect to wake up 1964 * from runtime suspend. If it is not there, don't allow runtime PM. 1965 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 1966 */ 1967 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 1968 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 1969 chip->allow_runtime_pm = false; 1970 1971 return slot; 1972 1973 remove: 1974 if (chip->fixes && chip->fixes->remove_slot) 1975 chip->fixes->remove_slot(slot, 0); 1976 1977 cleanup: 1978 if (slot->data && slot->data->cleanup) 1979 slot->data->cleanup(slot->data); 1980 1981 free: 1982 sdhci_free_host(host); 1983 1984 return ERR_PTR(ret); 1985 } 1986 1987 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 1988 { 1989 int dead; 1990 u32 scratch; 1991 1992 sdhci_pci_remove_own_cd(slot); 1993 1994 dead = 0; 1995 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 1996 if (scratch == (u32)-1) 1997 dead = 1; 1998 1999 sdhci_remove_host(slot->host, dead); 2000 2001 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 2002 slot->chip->fixes->remove_slot(slot, dead); 2003 2004 if (slot->data && slot->data->cleanup) 2005 slot->data->cleanup(slot->data); 2006 2007 sdhci_free_host(slot->host); 2008 } 2009 2010 static void sdhci_pci_runtime_pm_allow(struct device *dev) 2011 { 2012 pm_suspend_ignore_children(dev, 1); 2013 pm_runtime_set_autosuspend_delay(dev, 50); 2014 pm_runtime_use_autosuspend(dev); 2015 pm_runtime_allow(dev); 2016 /* Stay active until mmc core scans for a card */ 2017 pm_runtime_put_noidle(dev); 2018 } 2019 2020 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 2021 { 2022 pm_runtime_forbid(dev); 2023 pm_runtime_get_noresume(dev); 2024 } 2025 2026 static int sdhci_pci_probe(struct pci_dev *pdev, 2027 const struct pci_device_id *ent) 2028 { 2029 struct sdhci_pci_chip *chip; 2030 struct sdhci_pci_slot *slot; 2031 2032 u8 slots, first_bar; 2033 int ret, i; 2034 2035 BUG_ON(pdev == NULL); 2036 BUG_ON(ent == NULL); 2037 2038 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 2039 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 2040 2041 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 2042 if (ret) 2043 return ret; 2044 2045 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 2046 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 2047 if (slots == 0) 2048 return -ENODEV; 2049 2050 BUG_ON(slots > MAX_SLOTS); 2051 2052 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 2053 if (ret) 2054 return ret; 2055 2056 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 2057 2058 if (first_bar > 5) { 2059 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 2060 return -ENODEV; 2061 } 2062 2063 ret = pcim_enable_device(pdev); 2064 if (ret) 2065 return ret; 2066 2067 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 2068 if (!chip) 2069 return -ENOMEM; 2070 2071 chip->pdev = pdev; 2072 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 2073 if (chip->fixes) { 2074 chip->quirks = chip->fixes->quirks; 2075 chip->quirks2 = chip->fixes->quirks2; 2076 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 2077 } 2078 chip->num_slots = slots; 2079 chip->pm_retune = true; 2080 chip->rpm_retune = true; 2081 2082 pci_set_drvdata(pdev, chip); 2083 2084 if (chip->fixes && chip->fixes->probe) { 2085 ret = chip->fixes->probe(chip); 2086 if (ret) 2087 return ret; 2088 } 2089 2090 slots = chip->num_slots; /* Quirk may have changed this */ 2091 2092 for (i = 0; i < slots; i++) { 2093 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 2094 if (IS_ERR(slot)) { 2095 for (i--; i >= 0; i--) 2096 sdhci_pci_remove_slot(chip->slots[i]); 2097 return PTR_ERR(slot); 2098 } 2099 2100 chip->slots[i] = slot; 2101 } 2102 2103 if (chip->allow_runtime_pm) 2104 sdhci_pci_runtime_pm_allow(&pdev->dev); 2105 2106 return 0; 2107 } 2108 2109 static void sdhci_pci_remove(struct pci_dev *pdev) 2110 { 2111 int i; 2112 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 2113 2114 if (chip->allow_runtime_pm) 2115 sdhci_pci_runtime_pm_forbid(&pdev->dev); 2116 2117 for (i = 0; i < chip->num_slots; i++) 2118 sdhci_pci_remove_slot(chip->slots[i]); 2119 } 2120 2121 static struct pci_driver sdhci_driver = { 2122 .name = "sdhci-pci", 2123 .id_table = pci_ids, 2124 .probe = sdhci_pci_probe, 2125 .remove = sdhci_pci_remove, 2126 .driver = { 2127 .pm = &sdhci_pci_pm_ops 2128 }, 2129 }; 2130 2131 module_pci_driver(sdhci_driver); 2132 2133 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 2134 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 2135 MODULE_LICENSE("GPL"); 2136