1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 2 * 3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 * 10 * Thanks to the following companies for their support: 11 * 12 * - JMicron (hardware and technical support) 13 */ 14 15 #include <linux/bitfield.h> 16 #include <linux/string.h> 17 #include <linux/delay.h> 18 #include <linux/highmem.h> 19 #include <linux/module.h> 20 #include <linux/pci.h> 21 #include <linux/dma-mapping.h> 22 #include <linux/slab.h> 23 #include <linux/device.h> 24 #include <linux/mmc/host.h> 25 #include <linux/mmc/mmc.h> 26 #include <linux/scatterlist.h> 27 #include <linux/io.h> 28 #include <linux/gpio.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/mmc/slot-gpio.h> 31 #include <linux/mmc/sdhci-pci-data.h> 32 #include <linux/acpi.h> 33 34 #include "cqhci.h" 35 36 #include "sdhci.h" 37 #include "sdhci-pci.h" 38 39 static void sdhci_pci_hw_reset(struct sdhci_host *host); 40 41 #ifdef CONFIG_PM_SLEEP 42 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip) 43 { 44 mmc_pm_flag_t pm_flags = 0; 45 bool cap_cd_wake = false; 46 int i; 47 48 for (i = 0; i < chip->num_slots; i++) { 49 struct sdhci_pci_slot *slot = chip->slots[i]; 50 51 if (slot) { 52 pm_flags |= slot->host->mmc->pm_flags; 53 if (slot->host->mmc->caps & MMC_CAP_CD_WAKE) 54 cap_cd_wake = true; 55 } 56 } 57 58 if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ)) 59 return device_wakeup_enable(&chip->pdev->dev); 60 else if (!cap_cd_wake) 61 return device_wakeup_disable(&chip->pdev->dev); 62 63 return 0; 64 } 65 66 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 67 { 68 int i, ret; 69 70 sdhci_pci_init_wakeup(chip); 71 72 for (i = 0; i < chip->num_slots; i++) { 73 struct sdhci_pci_slot *slot = chip->slots[i]; 74 struct sdhci_host *host; 75 76 if (!slot) 77 continue; 78 79 host = slot->host; 80 81 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 82 mmc_retune_needed(host->mmc); 83 84 ret = sdhci_suspend_host(host); 85 if (ret) 86 goto err_pci_suspend; 87 88 if (device_may_wakeup(&chip->pdev->dev)) 89 mmc_gpio_set_cd_wake(host->mmc, true); 90 } 91 92 return 0; 93 94 err_pci_suspend: 95 while (--i >= 0) 96 sdhci_resume_host(chip->slots[i]->host); 97 return ret; 98 } 99 100 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip) 101 { 102 struct sdhci_pci_slot *slot; 103 int i, ret; 104 105 for (i = 0; i < chip->num_slots; i++) { 106 slot = chip->slots[i]; 107 if (!slot) 108 continue; 109 110 ret = sdhci_resume_host(slot->host); 111 if (ret) 112 return ret; 113 114 mmc_gpio_set_cd_wake(slot->host->mmc, false); 115 } 116 117 return 0; 118 } 119 120 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip) 121 { 122 int ret; 123 124 ret = cqhci_suspend(chip->slots[0]->host->mmc); 125 if (ret) 126 return ret; 127 128 return sdhci_pci_suspend_host(chip); 129 } 130 131 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip) 132 { 133 int ret; 134 135 ret = sdhci_pci_resume_host(chip); 136 if (ret) 137 return ret; 138 139 return cqhci_resume(chip->slots[0]->host->mmc); 140 } 141 #endif 142 143 #ifdef CONFIG_PM 144 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip) 145 { 146 struct sdhci_pci_slot *slot; 147 struct sdhci_host *host; 148 int i, ret; 149 150 for (i = 0; i < chip->num_slots; i++) { 151 slot = chip->slots[i]; 152 if (!slot) 153 continue; 154 155 host = slot->host; 156 157 ret = sdhci_runtime_suspend_host(host); 158 if (ret) 159 goto err_pci_runtime_suspend; 160 161 if (chip->rpm_retune && 162 host->tuning_mode != SDHCI_TUNING_MODE_3) 163 mmc_retune_needed(host->mmc); 164 } 165 166 return 0; 167 168 err_pci_runtime_suspend: 169 while (--i >= 0) 170 sdhci_runtime_resume_host(chip->slots[i]->host); 171 return ret; 172 } 173 174 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip) 175 { 176 struct sdhci_pci_slot *slot; 177 int i, ret; 178 179 for (i = 0; i < chip->num_slots; i++) { 180 slot = chip->slots[i]; 181 if (!slot) 182 continue; 183 184 ret = sdhci_runtime_resume_host(slot->host); 185 if (ret) 186 return ret; 187 } 188 189 return 0; 190 } 191 192 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip) 193 { 194 int ret; 195 196 ret = cqhci_suspend(chip->slots[0]->host->mmc); 197 if (ret) 198 return ret; 199 200 return sdhci_pci_runtime_suspend_host(chip); 201 } 202 203 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip) 204 { 205 int ret; 206 207 ret = sdhci_pci_runtime_resume_host(chip); 208 if (ret) 209 return ret; 210 211 return cqhci_resume(chip->slots[0]->host->mmc); 212 } 213 #endif 214 215 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask) 216 { 217 int cmd_error = 0; 218 int data_error = 0; 219 220 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 221 return intmask; 222 223 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 224 225 return 0; 226 } 227 228 static void sdhci_pci_dumpregs(struct mmc_host *mmc) 229 { 230 sdhci_dumpregs(mmc_priv(mmc)); 231 } 232 233 /*****************************************************************************\ 234 * * 235 * Hardware specific quirk handling * 236 * * 237 \*****************************************************************************/ 238 239 static int ricoh_probe(struct sdhci_pci_chip *chip) 240 { 241 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 242 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 243 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 244 return 0; 245 } 246 247 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 248 { 249 slot->host->caps = 250 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 251 & SDHCI_TIMEOUT_CLK_MASK) | 252 253 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 254 & SDHCI_CLOCK_BASE_MASK) | 255 256 SDHCI_TIMEOUT_CLK_UNIT | 257 SDHCI_CAN_VDD_330 | 258 SDHCI_CAN_DO_HISPD | 259 SDHCI_CAN_DO_SDMA; 260 return 0; 261 } 262 263 #ifdef CONFIG_PM_SLEEP 264 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 265 { 266 /* Apply a delay to allow controller to settle */ 267 /* Otherwise it becomes confused if card state changed 268 during suspend */ 269 msleep(500); 270 return sdhci_pci_resume_host(chip); 271 } 272 #endif 273 274 static const struct sdhci_pci_fixes sdhci_ricoh = { 275 .probe = ricoh_probe, 276 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 277 SDHCI_QUIRK_FORCE_DMA | 278 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 279 }; 280 281 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 282 .probe_slot = ricoh_mmc_probe_slot, 283 #ifdef CONFIG_PM_SLEEP 284 .resume = ricoh_mmc_resume, 285 #endif 286 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 287 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 288 SDHCI_QUIRK_NO_CARD_NO_RESET | 289 SDHCI_QUIRK_MISSING_CAPS 290 }; 291 292 static const struct sdhci_pci_fixes sdhci_ene_712 = { 293 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 294 SDHCI_QUIRK_BROKEN_DMA, 295 }; 296 297 static const struct sdhci_pci_fixes sdhci_ene_714 = { 298 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 299 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 300 SDHCI_QUIRK_BROKEN_DMA, 301 }; 302 303 static const struct sdhci_pci_fixes sdhci_cafe = { 304 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 305 SDHCI_QUIRK_NO_BUSY_IRQ | 306 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 307 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 308 }; 309 310 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 311 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 312 }; 313 314 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 315 { 316 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 317 return 0; 318 } 319 320 /* 321 * ADMA operation is disabled for Moorestown platform due to 322 * hardware bugs. 323 */ 324 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 325 { 326 /* 327 * slots number is fixed here for MRST as SDIO3/5 are never used and 328 * have hardware bugs. 329 */ 330 chip->num_slots = 1; 331 return 0; 332 } 333 334 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 335 { 336 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 337 return 0; 338 } 339 340 #ifdef CONFIG_PM 341 342 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 343 { 344 struct sdhci_pci_slot *slot = dev_id; 345 struct sdhci_host *host = slot->host; 346 347 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 348 return IRQ_HANDLED; 349 } 350 351 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 352 { 353 int err, irq, gpio = slot->cd_gpio; 354 355 slot->cd_gpio = -EINVAL; 356 slot->cd_irq = -EINVAL; 357 358 if (!gpio_is_valid(gpio)) 359 return; 360 361 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 362 if (err < 0) 363 goto out; 364 365 err = gpio_direction_input(gpio); 366 if (err < 0) 367 goto out_free; 368 369 irq = gpio_to_irq(gpio); 370 if (irq < 0) 371 goto out_free; 372 373 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 374 IRQF_TRIGGER_FALLING, "sd_cd", slot); 375 if (err) 376 goto out_free; 377 378 slot->cd_gpio = gpio; 379 slot->cd_irq = irq; 380 381 return; 382 383 out_free: 384 devm_gpio_free(&slot->chip->pdev->dev, gpio); 385 out: 386 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 387 } 388 389 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 390 { 391 if (slot->cd_irq >= 0) 392 free_irq(slot->cd_irq, slot); 393 } 394 395 #else 396 397 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 398 { 399 } 400 401 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 402 { 403 } 404 405 #endif 406 407 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 408 { 409 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 410 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC; 411 return 0; 412 } 413 414 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 415 { 416 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 417 return 0; 418 } 419 420 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 421 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 422 .probe_slot = mrst_hc_probe_slot, 423 }; 424 425 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 426 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 427 .probe = mrst_hc_probe, 428 }; 429 430 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 431 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 432 .allow_runtime_pm = true, 433 .own_cd_for_runtime_pm = true, 434 }; 435 436 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 437 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 438 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 439 .allow_runtime_pm = true, 440 .probe_slot = mfd_sdio_probe_slot, 441 }; 442 443 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 444 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 445 .allow_runtime_pm = true, 446 .probe_slot = mfd_emmc_probe_slot, 447 }; 448 449 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 450 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 451 .probe_slot = pch_hc_probe_slot, 452 }; 453 454 enum { 455 INTEL_DSM_FNS = 0, 456 INTEL_DSM_V18_SWITCH = 3, 457 INTEL_DSM_V33_SWITCH = 4, 458 INTEL_DSM_DRV_STRENGTH = 9, 459 INTEL_DSM_D3_RETUNE = 10, 460 }; 461 462 struct intel_host { 463 u32 dsm_fns; 464 int drv_strength; 465 bool d3_retune; 466 bool rpm_retune_ok; 467 u32 glk_rx_ctrl1; 468 u32 glk_tun_val; 469 }; 470 471 static const guid_t intel_dsm_guid = 472 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F, 473 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61); 474 475 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 476 unsigned int fn, u32 *result) 477 { 478 union acpi_object *obj; 479 int err = 0; 480 size_t len; 481 482 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL); 483 if (!obj) 484 return -EOPNOTSUPP; 485 486 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { 487 err = -EINVAL; 488 goto out; 489 } 490 491 len = min_t(size_t, obj->buffer.length, 4); 492 493 *result = 0; 494 memcpy(result, obj->buffer.pointer, len); 495 out: 496 ACPI_FREE(obj); 497 498 return err; 499 } 500 501 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 502 unsigned int fn, u32 *result) 503 { 504 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 505 return -EOPNOTSUPP; 506 507 return __intel_dsm(intel_host, dev, fn, result); 508 } 509 510 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 511 struct mmc_host *mmc) 512 { 513 int err; 514 u32 val; 515 516 intel_host->d3_retune = true; 517 518 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 519 if (err) { 520 pr_debug("%s: DSM not supported, error %d\n", 521 mmc_hostname(mmc), err); 522 return; 523 } 524 525 pr_debug("%s: DSM function mask %#x\n", 526 mmc_hostname(mmc), intel_host->dsm_fns); 527 528 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 529 intel_host->drv_strength = err ? 0 : val; 530 531 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 532 intel_host->d3_retune = err ? true : !!val; 533 } 534 535 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 536 { 537 u8 reg; 538 539 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 540 reg |= 0x10; 541 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 542 /* For eMMC, minimum is 1us but give it 9us for good measure */ 543 udelay(9); 544 reg &= ~0x10; 545 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 546 /* For eMMC, minimum is 200us but give it 300us for good measure */ 547 usleep_range(300, 1000); 548 } 549 550 static int intel_select_drive_strength(struct mmc_card *card, 551 unsigned int max_dtr, int host_drv, 552 int card_drv, int *drv_type) 553 { 554 struct sdhci_host *host = mmc_priv(card->host); 555 struct sdhci_pci_slot *slot = sdhci_priv(host); 556 struct intel_host *intel_host = sdhci_pci_priv(slot); 557 558 return intel_host->drv_strength; 559 } 560 561 static int bxt_get_cd(struct mmc_host *mmc) 562 { 563 int gpio_cd = mmc_gpio_get_cd(mmc); 564 struct sdhci_host *host = mmc_priv(mmc); 565 unsigned long flags; 566 int ret = 0; 567 568 if (!gpio_cd) 569 return 0; 570 571 spin_lock_irqsave(&host->lock, flags); 572 573 if (host->flags & SDHCI_DEVICE_DEAD) 574 goto out; 575 576 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 577 out: 578 spin_unlock_irqrestore(&host->lock, flags); 579 580 return ret; 581 } 582 583 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 584 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 585 586 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 587 unsigned short vdd) 588 { 589 int cntr; 590 u8 reg; 591 592 sdhci_set_power(host, mode, vdd); 593 594 if (mode == MMC_POWER_OFF) 595 return; 596 597 /* 598 * Bus power might not enable after D3 -> D0 transition due to the 599 * present state not yet having propagated. Retry for up to 2ms. 600 */ 601 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 602 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 603 if (reg & SDHCI_POWER_ON) 604 break; 605 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 606 reg |= SDHCI_POWER_ON; 607 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 608 } 609 } 610 611 #define INTEL_HS400_ES_REG 0x78 612 #define INTEL_HS400_ES_BIT BIT(0) 613 614 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc, 615 struct mmc_ios *ios) 616 { 617 struct sdhci_host *host = mmc_priv(mmc); 618 u32 val; 619 620 val = sdhci_readl(host, INTEL_HS400_ES_REG); 621 if (ios->enhanced_strobe) 622 val |= INTEL_HS400_ES_BIT; 623 else 624 val &= ~INTEL_HS400_ES_BIT; 625 sdhci_writel(host, val, INTEL_HS400_ES_REG); 626 } 627 628 static int intel_start_signal_voltage_switch(struct mmc_host *mmc, 629 struct mmc_ios *ios) 630 { 631 struct device *dev = mmc_dev(mmc); 632 struct sdhci_host *host = mmc_priv(mmc); 633 struct sdhci_pci_slot *slot = sdhci_priv(host); 634 struct intel_host *intel_host = sdhci_pci_priv(slot); 635 unsigned int fn; 636 u32 result = 0; 637 int err; 638 639 err = sdhci_start_signal_voltage_switch(mmc, ios); 640 if (err) 641 return err; 642 643 switch (ios->signal_voltage) { 644 case MMC_SIGNAL_VOLTAGE_330: 645 fn = INTEL_DSM_V33_SWITCH; 646 break; 647 case MMC_SIGNAL_VOLTAGE_180: 648 fn = INTEL_DSM_V18_SWITCH; 649 break; 650 default: 651 return 0; 652 } 653 654 err = intel_dsm(intel_host, dev, fn, &result); 655 pr_debug("%s: %s DSM fn %u error %d result %u\n", 656 mmc_hostname(mmc), __func__, fn, err, result); 657 658 return 0; 659 } 660 661 static const struct sdhci_ops sdhci_intel_byt_ops = { 662 .set_clock = sdhci_set_clock, 663 .set_power = sdhci_intel_set_power, 664 .enable_dma = sdhci_pci_enable_dma, 665 .set_bus_width = sdhci_set_bus_width, 666 .reset = sdhci_reset, 667 .set_uhs_signaling = sdhci_set_uhs_signaling, 668 .hw_reset = sdhci_pci_hw_reset, 669 }; 670 671 static const struct sdhci_ops sdhci_intel_glk_ops = { 672 .set_clock = sdhci_set_clock, 673 .set_power = sdhci_intel_set_power, 674 .enable_dma = sdhci_pci_enable_dma, 675 .set_bus_width = sdhci_set_bus_width, 676 .reset = sdhci_reset, 677 .set_uhs_signaling = sdhci_set_uhs_signaling, 678 .hw_reset = sdhci_pci_hw_reset, 679 .irq = sdhci_cqhci_irq, 680 }; 681 682 static void byt_read_dsm(struct sdhci_pci_slot *slot) 683 { 684 struct intel_host *intel_host = sdhci_pci_priv(slot); 685 struct device *dev = &slot->chip->pdev->dev; 686 struct mmc_host *mmc = slot->host->mmc; 687 688 intel_dsm_init(intel_host, dev, mmc); 689 slot->chip->rpm_retune = intel_host->d3_retune; 690 } 691 692 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode) 693 { 694 int err = sdhci_execute_tuning(mmc, opcode); 695 struct sdhci_host *host = mmc_priv(mmc); 696 697 if (err) 698 return err; 699 700 /* 701 * Tuning can leave the IP in an active state (Buffer Read Enable bit 702 * set) which prevents the entry to low power states (i.e. S0i3). Data 703 * reset will clear it. 704 */ 705 sdhci_reset(host, SDHCI_RESET_DATA); 706 707 return 0; 708 } 709 710 static void byt_probe_slot(struct sdhci_pci_slot *slot) 711 { 712 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 713 714 byt_read_dsm(slot); 715 716 ops->execute_tuning = intel_execute_tuning; 717 ops->start_signal_voltage_switch = intel_start_signal_voltage_switch; 718 } 719 720 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 721 { 722 byt_probe_slot(slot); 723 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 724 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 725 MMC_CAP_CMD_DURING_TFR | 726 MMC_CAP_WAIT_WHILE_BUSY; 727 slot->hw_reset = sdhci_pci_int_hw_reset; 728 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 729 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 730 slot->host->mmc_host_ops.select_drive_strength = 731 intel_select_drive_strength; 732 return 0; 733 } 734 735 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot) 736 { 737 int ret = byt_emmc_probe_slot(slot); 738 739 slot->host->mmc->caps2 |= MMC_CAP2_CQE; 740 741 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) { 742 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES, 743 slot->host->mmc_host_ops.hs400_enhanced_strobe = 744 intel_hs400_enhanced_strobe; 745 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; 746 } 747 748 return ret; 749 } 750 751 static const struct cqhci_host_ops glk_cqhci_ops = { 752 .enable = sdhci_cqe_enable, 753 .disable = sdhci_cqe_disable, 754 .dumpregs = sdhci_pci_dumpregs, 755 }; 756 757 static int glk_emmc_add_host(struct sdhci_pci_slot *slot) 758 { 759 struct device *dev = &slot->chip->pdev->dev; 760 struct sdhci_host *host = slot->host; 761 struct cqhci_host *cq_host; 762 bool dma64; 763 int ret; 764 765 ret = sdhci_setup_host(host); 766 if (ret) 767 return ret; 768 769 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); 770 if (!cq_host) { 771 ret = -ENOMEM; 772 goto cleanup; 773 } 774 775 cq_host->mmio = host->ioaddr + 0x200; 776 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 777 cq_host->ops = &glk_cqhci_ops; 778 779 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 780 if (dma64) 781 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 782 783 ret = cqhci_init(cq_host, host->mmc, dma64); 784 if (ret) 785 goto cleanup; 786 787 ret = __sdhci_add_host(host); 788 if (ret) 789 goto cleanup; 790 791 return 0; 792 793 cleanup: 794 sdhci_cleanup_host(host); 795 return ret; 796 } 797 798 #ifdef CONFIG_PM 799 #define GLK_RX_CTRL1 0x834 800 #define GLK_TUN_VAL 0x840 801 #define GLK_PATH_PLL GENMASK(13, 8) 802 #define GLK_DLY GENMASK(6, 0) 803 /* Workaround firmware failing to restore the tuning value */ 804 static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp) 805 { 806 struct sdhci_pci_slot *slot = chip->slots[0]; 807 struct intel_host *intel_host = sdhci_pci_priv(slot); 808 struct sdhci_host *host = slot->host; 809 u32 glk_rx_ctrl1; 810 u32 glk_tun_val; 811 u32 dly; 812 813 if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc)) 814 return; 815 816 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1); 817 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL); 818 819 if (susp) { 820 intel_host->glk_rx_ctrl1 = glk_rx_ctrl1; 821 intel_host->glk_tun_val = glk_tun_val; 822 return; 823 } 824 825 if (!intel_host->glk_tun_val) 826 return; 827 828 if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) { 829 intel_host->rpm_retune_ok = true; 830 return; 831 } 832 833 dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) + 834 (intel_host->glk_tun_val << 1)); 835 if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1)) 836 return; 837 838 glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly; 839 sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1); 840 841 intel_host->rpm_retune_ok = true; 842 chip->rpm_retune = true; 843 mmc_retune_needed(host->mmc); 844 pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc)); 845 } 846 847 static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp) 848 { 849 if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 850 !chip->rpm_retune) 851 glk_rpm_retune_wa(chip, susp); 852 } 853 854 static int glk_runtime_suspend(struct sdhci_pci_chip *chip) 855 { 856 glk_rpm_retune_chk(chip, true); 857 858 return sdhci_cqhci_runtime_suspend(chip); 859 } 860 861 static int glk_runtime_resume(struct sdhci_pci_chip *chip) 862 { 863 glk_rpm_retune_chk(chip, false); 864 865 return sdhci_cqhci_runtime_resume(chip); 866 } 867 #endif 868 869 #ifdef CONFIG_ACPI 870 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 871 { 872 acpi_status status; 873 unsigned long long max_freq; 874 875 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 876 "MXFQ", NULL, &max_freq); 877 if (ACPI_FAILURE(status)) { 878 dev_err(&slot->chip->pdev->dev, 879 "MXFQ not found in acpi table\n"); 880 return -EINVAL; 881 } 882 883 slot->host->mmc->f_max = max_freq * 1000000; 884 885 return 0; 886 } 887 #else 888 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 889 { 890 return 0; 891 } 892 #endif 893 894 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 895 { 896 int err; 897 898 byt_probe_slot(slot); 899 900 err = ni_set_max_freq(slot); 901 if (err) 902 return err; 903 904 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 905 MMC_CAP_WAIT_WHILE_BUSY; 906 return 0; 907 } 908 909 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 910 { 911 byt_probe_slot(slot); 912 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 913 MMC_CAP_WAIT_WHILE_BUSY; 914 return 0; 915 } 916 917 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 918 { 919 byt_probe_slot(slot); 920 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | 921 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE; 922 slot->cd_idx = 0; 923 slot->cd_override_level = true; 924 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 925 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 926 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 927 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) 928 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 929 930 if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI && 931 slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3) 932 slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V; 933 934 return 0; 935 } 936 937 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 938 .allow_runtime_pm = true, 939 .probe_slot = byt_emmc_probe_slot, 940 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 941 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 942 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 943 SDHCI_QUIRK2_STOP_WITH_TC, 944 .ops = &sdhci_intel_byt_ops, 945 .priv_size = sizeof(struct intel_host), 946 }; 947 948 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = { 949 .allow_runtime_pm = true, 950 .probe_slot = glk_emmc_probe_slot, 951 .add_host = glk_emmc_add_host, 952 #ifdef CONFIG_PM_SLEEP 953 .suspend = sdhci_cqhci_suspend, 954 .resume = sdhci_cqhci_resume, 955 #endif 956 #ifdef CONFIG_PM 957 .runtime_suspend = glk_runtime_suspend, 958 .runtime_resume = glk_runtime_resume, 959 #endif 960 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 961 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 962 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 963 SDHCI_QUIRK2_STOP_WITH_TC, 964 .ops = &sdhci_intel_glk_ops, 965 .priv_size = sizeof(struct intel_host), 966 }; 967 968 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 969 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 970 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 971 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 972 .allow_runtime_pm = true, 973 .probe_slot = ni_byt_sdio_probe_slot, 974 .ops = &sdhci_intel_byt_ops, 975 .priv_size = sizeof(struct intel_host), 976 }; 977 978 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 979 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 980 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 981 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 982 .allow_runtime_pm = true, 983 .probe_slot = byt_sdio_probe_slot, 984 .ops = &sdhci_intel_byt_ops, 985 .priv_size = sizeof(struct intel_host), 986 }; 987 988 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 989 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 990 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 991 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 992 SDHCI_QUIRK2_STOP_WITH_TC, 993 .allow_runtime_pm = true, 994 .own_cd_for_runtime_pm = true, 995 .probe_slot = byt_sd_probe_slot, 996 .ops = &sdhci_intel_byt_ops, 997 .priv_size = sizeof(struct intel_host), 998 }; 999 1000 /* Define Host controllers for Intel Merrifield platform */ 1001 #define INTEL_MRFLD_EMMC_0 0 1002 #define INTEL_MRFLD_EMMC_1 1 1003 #define INTEL_MRFLD_SD 2 1004 #define INTEL_MRFLD_SDIO 3 1005 1006 #ifdef CONFIG_ACPI 1007 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) 1008 { 1009 struct acpi_device *device, *child; 1010 1011 device = ACPI_COMPANION(&slot->chip->pdev->dev); 1012 if (!device) 1013 return; 1014 1015 acpi_device_fix_up_power(device); 1016 list_for_each_entry(child, &device->children, node) 1017 if (child->status.present && child->status.enabled) 1018 acpi_device_fix_up_power(child); 1019 } 1020 #else 1021 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {} 1022 #endif 1023 1024 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 1025 { 1026 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 1027 1028 switch (func) { 1029 case INTEL_MRFLD_EMMC_0: 1030 case INTEL_MRFLD_EMMC_1: 1031 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1032 MMC_CAP_8_BIT_DATA | 1033 MMC_CAP_1_8V_DDR; 1034 break; 1035 case INTEL_MRFLD_SD: 1036 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1037 break; 1038 case INTEL_MRFLD_SDIO: 1039 /* Advertise 2.0v for compatibility with the SDIO card's OCR */ 1040 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195; 1041 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1042 MMC_CAP_POWER_OFF_CARD; 1043 break; 1044 default: 1045 return -ENODEV; 1046 } 1047 1048 intel_mrfld_mmc_fix_up_power_slot(slot); 1049 return 0; 1050 } 1051 1052 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 1053 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1054 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 1055 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1056 .allow_runtime_pm = true, 1057 .probe_slot = intel_mrfld_mmc_probe_slot, 1058 }; 1059 1060 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 1061 { 1062 u8 scratch; 1063 int ret; 1064 1065 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 1066 if (ret) 1067 return ret; 1068 1069 /* 1070 * Turn PMOS on [bit 0], set over current detection to 2.4 V 1071 * [bit 1:2] and enable over current debouncing [bit 6]. 1072 */ 1073 if (on) 1074 scratch |= 0x47; 1075 else 1076 scratch &= ~0x47; 1077 1078 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 1079 } 1080 1081 static int jmicron_probe(struct sdhci_pci_chip *chip) 1082 { 1083 int ret; 1084 u16 mmcdev = 0; 1085 1086 if (chip->pdev->revision == 0) { 1087 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 1088 SDHCI_QUIRK_32BIT_DMA_SIZE | 1089 SDHCI_QUIRK_32BIT_ADMA_SIZE | 1090 SDHCI_QUIRK_RESET_AFTER_REQUEST | 1091 SDHCI_QUIRK_BROKEN_SMALL_PIO; 1092 } 1093 1094 /* 1095 * JMicron chips can have two interfaces to the same hardware 1096 * in order to work around limitations in Microsoft's driver. 1097 * We need to make sure we only bind to one of them. 1098 * 1099 * This code assumes two things: 1100 * 1101 * 1. The PCI code adds subfunctions in order. 1102 * 1103 * 2. The MMC interface has a lower subfunction number 1104 * than the SD interface. 1105 */ 1106 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 1107 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 1108 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 1109 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 1110 1111 if (mmcdev) { 1112 struct pci_dev *sd_dev; 1113 1114 sd_dev = NULL; 1115 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 1116 mmcdev, sd_dev)) != NULL) { 1117 if ((PCI_SLOT(chip->pdev->devfn) == 1118 PCI_SLOT(sd_dev->devfn)) && 1119 (chip->pdev->bus == sd_dev->bus)) 1120 break; 1121 } 1122 1123 if (sd_dev) { 1124 pci_dev_put(sd_dev); 1125 dev_info(&chip->pdev->dev, "Refusing to bind to " 1126 "secondary interface.\n"); 1127 return -ENODEV; 1128 } 1129 } 1130 1131 /* 1132 * JMicron chips need a bit of a nudge to enable the power 1133 * output pins. 1134 */ 1135 ret = jmicron_pmos(chip, 1); 1136 if (ret) { 1137 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1138 return ret; 1139 } 1140 1141 /* quirk for unsable RO-detection on JM388 chips */ 1142 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 1143 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1144 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 1145 1146 return 0; 1147 } 1148 1149 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 1150 { 1151 u8 scratch; 1152 1153 scratch = readb(host->ioaddr + 0xC0); 1154 1155 if (on) 1156 scratch |= 0x01; 1157 else 1158 scratch &= ~0x01; 1159 1160 writeb(scratch, host->ioaddr + 0xC0); 1161 } 1162 1163 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 1164 { 1165 if (slot->chip->pdev->revision == 0) { 1166 u16 version; 1167 1168 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 1169 version = (version & SDHCI_VENDOR_VER_MASK) >> 1170 SDHCI_VENDOR_VER_SHIFT; 1171 1172 /* 1173 * Older versions of the chip have lots of nasty glitches 1174 * in the ADMA engine. It's best just to avoid it 1175 * completely. 1176 */ 1177 if (version < 0xAC) 1178 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 1179 } 1180 1181 /* JM388 MMC doesn't support 1.8V while SD supports it */ 1182 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1183 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 1184 MMC_VDD_29_30 | MMC_VDD_30_31 | 1185 MMC_VDD_165_195; /* allow 1.8V */ 1186 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 1187 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 1188 } 1189 1190 /* 1191 * The secondary interface requires a bit set to get the 1192 * interrupts. 1193 */ 1194 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1195 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1196 jmicron_enable_mmc(slot->host, 1); 1197 1198 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 1199 1200 return 0; 1201 } 1202 1203 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 1204 { 1205 if (dead) 1206 return; 1207 1208 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1209 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1210 jmicron_enable_mmc(slot->host, 0); 1211 } 1212 1213 #ifdef CONFIG_PM_SLEEP 1214 static int jmicron_suspend(struct sdhci_pci_chip *chip) 1215 { 1216 int i, ret; 1217 1218 ret = sdhci_pci_suspend_host(chip); 1219 if (ret) 1220 return ret; 1221 1222 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1223 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1224 for (i = 0; i < chip->num_slots; i++) 1225 jmicron_enable_mmc(chip->slots[i]->host, 0); 1226 } 1227 1228 return 0; 1229 } 1230 1231 static int jmicron_resume(struct sdhci_pci_chip *chip) 1232 { 1233 int ret, i; 1234 1235 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1236 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1237 for (i = 0; i < chip->num_slots; i++) 1238 jmicron_enable_mmc(chip->slots[i]->host, 1); 1239 } 1240 1241 ret = jmicron_pmos(chip, 1); 1242 if (ret) { 1243 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1244 return ret; 1245 } 1246 1247 return sdhci_pci_resume_host(chip); 1248 } 1249 #endif 1250 1251 static const struct sdhci_pci_fixes sdhci_o2 = { 1252 .probe = sdhci_pci_o2_probe, 1253 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1254 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 1255 .probe_slot = sdhci_pci_o2_probe_slot, 1256 #ifdef CONFIG_PM_SLEEP 1257 .resume = sdhci_pci_o2_resume, 1258 #endif 1259 }; 1260 1261 static const struct sdhci_pci_fixes sdhci_jmicron = { 1262 .probe = jmicron_probe, 1263 1264 .probe_slot = jmicron_probe_slot, 1265 .remove_slot = jmicron_remove_slot, 1266 1267 #ifdef CONFIG_PM_SLEEP 1268 .suspend = jmicron_suspend, 1269 .resume = jmicron_resume, 1270 #endif 1271 }; 1272 1273 /* SysKonnect CardBus2SDIO extra registers */ 1274 #define SYSKT_CTRL 0x200 1275 #define SYSKT_RDFIFO_STAT 0x204 1276 #define SYSKT_WRFIFO_STAT 0x208 1277 #define SYSKT_POWER_DATA 0x20c 1278 #define SYSKT_POWER_330 0xef 1279 #define SYSKT_POWER_300 0xf8 1280 #define SYSKT_POWER_184 0xcc 1281 #define SYSKT_POWER_CMD 0x20d 1282 #define SYSKT_POWER_START (1 << 7) 1283 #define SYSKT_POWER_STATUS 0x20e 1284 #define SYSKT_POWER_STATUS_OK (1 << 0) 1285 #define SYSKT_BOARD_REV 0x210 1286 #define SYSKT_CHIP_REV 0x211 1287 #define SYSKT_CONF_DATA 0x212 1288 #define SYSKT_CONF_DATA_1V8 (1 << 2) 1289 #define SYSKT_CONF_DATA_2V5 (1 << 1) 1290 #define SYSKT_CONF_DATA_3V3 (1 << 0) 1291 1292 static int syskt_probe(struct sdhci_pci_chip *chip) 1293 { 1294 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1295 chip->pdev->class &= ~0x0000FF; 1296 chip->pdev->class |= PCI_SDHCI_IFDMA; 1297 } 1298 return 0; 1299 } 1300 1301 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 1302 { 1303 int tm, ps; 1304 1305 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 1306 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 1307 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 1308 "board rev %d.%d, chip rev %d.%d\n", 1309 board_rev >> 4, board_rev & 0xf, 1310 chip_rev >> 4, chip_rev & 0xf); 1311 if (chip_rev >= 0x20) 1312 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 1313 1314 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 1315 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 1316 udelay(50); 1317 tm = 10; /* Wait max 1 ms */ 1318 do { 1319 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 1320 if (ps & SYSKT_POWER_STATUS_OK) 1321 break; 1322 udelay(100); 1323 } while (--tm); 1324 if (!tm) { 1325 dev_err(&slot->chip->pdev->dev, 1326 "power regulator never stabilized"); 1327 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 1328 return -ENODEV; 1329 } 1330 1331 return 0; 1332 } 1333 1334 static const struct sdhci_pci_fixes sdhci_syskt = { 1335 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 1336 .probe = syskt_probe, 1337 .probe_slot = syskt_probe_slot, 1338 }; 1339 1340 static int via_probe(struct sdhci_pci_chip *chip) 1341 { 1342 if (chip->pdev->revision == 0x10) 1343 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 1344 1345 return 0; 1346 } 1347 1348 static const struct sdhci_pci_fixes sdhci_via = { 1349 .probe = via_probe, 1350 }; 1351 1352 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 1353 { 1354 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 1355 return 0; 1356 } 1357 1358 static const struct sdhci_pci_fixes sdhci_rtsx = { 1359 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1360 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 1361 SDHCI_QUIRK2_BROKEN_DDR50, 1362 .probe_slot = rtsx_probe_slot, 1363 }; 1364 1365 /*AMD chipset generation*/ 1366 enum amd_chipset_gen { 1367 AMD_CHIPSET_BEFORE_ML, 1368 AMD_CHIPSET_CZ, 1369 AMD_CHIPSET_NL, 1370 AMD_CHIPSET_UNKNOWN, 1371 }; 1372 1373 /* AMD registers */ 1374 #define AMD_SD_AUTO_PATTERN 0xB8 1375 #define AMD_MSLEEP_DURATION 4 1376 #define AMD_SD_MISC_CONTROL 0xD0 1377 #define AMD_MAX_TUNE_VALUE 0x0B 1378 #define AMD_AUTO_TUNE_SEL 0x10800 1379 #define AMD_FIFO_PTR 0x30 1380 #define AMD_BIT_MASK 0x1F 1381 1382 static void amd_tuning_reset(struct sdhci_host *host) 1383 { 1384 unsigned int val; 1385 1386 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1387 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 1388 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1389 1390 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1391 val &= ~SDHCI_CTRL_EXEC_TUNING; 1392 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1393 } 1394 1395 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 1396 { 1397 unsigned int val; 1398 1399 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 1400 val &= ~AMD_BIT_MASK; 1401 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 1402 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 1403 } 1404 1405 static void amd_enable_manual_tuning(struct pci_dev *pdev) 1406 { 1407 unsigned int val; 1408 1409 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 1410 val |= AMD_FIFO_PTR; 1411 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 1412 } 1413 1414 static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode) 1415 { 1416 struct sdhci_pci_slot *slot = sdhci_priv(host); 1417 struct pci_dev *pdev = slot->chip->pdev; 1418 u8 valid_win = 0; 1419 u8 valid_win_max = 0; 1420 u8 valid_win_end = 0; 1421 u8 ctrl, tune_around; 1422 1423 amd_tuning_reset(host); 1424 1425 for (tune_around = 0; tune_around < 12; tune_around++) { 1426 amd_config_tuning_phase(pdev, tune_around); 1427 1428 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1429 valid_win = 0; 1430 msleep(AMD_MSLEEP_DURATION); 1431 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 1432 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 1433 } else if (++valid_win > valid_win_max) { 1434 valid_win_max = valid_win; 1435 valid_win_end = tune_around; 1436 } 1437 } 1438 1439 if (!valid_win_max) { 1440 dev_err(&pdev->dev, "no tuning point found\n"); 1441 return -EIO; 1442 } 1443 1444 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 1445 1446 amd_enable_manual_tuning(pdev); 1447 1448 host->mmc->retune_period = 0; 1449 1450 return 0; 1451 } 1452 1453 static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode) 1454 { 1455 struct sdhci_host *host = mmc_priv(mmc); 1456 1457 /* AMD requires custom HS200 tuning */ 1458 if (host->timing == MMC_TIMING_MMC_HS200) 1459 return amd_execute_tuning_hs200(host, opcode); 1460 1461 /* Otherwise perform standard SDHCI tuning */ 1462 return sdhci_execute_tuning(mmc, opcode); 1463 } 1464 1465 static int amd_probe_slot(struct sdhci_pci_slot *slot) 1466 { 1467 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 1468 1469 ops->execute_tuning = amd_execute_tuning; 1470 1471 return 0; 1472 } 1473 1474 static int amd_probe(struct sdhci_pci_chip *chip) 1475 { 1476 struct pci_dev *smbus_dev; 1477 enum amd_chipset_gen gen; 1478 1479 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1480 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 1481 if (smbus_dev) { 1482 gen = AMD_CHIPSET_BEFORE_ML; 1483 } else { 1484 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1485 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1486 if (smbus_dev) { 1487 if (smbus_dev->revision < 0x51) 1488 gen = AMD_CHIPSET_CZ; 1489 else 1490 gen = AMD_CHIPSET_NL; 1491 } else { 1492 gen = AMD_CHIPSET_UNKNOWN; 1493 } 1494 } 1495 1496 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1497 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1498 1499 return 0; 1500 } 1501 1502 static const struct sdhci_ops amd_sdhci_pci_ops = { 1503 .set_clock = sdhci_set_clock, 1504 .enable_dma = sdhci_pci_enable_dma, 1505 .set_bus_width = sdhci_set_bus_width, 1506 .reset = sdhci_reset, 1507 .set_uhs_signaling = sdhci_set_uhs_signaling, 1508 }; 1509 1510 static const struct sdhci_pci_fixes sdhci_amd = { 1511 .probe = amd_probe, 1512 .ops = &amd_sdhci_pci_ops, 1513 .probe_slot = amd_probe_slot, 1514 }; 1515 1516 static const struct pci_device_id pci_ids[] = { 1517 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh), 1518 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc), 1519 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc), 1520 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc), 1521 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712), 1522 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712), 1523 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714), 1524 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714), 1525 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe), 1526 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron), 1527 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron), 1528 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron), 1529 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron), 1530 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt), 1531 SDHCI_PCI_DEVICE(VIA, 95D0, via), 1532 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx), 1533 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk), 1534 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0), 1535 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2), 1536 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2), 1537 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd), 1538 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio), 1539 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio), 1540 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc), 1541 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc), 1542 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio), 1543 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio), 1544 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc), 1545 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio), 1546 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio), 1547 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd), 1548 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc), 1549 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc), 1550 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio), 1551 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd), 1552 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd), 1553 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio), 1554 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio), 1555 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc), 1556 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc), 1557 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc), 1558 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc), 1559 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio), 1560 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd), 1561 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc), 1562 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc), 1563 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc), 1564 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio), 1565 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd), 1566 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc), 1567 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio), 1568 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd), 1569 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc), 1570 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio), 1571 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd), 1572 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc), 1573 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio), 1574 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd), 1575 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc), 1576 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd), 1577 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd), 1578 SDHCI_PCI_DEVICE(INTEL, ICP_EMMC, intel_glk_emmc), 1579 SDHCI_PCI_DEVICE(INTEL, ICP_SD, intel_byt_sd), 1580 SDHCI_PCI_DEVICE(O2, 8120, o2), 1581 SDHCI_PCI_DEVICE(O2, 8220, o2), 1582 SDHCI_PCI_DEVICE(O2, 8221, o2), 1583 SDHCI_PCI_DEVICE(O2, 8320, o2), 1584 SDHCI_PCI_DEVICE(O2, 8321, o2), 1585 SDHCI_PCI_DEVICE(O2, FUJIN2, o2), 1586 SDHCI_PCI_DEVICE(O2, SDS0, o2), 1587 SDHCI_PCI_DEVICE(O2, SDS1, o2), 1588 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2), 1589 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), 1590 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan), 1591 SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps), 1592 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), 1593 /* Generic SD host controller */ 1594 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, 1595 { /* end: all zeroes */ }, 1596 }; 1597 1598 MODULE_DEVICE_TABLE(pci, pci_ids); 1599 1600 /*****************************************************************************\ 1601 * * 1602 * SDHCI core callbacks * 1603 * * 1604 \*****************************************************************************/ 1605 1606 int sdhci_pci_enable_dma(struct sdhci_host *host) 1607 { 1608 struct sdhci_pci_slot *slot; 1609 struct pci_dev *pdev; 1610 1611 slot = sdhci_priv(host); 1612 pdev = slot->chip->pdev; 1613 1614 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1615 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1616 (host->flags & SDHCI_USE_SDMA)) { 1617 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1618 "doesn't fully claim to support it.\n"); 1619 } 1620 1621 pci_set_master(pdev); 1622 1623 return 0; 1624 } 1625 1626 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1627 { 1628 struct sdhci_pci_slot *slot = sdhci_priv(host); 1629 int rst_n_gpio = slot->rst_n_gpio; 1630 1631 if (!gpio_is_valid(rst_n_gpio)) 1632 return; 1633 gpio_set_value_cansleep(rst_n_gpio, 0); 1634 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1635 udelay(10); 1636 gpio_set_value_cansleep(rst_n_gpio, 1); 1637 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1638 usleep_range(300, 1000); 1639 } 1640 1641 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1642 { 1643 struct sdhci_pci_slot *slot = sdhci_priv(host); 1644 1645 if (slot->hw_reset) 1646 slot->hw_reset(host); 1647 } 1648 1649 static const struct sdhci_ops sdhci_pci_ops = { 1650 .set_clock = sdhci_set_clock, 1651 .enable_dma = sdhci_pci_enable_dma, 1652 .set_bus_width = sdhci_set_bus_width, 1653 .reset = sdhci_reset, 1654 .set_uhs_signaling = sdhci_set_uhs_signaling, 1655 .hw_reset = sdhci_pci_hw_reset, 1656 }; 1657 1658 /*****************************************************************************\ 1659 * * 1660 * Suspend/resume * 1661 * * 1662 \*****************************************************************************/ 1663 1664 #ifdef CONFIG_PM_SLEEP 1665 static int sdhci_pci_suspend(struct device *dev) 1666 { 1667 struct pci_dev *pdev = to_pci_dev(dev); 1668 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1669 1670 if (!chip) 1671 return 0; 1672 1673 if (chip->fixes && chip->fixes->suspend) 1674 return chip->fixes->suspend(chip); 1675 1676 return sdhci_pci_suspend_host(chip); 1677 } 1678 1679 static int sdhci_pci_resume(struct device *dev) 1680 { 1681 struct pci_dev *pdev = to_pci_dev(dev); 1682 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1683 1684 if (!chip) 1685 return 0; 1686 1687 if (chip->fixes && chip->fixes->resume) 1688 return chip->fixes->resume(chip); 1689 1690 return sdhci_pci_resume_host(chip); 1691 } 1692 #endif 1693 1694 #ifdef CONFIG_PM 1695 static int sdhci_pci_runtime_suspend(struct device *dev) 1696 { 1697 struct pci_dev *pdev = to_pci_dev(dev); 1698 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1699 1700 if (!chip) 1701 return 0; 1702 1703 if (chip->fixes && chip->fixes->runtime_suspend) 1704 return chip->fixes->runtime_suspend(chip); 1705 1706 return sdhci_pci_runtime_suspend_host(chip); 1707 } 1708 1709 static int sdhci_pci_runtime_resume(struct device *dev) 1710 { 1711 struct pci_dev *pdev = to_pci_dev(dev); 1712 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1713 1714 if (!chip) 1715 return 0; 1716 1717 if (chip->fixes && chip->fixes->runtime_resume) 1718 return chip->fixes->runtime_resume(chip); 1719 1720 return sdhci_pci_runtime_resume_host(chip); 1721 } 1722 #endif 1723 1724 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1725 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1726 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1727 sdhci_pci_runtime_resume, NULL) 1728 }; 1729 1730 /*****************************************************************************\ 1731 * * 1732 * Device probing/removal * 1733 * * 1734 \*****************************************************************************/ 1735 1736 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1737 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1738 int slotno) 1739 { 1740 struct sdhci_pci_slot *slot; 1741 struct sdhci_host *host; 1742 int ret, bar = first_bar + slotno; 1743 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 1744 1745 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1746 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1747 return ERR_PTR(-ENODEV); 1748 } 1749 1750 if (pci_resource_len(pdev, bar) < 0x100) { 1751 dev_err(&pdev->dev, "Invalid iomem size. You may " 1752 "experience problems.\n"); 1753 } 1754 1755 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1756 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1757 return ERR_PTR(-ENODEV); 1758 } 1759 1760 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1761 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1762 return ERR_PTR(-ENODEV); 1763 } 1764 1765 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 1766 if (IS_ERR(host)) { 1767 dev_err(&pdev->dev, "cannot allocate host\n"); 1768 return ERR_CAST(host); 1769 } 1770 1771 slot = sdhci_priv(host); 1772 1773 slot->chip = chip; 1774 slot->host = host; 1775 slot->rst_n_gpio = -EINVAL; 1776 slot->cd_gpio = -EINVAL; 1777 slot->cd_idx = -1; 1778 1779 /* Retrieve platform data if there is any */ 1780 if (*sdhci_pci_get_data) 1781 slot->data = sdhci_pci_get_data(pdev, slotno); 1782 1783 if (slot->data) { 1784 if (slot->data->setup) { 1785 ret = slot->data->setup(slot->data); 1786 if (ret) { 1787 dev_err(&pdev->dev, "platform setup failed\n"); 1788 goto free; 1789 } 1790 } 1791 slot->rst_n_gpio = slot->data->rst_n_gpio; 1792 slot->cd_gpio = slot->data->cd_gpio; 1793 } 1794 1795 host->hw_name = "PCI"; 1796 host->ops = chip->fixes && chip->fixes->ops ? 1797 chip->fixes->ops : 1798 &sdhci_pci_ops; 1799 host->quirks = chip->quirks; 1800 host->quirks2 = chip->quirks2; 1801 1802 host->irq = pdev->irq; 1803 1804 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1805 if (ret) { 1806 dev_err(&pdev->dev, "cannot request region\n"); 1807 goto cleanup; 1808 } 1809 1810 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1811 1812 if (chip->fixes && chip->fixes->probe_slot) { 1813 ret = chip->fixes->probe_slot(slot); 1814 if (ret) 1815 goto cleanup; 1816 } 1817 1818 if (gpio_is_valid(slot->rst_n_gpio)) { 1819 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1820 gpio_direction_output(slot->rst_n_gpio, 1); 1821 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1822 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1823 } else { 1824 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1825 slot->rst_n_gpio = -EINVAL; 1826 } 1827 } 1828 1829 host->mmc->pm_caps = MMC_PM_KEEP_POWER; 1830 host->mmc->slotno = slotno; 1831 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1832 1833 if (device_can_wakeup(&pdev->dev)) 1834 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ; 1835 1836 if (host->mmc->caps & MMC_CAP_CD_WAKE) 1837 device_init_wakeup(&pdev->dev, true); 1838 1839 if (slot->cd_idx >= 0) { 1840 ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx, 1841 slot->cd_override_level, 0, NULL); 1842 if (ret && ret != -EPROBE_DEFER) 1843 ret = mmc_gpiod_request_cd(host->mmc, NULL, 1844 slot->cd_idx, 1845 slot->cd_override_level, 1846 0, NULL); 1847 if (ret == -EPROBE_DEFER) 1848 goto remove; 1849 1850 if (ret) { 1851 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 1852 slot->cd_idx = -1; 1853 } 1854 } 1855 1856 if (chip->fixes && chip->fixes->add_host) 1857 ret = chip->fixes->add_host(slot); 1858 else 1859 ret = sdhci_add_host(host); 1860 if (ret) 1861 goto remove; 1862 1863 sdhci_pci_add_own_cd(slot); 1864 1865 /* 1866 * Check if the chip needs a separate GPIO for card detect to wake up 1867 * from runtime suspend. If it is not there, don't allow runtime PM. 1868 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 1869 */ 1870 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 1871 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 1872 chip->allow_runtime_pm = false; 1873 1874 return slot; 1875 1876 remove: 1877 if (chip->fixes && chip->fixes->remove_slot) 1878 chip->fixes->remove_slot(slot, 0); 1879 1880 cleanup: 1881 if (slot->data && slot->data->cleanup) 1882 slot->data->cleanup(slot->data); 1883 1884 free: 1885 sdhci_free_host(host); 1886 1887 return ERR_PTR(ret); 1888 } 1889 1890 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 1891 { 1892 int dead; 1893 u32 scratch; 1894 1895 sdhci_pci_remove_own_cd(slot); 1896 1897 dead = 0; 1898 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 1899 if (scratch == (u32)-1) 1900 dead = 1; 1901 1902 sdhci_remove_host(slot->host, dead); 1903 1904 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 1905 slot->chip->fixes->remove_slot(slot, dead); 1906 1907 if (slot->data && slot->data->cleanup) 1908 slot->data->cleanup(slot->data); 1909 1910 sdhci_free_host(slot->host); 1911 } 1912 1913 static void sdhci_pci_runtime_pm_allow(struct device *dev) 1914 { 1915 pm_suspend_ignore_children(dev, 1); 1916 pm_runtime_set_autosuspend_delay(dev, 50); 1917 pm_runtime_use_autosuspend(dev); 1918 pm_runtime_allow(dev); 1919 /* Stay active until mmc core scans for a card */ 1920 pm_runtime_put_noidle(dev); 1921 } 1922 1923 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 1924 { 1925 pm_runtime_forbid(dev); 1926 pm_runtime_get_noresume(dev); 1927 } 1928 1929 static int sdhci_pci_probe(struct pci_dev *pdev, 1930 const struct pci_device_id *ent) 1931 { 1932 struct sdhci_pci_chip *chip; 1933 struct sdhci_pci_slot *slot; 1934 1935 u8 slots, first_bar; 1936 int ret, i; 1937 1938 BUG_ON(pdev == NULL); 1939 BUG_ON(ent == NULL); 1940 1941 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 1942 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 1943 1944 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 1945 if (ret) 1946 return ret; 1947 1948 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 1949 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 1950 if (slots == 0) 1951 return -ENODEV; 1952 1953 BUG_ON(slots > MAX_SLOTS); 1954 1955 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 1956 if (ret) 1957 return ret; 1958 1959 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 1960 1961 if (first_bar > 5) { 1962 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 1963 return -ENODEV; 1964 } 1965 1966 ret = pcim_enable_device(pdev); 1967 if (ret) 1968 return ret; 1969 1970 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 1971 if (!chip) 1972 return -ENOMEM; 1973 1974 chip->pdev = pdev; 1975 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 1976 if (chip->fixes) { 1977 chip->quirks = chip->fixes->quirks; 1978 chip->quirks2 = chip->fixes->quirks2; 1979 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 1980 } 1981 chip->num_slots = slots; 1982 chip->pm_retune = true; 1983 chip->rpm_retune = true; 1984 1985 pci_set_drvdata(pdev, chip); 1986 1987 if (chip->fixes && chip->fixes->probe) { 1988 ret = chip->fixes->probe(chip); 1989 if (ret) 1990 return ret; 1991 } 1992 1993 slots = chip->num_slots; /* Quirk may have changed this */ 1994 1995 for (i = 0; i < slots; i++) { 1996 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 1997 if (IS_ERR(slot)) { 1998 for (i--; i >= 0; i--) 1999 sdhci_pci_remove_slot(chip->slots[i]); 2000 return PTR_ERR(slot); 2001 } 2002 2003 chip->slots[i] = slot; 2004 } 2005 2006 if (chip->allow_runtime_pm) 2007 sdhci_pci_runtime_pm_allow(&pdev->dev); 2008 2009 return 0; 2010 } 2011 2012 static void sdhci_pci_remove(struct pci_dev *pdev) 2013 { 2014 int i; 2015 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 2016 2017 if (chip->allow_runtime_pm) 2018 sdhci_pci_runtime_pm_forbid(&pdev->dev); 2019 2020 for (i = 0; i < chip->num_slots; i++) 2021 sdhci_pci_remove_slot(chip->slots[i]); 2022 } 2023 2024 static struct pci_driver sdhci_driver = { 2025 .name = "sdhci-pci", 2026 .id_table = pci_ids, 2027 .probe = sdhci_pci_probe, 2028 .remove = sdhci_pci_remove, 2029 .driver = { 2030 .pm = &sdhci_pci_pm_ops 2031 }, 2032 }; 2033 2034 module_pci_driver(sdhci_driver); 2035 2036 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 2037 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 2038 MODULE_LICENSE("GPL"); 2039