1 // SPDX-License-Identifier: GPL-2.0-only 2 /** 3 * SDHCI Controller driver for TI's OMAP SoCs 4 * 5 * Copyright (C) 2017 Texas Instruments 6 * Author: Kishon Vijay Abraham I <kishon@ti.com> 7 */ 8 9 #include <linux/delay.h> 10 #include <linux/mmc/mmc.h> 11 #include <linux/mmc/slot-gpio.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_device.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regulator/consumer.h> 18 #include <linux/pinctrl/consumer.h> 19 #include <linux/sys_soc.h> 20 #include <linux/thermal.h> 21 22 #include "sdhci-pltfm.h" 23 24 #define SDHCI_OMAP_SYSCONFIG 0x110 25 26 #define SDHCI_OMAP_CON 0x12c 27 #define CON_DW8 BIT(5) 28 #define CON_DMA_MASTER BIT(20) 29 #define CON_DDR BIT(19) 30 #define CON_CLKEXTFREE BIT(16) 31 #define CON_PADEN BIT(15) 32 #define CON_CTPL BIT(11) 33 #define CON_INIT BIT(1) 34 #define CON_OD BIT(0) 35 36 #define SDHCI_OMAP_DLL 0x0134 37 #define DLL_SWT BIT(20) 38 #define DLL_FORCE_SR_C_SHIFT 13 39 #define DLL_FORCE_SR_C_MASK (0x7f << DLL_FORCE_SR_C_SHIFT) 40 #define DLL_FORCE_VALUE BIT(12) 41 #define DLL_CALIB BIT(1) 42 43 #define SDHCI_OMAP_CMD 0x20c 44 45 #define SDHCI_OMAP_PSTATE 0x0224 46 #define PSTATE_DLEV_DAT0 BIT(20) 47 #define PSTATE_DATI BIT(1) 48 49 #define SDHCI_OMAP_HCTL 0x228 50 #define HCTL_SDBP BIT(8) 51 #define HCTL_SDVS_SHIFT 9 52 #define HCTL_SDVS_MASK (0x7 << HCTL_SDVS_SHIFT) 53 #define HCTL_SDVS_33 (0x7 << HCTL_SDVS_SHIFT) 54 #define HCTL_SDVS_30 (0x6 << HCTL_SDVS_SHIFT) 55 #define HCTL_SDVS_18 (0x5 << HCTL_SDVS_SHIFT) 56 57 #define SDHCI_OMAP_SYSCTL 0x22c 58 #define SYSCTL_CEN BIT(2) 59 #define SYSCTL_CLKD_SHIFT 6 60 #define SYSCTL_CLKD_MASK 0x3ff 61 62 #define SDHCI_OMAP_STAT 0x230 63 64 #define SDHCI_OMAP_IE 0x234 65 #define INT_CC_EN BIT(0) 66 67 #define SDHCI_OMAP_ISE 0x238 68 69 #define SDHCI_OMAP_AC12 0x23c 70 #define AC12_V1V8_SIGEN BIT(19) 71 #define AC12_SCLK_SEL BIT(23) 72 73 #define SDHCI_OMAP_CAPA 0x240 74 #define CAPA_VS33 BIT(24) 75 #define CAPA_VS30 BIT(25) 76 #define CAPA_VS18 BIT(26) 77 78 #define SDHCI_OMAP_CAPA2 0x0244 79 #define CAPA2_TSDR50 BIT(13) 80 81 #define SDHCI_OMAP_TIMEOUT 1 /* 1 msec */ 82 83 #define SYSCTL_CLKD_MAX 0x3FF 84 85 #define IOV_1V8 1800000 /* 180000 uV */ 86 #define IOV_3V0 3000000 /* 300000 uV */ 87 #define IOV_3V3 3300000 /* 330000 uV */ 88 89 #define MAX_PHASE_DELAY 0x7C 90 91 /* sdhci-omap controller flags */ 92 #define SDHCI_OMAP_REQUIRE_IODELAY BIT(0) 93 #define SDHCI_OMAP_SPECIAL_RESET BIT(1) 94 95 struct sdhci_omap_data { 96 u32 offset; 97 u8 flags; 98 }; 99 100 struct sdhci_omap_host { 101 char *version; 102 void __iomem *base; 103 struct device *dev; 104 struct regulator *pbias; 105 bool pbias_enabled; 106 struct sdhci_host *host; 107 u8 bus_mode; 108 u8 power_mode; 109 u8 timing; 110 u8 flags; 111 112 struct pinctrl *pinctrl; 113 struct pinctrl_state **pinctrl_state; 114 bool is_tuning; 115 /* Omap specific context save */ 116 u32 con; 117 u32 hctl; 118 u32 sysctl; 119 u32 capa; 120 u32 ie; 121 u32 ise; 122 }; 123 124 static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host); 125 static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host); 126 127 static inline u32 sdhci_omap_readl(struct sdhci_omap_host *host, 128 unsigned int offset) 129 { 130 return readl(host->base + offset); 131 } 132 133 static inline void sdhci_omap_writel(struct sdhci_omap_host *host, 134 unsigned int offset, u32 data) 135 { 136 writel(data, host->base + offset); 137 } 138 139 static int sdhci_omap_set_pbias(struct sdhci_omap_host *omap_host, 140 bool power_on, unsigned int iov) 141 { 142 int ret; 143 struct device *dev = omap_host->dev; 144 145 if (IS_ERR(omap_host->pbias)) 146 return 0; 147 148 if (power_on) { 149 ret = regulator_set_voltage(omap_host->pbias, iov, iov); 150 if (ret) { 151 dev_err(dev, "pbias set voltage failed\n"); 152 return ret; 153 } 154 155 if (omap_host->pbias_enabled) 156 return 0; 157 158 ret = regulator_enable(omap_host->pbias); 159 if (ret) { 160 dev_err(dev, "pbias reg enable fail\n"); 161 return ret; 162 } 163 164 omap_host->pbias_enabled = true; 165 } else { 166 if (!omap_host->pbias_enabled) 167 return 0; 168 169 ret = regulator_disable(omap_host->pbias); 170 if (ret) { 171 dev_err(dev, "pbias reg disable fail\n"); 172 return ret; 173 } 174 omap_host->pbias_enabled = false; 175 } 176 177 return 0; 178 } 179 180 static int sdhci_omap_enable_iov(struct sdhci_omap_host *omap_host, 181 unsigned int iov) 182 { 183 int ret; 184 struct sdhci_host *host = omap_host->host; 185 struct mmc_host *mmc = host->mmc; 186 187 ret = sdhci_omap_set_pbias(omap_host, false, 0); 188 if (ret) 189 return ret; 190 191 if (!IS_ERR(mmc->supply.vqmmc)) { 192 ret = regulator_set_voltage(mmc->supply.vqmmc, iov, iov); 193 if (ret) { 194 dev_err(mmc_dev(mmc), "vqmmc set voltage failed\n"); 195 return ret; 196 } 197 } 198 199 ret = sdhci_omap_set_pbias(omap_host, true, iov); 200 if (ret) 201 return ret; 202 203 return 0; 204 } 205 206 static void sdhci_omap_conf_bus_power(struct sdhci_omap_host *omap_host, 207 unsigned char signal_voltage) 208 { 209 u32 reg; 210 ktime_t timeout; 211 212 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL); 213 reg &= ~HCTL_SDVS_MASK; 214 215 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330) 216 reg |= HCTL_SDVS_33; 217 else 218 reg |= HCTL_SDVS_18; 219 220 sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg); 221 222 reg |= HCTL_SDBP; 223 sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg); 224 225 /* wait 1ms */ 226 timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT); 227 while (1) { 228 bool timedout = ktime_after(ktime_get(), timeout); 229 230 if (sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL) & HCTL_SDBP) 231 break; 232 if (WARN_ON(timedout)) 233 return; 234 usleep_range(5, 10); 235 } 236 } 237 238 static void sdhci_omap_enable_sdio_irq(struct mmc_host *mmc, int enable) 239 { 240 struct sdhci_host *host = mmc_priv(mmc); 241 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 242 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); 243 u32 reg; 244 245 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); 246 if (enable) 247 reg |= (CON_CTPL | CON_CLKEXTFREE); 248 else 249 reg &= ~(CON_CTPL | CON_CLKEXTFREE); 250 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); 251 252 sdhci_enable_sdio_irq(mmc, enable); 253 } 254 255 static inline void sdhci_omap_set_dll(struct sdhci_omap_host *omap_host, 256 int count) 257 { 258 int i; 259 u32 reg; 260 261 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL); 262 reg |= DLL_FORCE_VALUE; 263 reg &= ~DLL_FORCE_SR_C_MASK; 264 reg |= (count << DLL_FORCE_SR_C_SHIFT); 265 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg); 266 267 reg |= DLL_CALIB; 268 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg); 269 for (i = 0; i < 1000; i++) { 270 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL); 271 if (reg & DLL_CALIB) 272 break; 273 } 274 reg &= ~DLL_CALIB; 275 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg); 276 } 277 278 static void sdhci_omap_disable_tuning(struct sdhci_omap_host *omap_host) 279 { 280 u32 reg; 281 282 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12); 283 reg &= ~AC12_SCLK_SEL; 284 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg); 285 286 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL); 287 reg &= ~(DLL_FORCE_VALUE | DLL_SWT); 288 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg); 289 } 290 291 static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode) 292 { 293 struct sdhci_host *host = mmc_priv(mmc); 294 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 295 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); 296 struct thermal_zone_device *thermal_dev; 297 struct device *dev = omap_host->dev; 298 struct mmc_ios *ios = &mmc->ios; 299 u32 start_window = 0, max_window = 0; 300 bool single_point_failure = false; 301 bool dcrc_was_enabled = false; 302 u8 cur_match, prev_match = 0; 303 u32 length = 0, max_len = 0; 304 u32 phase_delay = 0; 305 int temperature; 306 int ret = 0; 307 u32 reg; 308 int i; 309 310 /* clock tuning is not needed for upto 52MHz */ 311 if (ios->clock <= 52000000) 312 return 0; 313 314 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA2); 315 if (ios->timing == MMC_TIMING_UHS_SDR50 && !(reg & CAPA2_TSDR50)) 316 return 0; 317 318 thermal_dev = thermal_zone_get_zone_by_name("cpu_thermal"); 319 if (IS_ERR(thermal_dev)) { 320 dev_err(dev, "Unable to get thermal zone for tuning\n"); 321 return PTR_ERR(thermal_dev); 322 } 323 324 ret = thermal_zone_get_temp(thermal_dev, &temperature); 325 if (ret) 326 return ret; 327 328 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL); 329 reg |= DLL_SWT; 330 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg); 331 332 /* 333 * OMAP5/DRA74X/DRA72x Errata i802: 334 * DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur 335 * during the tuning procedure. So disable it during the 336 * tuning procedure. 337 */ 338 if (host->ier & SDHCI_INT_DATA_CRC) { 339 host->ier &= ~SDHCI_INT_DATA_CRC; 340 dcrc_was_enabled = true; 341 } 342 343 omap_host->is_tuning = true; 344 345 /* 346 * Stage 1: Search for a maximum pass window ignoring any 347 * any single point failures. If the tuning value ends up 348 * near it, move away from it in stage 2 below 349 */ 350 while (phase_delay <= MAX_PHASE_DELAY) { 351 sdhci_omap_set_dll(omap_host, phase_delay); 352 353 cur_match = !mmc_send_tuning(mmc, opcode, NULL); 354 if (cur_match) { 355 if (prev_match) { 356 length++; 357 } else if (single_point_failure) { 358 /* ignore single point failure */ 359 length++; 360 } else { 361 start_window = phase_delay; 362 length = 1; 363 } 364 } else { 365 single_point_failure = prev_match; 366 } 367 368 if (length > max_len) { 369 max_window = start_window; 370 max_len = length; 371 } 372 373 prev_match = cur_match; 374 phase_delay += 4; 375 } 376 377 if (!max_len) { 378 dev_err(dev, "Unable to find match\n"); 379 ret = -EIO; 380 goto tuning_error; 381 } 382 383 /* 384 * Assign tuning value as a ratio of maximum pass window based 385 * on temperature 386 */ 387 if (temperature < -20000) 388 phase_delay = min(max_window + 4 * (max_len - 1) - 24, 389 max_window + 390 DIV_ROUND_UP(13 * max_len, 16) * 4); 391 else if (temperature < 20000) 392 phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4; 393 else if (temperature < 40000) 394 phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4; 395 else if (temperature < 70000) 396 phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4; 397 else if (temperature < 90000) 398 phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4; 399 else if (temperature < 120000) 400 phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4; 401 else 402 phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4; 403 404 /* 405 * Stage 2: Search for a single point failure near the chosen tuning 406 * value in two steps. First in the +3 to +10 range and then in the 407 * +2 to -10 range. If found, move away from it in the appropriate 408 * direction by the appropriate amount depending on the temperature. 409 */ 410 for (i = 3; i <= 10; i++) { 411 sdhci_omap_set_dll(omap_host, phase_delay + i); 412 413 if (mmc_send_tuning(mmc, opcode, NULL)) { 414 if (temperature < 10000) 415 phase_delay += i + 6; 416 else if (temperature < 20000) 417 phase_delay += i - 12; 418 else if (temperature < 70000) 419 phase_delay += i - 8; 420 else 421 phase_delay += i - 6; 422 423 goto single_failure_found; 424 } 425 } 426 427 for (i = 2; i >= -10; i--) { 428 sdhci_omap_set_dll(omap_host, phase_delay + i); 429 430 if (mmc_send_tuning(mmc, opcode, NULL)) { 431 if (temperature < 10000) 432 phase_delay += i + 12; 433 else if (temperature < 20000) 434 phase_delay += i + 8; 435 else if (temperature < 70000) 436 phase_delay += i + 8; 437 else if (temperature < 90000) 438 phase_delay += i + 10; 439 else 440 phase_delay += i + 12; 441 442 goto single_failure_found; 443 } 444 } 445 446 single_failure_found: 447 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12); 448 if (!(reg & AC12_SCLK_SEL)) { 449 ret = -EIO; 450 goto tuning_error; 451 } 452 453 sdhci_omap_set_dll(omap_host, phase_delay); 454 455 omap_host->is_tuning = false; 456 457 goto ret; 458 459 tuning_error: 460 omap_host->is_tuning = false; 461 dev_err(dev, "Tuning failed\n"); 462 sdhci_omap_disable_tuning(omap_host); 463 464 ret: 465 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 466 /* Reenable forbidden interrupt */ 467 if (dcrc_was_enabled) 468 host->ier |= SDHCI_INT_DATA_CRC; 469 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 470 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 471 return ret; 472 } 473 474 static int sdhci_omap_card_busy(struct mmc_host *mmc) 475 { 476 u32 reg, ac12; 477 int ret = false; 478 struct sdhci_host *host = mmc_priv(mmc); 479 struct sdhci_pltfm_host *pltfm_host; 480 struct sdhci_omap_host *omap_host; 481 u32 ier = host->ier; 482 483 pltfm_host = sdhci_priv(host); 484 omap_host = sdhci_pltfm_priv(pltfm_host); 485 486 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); 487 ac12 = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12); 488 reg &= ~CON_CLKEXTFREE; 489 if (ac12 & AC12_V1V8_SIGEN) 490 reg |= CON_CLKEXTFREE; 491 reg |= CON_PADEN; 492 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); 493 494 disable_irq(host->irq); 495 ier |= SDHCI_INT_CARD_INT; 496 sdhci_writel(host, ier, SDHCI_INT_ENABLE); 497 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE); 498 499 /* 500 * Delay is required for PSTATE to correctly reflect 501 * DLEV/CLEV values after PADEN is set. 502 */ 503 usleep_range(50, 100); 504 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_PSTATE); 505 if ((reg & PSTATE_DATI) || !(reg & PSTATE_DLEV_DAT0)) 506 ret = true; 507 508 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); 509 reg &= ~(CON_CLKEXTFREE | CON_PADEN); 510 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); 511 512 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 513 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 514 enable_irq(host->irq); 515 516 return ret; 517 } 518 519 static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc, 520 struct mmc_ios *ios) 521 { 522 u32 reg; 523 int ret; 524 unsigned int iov; 525 struct sdhci_host *host = mmc_priv(mmc); 526 struct sdhci_pltfm_host *pltfm_host; 527 struct sdhci_omap_host *omap_host; 528 struct device *dev; 529 530 pltfm_host = sdhci_priv(host); 531 omap_host = sdhci_pltfm_priv(pltfm_host); 532 dev = omap_host->dev; 533 534 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 535 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA); 536 if (!(reg & CAPA_VS33)) 537 return -EOPNOTSUPP; 538 539 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage); 540 541 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12); 542 reg &= ~AC12_V1V8_SIGEN; 543 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg); 544 545 iov = IOV_3V3; 546 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 547 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA); 548 if (!(reg & CAPA_VS18)) 549 return -EOPNOTSUPP; 550 551 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage); 552 553 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12); 554 reg |= AC12_V1V8_SIGEN; 555 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg); 556 557 iov = IOV_1V8; 558 } else { 559 return -EOPNOTSUPP; 560 } 561 562 ret = sdhci_omap_enable_iov(omap_host, iov); 563 if (ret) { 564 dev_err(dev, "failed to switch IO voltage to %dmV\n", iov); 565 return ret; 566 } 567 568 dev_dbg(dev, "IO voltage switched to %dmV\n", iov); 569 return 0; 570 } 571 572 static void sdhci_omap_set_timing(struct sdhci_omap_host *omap_host, u8 timing) 573 { 574 int ret; 575 struct pinctrl_state *pinctrl_state; 576 struct device *dev = omap_host->dev; 577 578 if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY)) 579 return; 580 581 if (omap_host->timing == timing) 582 return; 583 584 sdhci_omap_stop_clock(omap_host); 585 586 pinctrl_state = omap_host->pinctrl_state[timing]; 587 ret = pinctrl_select_state(omap_host->pinctrl, pinctrl_state); 588 if (ret) { 589 dev_err(dev, "failed to select pinctrl state\n"); 590 return; 591 } 592 593 sdhci_omap_start_clock(omap_host); 594 omap_host->timing = timing; 595 } 596 597 static void sdhci_omap_set_power_mode(struct sdhci_omap_host *omap_host, 598 u8 power_mode) 599 { 600 if (omap_host->bus_mode == MMC_POWER_OFF) 601 sdhci_omap_disable_tuning(omap_host); 602 omap_host->power_mode = power_mode; 603 } 604 605 static void sdhci_omap_set_bus_mode(struct sdhci_omap_host *omap_host, 606 unsigned int mode) 607 { 608 u32 reg; 609 610 if (omap_host->bus_mode == mode) 611 return; 612 613 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); 614 if (mode == MMC_BUSMODE_OPENDRAIN) 615 reg |= CON_OD; 616 else 617 reg &= ~CON_OD; 618 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); 619 620 omap_host->bus_mode = mode; 621 } 622 623 static void sdhci_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 624 { 625 struct sdhci_host *host = mmc_priv(mmc); 626 struct sdhci_pltfm_host *pltfm_host; 627 struct sdhci_omap_host *omap_host; 628 629 pltfm_host = sdhci_priv(host); 630 omap_host = sdhci_pltfm_priv(pltfm_host); 631 632 sdhci_omap_set_bus_mode(omap_host, ios->bus_mode); 633 sdhci_omap_set_timing(omap_host, ios->timing); 634 sdhci_set_ios(mmc, ios); 635 sdhci_omap_set_power_mode(omap_host, ios->power_mode); 636 } 637 638 static u16 sdhci_omap_calc_divisor(struct sdhci_pltfm_host *host, 639 unsigned int clock) 640 { 641 u16 dsor; 642 643 dsor = DIV_ROUND_UP(clk_get_rate(host->clk), clock); 644 if (dsor > SYSCTL_CLKD_MAX) 645 dsor = SYSCTL_CLKD_MAX; 646 647 return dsor; 648 } 649 650 static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host) 651 { 652 u32 reg; 653 654 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL); 655 reg |= SYSCTL_CEN; 656 sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg); 657 } 658 659 static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host) 660 { 661 u32 reg; 662 663 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL); 664 reg &= ~SYSCTL_CEN; 665 sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg); 666 } 667 668 static void sdhci_omap_set_clock(struct sdhci_host *host, unsigned int clock) 669 { 670 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 671 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); 672 unsigned long clkdiv; 673 674 sdhci_omap_stop_clock(omap_host); 675 676 if (!clock) 677 return; 678 679 clkdiv = sdhci_omap_calc_divisor(pltfm_host, clock); 680 clkdiv = (clkdiv & SYSCTL_CLKD_MASK) << SYSCTL_CLKD_SHIFT; 681 sdhci_enable_clk(host, clkdiv); 682 683 sdhci_omap_start_clock(omap_host); 684 } 685 686 static void sdhci_omap_set_power(struct sdhci_host *host, unsigned char mode, 687 unsigned short vdd) 688 { 689 struct mmc_host *mmc = host->mmc; 690 691 if (!IS_ERR(mmc->supply.vmmc)) 692 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 693 } 694 695 /* 696 * MMCHS_HL_HWINFO has the MADMA_EN bit set if the controller instance 697 * is connected to L3 interconnect and is bus master capable. Note that 698 * the MMCHS_HL_HWINFO register is in the module registers before the 699 * omap registers and sdhci registers. The offset can vary for omap 700 * registers depending on the SoC. Do not use sdhci_omap_readl() here. 701 */ 702 static bool sdhci_omap_has_adma(struct sdhci_omap_host *omap_host, int offset) 703 { 704 /* MMCHS_HL_HWINFO register is only available on omap4 and later */ 705 if (offset < 0x200) 706 return false; 707 708 return readl(omap_host->base + 4) & 1; 709 } 710 711 static int sdhci_omap_enable_dma(struct sdhci_host *host) 712 { 713 u32 reg; 714 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 715 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); 716 717 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); 718 reg &= ~CON_DMA_MASTER; 719 /* Switch to DMA slave mode when using external DMA */ 720 if (!host->use_external_dma) 721 reg |= CON_DMA_MASTER; 722 723 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); 724 725 return 0; 726 } 727 728 static unsigned int sdhci_omap_get_min_clock(struct sdhci_host *host) 729 { 730 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 731 732 return clk_get_rate(pltfm_host->clk) / SYSCTL_CLKD_MAX; 733 } 734 735 static void sdhci_omap_set_bus_width(struct sdhci_host *host, int width) 736 { 737 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 738 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); 739 u32 reg; 740 741 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); 742 if (width == MMC_BUS_WIDTH_8) 743 reg |= CON_DW8; 744 else 745 reg &= ~CON_DW8; 746 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); 747 748 sdhci_set_bus_width(host, width); 749 } 750 751 static void sdhci_omap_init_74_clocks(struct sdhci_host *host, u8 power_mode) 752 { 753 u32 reg; 754 ktime_t timeout; 755 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 756 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); 757 758 if (omap_host->power_mode == power_mode) 759 return; 760 761 if (power_mode != MMC_POWER_ON) 762 return; 763 764 disable_irq(host->irq); 765 766 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); 767 reg |= CON_INIT; 768 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); 769 sdhci_omap_writel(omap_host, SDHCI_OMAP_CMD, 0x0); 770 771 /* wait 1ms */ 772 timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT); 773 while (1) { 774 bool timedout = ktime_after(ktime_get(), timeout); 775 776 if (sdhci_omap_readl(omap_host, SDHCI_OMAP_STAT) & INT_CC_EN) 777 break; 778 if (WARN_ON(timedout)) 779 return; 780 usleep_range(5, 10); 781 } 782 783 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); 784 reg &= ~CON_INIT; 785 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); 786 sdhci_omap_writel(omap_host, SDHCI_OMAP_STAT, INT_CC_EN); 787 788 enable_irq(host->irq); 789 } 790 791 static void sdhci_omap_set_uhs_signaling(struct sdhci_host *host, 792 unsigned int timing) 793 { 794 u32 reg; 795 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 796 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); 797 798 sdhci_omap_stop_clock(omap_host); 799 800 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); 801 if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52) 802 reg |= CON_DDR; 803 else 804 reg &= ~CON_DDR; 805 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); 806 807 sdhci_set_uhs_signaling(host, timing); 808 sdhci_omap_start_clock(omap_host); 809 } 810 811 #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */ 812 static void sdhci_omap_reset(struct sdhci_host *host, u8 mask) 813 { 814 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 815 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); 816 unsigned long limit = MMC_TIMEOUT_US; 817 unsigned long i = 0; 818 u32 sysc; 819 820 /* Save target module sysconfig configured by SoC PM layer */ 821 if (mask & SDHCI_RESET_ALL) 822 sysc = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCONFIG); 823 824 /* Don't reset data lines during tuning operation */ 825 if (omap_host->is_tuning) 826 mask &= ~SDHCI_RESET_DATA; 827 828 if (omap_host->flags & SDHCI_OMAP_SPECIAL_RESET) { 829 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 830 while ((!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask)) && 831 (i++ < limit)) 832 udelay(1); 833 i = 0; 834 while ((sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) && 835 (i++ < limit)) 836 udelay(1); 837 838 if (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) 839 dev_err(mmc_dev(host->mmc), 840 "Timeout waiting on controller reset in %s\n", 841 __func__); 842 843 goto restore_sysc; 844 } 845 846 sdhci_reset(host, mask); 847 848 restore_sysc: 849 if (mask & SDHCI_RESET_ALL) 850 sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCONFIG, sysc); 851 } 852 853 #define CMD_ERR_MASK (SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX |\ 854 SDHCI_INT_TIMEOUT) 855 #define CMD_MASK (CMD_ERR_MASK | SDHCI_INT_RESPONSE) 856 857 static u32 sdhci_omap_irq(struct sdhci_host *host, u32 intmask) 858 { 859 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 860 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); 861 862 if (omap_host->is_tuning && host->cmd && !host->data_early && 863 (intmask & CMD_ERR_MASK)) { 864 865 /* 866 * Since we are not resetting data lines during tuning 867 * operation, data error or data complete interrupts 868 * might still arrive. Mark this request as a failure 869 * but still wait for the data interrupt 870 */ 871 if (intmask & SDHCI_INT_TIMEOUT) 872 host->cmd->error = -ETIMEDOUT; 873 else 874 host->cmd->error = -EILSEQ; 875 876 host->cmd = NULL; 877 878 /* 879 * Sometimes command error interrupts and command complete 880 * interrupt will arrive together. Clear all command related 881 * interrupts here. 882 */ 883 sdhci_writel(host, intmask & CMD_MASK, SDHCI_INT_STATUS); 884 intmask &= ~CMD_MASK; 885 } 886 887 return intmask; 888 } 889 890 static void sdhci_omap_set_timeout(struct sdhci_host *host, 891 struct mmc_command *cmd) 892 { 893 if (cmd->opcode == MMC_ERASE) 894 sdhci_set_data_timeout_irq(host, false); 895 896 __sdhci_set_timeout(host, cmd); 897 } 898 899 static struct sdhci_ops sdhci_omap_ops = { 900 .set_clock = sdhci_omap_set_clock, 901 .set_power = sdhci_omap_set_power, 902 .enable_dma = sdhci_omap_enable_dma, 903 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 904 .get_min_clock = sdhci_omap_get_min_clock, 905 .set_bus_width = sdhci_omap_set_bus_width, 906 .platform_send_init_74_clocks = sdhci_omap_init_74_clocks, 907 .reset = sdhci_omap_reset, 908 .set_uhs_signaling = sdhci_omap_set_uhs_signaling, 909 .irq = sdhci_omap_irq, 910 .set_timeout = sdhci_omap_set_timeout, 911 }; 912 913 static int sdhci_omap_set_capabilities(struct sdhci_omap_host *omap_host) 914 { 915 u32 reg; 916 int ret = 0; 917 struct device *dev = omap_host->dev; 918 struct regulator *vqmmc; 919 920 vqmmc = regulator_get(dev, "vqmmc"); 921 if (IS_ERR(vqmmc)) { 922 ret = PTR_ERR(vqmmc); 923 goto reg_put; 924 } 925 926 /* voltage capabilities might be set by boot loader, clear it */ 927 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA); 928 reg &= ~(CAPA_VS18 | CAPA_VS30 | CAPA_VS33); 929 930 if (regulator_is_supported_voltage(vqmmc, IOV_3V3, IOV_3V3)) 931 reg |= CAPA_VS33; 932 if (regulator_is_supported_voltage(vqmmc, IOV_1V8, IOV_1V8)) 933 reg |= CAPA_VS18; 934 935 sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, reg); 936 937 reg_put: 938 regulator_put(vqmmc); 939 940 return ret; 941 } 942 943 static const struct sdhci_pltfm_data sdhci_omap_pdata = { 944 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | 945 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 946 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | 947 SDHCI_QUIRK_NO_HISPD_BIT | 948 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC, 949 .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN | 950 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 951 SDHCI_QUIRK2_RSP_136_HAS_CRC | 952 SDHCI_QUIRK2_DISABLE_HW_TIMEOUT, 953 .ops = &sdhci_omap_ops, 954 }; 955 956 static const struct sdhci_omap_data k2g_data = { 957 .offset = 0x200, 958 }; 959 960 static const struct sdhci_omap_data am335_data = { 961 .offset = 0x200, 962 .flags = SDHCI_OMAP_SPECIAL_RESET, 963 }; 964 965 static const struct sdhci_omap_data am437_data = { 966 .offset = 0x200, 967 .flags = SDHCI_OMAP_SPECIAL_RESET, 968 }; 969 970 static const struct sdhci_omap_data dra7_data = { 971 .offset = 0x200, 972 .flags = SDHCI_OMAP_REQUIRE_IODELAY, 973 }; 974 975 static const struct of_device_id omap_sdhci_match[] = { 976 { .compatible = "ti,dra7-sdhci", .data = &dra7_data }, 977 { .compatible = "ti,k2g-sdhci", .data = &k2g_data }, 978 { .compatible = "ti,am335-sdhci", .data = &am335_data }, 979 { .compatible = "ti,am437-sdhci", .data = &am437_data }, 980 {}, 981 }; 982 MODULE_DEVICE_TABLE(of, omap_sdhci_match); 983 984 static struct pinctrl_state 985 *sdhci_omap_iodelay_pinctrl_state(struct sdhci_omap_host *omap_host, char *mode, 986 u32 *caps, u32 capmask) 987 { 988 struct device *dev = omap_host->dev; 989 char *version = omap_host->version; 990 struct pinctrl_state *pinctrl_state = ERR_PTR(-ENODEV); 991 char str[20]; 992 993 if (!(*caps & capmask)) 994 goto ret; 995 996 if (version) { 997 snprintf(str, 20, "%s-%s", mode, version); 998 pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, str); 999 } 1000 1001 if (IS_ERR(pinctrl_state)) 1002 pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, mode); 1003 1004 if (IS_ERR(pinctrl_state)) { 1005 dev_err(dev, "no pinctrl state for %s mode", mode); 1006 *caps &= ~capmask; 1007 } 1008 1009 ret: 1010 return pinctrl_state; 1011 } 1012 1013 static int sdhci_omap_config_iodelay_pinctrl_state(struct sdhci_omap_host 1014 *omap_host) 1015 { 1016 struct device *dev = omap_host->dev; 1017 struct sdhci_host *host = omap_host->host; 1018 struct mmc_host *mmc = host->mmc; 1019 u32 *caps = &mmc->caps; 1020 u32 *caps2 = &mmc->caps2; 1021 struct pinctrl_state *state; 1022 struct pinctrl_state **pinctrl_state; 1023 1024 if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY)) 1025 return 0; 1026 1027 pinctrl_state = devm_kcalloc(dev, 1028 MMC_TIMING_MMC_HS200 + 1, 1029 sizeof(*pinctrl_state), 1030 GFP_KERNEL); 1031 if (!pinctrl_state) 1032 return -ENOMEM; 1033 1034 omap_host->pinctrl = devm_pinctrl_get(omap_host->dev); 1035 if (IS_ERR(omap_host->pinctrl)) { 1036 dev_err(dev, "Cannot get pinctrl\n"); 1037 return PTR_ERR(omap_host->pinctrl); 1038 } 1039 1040 state = pinctrl_lookup_state(omap_host->pinctrl, "default"); 1041 if (IS_ERR(state)) { 1042 dev_err(dev, "no pinctrl state for default mode\n"); 1043 return PTR_ERR(state); 1044 } 1045 pinctrl_state[MMC_TIMING_LEGACY] = state; 1046 1047 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr104", caps, 1048 MMC_CAP_UHS_SDR104); 1049 if (!IS_ERR(state)) 1050 pinctrl_state[MMC_TIMING_UHS_SDR104] = state; 1051 1052 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr50", caps, 1053 MMC_CAP_UHS_DDR50); 1054 if (!IS_ERR(state)) 1055 pinctrl_state[MMC_TIMING_UHS_DDR50] = state; 1056 1057 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr50", caps, 1058 MMC_CAP_UHS_SDR50); 1059 if (!IS_ERR(state)) 1060 pinctrl_state[MMC_TIMING_UHS_SDR50] = state; 1061 1062 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr25", caps, 1063 MMC_CAP_UHS_SDR25); 1064 if (!IS_ERR(state)) 1065 pinctrl_state[MMC_TIMING_UHS_SDR25] = state; 1066 1067 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr12", caps, 1068 MMC_CAP_UHS_SDR12); 1069 if (!IS_ERR(state)) 1070 pinctrl_state[MMC_TIMING_UHS_SDR12] = state; 1071 1072 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_1_8v", caps, 1073 MMC_CAP_1_8V_DDR); 1074 if (!IS_ERR(state)) { 1075 pinctrl_state[MMC_TIMING_MMC_DDR52] = state; 1076 } else { 1077 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_3_3v", 1078 caps, 1079 MMC_CAP_3_3V_DDR); 1080 if (!IS_ERR(state)) 1081 pinctrl_state[MMC_TIMING_MMC_DDR52] = state; 1082 } 1083 1084 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps, 1085 MMC_CAP_SD_HIGHSPEED); 1086 if (!IS_ERR(state)) 1087 pinctrl_state[MMC_TIMING_SD_HS] = state; 1088 1089 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps, 1090 MMC_CAP_MMC_HIGHSPEED); 1091 if (!IS_ERR(state)) 1092 pinctrl_state[MMC_TIMING_MMC_HS] = state; 1093 1094 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs200_1_8v", caps2, 1095 MMC_CAP2_HS200_1_8V_SDR); 1096 if (!IS_ERR(state)) 1097 pinctrl_state[MMC_TIMING_MMC_HS200] = state; 1098 1099 omap_host->pinctrl_state = pinctrl_state; 1100 1101 return 0; 1102 } 1103 1104 static const struct soc_device_attribute sdhci_omap_soc_devices[] = { 1105 { 1106 .machine = "DRA7[45]*", 1107 .revision = "ES1.[01]", 1108 }, 1109 { 1110 /* sentinel */ 1111 } 1112 }; 1113 1114 static int sdhci_omap_probe(struct platform_device *pdev) 1115 { 1116 int ret; 1117 u32 offset; 1118 struct device *dev = &pdev->dev; 1119 struct sdhci_host *host; 1120 struct sdhci_pltfm_host *pltfm_host; 1121 struct sdhci_omap_host *omap_host; 1122 struct mmc_host *mmc; 1123 const struct of_device_id *match; 1124 struct sdhci_omap_data *data; 1125 const struct soc_device_attribute *soc; 1126 struct resource *regs; 1127 1128 match = of_match_device(omap_sdhci_match, dev); 1129 if (!match) 1130 return -EINVAL; 1131 1132 data = (struct sdhci_omap_data *)match->data; 1133 if (!data) { 1134 dev_err(dev, "no sdhci omap data\n"); 1135 return -EINVAL; 1136 } 1137 offset = data->offset; 1138 1139 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1140 if (!regs) 1141 return -ENXIO; 1142 1143 host = sdhci_pltfm_init(pdev, &sdhci_omap_pdata, 1144 sizeof(*omap_host)); 1145 if (IS_ERR(host)) { 1146 dev_err(dev, "Failed sdhci_pltfm_init\n"); 1147 return PTR_ERR(host); 1148 } 1149 1150 pltfm_host = sdhci_priv(host); 1151 omap_host = sdhci_pltfm_priv(pltfm_host); 1152 omap_host->host = host; 1153 omap_host->base = host->ioaddr; 1154 omap_host->dev = dev; 1155 omap_host->power_mode = MMC_POWER_UNDEFINED; 1156 omap_host->timing = MMC_TIMING_LEGACY; 1157 omap_host->flags = data->flags; 1158 host->ioaddr += offset; 1159 host->mapbase = regs->start + offset; 1160 1161 mmc = host->mmc; 1162 sdhci_get_of_property(pdev); 1163 ret = mmc_of_parse(mmc); 1164 if (ret) 1165 goto err_pltfm_free; 1166 1167 soc = soc_device_match(sdhci_omap_soc_devices); 1168 if (soc) { 1169 omap_host->version = "rev11"; 1170 if (!strcmp(dev_name(dev), "4809c000.mmc")) 1171 mmc->f_max = 96000000; 1172 if (!strcmp(dev_name(dev), "480b4000.mmc")) 1173 mmc->f_max = 48000000; 1174 if (!strcmp(dev_name(dev), "480ad000.mmc")) 1175 mmc->f_max = 48000000; 1176 } 1177 1178 if (!mmc_can_gpio_ro(mmc)) 1179 mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT; 1180 1181 pltfm_host->clk = devm_clk_get(dev, "fck"); 1182 if (IS_ERR(pltfm_host->clk)) { 1183 ret = PTR_ERR(pltfm_host->clk); 1184 goto err_pltfm_free; 1185 } 1186 1187 ret = clk_set_rate(pltfm_host->clk, mmc->f_max); 1188 if (ret) { 1189 dev_err(dev, "failed to set clock to %d\n", mmc->f_max); 1190 goto err_pltfm_free; 1191 } 1192 1193 omap_host->pbias = devm_regulator_get_optional(dev, "pbias"); 1194 if (IS_ERR(omap_host->pbias)) { 1195 ret = PTR_ERR(omap_host->pbias); 1196 if (ret != -ENODEV) 1197 goto err_pltfm_free; 1198 dev_dbg(dev, "unable to get pbias regulator %d\n", ret); 1199 } 1200 omap_host->pbias_enabled = false; 1201 1202 /* 1203 * omap_device_pm_domain has callbacks to enable the main 1204 * functional clock, interface clock and also configure the 1205 * SYSCONFIG register of omap devices. The callback will be invoked 1206 * as part of pm_runtime_get_sync. 1207 */ 1208 pm_runtime_enable(dev); 1209 ret = pm_runtime_resume_and_get(dev); 1210 if (ret) { 1211 dev_err(dev, "pm_runtime_get_sync failed\n"); 1212 goto err_rpm_disable; 1213 } 1214 1215 ret = sdhci_omap_set_capabilities(omap_host); 1216 if (ret) { 1217 dev_err(dev, "failed to set system capabilities\n"); 1218 goto err_put_sync; 1219 } 1220 1221 host->mmc_host_ops.start_signal_voltage_switch = 1222 sdhci_omap_start_signal_voltage_switch; 1223 host->mmc_host_ops.set_ios = sdhci_omap_set_ios; 1224 host->mmc_host_ops.card_busy = sdhci_omap_card_busy; 1225 host->mmc_host_ops.execute_tuning = sdhci_omap_execute_tuning; 1226 host->mmc_host_ops.enable_sdio_irq = sdhci_omap_enable_sdio_irq; 1227 1228 /* 1229 * Switch to external DMA only if there is the "dmas" property and 1230 * ADMA is not available on the controller instance. 1231 */ 1232 if (device_property_present(dev, "dmas") && 1233 !sdhci_omap_has_adma(omap_host, offset)) 1234 sdhci_switch_external_dma(host, true); 1235 1236 if (device_property_read_bool(dev, "ti,non-removable")) { 1237 dev_warn_once(dev, "using old ti,non-removable property\n"); 1238 mmc->caps |= MMC_CAP_NONREMOVABLE; 1239 } 1240 1241 /* R1B responses is required to properly manage HW busy detection. */ 1242 mmc->caps |= MMC_CAP_NEED_RSP_BUSY; 1243 1244 ret = sdhci_setup_host(host); 1245 if (ret) 1246 goto err_put_sync; 1247 1248 ret = sdhci_omap_config_iodelay_pinctrl_state(omap_host); 1249 if (ret) 1250 goto err_cleanup_host; 1251 1252 ret = __sdhci_add_host(host); 1253 if (ret) 1254 goto err_cleanup_host; 1255 1256 return 0; 1257 1258 err_cleanup_host: 1259 sdhci_cleanup_host(host); 1260 1261 err_put_sync: 1262 pm_runtime_put_sync(dev); 1263 1264 err_rpm_disable: 1265 pm_runtime_disable(dev); 1266 1267 err_pltfm_free: 1268 sdhci_pltfm_free(pdev); 1269 return ret; 1270 } 1271 1272 static int sdhci_omap_remove(struct platform_device *pdev) 1273 { 1274 struct device *dev = &pdev->dev; 1275 struct sdhci_host *host = platform_get_drvdata(pdev); 1276 1277 sdhci_remove_host(host, true); 1278 pm_runtime_put_sync(dev); 1279 pm_runtime_disable(dev); 1280 sdhci_pltfm_free(pdev); 1281 1282 return 0; 1283 } 1284 #ifdef CONFIG_PM_SLEEP 1285 static void sdhci_omap_context_save(struct sdhci_omap_host *omap_host) 1286 { 1287 omap_host->con = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); 1288 omap_host->hctl = sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL); 1289 omap_host->sysctl = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL); 1290 omap_host->capa = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA); 1291 omap_host->ie = sdhci_omap_readl(omap_host, SDHCI_OMAP_IE); 1292 omap_host->ise = sdhci_omap_readl(omap_host, SDHCI_OMAP_ISE); 1293 } 1294 1295 /* Order matters here, HCTL must be restored in two phases */ 1296 static void sdhci_omap_context_restore(struct sdhci_omap_host *omap_host) 1297 { 1298 sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, omap_host->hctl); 1299 sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, omap_host->capa); 1300 sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, omap_host->hctl); 1301 1302 sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, omap_host->sysctl); 1303 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, omap_host->con); 1304 sdhci_omap_writel(omap_host, SDHCI_OMAP_IE, omap_host->ie); 1305 sdhci_omap_writel(omap_host, SDHCI_OMAP_ISE, omap_host->ise); 1306 } 1307 1308 static int __maybe_unused sdhci_omap_suspend(struct device *dev) 1309 { 1310 struct sdhci_host *host = dev_get_drvdata(dev); 1311 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1312 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); 1313 1314 sdhci_suspend_host(host); 1315 1316 sdhci_omap_context_save(omap_host); 1317 1318 pinctrl_pm_select_idle_state(dev); 1319 1320 pm_runtime_force_suspend(dev); 1321 1322 return 0; 1323 } 1324 1325 static int __maybe_unused sdhci_omap_resume(struct device *dev) 1326 { 1327 struct sdhci_host *host = dev_get_drvdata(dev); 1328 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1329 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); 1330 1331 pm_runtime_force_resume(dev); 1332 1333 pinctrl_pm_select_default_state(dev); 1334 1335 sdhci_omap_context_restore(omap_host); 1336 1337 sdhci_resume_host(host); 1338 1339 return 0; 1340 } 1341 #endif 1342 static SIMPLE_DEV_PM_OPS(sdhci_omap_dev_pm_ops, sdhci_omap_suspend, 1343 sdhci_omap_resume); 1344 1345 static struct platform_driver sdhci_omap_driver = { 1346 .probe = sdhci_omap_probe, 1347 .remove = sdhci_omap_remove, 1348 .driver = { 1349 .name = "sdhci-omap", 1350 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1351 .pm = &sdhci_omap_dev_pm_ops, 1352 .of_match_table = omap_sdhci_match, 1353 }, 1354 }; 1355 1356 module_platform_driver(sdhci_omap_driver); 1357 1358 MODULE_DESCRIPTION("SDHCI driver for OMAP SoCs"); 1359 MODULE_AUTHOR("Texas Instruments Inc."); 1360 MODULE_LICENSE("GPL v2"); 1361 MODULE_ALIAS("platform:sdhci_omap"); 1362