1 // SPDX-License-Identifier: GPL-2.0-only 2 /** 3 * SDHCI Controller driver for TI's OMAP SoCs 4 * 5 * Copyright (C) 2017 Texas Instruments 6 * Author: Kishon Vijay Abraham I <kishon@ti.com> 7 */ 8 9 #include <linux/delay.h> 10 #include <linux/mmc/slot-gpio.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_device.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/pinctrl/consumer.h> 18 #include <linux/sys_soc.h> 19 #include <linux/thermal.h> 20 21 #include "sdhci-pltfm.h" 22 23 #define SDHCI_OMAP_CON 0x12c 24 #define CON_DW8 BIT(5) 25 #define CON_DMA_MASTER BIT(20) 26 #define CON_DDR BIT(19) 27 #define CON_CLKEXTFREE BIT(16) 28 #define CON_PADEN BIT(15) 29 #define CON_CTPL BIT(11) 30 #define CON_INIT BIT(1) 31 #define CON_OD BIT(0) 32 33 #define SDHCI_OMAP_DLL 0x0134 34 #define DLL_SWT BIT(20) 35 #define DLL_FORCE_SR_C_SHIFT 13 36 #define DLL_FORCE_SR_C_MASK (0x7f << DLL_FORCE_SR_C_SHIFT) 37 #define DLL_FORCE_VALUE BIT(12) 38 #define DLL_CALIB BIT(1) 39 40 #define SDHCI_OMAP_CMD 0x20c 41 42 #define SDHCI_OMAP_PSTATE 0x0224 43 #define PSTATE_DLEV_DAT0 BIT(20) 44 #define PSTATE_DATI BIT(1) 45 46 #define SDHCI_OMAP_HCTL 0x228 47 #define HCTL_SDBP BIT(8) 48 #define HCTL_SDVS_SHIFT 9 49 #define HCTL_SDVS_MASK (0x7 << HCTL_SDVS_SHIFT) 50 #define HCTL_SDVS_33 (0x7 << HCTL_SDVS_SHIFT) 51 #define HCTL_SDVS_30 (0x6 << HCTL_SDVS_SHIFT) 52 #define HCTL_SDVS_18 (0x5 << HCTL_SDVS_SHIFT) 53 54 #define SDHCI_OMAP_SYSCTL 0x22c 55 #define SYSCTL_CEN BIT(2) 56 #define SYSCTL_CLKD_SHIFT 6 57 #define SYSCTL_CLKD_MASK 0x3ff 58 59 #define SDHCI_OMAP_STAT 0x230 60 61 #define SDHCI_OMAP_IE 0x234 62 #define INT_CC_EN BIT(0) 63 64 #define SDHCI_OMAP_AC12 0x23c 65 #define AC12_V1V8_SIGEN BIT(19) 66 #define AC12_SCLK_SEL BIT(23) 67 68 #define SDHCI_OMAP_CAPA 0x240 69 #define CAPA_VS33 BIT(24) 70 #define CAPA_VS30 BIT(25) 71 #define CAPA_VS18 BIT(26) 72 73 #define SDHCI_OMAP_CAPA2 0x0244 74 #define CAPA2_TSDR50 BIT(13) 75 76 #define SDHCI_OMAP_TIMEOUT 1 /* 1 msec */ 77 78 #define SYSCTL_CLKD_MAX 0x3FF 79 80 #define IOV_1V8 1800000 /* 180000 uV */ 81 #define IOV_3V0 3000000 /* 300000 uV */ 82 #define IOV_3V3 3300000 /* 330000 uV */ 83 84 #define MAX_PHASE_DELAY 0x7C 85 86 /* sdhci-omap controller flags */ 87 #define SDHCI_OMAP_REQUIRE_IODELAY BIT(0) 88 89 struct sdhci_omap_data { 90 u32 offset; 91 u8 flags; 92 }; 93 94 struct sdhci_omap_host { 95 char *version; 96 void __iomem *base; 97 struct device *dev; 98 struct regulator *pbias; 99 bool pbias_enabled; 100 struct sdhci_host *host; 101 u8 bus_mode; 102 u8 power_mode; 103 u8 timing; 104 u8 flags; 105 106 struct pinctrl *pinctrl; 107 struct pinctrl_state **pinctrl_state; 108 bool is_tuning; 109 }; 110 111 static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host); 112 static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host); 113 114 static inline u32 sdhci_omap_readl(struct sdhci_omap_host *host, 115 unsigned int offset) 116 { 117 return readl(host->base + offset); 118 } 119 120 static inline void sdhci_omap_writel(struct sdhci_omap_host *host, 121 unsigned int offset, u32 data) 122 { 123 writel(data, host->base + offset); 124 } 125 126 static int sdhci_omap_set_pbias(struct sdhci_omap_host *omap_host, 127 bool power_on, unsigned int iov) 128 { 129 int ret; 130 struct device *dev = omap_host->dev; 131 132 if (IS_ERR(omap_host->pbias)) 133 return 0; 134 135 if (power_on) { 136 ret = regulator_set_voltage(omap_host->pbias, iov, iov); 137 if (ret) { 138 dev_err(dev, "pbias set voltage failed\n"); 139 return ret; 140 } 141 142 if (omap_host->pbias_enabled) 143 return 0; 144 145 ret = regulator_enable(omap_host->pbias); 146 if (ret) { 147 dev_err(dev, "pbias reg enable fail\n"); 148 return ret; 149 } 150 151 omap_host->pbias_enabled = true; 152 } else { 153 if (!omap_host->pbias_enabled) 154 return 0; 155 156 ret = regulator_disable(omap_host->pbias); 157 if (ret) { 158 dev_err(dev, "pbias reg disable fail\n"); 159 return ret; 160 } 161 omap_host->pbias_enabled = false; 162 } 163 164 return 0; 165 } 166 167 static int sdhci_omap_enable_iov(struct sdhci_omap_host *omap_host, 168 unsigned int iov) 169 { 170 int ret; 171 struct sdhci_host *host = omap_host->host; 172 struct mmc_host *mmc = host->mmc; 173 174 ret = sdhci_omap_set_pbias(omap_host, false, 0); 175 if (ret) 176 return ret; 177 178 if (!IS_ERR(mmc->supply.vqmmc)) { 179 ret = regulator_set_voltage(mmc->supply.vqmmc, iov, iov); 180 if (ret) { 181 dev_err(mmc_dev(mmc), "vqmmc set voltage failed\n"); 182 return ret; 183 } 184 } 185 186 ret = sdhci_omap_set_pbias(omap_host, true, iov); 187 if (ret) 188 return ret; 189 190 return 0; 191 } 192 193 static void sdhci_omap_conf_bus_power(struct sdhci_omap_host *omap_host, 194 unsigned char signal_voltage) 195 { 196 u32 reg; 197 ktime_t timeout; 198 199 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL); 200 reg &= ~HCTL_SDVS_MASK; 201 202 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330) 203 reg |= HCTL_SDVS_33; 204 else 205 reg |= HCTL_SDVS_18; 206 207 sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg); 208 209 reg |= HCTL_SDBP; 210 sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg); 211 212 /* wait 1ms */ 213 timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT); 214 while (1) { 215 bool timedout = ktime_after(ktime_get(), timeout); 216 217 if (sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL) & HCTL_SDBP) 218 break; 219 if (WARN_ON(timedout)) 220 return; 221 usleep_range(5, 10); 222 } 223 } 224 225 static void sdhci_omap_enable_sdio_irq(struct mmc_host *mmc, int enable) 226 { 227 struct sdhci_host *host = mmc_priv(mmc); 228 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 229 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); 230 u32 reg; 231 232 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); 233 if (enable) 234 reg |= (CON_CTPL | CON_CLKEXTFREE); 235 else 236 reg &= ~(CON_CTPL | CON_CLKEXTFREE); 237 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); 238 239 sdhci_enable_sdio_irq(mmc, enable); 240 } 241 242 static inline void sdhci_omap_set_dll(struct sdhci_omap_host *omap_host, 243 int count) 244 { 245 int i; 246 u32 reg; 247 248 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL); 249 reg |= DLL_FORCE_VALUE; 250 reg &= ~DLL_FORCE_SR_C_MASK; 251 reg |= (count << DLL_FORCE_SR_C_SHIFT); 252 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg); 253 254 reg |= DLL_CALIB; 255 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg); 256 for (i = 0; i < 1000; i++) { 257 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL); 258 if (reg & DLL_CALIB) 259 break; 260 } 261 reg &= ~DLL_CALIB; 262 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg); 263 } 264 265 static void sdhci_omap_disable_tuning(struct sdhci_omap_host *omap_host) 266 { 267 u32 reg; 268 269 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12); 270 reg &= ~AC12_SCLK_SEL; 271 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg); 272 273 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL); 274 reg &= ~(DLL_FORCE_VALUE | DLL_SWT); 275 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg); 276 } 277 278 static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode) 279 { 280 struct sdhci_host *host = mmc_priv(mmc); 281 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 282 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); 283 struct thermal_zone_device *thermal_dev; 284 struct device *dev = omap_host->dev; 285 struct mmc_ios *ios = &mmc->ios; 286 u32 start_window = 0, max_window = 0; 287 bool single_point_failure = false; 288 bool dcrc_was_enabled = false; 289 u8 cur_match, prev_match = 0; 290 u32 length = 0, max_len = 0; 291 u32 phase_delay = 0; 292 int temperature; 293 int ret = 0; 294 u32 reg; 295 int i; 296 297 /* clock tuning is not needed for upto 52MHz */ 298 if (ios->clock <= 52000000) 299 return 0; 300 301 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA2); 302 if (ios->timing == MMC_TIMING_UHS_SDR50 && !(reg & CAPA2_TSDR50)) 303 return 0; 304 305 thermal_dev = thermal_zone_get_zone_by_name("cpu_thermal"); 306 if (IS_ERR(thermal_dev)) { 307 dev_err(dev, "Unable to get thermal zone for tuning\n"); 308 return PTR_ERR(thermal_dev); 309 } 310 311 ret = thermal_zone_get_temp(thermal_dev, &temperature); 312 if (ret) 313 return ret; 314 315 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL); 316 reg |= DLL_SWT; 317 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg); 318 319 /* 320 * OMAP5/DRA74X/DRA72x Errata i802: 321 * DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur 322 * during the tuning procedure. So disable it during the 323 * tuning procedure. 324 */ 325 if (host->ier & SDHCI_INT_DATA_CRC) { 326 host->ier &= ~SDHCI_INT_DATA_CRC; 327 dcrc_was_enabled = true; 328 } 329 330 omap_host->is_tuning = true; 331 332 /* 333 * Stage 1: Search for a maximum pass window ignoring any 334 * any single point failures. If the tuning value ends up 335 * near it, move away from it in stage 2 below 336 */ 337 while (phase_delay <= MAX_PHASE_DELAY) { 338 sdhci_omap_set_dll(omap_host, phase_delay); 339 340 cur_match = !mmc_send_tuning(mmc, opcode, NULL); 341 if (cur_match) { 342 if (prev_match) { 343 length++; 344 } else if (single_point_failure) { 345 /* ignore single point failure */ 346 length++; 347 } else { 348 start_window = phase_delay; 349 length = 1; 350 } 351 } else { 352 single_point_failure = prev_match; 353 } 354 355 if (length > max_len) { 356 max_window = start_window; 357 max_len = length; 358 } 359 360 prev_match = cur_match; 361 phase_delay += 4; 362 } 363 364 if (!max_len) { 365 dev_err(dev, "Unable to find match\n"); 366 ret = -EIO; 367 goto tuning_error; 368 } 369 370 /* 371 * Assign tuning value as a ratio of maximum pass window based 372 * on temperature 373 */ 374 if (temperature < -20000) 375 phase_delay = min(max_window + 4 * (max_len - 1) - 24, 376 max_window + 377 DIV_ROUND_UP(13 * max_len, 16) * 4); 378 else if (temperature < 20000) 379 phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4; 380 else if (temperature < 40000) 381 phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4; 382 else if (temperature < 70000) 383 phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4; 384 else if (temperature < 90000) 385 phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4; 386 else if (temperature < 120000) 387 phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4; 388 else 389 phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4; 390 391 /* 392 * Stage 2: Search for a single point failure near the chosen tuning 393 * value in two steps. First in the +3 to +10 range and then in the 394 * +2 to -10 range. If found, move away from it in the appropriate 395 * direction by the appropriate amount depending on the temperature. 396 */ 397 for (i = 3; i <= 10; i++) { 398 sdhci_omap_set_dll(omap_host, phase_delay + i); 399 400 if (mmc_send_tuning(mmc, opcode, NULL)) { 401 if (temperature < 10000) 402 phase_delay += i + 6; 403 else if (temperature < 20000) 404 phase_delay += i - 12; 405 else if (temperature < 70000) 406 phase_delay += i - 8; 407 else 408 phase_delay += i - 6; 409 410 goto single_failure_found; 411 } 412 } 413 414 for (i = 2; i >= -10; i--) { 415 sdhci_omap_set_dll(omap_host, phase_delay + i); 416 417 if (mmc_send_tuning(mmc, opcode, NULL)) { 418 if (temperature < 10000) 419 phase_delay += i + 12; 420 else if (temperature < 20000) 421 phase_delay += i + 8; 422 else if (temperature < 70000) 423 phase_delay += i + 8; 424 else if (temperature < 90000) 425 phase_delay += i + 10; 426 else 427 phase_delay += i + 12; 428 429 goto single_failure_found; 430 } 431 } 432 433 single_failure_found: 434 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12); 435 if (!(reg & AC12_SCLK_SEL)) { 436 ret = -EIO; 437 goto tuning_error; 438 } 439 440 sdhci_omap_set_dll(omap_host, phase_delay); 441 442 omap_host->is_tuning = false; 443 444 goto ret; 445 446 tuning_error: 447 omap_host->is_tuning = false; 448 dev_err(dev, "Tuning failed\n"); 449 sdhci_omap_disable_tuning(omap_host); 450 451 ret: 452 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 453 /* Reenable forbidden interrupt */ 454 if (dcrc_was_enabled) 455 host->ier |= SDHCI_INT_DATA_CRC; 456 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 457 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 458 return ret; 459 } 460 461 static int sdhci_omap_card_busy(struct mmc_host *mmc) 462 { 463 u32 reg, ac12; 464 int ret = false; 465 struct sdhci_host *host = mmc_priv(mmc); 466 struct sdhci_pltfm_host *pltfm_host; 467 struct sdhci_omap_host *omap_host; 468 u32 ier = host->ier; 469 470 pltfm_host = sdhci_priv(host); 471 omap_host = sdhci_pltfm_priv(pltfm_host); 472 473 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); 474 ac12 = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12); 475 reg &= ~CON_CLKEXTFREE; 476 if (ac12 & AC12_V1V8_SIGEN) 477 reg |= CON_CLKEXTFREE; 478 reg |= CON_PADEN; 479 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); 480 481 disable_irq(host->irq); 482 ier |= SDHCI_INT_CARD_INT; 483 sdhci_writel(host, ier, SDHCI_INT_ENABLE); 484 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE); 485 486 /* 487 * Delay is required for PSTATE to correctly reflect 488 * DLEV/CLEV values after PADEN is set. 489 */ 490 usleep_range(50, 100); 491 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_PSTATE); 492 if ((reg & PSTATE_DATI) || !(reg & PSTATE_DLEV_DAT0)) 493 ret = true; 494 495 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); 496 reg &= ~(CON_CLKEXTFREE | CON_PADEN); 497 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); 498 499 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 500 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 501 enable_irq(host->irq); 502 503 return ret; 504 } 505 506 static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc, 507 struct mmc_ios *ios) 508 { 509 u32 reg; 510 int ret; 511 unsigned int iov; 512 struct sdhci_host *host = mmc_priv(mmc); 513 struct sdhci_pltfm_host *pltfm_host; 514 struct sdhci_omap_host *omap_host; 515 struct device *dev; 516 517 pltfm_host = sdhci_priv(host); 518 omap_host = sdhci_pltfm_priv(pltfm_host); 519 dev = omap_host->dev; 520 521 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 522 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA); 523 if (!(reg & CAPA_VS33)) 524 return -EOPNOTSUPP; 525 526 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage); 527 528 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12); 529 reg &= ~AC12_V1V8_SIGEN; 530 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg); 531 532 iov = IOV_3V3; 533 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 534 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA); 535 if (!(reg & CAPA_VS18)) 536 return -EOPNOTSUPP; 537 538 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage); 539 540 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12); 541 reg |= AC12_V1V8_SIGEN; 542 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg); 543 544 iov = IOV_1V8; 545 } else { 546 return -EOPNOTSUPP; 547 } 548 549 ret = sdhci_omap_enable_iov(omap_host, iov); 550 if (ret) { 551 dev_err(dev, "failed to switch IO voltage to %dmV\n", iov); 552 return ret; 553 } 554 555 dev_dbg(dev, "IO voltage switched to %dmV\n", iov); 556 return 0; 557 } 558 559 static void sdhci_omap_set_timing(struct sdhci_omap_host *omap_host, u8 timing) 560 { 561 int ret; 562 struct pinctrl_state *pinctrl_state; 563 struct device *dev = omap_host->dev; 564 565 if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY)) 566 return; 567 568 if (omap_host->timing == timing) 569 return; 570 571 sdhci_omap_stop_clock(omap_host); 572 573 pinctrl_state = omap_host->pinctrl_state[timing]; 574 ret = pinctrl_select_state(omap_host->pinctrl, pinctrl_state); 575 if (ret) { 576 dev_err(dev, "failed to select pinctrl state\n"); 577 return; 578 } 579 580 sdhci_omap_start_clock(omap_host); 581 omap_host->timing = timing; 582 } 583 584 static void sdhci_omap_set_power_mode(struct sdhci_omap_host *omap_host, 585 u8 power_mode) 586 { 587 if (omap_host->bus_mode == MMC_POWER_OFF) 588 sdhci_omap_disable_tuning(omap_host); 589 omap_host->power_mode = power_mode; 590 } 591 592 static void sdhci_omap_set_bus_mode(struct sdhci_omap_host *omap_host, 593 unsigned int mode) 594 { 595 u32 reg; 596 597 if (omap_host->bus_mode == mode) 598 return; 599 600 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); 601 if (mode == MMC_BUSMODE_OPENDRAIN) 602 reg |= CON_OD; 603 else 604 reg &= ~CON_OD; 605 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); 606 607 omap_host->bus_mode = mode; 608 } 609 610 static void sdhci_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 611 { 612 struct sdhci_host *host = mmc_priv(mmc); 613 struct sdhci_pltfm_host *pltfm_host; 614 struct sdhci_omap_host *omap_host; 615 616 pltfm_host = sdhci_priv(host); 617 omap_host = sdhci_pltfm_priv(pltfm_host); 618 619 sdhci_omap_set_bus_mode(omap_host, ios->bus_mode); 620 sdhci_omap_set_timing(omap_host, ios->timing); 621 sdhci_set_ios(mmc, ios); 622 sdhci_omap_set_power_mode(omap_host, ios->power_mode); 623 } 624 625 static u16 sdhci_omap_calc_divisor(struct sdhci_pltfm_host *host, 626 unsigned int clock) 627 { 628 u16 dsor; 629 630 dsor = DIV_ROUND_UP(clk_get_rate(host->clk), clock); 631 if (dsor > SYSCTL_CLKD_MAX) 632 dsor = SYSCTL_CLKD_MAX; 633 634 return dsor; 635 } 636 637 static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host) 638 { 639 u32 reg; 640 641 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL); 642 reg |= SYSCTL_CEN; 643 sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg); 644 } 645 646 static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host) 647 { 648 u32 reg; 649 650 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL); 651 reg &= ~SYSCTL_CEN; 652 sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg); 653 } 654 655 static void sdhci_omap_set_clock(struct sdhci_host *host, unsigned int clock) 656 { 657 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 658 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); 659 unsigned long clkdiv; 660 661 sdhci_omap_stop_clock(omap_host); 662 663 if (!clock) 664 return; 665 666 clkdiv = sdhci_omap_calc_divisor(pltfm_host, clock); 667 clkdiv = (clkdiv & SYSCTL_CLKD_MASK) << SYSCTL_CLKD_SHIFT; 668 sdhci_enable_clk(host, clkdiv); 669 670 sdhci_omap_start_clock(omap_host); 671 } 672 673 static void sdhci_omap_set_power(struct sdhci_host *host, unsigned char mode, 674 unsigned short vdd) 675 { 676 struct mmc_host *mmc = host->mmc; 677 678 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 679 } 680 681 static int sdhci_omap_enable_dma(struct sdhci_host *host) 682 { 683 u32 reg; 684 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 685 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); 686 687 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); 688 reg |= CON_DMA_MASTER; 689 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); 690 691 return 0; 692 } 693 694 static unsigned int sdhci_omap_get_min_clock(struct sdhci_host *host) 695 { 696 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 697 698 return clk_get_rate(pltfm_host->clk) / SYSCTL_CLKD_MAX; 699 } 700 701 static void sdhci_omap_set_bus_width(struct sdhci_host *host, int width) 702 { 703 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 704 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); 705 u32 reg; 706 707 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); 708 if (width == MMC_BUS_WIDTH_8) 709 reg |= CON_DW8; 710 else 711 reg &= ~CON_DW8; 712 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); 713 714 sdhci_set_bus_width(host, width); 715 } 716 717 static void sdhci_omap_init_74_clocks(struct sdhci_host *host, u8 power_mode) 718 { 719 u32 reg; 720 ktime_t timeout; 721 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 722 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); 723 724 if (omap_host->power_mode == power_mode) 725 return; 726 727 if (power_mode != MMC_POWER_ON) 728 return; 729 730 disable_irq(host->irq); 731 732 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); 733 reg |= CON_INIT; 734 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); 735 sdhci_omap_writel(omap_host, SDHCI_OMAP_CMD, 0x0); 736 737 /* wait 1ms */ 738 timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT); 739 while (1) { 740 bool timedout = ktime_after(ktime_get(), timeout); 741 742 if (sdhci_omap_readl(omap_host, SDHCI_OMAP_STAT) & INT_CC_EN) 743 break; 744 if (WARN_ON(timedout)) 745 return; 746 usleep_range(5, 10); 747 } 748 749 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); 750 reg &= ~CON_INIT; 751 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); 752 sdhci_omap_writel(omap_host, SDHCI_OMAP_STAT, INT_CC_EN); 753 754 enable_irq(host->irq); 755 } 756 757 static void sdhci_omap_set_uhs_signaling(struct sdhci_host *host, 758 unsigned int timing) 759 { 760 u32 reg; 761 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 762 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); 763 764 sdhci_omap_stop_clock(omap_host); 765 766 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); 767 if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52) 768 reg |= CON_DDR; 769 else 770 reg &= ~CON_DDR; 771 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); 772 773 sdhci_set_uhs_signaling(host, timing); 774 sdhci_omap_start_clock(omap_host); 775 } 776 777 static void sdhci_omap_reset(struct sdhci_host *host, u8 mask) 778 { 779 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 780 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); 781 782 /* Don't reset data lines during tuning operation */ 783 if (omap_host->is_tuning) 784 mask &= ~SDHCI_RESET_DATA; 785 786 sdhci_reset(host, mask); 787 } 788 789 #define CMD_ERR_MASK (SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX |\ 790 SDHCI_INT_TIMEOUT) 791 #define CMD_MASK (CMD_ERR_MASK | SDHCI_INT_RESPONSE) 792 793 static u32 sdhci_omap_irq(struct sdhci_host *host, u32 intmask) 794 { 795 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 796 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); 797 798 if (omap_host->is_tuning && host->cmd && !host->data_early && 799 (intmask & CMD_ERR_MASK)) { 800 801 /* 802 * Since we are not resetting data lines during tuning 803 * operation, data error or data complete interrupts 804 * might still arrive. Mark this request as a failure 805 * but still wait for the data interrupt 806 */ 807 if (intmask & SDHCI_INT_TIMEOUT) 808 host->cmd->error = -ETIMEDOUT; 809 else 810 host->cmd->error = -EILSEQ; 811 812 host->cmd = NULL; 813 814 /* 815 * Sometimes command error interrupts and command complete 816 * interrupt will arrive together. Clear all command related 817 * interrupts here. 818 */ 819 sdhci_writel(host, intmask & CMD_MASK, SDHCI_INT_STATUS); 820 intmask &= ~CMD_MASK; 821 } 822 823 return intmask; 824 } 825 826 static struct sdhci_ops sdhci_omap_ops = { 827 .set_clock = sdhci_omap_set_clock, 828 .set_power = sdhci_omap_set_power, 829 .enable_dma = sdhci_omap_enable_dma, 830 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 831 .get_min_clock = sdhci_omap_get_min_clock, 832 .set_bus_width = sdhci_omap_set_bus_width, 833 .platform_send_init_74_clocks = sdhci_omap_init_74_clocks, 834 .reset = sdhci_omap_reset, 835 .set_uhs_signaling = sdhci_omap_set_uhs_signaling, 836 .irq = sdhci_omap_irq, 837 }; 838 839 static int sdhci_omap_set_capabilities(struct sdhci_omap_host *omap_host) 840 { 841 u32 reg; 842 int ret = 0; 843 struct device *dev = omap_host->dev; 844 struct regulator *vqmmc; 845 846 vqmmc = regulator_get(dev, "vqmmc"); 847 if (IS_ERR(vqmmc)) { 848 ret = PTR_ERR(vqmmc); 849 goto reg_put; 850 } 851 852 /* voltage capabilities might be set by boot loader, clear it */ 853 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA); 854 reg &= ~(CAPA_VS18 | CAPA_VS30 | CAPA_VS33); 855 856 if (regulator_is_supported_voltage(vqmmc, IOV_3V3, IOV_3V3)) 857 reg |= CAPA_VS33; 858 if (regulator_is_supported_voltage(vqmmc, IOV_1V8, IOV_1V8)) 859 reg |= CAPA_VS18; 860 861 sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, reg); 862 863 reg_put: 864 regulator_put(vqmmc); 865 866 return ret; 867 } 868 869 static const struct sdhci_pltfm_data sdhci_omap_pdata = { 870 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | 871 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 872 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | 873 SDHCI_QUIRK_NO_HISPD_BIT | 874 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC, 875 .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN | 876 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 877 SDHCI_QUIRK2_RSP_136_HAS_CRC | 878 SDHCI_QUIRK2_DISABLE_HW_TIMEOUT, 879 .ops = &sdhci_omap_ops, 880 }; 881 882 static const struct sdhci_omap_data k2g_data = { 883 .offset = 0x200, 884 }; 885 886 static const struct sdhci_omap_data dra7_data = { 887 .offset = 0x200, 888 .flags = SDHCI_OMAP_REQUIRE_IODELAY, 889 }; 890 891 static const struct of_device_id omap_sdhci_match[] = { 892 { .compatible = "ti,dra7-sdhci", .data = &dra7_data }, 893 { .compatible = "ti,k2g-sdhci", .data = &k2g_data }, 894 {}, 895 }; 896 MODULE_DEVICE_TABLE(of, omap_sdhci_match); 897 898 static struct pinctrl_state 899 *sdhci_omap_iodelay_pinctrl_state(struct sdhci_omap_host *omap_host, char *mode, 900 u32 *caps, u32 capmask) 901 { 902 struct device *dev = omap_host->dev; 903 char *version = omap_host->version; 904 struct pinctrl_state *pinctrl_state = ERR_PTR(-ENODEV); 905 char str[20]; 906 907 if (!(*caps & capmask)) 908 goto ret; 909 910 if (version) { 911 snprintf(str, 20, "%s-%s", mode, version); 912 pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, str); 913 } 914 915 if (IS_ERR(pinctrl_state)) 916 pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, mode); 917 918 if (IS_ERR(pinctrl_state)) { 919 dev_err(dev, "no pinctrl state for %s mode", mode); 920 *caps &= ~capmask; 921 } 922 923 ret: 924 return pinctrl_state; 925 } 926 927 static int sdhci_omap_config_iodelay_pinctrl_state(struct sdhci_omap_host 928 *omap_host) 929 { 930 struct device *dev = omap_host->dev; 931 struct sdhci_host *host = omap_host->host; 932 struct mmc_host *mmc = host->mmc; 933 u32 *caps = &mmc->caps; 934 u32 *caps2 = &mmc->caps2; 935 struct pinctrl_state *state; 936 struct pinctrl_state **pinctrl_state; 937 938 if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY)) 939 return 0; 940 941 pinctrl_state = devm_kcalloc(dev, 942 MMC_TIMING_MMC_HS200 + 1, 943 sizeof(*pinctrl_state), 944 GFP_KERNEL); 945 if (!pinctrl_state) 946 return -ENOMEM; 947 948 omap_host->pinctrl = devm_pinctrl_get(omap_host->dev); 949 if (IS_ERR(omap_host->pinctrl)) { 950 dev_err(dev, "Cannot get pinctrl\n"); 951 return PTR_ERR(omap_host->pinctrl); 952 } 953 954 state = pinctrl_lookup_state(omap_host->pinctrl, "default"); 955 if (IS_ERR(state)) { 956 dev_err(dev, "no pinctrl state for default mode\n"); 957 return PTR_ERR(state); 958 } 959 pinctrl_state[MMC_TIMING_LEGACY] = state; 960 961 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr104", caps, 962 MMC_CAP_UHS_SDR104); 963 if (!IS_ERR(state)) 964 pinctrl_state[MMC_TIMING_UHS_SDR104] = state; 965 966 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr50", caps, 967 MMC_CAP_UHS_DDR50); 968 if (!IS_ERR(state)) 969 pinctrl_state[MMC_TIMING_UHS_DDR50] = state; 970 971 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr50", caps, 972 MMC_CAP_UHS_SDR50); 973 if (!IS_ERR(state)) 974 pinctrl_state[MMC_TIMING_UHS_SDR50] = state; 975 976 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr25", caps, 977 MMC_CAP_UHS_SDR25); 978 if (!IS_ERR(state)) 979 pinctrl_state[MMC_TIMING_UHS_SDR25] = state; 980 981 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr12", caps, 982 MMC_CAP_UHS_SDR12); 983 if (!IS_ERR(state)) 984 pinctrl_state[MMC_TIMING_UHS_SDR12] = state; 985 986 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_1_8v", caps, 987 MMC_CAP_1_8V_DDR); 988 if (!IS_ERR(state)) { 989 pinctrl_state[MMC_TIMING_MMC_DDR52] = state; 990 } else { 991 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_3_3v", 992 caps, 993 MMC_CAP_3_3V_DDR); 994 if (!IS_ERR(state)) 995 pinctrl_state[MMC_TIMING_MMC_DDR52] = state; 996 } 997 998 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps, 999 MMC_CAP_SD_HIGHSPEED); 1000 if (!IS_ERR(state)) 1001 pinctrl_state[MMC_TIMING_SD_HS] = state; 1002 1003 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps, 1004 MMC_CAP_MMC_HIGHSPEED); 1005 if (!IS_ERR(state)) 1006 pinctrl_state[MMC_TIMING_MMC_HS] = state; 1007 1008 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs200_1_8v", caps2, 1009 MMC_CAP2_HS200_1_8V_SDR); 1010 if (!IS_ERR(state)) 1011 pinctrl_state[MMC_TIMING_MMC_HS200] = state; 1012 1013 omap_host->pinctrl_state = pinctrl_state; 1014 1015 return 0; 1016 } 1017 1018 static const struct soc_device_attribute sdhci_omap_soc_devices[] = { 1019 { 1020 .machine = "DRA7[45]*", 1021 .revision = "ES1.[01]", 1022 }, 1023 { 1024 /* sentinel */ 1025 } 1026 }; 1027 1028 static int sdhci_omap_probe(struct platform_device *pdev) 1029 { 1030 int ret; 1031 u32 offset; 1032 struct device *dev = &pdev->dev; 1033 struct sdhci_host *host; 1034 struct sdhci_pltfm_host *pltfm_host; 1035 struct sdhci_omap_host *omap_host; 1036 struct mmc_host *mmc; 1037 const struct of_device_id *match; 1038 struct sdhci_omap_data *data; 1039 const struct soc_device_attribute *soc; 1040 1041 match = of_match_device(omap_sdhci_match, dev); 1042 if (!match) 1043 return -EINVAL; 1044 1045 data = (struct sdhci_omap_data *)match->data; 1046 if (!data) { 1047 dev_err(dev, "no sdhci omap data\n"); 1048 return -EINVAL; 1049 } 1050 offset = data->offset; 1051 1052 host = sdhci_pltfm_init(pdev, &sdhci_omap_pdata, 1053 sizeof(*omap_host)); 1054 if (IS_ERR(host)) { 1055 dev_err(dev, "Failed sdhci_pltfm_init\n"); 1056 return PTR_ERR(host); 1057 } 1058 1059 pltfm_host = sdhci_priv(host); 1060 omap_host = sdhci_pltfm_priv(pltfm_host); 1061 omap_host->host = host; 1062 omap_host->base = host->ioaddr; 1063 omap_host->dev = dev; 1064 omap_host->power_mode = MMC_POWER_UNDEFINED; 1065 omap_host->timing = MMC_TIMING_LEGACY; 1066 omap_host->flags = data->flags; 1067 host->ioaddr += offset; 1068 1069 mmc = host->mmc; 1070 sdhci_get_of_property(pdev); 1071 ret = mmc_of_parse(mmc); 1072 if (ret) 1073 goto err_pltfm_free; 1074 1075 soc = soc_device_match(sdhci_omap_soc_devices); 1076 if (soc) { 1077 omap_host->version = "rev11"; 1078 if (!strcmp(dev_name(dev), "4809c000.mmc")) 1079 mmc->f_max = 96000000; 1080 if (!strcmp(dev_name(dev), "480b4000.mmc")) 1081 mmc->f_max = 48000000; 1082 if (!strcmp(dev_name(dev), "480ad000.mmc")) 1083 mmc->f_max = 48000000; 1084 } 1085 1086 if (!mmc_can_gpio_ro(mmc)) 1087 mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT; 1088 1089 pltfm_host->clk = devm_clk_get(dev, "fck"); 1090 if (IS_ERR(pltfm_host->clk)) { 1091 ret = PTR_ERR(pltfm_host->clk); 1092 goto err_pltfm_free; 1093 } 1094 1095 ret = clk_set_rate(pltfm_host->clk, mmc->f_max); 1096 if (ret) { 1097 dev_err(dev, "failed to set clock to %d\n", mmc->f_max); 1098 goto err_pltfm_free; 1099 } 1100 1101 omap_host->pbias = devm_regulator_get_optional(dev, "pbias"); 1102 if (IS_ERR(omap_host->pbias)) { 1103 ret = PTR_ERR(omap_host->pbias); 1104 if (ret != -ENODEV) 1105 goto err_pltfm_free; 1106 dev_dbg(dev, "unable to get pbias regulator %d\n", ret); 1107 } 1108 omap_host->pbias_enabled = false; 1109 1110 /* 1111 * omap_device_pm_domain has callbacks to enable the main 1112 * functional clock, interface clock and also configure the 1113 * SYSCONFIG register of omap devices. The callback will be invoked 1114 * as part of pm_runtime_get_sync. 1115 */ 1116 pm_runtime_enable(dev); 1117 ret = pm_runtime_get_sync(dev); 1118 if (ret < 0) { 1119 dev_err(dev, "pm_runtime_get_sync failed\n"); 1120 pm_runtime_put_noidle(dev); 1121 goto err_rpm_disable; 1122 } 1123 1124 ret = sdhci_omap_set_capabilities(omap_host); 1125 if (ret) { 1126 dev_err(dev, "failed to set system capabilities\n"); 1127 goto err_put_sync; 1128 } 1129 1130 host->mmc_host_ops.start_signal_voltage_switch = 1131 sdhci_omap_start_signal_voltage_switch; 1132 host->mmc_host_ops.set_ios = sdhci_omap_set_ios; 1133 host->mmc_host_ops.card_busy = sdhci_omap_card_busy; 1134 host->mmc_host_ops.execute_tuning = sdhci_omap_execute_tuning; 1135 host->mmc_host_ops.enable_sdio_irq = sdhci_omap_enable_sdio_irq; 1136 1137 ret = sdhci_setup_host(host); 1138 if (ret) 1139 goto err_put_sync; 1140 1141 ret = sdhci_omap_config_iodelay_pinctrl_state(omap_host); 1142 if (ret) 1143 goto err_cleanup_host; 1144 1145 ret = __sdhci_add_host(host); 1146 if (ret) 1147 goto err_cleanup_host; 1148 1149 return 0; 1150 1151 err_cleanup_host: 1152 sdhci_cleanup_host(host); 1153 1154 err_put_sync: 1155 pm_runtime_put_sync(dev); 1156 1157 err_rpm_disable: 1158 pm_runtime_disable(dev); 1159 1160 err_pltfm_free: 1161 sdhci_pltfm_free(pdev); 1162 return ret; 1163 } 1164 1165 static int sdhci_omap_remove(struct platform_device *pdev) 1166 { 1167 struct device *dev = &pdev->dev; 1168 struct sdhci_host *host = platform_get_drvdata(pdev); 1169 1170 sdhci_remove_host(host, true); 1171 pm_runtime_put_sync(dev); 1172 pm_runtime_disable(dev); 1173 sdhci_pltfm_free(pdev); 1174 1175 return 0; 1176 } 1177 1178 static struct platform_driver sdhci_omap_driver = { 1179 .probe = sdhci_omap_probe, 1180 .remove = sdhci_omap_remove, 1181 .driver = { 1182 .name = "sdhci-omap", 1183 .of_match_table = omap_sdhci_match, 1184 }, 1185 }; 1186 1187 module_platform_driver(sdhci_omap_driver); 1188 1189 MODULE_DESCRIPTION("SDHCI driver for OMAP SoCs"); 1190 MODULE_AUTHOR("Texas Instruments Inc."); 1191 MODULE_LICENSE("GPL v2"); 1192 MODULE_ALIAS("platform:sdhci_omap"); 1193