1 /* 2 * Freescale eSDHC controller driver. 3 * 4 * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc. 5 * Copyright (c) 2009 MontaVista Software, Inc. 6 * 7 * Authors: Xiaobo Xie <X.Xie@freescale.com> 8 * Anton Vorontsov <avorontsov@ru.mvista.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or (at 13 * your option) any later version. 14 */ 15 16 #include <linux/err.h> 17 #include <linux/io.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/delay.h> 21 #include <linux/module.h> 22 #include <linux/sys_soc.h> 23 #include <linux/clk.h> 24 #include <linux/ktime.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/mmc/host.h> 27 #include "sdhci-pltfm.h" 28 #include "sdhci-esdhc.h" 29 30 #define VENDOR_V_22 0x12 31 #define VENDOR_V_23 0x13 32 33 #define MMC_TIMING_NUM (MMC_TIMING_MMC_HS400 + 1) 34 35 struct esdhc_clk_fixup { 36 const unsigned int sd_dflt_max_clk; 37 const unsigned int max_clk[MMC_TIMING_NUM]; 38 }; 39 40 static const struct esdhc_clk_fixup ls1021a_esdhc_clk = { 41 .sd_dflt_max_clk = 25000000, 42 .max_clk[MMC_TIMING_MMC_HS] = 46500000, 43 .max_clk[MMC_TIMING_SD_HS] = 46500000, 44 }; 45 46 static const struct esdhc_clk_fixup ls1046a_esdhc_clk = { 47 .sd_dflt_max_clk = 25000000, 48 .max_clk[MMC_TIMING_UHS_SDR104] = 167000000, 49 .max_clk[MMC_TIMING_MMC_HS200] = 167000000, 50 }; 51 52 static const struct esdhc_clk_fixup ls1012a_esdhc_clk = { 53 .sd_dflt_max_clk = 25000000, 54 .max_clk[MMC_TIMING_UHS_SDR104] = 125000000, 55 .max_clk[MMC_TIMING_MMC_HS200] = 125000000, 56 }; 57 58 static const struct esdhc_clk_fixup p1010_esdhc_clk = { 59 .sd_dflt_max_clk = 20000000, 60 .max_clk[MMC_TIMING_LEGACY] = 20000000, 61 .max_clk[MMC_TIMING_MMC_HS] = 42000000, 62 .max_clk[MMC_TIMING_SD_HS] = 40000000, 63 }; 64 65 static const struct of_device_id sdhci_esdhc_of_match[] = { 66 { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk}, 67 { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk}, 68 { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk}, 69 { .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk}, 70 { .compatible = "fsl,mpc8379-esdhc" }, 71 { .compatible = "fsl,mpc8536-esdhc" }, 72 { .compatible = "fsl,esdhc" }, 73 { } 74 }; 75 MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match); 76 77 struct sdhci_esdhc { 78 u8 vendor_ver; 79 u8 spec_ver; 80 bool quirk_incorrect_hostver; 81 unsigned int peripheral_clock; 82 const struct esdhc_clk_fixup *clk_fixup; 83 }; 84 85 /** 86 * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register 87 * to make it compatible with SD spec. 88 * 89 * @host: pointer to sdhci_host 90 * @spec_reg: SD spec register address 91 * @value: 32bit eSDHC register value on spec_reg address 92 * 93 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 94 * registers are 32 bits. There are differences in register size, register 95 * address, register function, bit position and function between eSDHC spec 96 * and SD spec. 97 * 98 * Return a fixed up register value 99 */ 100 static u32 esdhc_readl_fixup(struct sdhci_host *host, 101 int spec_reg, u32 value) 102 { 103 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 104 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 105 u32 ret; 106 107 /* 108 * The bit of ADMA flag in eSDHC is not compatible with standard 109 * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is 110 * supported by eSDHC. 111 * And for many FSL eSDHC controller, the reset value of field 112 * SDHCI_CAN_DO_ADMA1 is 1, but some of them can't support ADMA, 113 * only these vendor version is greater than 2.2/0x12 support ADMA. 114 */ 115 if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) { 116 if (esdhc->vendor_ver > VENDOR_V_22) { 117 ret = value | SDHCI_CAN_DO_ADMA2; 118 return ret; 119 } 120 } 121 /* 122 * The DAT[3:0] line signal levels and the CMD line signal level are 123 * not compatible with standard SDHC register. The line signal levels 124 * DAT[7:0] are at bits 31:24 and the command line signal level is at 125 * bit 23. All other bits are the same as in the standard SDHC 126 * register. 127 */ 128 if (spec_reg == SDHCI_PRESENT_STATE) { 129 ret = value & 0x000fffff; 130 ret |= (value >> 4) & SDHCI_DATA_LVL_MASK; 131 ret |= (value << 1) & SDHCI_CMD_LVL; 132 return ret; 133 } 134 135 /* 136 * DTS properties of mmc host are used to enable each speed mode 137 * according to soc and board capability. So clean up 138 * SDR50/SDR104/DDR50 support bits here. 139 */ 140 if (spec_reg == SDHCI_CAPABILITIES_1) { 141 ret = value & ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | 142 SDHCI_SUPPORT_DDR50); 143 return ret; 144 } 145 146 ret = value; 147 return ret; 148 } 149 150 static u16 esdhc_readw_fixup(struct sdhci_host *host, 151 int spec_reg, u32 value) 152 { 153 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 154 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 155 u16 ret; 156 int shift = (spec_reg & 0x2) * 8; 157 158 if (spec_reg == SDHCI_HOST_VERSION) 159 ret = value & 0xffff; 160 else 161 ret = (value >> shift) & 0xffff; 162 /* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect 163 * vendor version and spec version information. 164 */ 165 if ((spec_reg == SDHCI_HOST_VERSION) && 166 (esdhc->quirk_incorrect_hostver)) 167 ret = (VENDOR_V_23 << SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200; 168 return ret; 169 } 170 171 static u8 esdhc_readb_fixup(struct sdhci_host *host, 172 int spec_reg, u32 value) 173 { 174 u8 ret; 175 u8 dma_bits; 176 int shift = (spec_reg & 0x3) * 8; 177 178 ret = (value >> shift) & 0xff; 179 180 /* 181 * "DMA select" locates at offset 0x28 in SD specification, but on 182 * P5020 or P3041, it locates at 0x29. 183 */ 184 if (spec_reg == SDHCI_HOST_CONTROL) { 185 /* DMA select is 22,23 bits in Protocol Control Register */ 186 dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK; 187 /* fixup the result */ 188 ret &= ~SDHCI_CTRL_DMA_MASK; 189 ret |= dma_bits; 190 } 191 return ret; 192 } 193 194 /** 195 * esdhc_write*_fixup - Fixup the SD spec register value so that it could be 196 * written into eSDHC register. 197 * 198 * @host: pointer to sdhci_host 199 * @spec_reg: SD spec register address 200 * @value: 8/16/32bit SD spec register value that would be written 201 * @old_value: 32bit eSDHC register value on spec_reg address 202 * 203 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 204 * registers are 32 bits. There are differences in register size, register 205 * address, register function, bit position and function between eSDHC spec 206 * and SD spec. 207 * 208 * Return a fixed up register value 209 */ 210 static u32 esdhc_writel_fixup(struct sdhci_host *host, 211 int spec_reg, u32 value, u32 old_value) 212 { 213 u32 ret; 214 215 /* 216 * Enabling IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE] 217 * when SYSCTL[RSTD] is set for some special operations. 218 * No any impact on other operation. 219 */ 220 if (spec_reg == SDHCI_INT_ENABLE) 221 ret = value | SDHCI_INT_BLK_GAP; 222 else 223 ret = value; 224 225 return ret; 226 } 227 228 static u32 esdhc_writew_fixup(struct sdhci_host *host, 229 int spec_reg, u16 value, u32 old_value) 230 { 231 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 232 int shift = (spec_reg & 0x2) * 8; 233 u32 ret; 234 235 switch (spec_reg) { 236 case SDHCI_TRANSFER_MODE: 237 /* 238 * Postpone this write, we must do it together with a 239 * command write that is down below. Return old value. 240 */ 241 pltfm_host->xfer_mode_shadow = value; 242 return old_value; 243 case SDHCI_COMMAND: 244 ret = (value << 16) | pltfm_host->xfer_mode_shadow; 245 return ret; 246 } 247 248 ret = old_value & (~(0xffff << shift)); 249 ret |= (value << shift); 250 251 if (spec_reg == SDHCI_BLOCK_SIZE) { 252 /* 253 * Two last DMA bits are reserved, and first one is used for 254 * non-standard blksz of 4096 bytes that we don't support 255 * yet. So clear the DMA boundary bits. 256 */ 257 ret &= (~SDHCI_MAKE_BLKSZ(0x7, 0)); 258 } 259 return ret; 260 } 261 262 static u32 esdhc_writeb_fixup(struct sdhci_host *host, 263 int spec_reg, u8 value, u32 old_value) 264 { 265 u32 ret; 266 u32 dma_bits; 267 u8 tmp; 268 int shift = (spec_reg & 0x3) * 8; 269 270 /* 271 * eSDHC doesn't have a standard power control register, so we do 272 * nothing here to avoid incorrect operation. 273 */ 274 if (spec_reg == SDHCI_POWER_CONTROL) 275 return old_value; 276 /* 277 * "DMA select" location is offset 0x28 in SD specification, but on 278 * P5020 or P3041, it's located at 0x29. 279 */ 280 if (spec_reg == SDHCI_HOST_CONTROL) { 281 /* 282 * If host control register is not standard, exit 283 * this function 284 */ 285 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL) 286 return old_value; 287 288 /* DMA select is 22,23 bits in Protocol Control Register */ 289 dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5; 290 ret = (old_value & (~(SDHCI_CTRL_DMA_MASK << 5))) | dma_bits; 291 tmp = (value & (~SDHCI_CTRL_DMA_MASK)) | 292 (old_value & SDHCI_CTRL_DMA_MASK); 293 ret = (ret & (~0xff)) | tmp; 294 295 /* Prevent SDHCI core from writing reserved bits (e.g. HISPD) */ 296 ret &= ~ESDHC_HOST_CONTROL_RES; 297 return ret; 298 } 299 300 ret = (old_value & (~(0xff << shift))) | (value << shift); 301 return ret; 302 } 303 304 static u32 esdhc_be_readl(struct sdhci_host *host, int reg) 305 { 306 u32 ret; 307 u32 value; 308 309 if (reg == SDHCI_CAPABILITIES_1) 310 value = ioread32be(host->ioaddr + ESDHC_CAPABILITIES_1); 311 else 312 value = ioread32be(host->ioaddr + reg); 313 314 ret = esdhc_readl_fixup(host, reg, value); 315 316 return ret; 317 } 318 319 static u32 esdhc_le_readl(struct sdhci_host *host, int reg) 320 { 321 u32 ret; 322 u32 value; 323 324 if (reg == SDHCI_CAPABILITIES_1) 325 value = ioread32(host->ioaddr + ESDHC_CAPABILITIES_1); 326 else 327 value = ioread32(host->ioaddr + reg); 328 329 ret = esdhc_readl_fixup(host, reg, value); 330 331 return ret; 332 } 333 334 static u16 esdhc_be_readw(struct sdhci_host *host, int reg) 335 { 336 u16 ret; 337 u32 value; 338 int base = reg & ~0x3; 339 340 value = ioread32be(host->ioaddr + base); 341 ret = esdhc_readw_fixup(host, reg, value); 342 return ret; 343 } 344 345 static u16 esdhc_le_readw(struct sdhci_host *host, int reg) 346 { 347 u16 ret; 348 u32 value; 349 int base = reg & ~0x3; 350 351 value = ioread32(host->ioaddr + base); 352 ret = esdhc_readw_fixup(host, reg, value); 353 return ret; 354 } 355 356 static u8 esdhc_be_readb(struct sdhci_host *host, int reg) 357 { 358 u8 ret; 359 u32 value; 360 int base = reg & ~0x3; 361 362 value = ioread32be(host->ioaddr + base); 363 ret = esdhc_readb_fixup(host, reg, value); 364 return ret; 365 } 366 367 static u8 esdhc_le_readb(struct sdhci_host *host, int reg) 368 { 369 u8 ret; 370 u32 value; 371 int base = reg & ~0x3; 372 373 value = ioread32(host->ioaddr + base); 374 ret = esdhc_readb_fixup(host, reg, value); 375 return ret; 376 } 377 378 static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg) 379 { 380 u32 value; 381 382 value = esdhc_writel_fixup(host, reg, val, 0); 383 iowrite32be(value, host->ioaddr + reg); 384 } 385 386 static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg) 387 { 388 u32 value; 389 390 value = esdhc_writel_fixup(host, reg, val, 0); 391 iowrite32(value, host->ioaddr + reg); 392 } 393 394 static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg) 395 { 396 int base = reg & ~0x3; 397 u32 value; 398 u32 ret; 399 400 value = ioread32be(host->ioaddr + base); 401 ret = esdhc_writew_fixup(host, reg, val, value); 402 if (reg != SDHCI_TRANSFER_MODE) 403 iowrite32be(ret, host->ioaddr + base); 404 } 405 406 static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg) 407 { 408 int base = reg & ~0x3; 409 u32 value; 410 u32 ret; 411 412 value = ioread32(host->ioaddr + base); 413 ret = esdhc_writew_fixup(host, reg, val, value); 414 if (reg != SDHCI_TRANSFER_MODE) 415 iowrite32(ret, host->ioaddr + base); 416 } 417 418 static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg) 419 { 420 int base = reg & ~0x3; 421 u32 value; 422 u32 ret; 423 424 value = ioread32be(host->ioaddr + base); 425 ret = esdhc_writeb_fixup(host, reg, val, value); 426 iowrite32be(ret, host->ioaddr + base); 427 } 428 429 static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg) 430 { 431 int base = reg & ~0x3; 432 u32 value; 433 u32 ret; 434 435 value = ioread32(host->ioaddr + base); 436 ret = esdhc_writeb_fixup(host, reg, val, value); 437 iowrite32(ret, host->ioaddr + base); 438 } 439 440 /* 441 * For Abort or Suspend after Stop at Block Gap, ignore the ADMA 442 * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC]) 443 * and Block Gap Event(IRQSTAT[BGE]) are also set. 444 * For Continue, apply soft reset for data(SYSCTL[RSTD]); 445 * and re-issue the entire read transaction from beginning. 446 */ 447 static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask) 448 { 449 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 450 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 451 bool applicable; 452 dma_addr_t dmastart; 453 dma_addr_t dmanow; 454 455 applicable = (intmask & SDHCI_INT_DATA_END) && 456 (intmask & SDHCI_INT_BLK_GAP) && 457 (esdhc->vendor_ver == VENDOR_V_23); 458 if (!applicable) 459 return; 460 461 host->data->error = 0; 462 dmastart = sg_dma_address(host->data->sg); 463 dmanow = dmastart + host->data->bytes_xfered; 464 /* 465 * Force update to the next DMA block boundary. 466 */ 467 dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 468 SDHCI_DEFAULT_BOUNDARY_SIZE; 469 host->data->bytes_xfered = dmanow - dmastart; 470 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 471 } 472 473 static int esdhc_of_enable_dma(struct sdhci_host *host) 474 { 475 u32 value; 476 struct device *dev = mmc_dev(host->mmc); 477 478 if (of_device_is_compatible(dev->of_node, "fsl,ls1043a-esdhc") || 479 of_device_is_compatible(dev->of_node, "fsl,ls1046a-esdhc")) 480 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); 481 482 value = sdhci_readl(host, ESDHC_DMA_SYSCTL); 483 value |= ESDHC_DMA_SNOOP; 484 sdhci_writel(host, value, ESDHC_DMA_SYSCTL); 485 return 0; 486 } 487 488 static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host) 489 { 490 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 491 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 492 493 if (esdhc->peripheral_clock) 494 return esdhc->peripheral_clock; 495 else 496 return pltfm_host->clock; 497 } 498 499 static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host) 500 { 501 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 502 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 503 unsigned int clock; 504 505 if (esdhc->peripheral_clock) 506 clock = esdhc->peripheral_clock; 507 else 508 clock = pltfm_host->clock; 509 return clock / 256 / 16; 510 } 511 512 static void esdhc_clock_enable(struct sdhci_host *host, bool enable) 513 { 514 u32 val; 515 ktime_t timeout; 516 517 val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 518 519 if (enable) 520 val |= ESDHC_CLOCK_SDCLKEN; 521 else 522 val &= ~ESDHC_CLOCK_SDCLKEN; 523 524 sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL); 525 526 /* Wait max 20 ms */ 527 timeout = ktime_add_ms(ktime_get(), 20); 528 val = ESDHC_CLOCK_STABLE; 529 while (!(sdhci_readl(host, ESDHC_PRSSTAT) & val)) { 530 if (ktime_after(ktime_get(), timeout)) { 531 pr_err("%s: Internal clock never stabilised.\n", 532 mmc_hostname(host->mmc)); 533 break; 534 } 535 udelay(10); 536 } 537 } 538 539 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock) 540 { 541 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 542 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 543 int pre_div = 1; 544 int div = 1; 545 ktime_t timeout; 546 long fixup = 0; 547 u32 temp; 548 549 host->mmc->actual_clock = 0; 550 551 if (clock == 0) { 552 esdhc_clock_enable(host, false); 553 return; 554 } 555 556 /* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */ 557 if (esdhc->vendor_ver < VENDOR_V_23) 558 pre_div = 2; 559 560 if (host->mmc->card && mmc_card_sd(host->mmc->card) && 561 esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY) 562 fixup = esdhc->clk_fixup->sd_dflt_max_clk; 563 else if (esdhc->clk_fixup) 564 fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing]; 565 566 if (fixup && clock > fixup) 567 clock = fixup; 568 569 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 570 temp &= ~(ESDHC_CLOCK_SDCLKEN | ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | 571 ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK); 572 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 573 574 while (host->max_clk / pre_div / 16 > clock && pre_div < 256) 575 pre_div *= 2; 576 577 while (host->max_clk / pre_div / div > clock && div < 16) 578 div++; 579 580 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 581 clock, host->max_clk / pre_div / div); 582 host->mmc->actual_clock = host->max_clk / pre_div / div; 583 pre_div >>= 1; 584 div--; 585 586 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 587 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 588 | (div << ESDHC_DIVIDER_SHIFT) 589 | (pre_div << ESDHC_PREDIV_SHIFT)); 590 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 591 592 /* Wait max 20 ms */ 593 timeout = ktime_add_ms(ktime_get(), 20); 594 while (!(sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE)) { 595 if (ktime_after(ktime_get(), timeout)) { 596 pr_err("%s: Internal clock never stabilised.\n", 597 mmc_hostname(host->mmc)); 598 return; 599 } 600 udelay(10); 601 } 602 603 temp |= ESDHC_CLOCK_SDCLKEN; 604 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 605 } 606 607 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 608 { 609 u32 ctrl; 610 611 ctrl = sdhci_readl(host, ESDHC_PROCTL); 612 ctrl &= (~ESDHC_CTRL_BUSWIDTH_MASK); 613 switch (width) { 614 case MMC_BUS_WIDTH_8: 615 ctrl |= ESDHC_CTRL_8BITBUS; 616 break; 617 618 case MMC_BUS_WIDTH_4: 619 ctrl |= ESDHC_CTRL_4BITBUS; 620 break; 621 622 default: 623 break; 624 } 625 626 sdhci_writel(host, ctrl, ESDHC_PROCTL); 627 } 628 629 static void esdhc_reset(struct sdhci_host *host, u8 mask) 630 { 631 u32 val; 632 633 sdhci_reset(host, mask); 634 635 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 636 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 637 638 if (mask & SDHCI_RESET_ALL) { 639 val = sdhci_readl(host, ESDHC_TBCTL); 640 val &= ~ESDHC_TB_EN; 641 sdhci_writel(host, val, ESDHC_TBCTL); 642 } 643 } 644 645 /* The SCFG, Supplemental Configuration Unit, provides SoC specific 646 * configuration and status registers for the device. There is a 647 * SDHC IO VSEL control register on SCFG for some platforms. It's 648 * used to support SDHC IO voltage switching. 649 */ 650 static const struct of_device_id scfg_device_ids[] = { 651 { .compatible = "fsl,t1040-scfg", }, 652 { .compatible = "fsl,ls1012a-scfg", }, 653 { .compatible = "fsl,ls1046a-scfg", }, 654 {} 655 }; 656 657 /* SDHC IO VSEL control register definition */ 658 #define SCFG_SDHCIOVSELCR 0x408 659 #define SDHCIOVSELCR_TGLEN 0x80000000 660 #define SDHCIOVSELCR_VSELVAL 0x60000000 661 #define SDHCIOVSELCR_SDHC_VS 0x00000001 662 663 static int esdhc_signal_voltage_switch(struct mmc_host *mmc, 664 struct mmc_ios *ios) 665 { 666 struct sdhci_host *host = mmc_priv(mmc); 667 struct device_node *scfg_node; 668 void __iomem *scfg_base = NULL; 669 u32 sdhciovselcr; 670 u32 val; 671 672 /* 673 * Signal Voltage Switching is only applicable for Host Controllers 674 * v3.00 and above. 675 */ 676 if (host->version < SDHCI_SPEC_300) 677 return 0; 678 679 val = sdhci_readl(host, ESDHC_PROCTL); 680 681 switch (ios->signal_voltage) { 682 case MMC_SIGNAL_VOLTAGE_330: 683 val &= ~ESDHC_VOLT_SEL; 684 sdhci_writel(host, val, ESDHC_PROCTL); 685 return 0; 686 case MMC_SIGNAL_VOLTAGE_180: 687 scfg_node = of_find_matching_node(NULL, scfg_device_ids); 688 if (scfg_node) 689 scfg_base = of_iomap(scfg_node, 0); 690 if (scfg_base) { 691 sdhciovselcr = SDHCIOVSELCR_TGLEN | 692 SDHCIOVSELCR_VSELVAL; 693 iowrite32be(sdhciovselcr, 694 scfg_base + SCFG_SDHCIOVSELCR); 695 696 val |= ESDHC_VOLT_SEL; 697 sdhci_writel(host, val, ESDHC_PROCTL); 698 mdelay(5); 699 700 sdhciovselcr = SDHCIOVSELCR_TGLEN | 701 SDHCIOVSELCR_SDHC_VS; 702 iowrite32be(sdhciovselcr, 703 scfg_base + SCFG_SDHCIOVSELCR); 704 iounmap(scfg_base); 705 } else { 706 val |= ESDHC_VOLT_SEL; 707 sdhci_writel(host, val, ESDHC_PROCTL); 708 } 709 return 0; 710 default: 711 return 0; 712 } 713 } 714 715 static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) 716 { 717 struct sdhci_host *host = mmc_priv(mmc); 718 u32 val; 719 720 /* Use tuning block for tuning procedure */ 721 esdhc_clock_enable(host, false); 722 val = sdhci_readl(host, ESDHC_DMA_SYSCTL); 723 val |= ESDHC_FLUSH_ASYNC_FIFO; 724 sdhci_writel(host, val, ESDHC_DMA_SYSCTL); 725 726 val = sdhci_readl(host, ESDHC_TBCTL); 727 val |= ESDHC_TB_EN; 728 sdhci_writel(host, val, ESDHC_TBCTL); 729 esdhc_clock_enable(host, true); 730 731 return sdhci_execute_tuning(mmc, opcode); 732 } 733 734 #ifdef CONFIG_PM_SLEEP 735 static u32 esdhc_proctl; 736 static int esdhc_of_suspend(struct device *dev) 737 { 738 struct sdhci_host *host = dev_get_drvdata(dev); 739 740 esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL); 741 742 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 743 mmc_retune_needed(host->mmc); 744 745 return sdhci_suspend_host(host); 746 } 747 748 static int esdhc_of_resume(struct device *dev) 749 { 750 struct sdhci_host *host = dev_get_drvdata(dev); 751 int ret = sdhci_resume_host(host); 752 753 if (ret == 0) { 754 /* Isn't this already done by sdhci_resume_host() ? --rmk */ 755 esdhc_of_enable_dma(host); 756 sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL); 757 } 758 return ret; 759 } 760 #endif 761 762 static SIMPLE_DEV_PM_OPS(esdhc_of_dev_pm_ops, 763 esdhc_of_suspend, 764 esdhc_of_resume); 765 766 static const struct sdhci_ops sdhci_esdhc_be_ops = { 767 .read_l = esdhc_be_readl, 768 .read_w = esdhc_be_readw, 769 .read_b = esdhc_be_readb, 770 .write_l = esdhc_be_writel, 771 .write_w = esdhc_be_writew, 772 .write_b = esdhc_be_writeb, 773 .set_clock = esdhc_of_set_clock, 774 .enable_dma = esdhc_of_enable_dma, 775 .get_max_clock = esdhc_of_get_max_clock, 776 .get_min_clock = esdhc_of_get_min_clock, 777 .adma_workaround = esdhc_of_adma_workaround, 778 .set_bus_width = esdhc_pltfm_set_bus_width, 779 .reset = esdhc_reset, 780 .set_uhs_signaling = sdhci_set_uhs_signaling, 781 }; 782 783 static const struct sdhci_ops sdhci_esdhc_le_ops = { 784 .read_l = esdhc_le_readl, 785 .read_w = esdhc_le_readw, 786 .read_b = esdhc_le_readb, 787 .write_l = esdhc_le_writel, 788 .write_w = esdhc_le_writew, 789 .write_b = esdhc_le_writeb, 790 .set_clock = esdhc_of_set_clock, 791 .enable_dma = esdhc_of_enable_dma, 792 .get_max_clock = esdhc_of_get_max_clock, 793 .get_min_clock = esdhc_of_get_min_clock, 794 .adma_workaround = esdhc_of_adma_workaround, 795 .set_bus_width = esdhc_pltfm_set_bus_width, 796 .reset = esdhc_reset, 797 .set_uhs_signaling = sdhci_set_uhs_signaling, 798 }; 799 800 static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = { 801 .quirks = ESDHC_DEFAULT_QUIRKS | 802 #ifdef CONFIG_PPC 803 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 804 #endif 805 SDHCI_QUIRK_NO_CARD_NO_RESET | 806 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 807 .ops = &sdhci_esdhc_be_ops, 808 }; 809 810 static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = { 811 .quirks = ESDHC_DEFAULT_QUIRKS | 812 SDHCI_QUIRK_NO_CARD_NO_RESET | 813 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 814 .ops = &sdhci_esdhc_le_ops, 815 }; 816 817 static struct soc_device_attribute soc_incorrect_hostver[] = { 818 { .family = "QorIQ T4240", .revision = "1.0", }, 819 { .family = "QorIQ T4240", .revision = "2.0", }, 820 { }, 821 }; 822 823 static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host) 824 { 825 const struct of_device_id *match; 826 struct sdhci_pltfm_host *pltfm_host; 827 struct sdhci_esdhc *esdhc; 828 struct device_node *np; 829 struct clk *clk; 830 u32 val; 831 u16 host_ver; 832 833 pltfm_host = sdhci_priv(host); 834 esdhc = sdhci_pltfm_priv(pltfm_host); 835 836 host_ver = sdhci_readw(host, SDHCI_HOST_VERSION); 837 esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >> 838 SDHCI_VENDOR_VER_SHIFT; 839 esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK; 840 if (soc_device_match(soc_incorrect_hostver)) 841 esdhc->quirk_incorrect_hostver = true; 842 else 843 esdhc->quirk_incorrect_hostver = false; 844 845 match = of_match_node(sdhci_esdhc_of_match, pdev->dev.of_node); 846 if (match) 847 esdhc->clk_fixup = match->data; 848 np = pdev->dev.of_node; 849 clk = of_clk_get(np, 0); 850 if (!IS_ERR(clk)) { 851 /* 852 * esdhc->peripheral_clock would be assigned with a value 853 * which is eSDHC base clock when use periperal clock. 854 * For ls1046a, the clock value got by common clk API is 855 * peripheral clock while the eSDHC base clock is 1/2 856 * peripheral clock. 857 */ 858 if (of_device_is_compatible(np, "fsl,ls1046a-esdhc")) 859 esdhc->peripheral_clock = clk_get_rate(clk) / 2; 860 else 861 esdhc->peripheral_clock = clk_get_rate(clk); 862 863 clk_put(clk); 864 } 865 866 if (esdhc->peripheral_clock) { 867 esdhc_clock_enable(host, false); 868 val = sdhci_readl(host, ESDHC_DMA_SYSCTL); 869 val |= ESDHC_PERIPHERAL_CLK_SEL; 870 sdhci_writel(host, val, ESDHC_DMA_SYSCTL); 871 esdhc_clock_enable(host, true); 872 } 873 } 874 875 static int sdhci_esdhc_probe(struct platform_device *pdev) 876 { 877 struct sdhci_host *host; 878 struct device_node *np; 879 struct sdhci_pltfm_host *pltfm_host; 880 struct sdhci_esdhc *esdhc; 881 int ret; 882 883 np = pdev->dev.of_node; 884 885 if (of_property_read_bool(np, "little-endian")) 886 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata, 887 sizeof(struct sdhci_esdhc)); 888 else 889 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata, 890 sizeof(struct sdhci_esdhc)); 891 892 if (IS_ERR(host)) 893 return PTR_ERR(host); 894 895 host->mmc_host_ops.start_signal_voltage_switch = 896 esdhc_signal_voltage_switch; 897 host->mmc_host_ops.execute_tuning = esdhc_execute_tuning; 898 host->tuning_delay = 1; 899 900 esdhc_init(pdev, host); 901 902 sdhci_get_of_property(pdev); 903 904 pltfm_host = sdhci_priv(host); 905 esdhc = sdhci_pltfm_priv(pltfm_host); 906 if (esdhc->vendor_ver == VENDOR_V_22) 907 host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; 908 909 if (esdhc->vendor_ver > VENDOR_V_22) 910 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; 911 912 if (of_device_is_compatible(np, "fsl,p5040-esdhc") || 913 of_device_is_compatible(np, "fsl,p5020-esdhc") || 914 of_device_is_compatible(np, "fsl,p4080-esdhc") || 915 of_device_is_compatible(np, "fsl,p1020-esdhc") || 916 of_device_is_compatible(np, "fsl,t1040-esdhc")) 917 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 918 919 if (of_device_is_compatible(np, "fsl,ls1021a-esdhc")) 920 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 921 922 if (of_device_is_compatible(np, "fsl,p2020-esdhc")) { 923 /* 924 * Freescale messed up with P2020 as it has a non-standard 925 * host control register 926 */ 927 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL; 928 } 929 930 /* call to generic mmc_of_parse to support additional capabilities */ 931 ret = mmc_of_parse(host->mmc); 932 if (ret) 933 goto err; 934 935 mmc_of_parse_voltage(np, &host->ocr_mask); 936 937 ret = sdhci_add_host(host); 938 if (ret) 939 goto err; 940 941 return 0; 942 err: 943 sdhci_pltfm_free(pdev); 944 return ret; 945 } 946 947 static struct platform_driver sdhci_esdhc_driver = { 948 .driver = { 949 .name = "sdhci-esdhc", 950 .of_match_table = sdhci_esdhc_of_match, 951 .pm = &esdhc_of_dev_pm_ops, 952 }, 953 .probe = sdhci_esdhc_probe, 954 .remove = sdhci_pltfm_unregister, 955 }; 956 957 module_platform_driver(sdhci_esdhc_driver); 958 959 MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC"); 960 MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, " 961 "Anton Vorontsov <avorontsov@ru.mvista.com>"); 962 MODULE_LICENSE("GPL v2"); 963