1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Freescale eSDHC controller driver. 4 * 5 * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc. 6 * Copyright (c) 2009 MontaVista Software, Inc. 7 * 8 * Authors: Xiaobo Xie <X.Xie@freescale.com> 9 * Anton Vorontsov <avorontsov@ru.mvista.com> 10 */ 11 12 #include <linux/err.h> 13 #include <linux/io.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/delay.h> 17 #include <linux/module.h> 18 #include <linux/sys_soc.h> 19 #include <linux/clk.h> 20 #include <linux/ktime.h> 21 #include <linux/dma-mapping.h> 22 #include <linux/mmc/host.h> 23 #include <linux/mmc/mmc.h> 24 #include "sdhci-pltfm.h" 25 #include "sdhci-esdhc.h" 26 27 #define VENDOR_V_22 0x12 28 #define VENDOR_V_23 0x13 29 30 #define MMC_TIMING_NUM (MMC_TIMING_MMC_HS400 + 1) 31 32 struct esdhc_clk_fixup { 33 const unsigned int sd_dflt_max_clk; 34 const unsigned int max_clk[MMC_TIMING_NUM]; 35 }; 36 37 static const struct esdhc_clk_fixup ls1021a_esdhc_clk = { 38 .sd_dflt_max_clk = 25000000, 39 .max_clk[MMC_TIMING_MMC_HS] = 46500000, 40 .max_clk[MMC_TIMING_SD_HS] = 46500000, 41 }; 42 43 static const struct esdhc_clk_fixup ls1046a_esdhc_clk = { 44 .sd_dflt_max_clk = 25000000, 45 .max_clk[MMC_TIMING_UHS_SDR104] = 167000000, 46 .max_clk[MMC_TIMING_MMC_HS200] = 167000000, 47 }; 48 49 static const struct esdhc_clk_fixup ls1012a_esdhc_clk = { 50 .sd_dflt_max_clk = 25000000, 51 .max_clk[MMC_TIMING_UHS_SDR104] = 125000000, 52 .max_clk[MMC_TIMING_MMC_HS200] = 125000000, 53 }; 54 55 static const struct esdhc_clk_fixup p1010_esdhc_clk = { 56 .sd_dflt_max_clk = 20000000, 57 .max_clk[MMC_TIMING_LEGACY] = 20000000, 58 .max_clk[MMC_TIMING_MMC_HS] = 42000000, 59 .max_clk[MMC_TIMING_SD_HS] = 40000000, 60 }; 61 62 static const struct of_device_id sdhci_esdhc_of_match[] = { 63 { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk}, 64 { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk}, 65 { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk}, 66 { .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk}, 67 { .compatible = "fsl,mpc8379-esdhc" }, 68 { .compatible = "fsl,mpc8536-esdhc" }, 69 { .compatible = "fsl,esdhc" }, 70 { } 71 }; 72 MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match); 73 74 struct sdhci_esdhc { 75 u8 vendor_ver; 76 u8 spec_ver; 77 bool quirk_incorrect_hostver; 78 bool quirk_limited_clk_division; 79 bool quirk_unreliable_pulse_detection; 80 bool quirk_tuning_erratum_type1; 81 bool quirk_tuning_erratum_type2; 82 bool quirk_ignore_data_inhibit; 83 bool quirk_delay_before_data_reset; 84 bool in_sw_tuning; 85 unsigned int peripheral_clock; 86 const struct esdhc_clk_fixup *clk_fixup; 87 u32 div_ratio; 88 }; 89 90 /** 91 * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register 92 * to make it compatible with SD spec. 93 * 94 * @host: pointer to sdhci_host 95 * @spec_reg: SD spec register address 96 * @value: 32bit eSDHC register value on spec_reg address 97 * 98 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 99 * registers are 32 bits. There are differences in register size, register 100 * address, register function, bit position and function between eSDHC spec 101 * and SD spec. 102 * 103 * Return a fixed up register value 104 */ 105 static u32 esdhc_readl_fixup(struct sdhci_host *host, 106 int spec_reg, u32 value) 107 { 108 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 109 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 110 u32 ret; 111 112 /* 113 * The bit of ADMA flag in eSDHC is not compatible with standard 114 * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is 115 * supported by eSDHC. 116 * And for many FSL eSDHC controller, the reset value of field 117 * SDHCI_CAN_DO_ADMA1 is 1, but some of them can't support ADMA, 118 * only these vendor version is greater than 2.2/0x12 support ADMA. 119 */ 120 if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) { 121 if (esdhc->vendor_ver > VENDOR_V_22) { 122 ret = value | SDHCI_CAN_DO_ADMA2; 123 return ret; 124 } 125 } 126 /* 127 * The DAT[3:0] line signal levels and the CMD line signal level are 128 * not compatible with standard SDHC register. The line signal levels 129 * DAT[7:0] are at bits 31:24 and the command line signal level is at 130 * bit 23. All other bits are the same as in the standard SDHC 131 * register. 132 */ 133 if (spec_reg == SDHCI_PRESENT_STATE) { 134 ret = value & 0x000fffff; 135 ret |= (value >> 4) & SDHCI_DATA_LVL_MASK; 136 ret |= (value << 1) & SDHCI_CMD_LVL; 137 return ret; 138 } 139 140 /* 141 * DTS properties of mmc host are used to enable each speed mode 142 * according to soc and board capability. So clean up 143 * SDR50/SDR104/DDR50 support bits here. 144 */ 145 if (spec_reg == SDHCI_CAPABILITIES_1) { 146 ret = value & ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | 147 SDHCI_SUPPORT_DDR50); 148 return ret; 149 } 150 151 /* 152 * Some controllers have unreliable Data Line Active 153 * bit for commands with busy signal. This affects 154 * Command Inhibit (data) bit. Just ignore it since 155 * MMC core driver has already polled card status 156 * with CMD13 after any command with busy siganl. 157 */ 158 if ((spec_reg == SDHCI_PRESENT_STATE) && 159 (esdhc->quirk_ignore_data_inhibit == true)) { 160 ret = value & ~SDHCI_DATA_INHIBIT; 161 return ret; 162 } 163 164 ret = value; 165 return ret; 166 } 167 168 static u16 esdhc_readw_fixup(struct sdhci_host *host, 169 int spec_reg, u32 value) 170 { 171 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 172 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 173 u16 ret; 174 int shift = (spec_reg & 0x2) * 8; 175 176 if (spec_reg == SDHCI_HOST_VERSION) 177 ret = value & 0xffff; 178 else 179 ret = (value >> shift) & 0xffff; 180 /* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect 181 * vendor version and spec version information. 182 */ 183 if ((spec_reg == SDHCI_HOST_VERSION) && 184 (esdhc->quirk_incorrect_hostver)) 185 ret = (VENDOR_V_23 << SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200; 186 return ret; 187 } 188 189 static u8 esdhc_readb_fixup(struct sdhci_host *host, 190 int spec_reg, u32 value) 191 { 192 u8 ret; 193 u8 dma_bits; 194 int shift = (spec_reg & 0x3) * 8; 195 196 ret = (value >> shift) & 0xff; 197 198 /* 199 * "DMA select" locates at offset 0x28 in SD specification, but on 200 * P5020 or P3041, it locates at 0x29. 201 */ 202 if (spec_reg == SDHCI_HOST_CONTROL) { 203 /* DMA select is 22,23 bits in Protocol Control Register */ 204 dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK; 205 /* fixup the result */ 206 ret &= ~SDHCI_CTRL_DMA_MASK; 207 ret |= dma_bits; 208 } 209 return ret; 210 } 211 212 /** 213 * esdhc_write*_fixup - Fixup the SD spec register value so that it could be 214 * written into eSDHC register. 215 * 216 * @host: pointer to sdhci_host 217 * @spec_reg: SD spec register address 218 * @value: 8/16/32bit SD spec register value that would be written 219 * @old_value: 32bit eSDHC register value on spec_reg address 220 * 221 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 222 * registers are 32 bits. There are differences in register size, register 223 * address, register function, bit position and function between eSDHC spec 224 * and SD spec. 225 * 226 * Return a fixed up register value 227 */ 228 static u32 esdhc_writel_fixup(struct sdhci_host *host, 229 int spec_reg, u32 value, u32 old_value) 230 { 231 u32 ret; 232 233 /* 234 * Enabling IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE] 235 * when SYSCTL[RSTD] is set for some special operations. 236 * No any impact on other operation. 237 */ 238 if (spec_reg == SDHCI_INT_ENABLE) 239 ret = value | SDHCI_INT_BLK_GAP; 240 else 241 ret = value; 242 243 return ret; 244 } 245 246 static u32 esdhc_writew_fixup(struct sdhci_host *host, 247 int spec_reg, u16 value, u32 old_value) 248 { 249 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 250 int shift = (spec_reg & 0x2) * 8; 251 u32 ret; 252 253 switch (spec_reg) { 254 case SDHCI_TRANSFER_MODE: 255 /* 256 * Postpone this write, we must do it together with a 257 * command write that is down below. Return old value. 258 */ 259 pltfm_host->xfer_mode_shadow = value; 260 return old_value; 261 case SDHCI_COMMAND: 262 ret = (value << 16) | pltfm_host->xfer_mode_shadow; 263 return ret; 264 } 265 266 ret = old_value & (~(0xffff << shift)); 267 ret |= (value << shift); 268 269 if (spec_reg == SDHCI_BLOCK_SIZE) { 270 /* 271 * Two last DMA bits are reserved, and first one is used for 272 * non-standard blksz of 4096 bytes that we don't support 273 * yet. So clear the DMA boundary bits. 274 */ 275 ret &= (~SDHCI_MAKE_BLKSZ(0x7, 0)); 276 } 277 return ret; 278 } 279 280 static u32 esdhc_writeb_fixup(struct sdhci_host *host, 281 int spec_reg, u8 value, u32 old_value) 282 { 283 u32 ret; 284 u32 dma_bits; 285 u8 tmp; 286 int shift = (spec_reg & 0x3) * 8; 287 288 /* 289 * eSDHC doesn't have a standard power control register, so we do 290 * nothing here to avoid incorrect operation. 291 */ 292 if (spec_reg == SDHCI_POWER_CONTROL) 293 return old_value; 294 /* 295 * "DMA select" location is offset 0x28 in SD specification, but on 296 * P5020 or P3041, it's located at 0x29. 297 */ 298 if (spec_reg == SDHCI_HOST_CONTROL) { 299 /* 300 * If host control register is not standard, exit 301 * this function 302 */ 303 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL) 304 return old_value; 305 306 /* DMA select is 22,23 bits in Protocol Control Register */ 307 dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5; 308 ret = (old_value & (~(SDHCI_CTRL_DMA_MASK << 5))) | dma_bits; 309 tmp = (value & (~SDHCI_CTRL_DMA_MASK)) | 310 (old_value & SDHCI_CTRL_DMA_MASK); 311 ret = (ret & (~0xff)) | tmp; 312 313 /* Prevent SDHCI core from writing reserved bits (e.g. HISPD) */ 314 ret &= ~ESDHC_HOST_CONTROL_RES; 315 return ret; 316 } 317 318 ret = (old_value & (~(0xff << shift))) | (value << shift); 319 return ret; 320 } 321 322 static u32 esdhc_be_readl(struct sdhci_host *host, int reg) 323 { 324 u32 ret; 325 u32 value; 326 327 if (reg == SDHCI_CAPABILITIES_1) 328 value = ioread32be(host->ioaddr + ESDHC_CAPABILITIES_1); 329 else 330 value = ioread32be(host->ioaddr + reg); 331 332 ret = esdhc_readl_fixup(host, reg, value); 333 334 return ret; 335 } 336 337 static u32 esdhc_le_readl(struct sdhci_host *host, int reg) 338 { 339 u32 ret; 340 u32 value; 341 342 if (reg == SDHCI_CAPABILITIES_1) 343 value = ioread32(host->ioaddr + ESDHC_CAPABILITIES_1); 344 else 345 value = ioread32(host->ioaddr + reg); 346 347 ret = esdhc_readl_fixup(host, reg, value); 348 349 return ret; 350 } 351 352 static u16 esdhc_be_readw(struct sdhci_host *host, int reg) 353 { 354 u16 ret; 355 u32 value; 356 int base = reg & ~0x3; 357 358 value = ioread32be(host->ioaddr + base); 359 ret = esdhc_readw_fixup(host, reg, value); 360 return ret; 361 } 362 363 static u16 esdhc_le_readw(struct sdhci_host *host, int reg) 364 { 365 u16 ret; 366 u32 value; 367 int base = reg & ~0x3; 368 369 value = ioread32(host->ioaddr + base); 370 ret = esdhc_readw_fixup(host, reg, value); 371 return ret; 372 } 373 374 static u8 esdhc_be_readb(struct sdhci_host *host, int reg) 375 { 376 u8 ret; 377 u32 value; 378 int base = reg & ~0x3; 379 380 value = ioread32be(host->ioaddr + base); 381 ret = esdhc_readb_fixup(host, reg, value); 382 return ret; 383 } 384 385 static u8 esdhc_le_readb(struct sdhci_host *host, int reg) 386 { 387 u8 ret; 388 u32 value; 389 int base = reg & ~0x3; 390 391 value = ioread32(host->ioaddr + base); 392 ret = esdhc_readb_fixup(host, reg, value); 393 return ret; 394 } 395 396 static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg) 397 { 398 u32 value; 399 400 value = esdhc_writel_fixup(host, reg, val, 0); 401 iowrite32be(value, host->ioaddr + reg); 402 } 403 404 static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg) 405 { 406 u32 value; 407 408 value = esdhc_writel_fixup(host, reg, val, 0); 409 iowrite32(value, host->ioaddr + reg); 410 } 411 412 static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg) 413 { 414 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 415 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 416 int base = reg & ~0x3; 417 u32 value; 418 u32 ret; 419 420 value = ioread32be(host->ioaddr + base); 421 ret = esdhc_writew_fixup(host, reg, val, value); 422 if (reg != SDHCI_TRANSFER_MODE) 423 iowrite32be(ret, host->ioaddr + base); 424 425 /* Starting SW tuning requires ESDHC_SMPCLKSEL to be set 426 * 1us later after ESDHC_EXTN is set. 427 */ 428 if (base == ESDHC_SYSTEM_CONTROL_2) { 429 if (!(value & ESDHC_EXTN) && (ret & ESDHC_EXTN) && 430 esdhc->in_sw_tuning) { 431 udelay(1); 432 ret |= ESDHC_SMPCLKSEL; 433 iowrite32be(ret, host->ioaddr + base); 434 } 435 } 436 } 437 438 static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg) 439 { 440 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 441 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 442 int base = reg & ~0x3; 443 u32 value; 444 u32 ret; 445 446 value = ioread32(host->ioaddr + base); 447 ret = esdhc_writew_fixup(host, reg, val, value); 448 if (reg != SDHCI_TRANSFER_MODE) 449 iowrite32(ret, host->ioaddr + base); 450 451 /* Starting SW tuning requires ESDHC_SMPCLKSEL to be set 452 * 1us later after ESDHC_EXTN is set. 453 */ 454 if (base == ESDHC_SYSTEM_CONTROL_2) { 455 if (!(value & ESDHC_EXTN) && (ret & ESDHC_EXTN) && 456 esdhc->in_sw_tuning) { 457 udelay(1); 458 ret |= ESDHC_SMPCLKSEL; 459 iowrite32(ret, host->ioaddr + base); 460 } 461 } 462 } 463 464 static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg) 465 { 466 int base = reg & ~0x3; 467 u32 value; 468 u32 ret; 469 470 value = ioread32be(host->ioaddr + base); 471 ret = esdhc_writeb_fixup(host, reg, val, value); 472 iowrite32be(ret, host->ioaddr + base); 473 } 474 475 static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg) 476 { 477 int base = reg & ~0x3; 478 u32 value; 479 u32 ret; 480 481 value = ioread32(host->ioaddr + base); 482 ret = esdhc_writeb_fixup(host, reg, val, value); 483 iowrite32(ret, host->ioaddr + base); 484 } 485 486 /* 487 * For Abort or Suspend after Stop at Block Gap, ignore the ADMA 488 * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC]) 489 * and Block Gap Event(IRQSTAT[BGE]) are also set. 490 * For Continue, apply soft reset for data(SYSCTL[RSTD]); 491 * and re-issue the entire read transaction from beginning. 492 */ 493 static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask) 494 { 495 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 496 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 497 bool applicable; 498 dma_addr_t dmastart; 499 dma_addr_t dmanow; 500 501 applicable = (intmask & SDHCI_INT_DATA_END) && 502 (intmask & SDHCI_INT_BLK_GAP) && 503 (esdhc->vendor_ver == VENDOR_V_23); 504 if (!applicable) 505 return; 506 507 host->data->error = 0; 508 dmastart = sg_dma_address(host->data->sg); 509 dmanow = dmastart + host->data->bytes_xfered; 510 /* 511 * Force update to the next DMA block boundary. 512 */ 513 dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 514 SDHCI_DEFAULT_BOUNDARY_SIZE; 515 host->data->bytes_xfered = dmanow - dmastart; 516 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 517 } 518 519 static int esdhc_of_enable_dma(struct sdhci_host *host) 520 { 521 u32 value; 522 struct device *dev = mmc_dev(host->mmc); 523 524 if (of_device_is_compatible(dev->of_node, "fsl,ls1043a-esdhc") || 525 of_device_is_compatible(dev->of_node, "fsl,ls1046a-esdhc")) 526 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); 527 528 value = sdhci_readl(host, ESDHC_DMA_SYSCTL); 529 530 if (of_dma_is_coherent(dev->of_node)) 531 value |= ESDHC_DMA_SNOOP; 532 else 533 value &= ~ESDHC_DMA_SNOOP; 534 535 sdhci_writel(host, value, ESDHC_DMA_SYSCTL); 536 return 0; 537 } 538 539 static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host) 540 { 541 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 542 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 543 544 if (esdhc->peripheral_clock) 545 return esdhc->peripheral_clock; 546 else 547 return pltfm_host->clock; 548 } 549 550 static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host) 551 { 552 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 553 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 554 unsigned int clock; 555 556 if (esdhc->peripheral_clock) 557 clock = esdhc->peripheral_clock; 558 else 559 clock = pltfm_host->clock; 560 return clock / 256 / 16; 561 } 562 563 static void esdhc_clock_enable(struct sdhci_host *host, bool enable) 564 { 565 u32 val; 566 ktime_t timeout; 567 568 val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 569 570 if (enable) 571 val |= ESDHC_CLOCK_SDCLKEN; 572 else 573 val &= ~ESDHC_CLOCK_SDCLKEN; 574 575 sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL); 576 577 /* Wait max 20 ms */ 578 timeout = ktime_add_ms(ktime_get(), 20); 579 val = ESDHC_CLOCK_STABLE; 580 while (1) { 581 bool timedout = ktime_after(ktime_get(), timeout); 582 583 if (sdhci_readl(host, ESDHC_PRSSTAT) & val) 584 break; 585 if (timedout) { 586 pr_err("%s: Internal clock never stabilised.\n", 587 mmc_hostname(host->mmc)); 588 break; 589 } 590 udelay(10); 591 } 592 } 593 594 static void esdhc_flush_async_fifo(struct sdhci_host *host) 595 { 596 ktime_t timeout; 597 u32 val; 598 599 val = sdhci_readl(host, ESDHC_DMA_SYSCTL); 600 val |= ESDHC_FLUSH_ASYNC_FIFO; 601 sdhci_writel(host, val, ESDHC_DMA_SYSCTL); 602 603 /* Wait max 20 ms */ 604 timeout = ktime_add_ms(ktime_get(), 20); 605 while (1) { 606 bool timedout = ktime_after(ktime_get(), timeout); 607 608 if (!(sdhci_readl(host, ESDHC_DMA_SYSCTL) & 609 ESDHC_FLUSH_ASYNC_FIFO)) 610 break; 611 if (timedout) { 612 pr_err("%s: flushing asynchronous FIFO timeout.\n", 613 mmc_hostname(host->mmc)); 614 break; 615 } 616 usleep_range(10, 20); 617 } 618 } 619 620 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock) 621 { 622 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 623 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 624 int pre_div = 1; 625 int div = 1; 626 int division; 627 ktime_t timeout; 628 long fixup = 0; 629 u32 temp; 630 631 host->mmc->actual_clock = 0; 632 633 if (clock == 0) { 634 esdhc_clock_enable(host, false); 635 return; 636 } 637 638 /* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */ 639 if (esdhc->vendor_ver < VENDOR_V_23) 640 pre_div = 2; 641 642 if (host->mmc->card && mmc_card_sd(host->mmc->card) && 643 esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY) 644 fixup = esdhc->clk_fixup->sd_dflt_max_clk; 645 else if (esdhc->clk_fixup) 646 fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing]; 647 648 if (fixup && clock > fixup) 649 clock = fixup; 650 651 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 652 temp &= ~(ESDHC_CLOCK_SDCLKEN | ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | 653 ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK); 654 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 655 656 while (host->max_clk / pre_div / 16 > clock && pre_div < 256) 657 pre_div *= 2; 658 659 while (host->max_clk / pre_div / div > clock && div < 16) 660 div++; 661 662 if (esdhc->quirk_limited_clk_division && 663 clock == MMC_HS200_MAX_DTR && 664 (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 || 665 host->flags & SDHCI_HS400_TUNING)) { 666 division = pre_div * div; 667 if (division <= 4) { 668 pre_div = 4; 669 div = 1; 670 } else if (division <= 8) { 671 pre_div = 4; 672 div = 2; 673 } else if (division <= 12) { 674 pre_div = 4; 675 div = 3; 676 } else { 677 pr_warn("%s: using unsupported clock division.\n", 678 mmc_hostname(host->mmc)); 679 } 680 } 681 682 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 683 clock, host->max_clk / pre_div / div); 684 host->mmc->actual_clock = host->max_clk / pre_div / div; 685 esdhc->div_ratio = pre_div * div; 686 pre_div >>= 1; 687 div--; 688 689 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 690 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 691 | (div << ESDHC_DIVIDER_SHIFT) 692 | (pre_div << ESDHC_PREDIV_SHIFT)); 693 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 694 695 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && 696 clock == MMC_HS200_MAX_DTR) { 697 temp = sdhci_readl(host, ESDHC_TBCTL); 698 sdhci_writel(host, temp | ESDHC_HS400_MODE, ESDHC_TBCTL); 699 temp = sdhci_readl(host, ESDHC_SDCLKCTL); 700 sdhci_writel(host, temp | ESDHC_CMD_CLK_CTL, ESDHC_SDCLKCTL); 701 esdhc_clock_enable(host, true); 702 703 temp = sdhci_readl(host, ESDHC_DLLCFG0); 704 temp |= ESDHC_DLL_ENABLE; 705 if (host->mmc->actual_clock == MMC_HS200_MAX_DTR) 706 temp |= ESDHC_DLL_FREQ_SEL; 707 sdhci_writel(host, temp, ESDHC_DLLCFG0); 708 temp = sdhci_readl(host, ESDHC_TBCTL); 709 sdhci_writel(host, temp | ESDHC_HS400_WNDW_ADJUST, ESDHC_TBCTL); 710 711 esdhc_clock_enable(host, false); 712 esdhc_flush_async_fifo(host); 713 } 714 715 /* Wait max 20 ms */ 716 timeout = ktime_add_ms(ktime_get(), 20); 717 while (1) { 718 bool timedout = ktime_after(ktime_get(), timeout); 719 720 if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE) 721 break; 722 if (timedout) { 723 pr_err("%s: Internal clock never stabilised.\n", 724 mmc_hostname(host->mmc)); 725 return; 726 } 727 udelay(10); 728 } 729 730 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 731 temp |= ESDHC_CLOCK_SDCLKEN; 732 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 733 } 734 735 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 736 { 737 u32 ctrl; 738 739 ctrl = sdhci_readl(host, ESDHC_PROCTL); 740 ctrl &= (~ESDHC_CTRL_BUSWIDTH_MASK); 741 switch (width) { 742 case MMC_BUS_WIDTH_8: 743 ctrl |= ESDHC_CTRL_8BITBUS; 744 break; 745 746 case MMC_BUS_WIDTH_4: 747 ctrl |= ESDHC_CTRL_4BITBUS; 748 break; 749 750 default: 751 break; 752 } 753 754 sdhci_writel(host, ctrl, ESDHC_PROCTL); 755 } 756 757 static void esdhc_reset(struct sdhci_host *host, u8 mask) 758 { 759 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 760 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 761 u32 val; 762 763 if (esdhc->quirk_delay_before_data_reset && 764 (mask & SDHCI_RESET_DATA) && 765 (host->flags & SDHCI_REQ_USE_DMA)) 766 mdelay(5); 767 768 sdhci_reset(host, mask); 769 770 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 771 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 772 773 if (mask & SDHCI_RESET_ALL) { 774 val = sdhci_readl(host, ESDHC_TBCTL); 775 val &= ~ESDHC_TB_EN; 776 sdhci_writel(host, val, ESDHC_TBCTL); 777 778 if (esdhc->quirk_unreliable_pulse_detection) { 779 val = sdhci_readl(host, ESDHC_DLLCFG1); 780 val &= ~ESDHC_DLL_PD_PULSE_STRETCH_SEL; 781 sdhci_writel(host, val, ESDHC_DLLCFG1); 782 } 783 } 784 } 785 786 /* The SCFG, Supplemental Configuration Unit, provides SoC specific 787 * configuration and status registers for the device. There is a 788 * SDHC IO VSEL control register on SCFG for some platforms. It's 789 * used to support SDHC IO voltage switching. 790 */ 791 static const struct of_device_id scfg_device_ids[] = { 792 { .compatible = "fsl,t1040-scfg", }, 793 { .compatible = "fsl,ls1012a-scfg", }, 794 { .compatible = "fsl,ls1046a-scfg", }, 795 {} 796 }; 797 798 /* SDHC IO VSEL control register definition */ 799 #define SCFG_SDHCIOVSELCR 0x408 800 #define SDHCIOVSELCR_TGLEN 0x80000000 801 #define SDHCIOVSELCR_VSELVAL 0x60000000 802 #define SDHCIOVSELCR_SDHC_VS 0x00000001 803 804 static int esdhc_signal_voltage_switch(struct mmc_host *mmc, 805 struct mmc_ios *ios) 806 { 807 struct sdhci_host *host = mmc_priv(mmc); 808 struct device_node *scfg_node; 809 void __iomem *scfg_base = NULL; 810 u32 sdhciovselcr; 811 u32 val; 812 813 /* 814 * Signal Voltage Switching is only applicable for Host Controllers 815 * v3.00 and above. 816 */ 817 if (host->version < SDHCI_SPEC_300) 818 return 0; 819 820 val = sdhci_readl(host, ESDHC_PROCTL); 821 822 switch (ios->signal_voltage) { 823 case MMC_SIGNAL_VOLTAGE_330: 824 val &= ~ESDHC_VOLT_SEL; 825 sdhci_writel(host, val, ESDHC_PROCTL); 826 return 0; 827 case MMC_SIGNAL_VOLTAGE_180: 828 scfg_node = of_find_matching_node(NULL, scfg_device_ids); 829 if (scfg_node) 830 scfg_base = of_iomap(scfg_node, 0); 831 if (scfg_base) { 832 sdhciovselcr = SDHCIOVSELCR_TGLEN | 833 SDHCIOVSELCR_VSELVAL; 834 iowrite32be(sdhciovselcr, 835 scfg_base + SCFG_SDHCIOVSELCR); 836 837 val |= ESDHC_VOLT_SEL; 838 sdhci_writel(host, val, ESDHC_PROCTL); 839 mdelay(5); 840 841 sdhciovselcr = SDHCIOVSELCR_TGLEN | 842 SDHCIOVSELCR_SDHC_VS; 843 iowrite32be(sdhciovselcr, 844 scfg_base + SCFG_SDHCIOVSELCR); 845 iounmap(scfg_base); 846 } else { 847 val |= ESDHC_VOLT_SEL; 848 sdhci_writel(host, val, ESDHC_PROCTL); 849 } 850 return 0; 851 default: 852 return 0; 853 } 854 } 855 856 static struct soc_device_attribute soc_tuning_erratum_type1[] = { 857 { .family = "QorIQ T1023", .revision = "1.0", }, 858 { .family = "QorIQ T1040", .revision = "1.0", }, 859 { .family = "QorIQ T2080", .revision = "1.0", }, 860 { .family = "QorIQ LS1021A", .revision = "1.0", }, 861 { }, 862 }; 863 864 static struct soc_device_attribute soc_tuning_erratum_type2[] = { 865 { .family = "QorIQ LS1012A", .revision = "1.0", }, 866 { .family = "QorIQ LS1043A", .revision = "1.*", }, 867 { .family = "QorIQ LS1046A", .revision = "1.0", }, 868 { .family = "QorIQ LS1080A", .revision = "1.0", }, 869 { .family = "QorIQ LS2080A", .revision = "1.0", }, 870 { .family = "QorIQ LA1575A", .revision = "1.0", }, 871 { }, 872 }; 873 874 static void esdhc_tuning_block_enable(struct sdhci_host *host, bool enable) 875 { 876 u32 val; 877 878 esdhc_clock_enable(host, false); 879 esdhc_flush_async_fifo(host); 880 881 val = sdhci_readl(host, ESDHC_TBCTL); 882 if (enable) 883 val |= ESDHC_TB_EN; 884 else 885 val &= ~ESDHC_TB_EN; 886 sdhci_writel(host, val, ESDHC_TBCTL); 887 888 esdhc_clock_enable(host, true); 889 } 890 891 static void esdhc_prepare_sw_tuning(struct sdhci_host *host, u8 *window_start, 892 u8 *window_end) 893 { 894 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 895 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 896 u8 tbstat_15_8, tbstat_7_0; 897 u32 val; 898 899 if (esdhc->quirk_tuning_erratum_type1) { 900 *window_start = 5 * esdhc->div_ratio; 901 *window_end = 3 * esdhc->div_ratio; 902 return; 903 } 904 905 /* Write TBCTL[11:8]=4'h8 */ 906 val = sdhci_readl(host, ESDHC_TBCTL); 907 val &= ~(0xf << 8); 908 val |= 8 << 8; 909 sdhci_writel(host, val, ESDHC_TBCTL); 910 911 mdelay(1); 912 913 /* Read TBCTL[31:0] register and rewrite again */ 914 val = sdhci_readl(host, ESDHC_TBCTL); 915 sdhci_writel(host, val, ESDHC_TBCTL); 916 917 mdelay(1); 918 919 /* Read the TBSTAT[31:0] register twice */ 920 val = sdhci_readl(host, ESDHC_TBSTAT); 921 val = sdhci_readl(host, ESDHC_TBSTAT); 922 923 /* Reset data lines by setting ESDHCCTL[RSTD] */ 924 sdhci_reset(host, SDHCI_RESET_DATA); 925 /* Write 32'hFFFF_FFFF to IRQSTAT register */ 926 sdhci_writel(host, 0xFFFFFFFF, SDHCI_INT_STATUS); 927 928 /* If TBSTAT[15:8]-TBSTAT[7:0] > 4 * div_ratio 929 * or TBSTAT[7:0]-TBSTAT[15:8] > 4 * div_ratio, 930 * then program TBPTR[TB_WNDW_END_PTR] = 4 * div_ratio 931 * and program TBPTR[TB_WNDW_START_PTR] = 8 * div_ratio. 932 */ 933 tbstat_7_0 = val & 0xff; 934 tbstat_15_8 = (val >> 8) & 0xff; 935 936 if (abs(tbstat_15_8 - tbstat_7_0) > (4 * esdhc->div_ratio)) { 937 *window_start = 8 * esdhc->div_ratio; 938 *window_end = 4 * esdhc->div_ratio; 939 } else { 940 *window_start = 5 * esdhc->div_ratio; 941 *window_end = 3 * esdhc->div_ratio; 942 } 943 } 944 945 static int esdhc_execute_sw_tuning(struct mmc_host *mmc, u32 opcode, 946 u8 window_start, u8 window_end) 947 { 948 struct sdhci_host *host = mmc_priv(mmc); 949 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 950 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 951 u32 val; 952 int ret; 953 954 /* Program TBPTR[TB_WNDW_END_PTR] and TBPTR[TB_WNDW_START_PTR] */ 955 val = ((u32)window_start << ESDHC_WNDW_STRT_PTR_SHIFT) & 956 ESDHC_WNDW_STRT_PTR_MASK; 957 val |= window_end & ESDHC_WNDW_END_PTR_MASK; 958 sdhci_writel(host, val, ESDHC_TBPTR); 959 960 /* Program the software tuning mode by setting TBCTL[TB_MODE]=2'h3 */ 961 val = sdhci_readl(host, ESDHC_TBCTL); 962 val &= ~ESDHC_TB_MODE_MASK; 963 val |= ESDHC_TB_MODE_SW; 964 sdhci_writel(host, val, ESDHC_TBCTL); 965 966 esdhc->in_sw_tuning = true; 967 ret = sdhci_execute_tuning(mmc, opcode); 968 esdhc->in_sw_tuning = false; 969 return ret; 970 } 971 972 static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) 973 { 974 struct sdhci_host *host = mmc_priv(mmc); 975 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 976 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 977 u8 window_start, window_end; 978 int ret, retries = 1; 979 bool hs400_tuning; 980 unsigned int clk; 981 u32 val; 982 983 /* For tuning mode, the sd clock divisor value 984 * must be larger than 3 according to reference manual. 985 */ 986 clk = esdhc->peripheral_clock / 3; 987 if (host->clock > clk) 988 esdhc_of_set_clock(host, clk); 989 990 esdhc_tuning_block_enable(host, true); 991 992 hs400_tuning = host->flags & SDHCI_HS400_TUNING; 993 994 do { 995 if (esdhc->quirk_limited_clk_division && 996 hs400_tuning) 997 esdhc_of_set_clock(host, host->clock); 998 999 /* Do HW tuning */ 1000 val = sdhci_readl(host, ESDHC_TBCTL); 1001 val &= ~ESDHC_TB_MODE_MASK; 1002 val |= ESDHC_TB_MODE_3; 1003 sdhci_writel(host, val, ESDHC_TBCTL); 1004 1005 ret = sdhci_execute_tuning(mmc, opcode); 1006 if (ret) 1007 break; 1008 1009 /* If HW tuning fails and triggers erratum, 1010 * try workaround. 1011 */ 1012 ret = host->tuning_err; 1013 if (ret == -EAGAIN && 1014 (esdhc->quirk_tuning_erratum_type1 || 1015 esdhc->quirk_tuning_erratum_type2)) { 1016 /* Recover HS400 tuning flag */ 1017 if (hs400_tuning) 1018 host->flags |= SDHCI_HS400_TUNING; 1019 pr_info("%s: Hold on to use fixed sampling clock. Try SW tuning!\n", 1020 mmc_hostname(mmc)); 1021 /* Do SW tuning */ 1022 esdhc_prepare_sw_tuning(host, &window_start, 1023 &window_end); 1024 ret = esdhc_execute_sw_tuning(mmc, opcode, 1025 window_start, 1026 window_end); 1027 if (ret) 1028 break; 1029 1030 /* Retry both HW/SW tuning with reduced clock. */ 1031 ret = host->tuning_err; 1032 if (ret == -EAGAIN && retries) { 1033 /* Recover HS400 tuning flag */ 1034 if (hs400_tuning) 1035 host->flags |= SDHCI_HS400_TUNING; 1036 1037 clk = host->max_clk / (esdhc->div_ratio + 1); 1038 esdhc_of_set_clock(host, clk); 1039 pr_info("%s: Hold on to use fixed sampling clock. Try tuning with reduced clock!\n", 1040 mmc_hostname(mmc)); 1041 } else { 1042 break; 1043 } 1044 } else { 1045 break; 1046 } 1047 } while (retries--); 1048 1049 if (ret) { 1050 esdhc_tuning_block_enable(host, false); 1051 } else if (hs400_tuning) { 1052 val = sdhci_readl(host, ESDHC_SDTIMNGCTL); 1053 val |= ESDHC_FLW_CTL_BG; 1054 sdhci_writel(host, val, ESDHC_SDTIMNGCTL); 1055 } 1056 1057 return ret; 1058 } 1059 1060 static void esdhc_set_uhs_signaling(struct sdhci_host *host, 1061 unsigned int timing) 1062 { 1063 if (timing == MMC_TIMING_MMC_HS400) 1064 esdhc_tuning_block_enable(host, true); 1065 else 1066 sdhci_set_uhs_signaling(host, timing); 1067 } 1068 1069 static u32 esdhc_irq(struct sdhci_host *host, u32 intmask) 1070 { 1071 u32 command; 1072 1073 if (of_find_compatible_node(NULL, NULL, 1074 "fsl,p2020-esdhc")) { 1075 command = SDHCI_GET_CMD(sdhci_readw(host, 1076 SDHCI_COMMAND)); 1077 if (command == MMC_WRITE_MULTIPLE_BLOCK && 1078 sdhci_readw(host, SDHCI_BLOCK_COUNT) && 1079 intmask & SDHCI_INT_DATA_END) { 1080 intmask &= ~SDHCI_INT_DATA_END; 1081 sdhci_writel(host, SDHCI_INT_DATA_END, 1082 SDHCI_INT_STATUS); 1083 } 1084 } 1085 return intmask; 1086 } 1087 1088 #ifdef CONFIG_PM_SLEEP 1089 static u32 esdhc_proctl; 1090 static int esdhc_of_suspend(struct device *dev) 1091 { 1092 struct sdhci_host *host = dev_get_drvdata(dev); 1093 1094 esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL); 1095 1096 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1097 mmc_retune_needed(host->mmc); 1098 1099 return sdhci_suspend_host(host); 1100 } 1101 1102 static int esdhc_of_resume(struct device *dev) 1103 { 1104 struct sdhci_host *host = dev_get_drvdata(dev); 1105 int ret = sdhci_resume_host(host); 1106 1107 if (ret == 0) { 1108 /* Isn't this already done by sdhci_resume_host() ? --rmk */ 1109 esdhc_of_enable_dma(host); 1110 sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL); 1111 } 1112 return ret; 1113 } 1114 #endif 1115 1116 static SIMPLE_DEV_PM_OPS(esdhc_of_dev_pm_ops, 1117 esdhc_of_suspend, 1118 esdhc_of_resume); 1119 1120 static const struct sdhci_ops sdhci_esdhc_be_ops = { 1121 .read_l = esdhc_be_readl, 1122 .read_w = esdhc_be_readw, 1123 .read_b = esdhc_be_readb, 1124 .write_l = esdhc_be_writel, 1125 .write_w = esdhc_be_writew, 1126 .write_b = esdhc_be_writeb, 1127 .set_clock = esdhc_of_set_clock, 1128 .enable_dma = esdhc_of_enable_dma, 1129 .get_max_clock = esdhc_of_get_max_clock, 1130 .get_min_clock = esdhc_of_get_min_clock, 1131 .adma_workaround = esdhc_of_adma_workaround, 1132 .set_bus_width = esdhc_pltfm_set_bus_width, 1133 .reset = esdhc_reset, 1134 .set_uhs_signaling = esdhc_set_uhs_signaling, 1135 .irq = esdhc_irq, 1136 }; 1137 1138 static const struct sdhci_ops sdhci_esdhc_le_ops = { 1139 .read_l = esdhc_le_readl, 1140 .read_w = esdhc_le_readw, 1141 .read_b = esdhc_le_readb, 1142 .write_l = esdhc_le_writel, 1143 .write_w = esdhc_le_writew, 1144 .write_b = esdhc_le_writeb, 1145 .set_clock = esdhc_of_set_clock, 1146 .enable_dma = esdhc_of_enable_dma, 1147 .get_max_clock = esdhc_of_get_max_clock, 1148 .get_min_clock = esdhc_of_get_min_clock, 1149 .adma_workaround = esdhc_of_adma_workaround, 1150 .set_bus_width = esdhc_pltfm_set_bus_width, 1151 .reset = esdhc_reset, 1152 .set_uhs_signaling = esdhc_set_uhs_signaling, 1153 .irq = esdhc_irq, 1154 }; 1155 1156 static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = { 1157 .quirks = ESDHC_DEFAULT_QUIRKS | 1158 #ifdef CONFIG_PPC 1159 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 1160 #endif 1161 SDHCI_QUIRK_NO_CARD_NO_RESET | 1162 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1163 .ops = &sdhci_esdhc_be_ops, 1164 }; 1165 1166 static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = { 1167 .quirks = ESDHC_DEFAULT_QUIRKS | 1168 SDHCI_QUIRK_NO_CARD_NO_RESET | 1169 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1170 .ops = &sdhci_esdhc_le_ops, 1171 }; 1172 1173 static struct soc_device_attribute soc_incorrect_hostver[] = { 1174 { .family = "QorIQ T4240", .revision = "1.0", }, 1175 { .family = "QorIQ T4240", .revision = "2.0", }, 1176 { }, 1177 }; 1178 1179 static struct soc_device_attribute soc_fixup_sdhc_clkdivs[] = { 1180 { .family = "QorIQ LX2160A", .revision = "1.0", }, 1181 { .family = "QorIQ LX2160A", .revision = "2.0", }, 1182 { .family = "QorIQ LS1028A", .revision = "1.0", }, 1183 { }, 1184 }; 1185 1186 static struct soc_device_attribute soc_unreliable_pulse_detection[] = { 1187 { .family = "QorIQ LX2160A", .revision = "1.0", }, 1188 { }, 1189 }; 1190 1191 static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host) 1192 { 1193 const struct of_device_id *match; 1194 struct sdhci_pltfm_host *pltfm_host; 1195 struct sdhci_esdhc *esdhc; 1196 struct device_node *np; 1197 struct clk *clk; 1198 u32 val; 1199 u16 host_ver; 1200 1201 pltfm_host = sdhci_priv(host); 1202 esdhc = sdhci_pltfm_priv(pltfm_host); 1203 1204 host_ver = sdhci_readw(host, SDHCI_HOST_VERSION); 1205 esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >> 1206 SDHCI_VENDOR_VER_SHIFT; 1207 esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK; 1208 if (soc_device_match(soc_incorrect_hostver)) 1209 esdhc->quirk_incorrect_hostver = true; 1210 else 1211 esdhc->quirk_incorrect_hostver = false; 1212 1213 if (soc_device_match(soc_fixup_sdhc_clkdivs)) 1214 esdhc->quirk_limited_clk_division = true; 1215 else 1216 esdhc->quirk_limited_clk_division = false; 1217 1218 if (soc_device_match(soc_unreliable_pulse_detection)) 1219 esdhc->quirk_unreliable_pulse_detection = true; 1220 else 1221 esdhc->quirk_unreliable_pulse_detection = false; 1222 1223 match = of_match_node(sdhci_esdhc_of_match, pdev->dev.of_node); 1224 if (match) 1225 esdhc->clk_fixup = match->data; 1226 np = pdev->dev.of_node; 1227 1228 if (of_device_is_compatible(np, "fsl,p2020-esdhc")) 1229 esdhc->quirk_delay_before_data_reset = true; 1230 1231 clk = of_clk_get(np, 0); 1232 if (!IS_ERR(clk)) { 1233 /* 1234 * esdhc->peripheral_clock would be assigned with a value 1235 * which is eSDHC base clock when use periperal clock. 1236 * For some platforms, the clock value got by common clk 1237 * API is peripheral clock while the eSDHC base clock is 1238 * 1/2 peripheral clock. 1239 */ 1240 if (of_device_is_compatible(np, "fsl,ls1046a-esdhc") || 1241 of_device_is_compatible(np, "fsl,ls1028a-esdhc")) 1242 esdhc->peripheral_clock = clk_get_rate(clk) / 2; 1243 else 1244 esdhc->peripheral_clock = clk_get_rate(clk); 1245 1246 clk_put(clk); 1247 } 1248 1249 if (esdhc->peripheral_clock) { 1250 esdhc_clock_enable(host, false); 1251 val = sdhci_readl(host, ESDHC_DMA_SYSCTL); 1252 val |= ESDHC_PERIPHERAL_CLK_SEL; 1253 sdhci_writel(host, val, ESDHC_DMA_SYSCTL); 1254 esdhc_clock_enable(host, true); 1255 } 1256 } 1257 1258 static int esdhc_hs400_prepare_ddr(struct mmc_host *mmc) 1259 { 1260 esdhc_tuning_block_enable(mmc_priv(mmc), false); 1261 return 0; 1262 } 1263 1264 static int sdhci_esdhc_probe(struct platform_device *pdev) 1265 { 1266 struct sdhci_host *host; 1267 struct device_node *np; 1268 struct sdhci_pltfm_host *pltfm_host; 1269 struct sdhci_esdhc *esdhc; 1270 int ret; 1271 1272 np = pdev->dev.of_node; 1273 1274 if (of_property_read_bool(np, "little-endian")) 1275 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata, 1276 sizeof(struct sdhci_esdhc)); 1277 else 1278 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata, 1279 sizeof(struct sdhci_esdhc)); 1280 1281 if (IS_ERR(host)) 1282 return PTR_ERR(host); 1283 1284 host->mmc_host_ops.start_signal_voltage_switch = 1285 esdhc_signal_voltage_switch; 1286 host->mmc_host_ops.execute_tuning = esdhc_execute_tuning; 1287 host->mmc_host_ops.hs400_prepare_ddr = esdhc_hs400_prepare_ddr; 1288 host->tuning_delay = 1; 1289 1290 esdhc_init(pdev, host); 1291 1292 sdhci_get_of_property(pdev); 1293 1294 pltfm_host = sdhci_priv(host); 1295 esdhc = sdhci_pltfm_priv(pltfm_host); 1296 if (soc_device_match(soc_tuning_erratum_type1)) 1297 esdhc->quirk_tuning_erratum_type1 = true; 1298 else 1299 esdhc->quirk_tuning_erratum_type1 = false; 1300 1301 if (soc_device_match(soc_tuning_erratum_type2)) 1302 esdhc->quirk_tuning_erratum_type2 = true; 1303 else 1304 esdhc->quirk_tuning_erratum_type2 = false; 1305 1306 if (esdhc->vendor_ver == VENDOR_V_22) 1307 host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; 1308 1309 if (esdhc->vendor_ver > VENDOR_V_22) 1310 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; 1311 1312 if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc")) { 1313 host->quirks |= SDHCI_QUIRK_RESET_AFTER_REQUEST; 1314 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 1315 } 1316 1317 if (of_device_is_compatible(np, "fsl,p5040-esdhc") || 1318 of_device_is_compatible(np, "fsl,p5020-esdhc") || 1319 of_device_is_compatible(np, "fsl,p4080-esdhc") || 1320 of_device_is_compatible(np, "fsl,p1020-esdhc") || 1321 of_device_is_compatible(np, "fsl,t1040-esdhc")) 1322 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 1323 1324 if (of_device_is_compatible(np, "fsl,ls1021a-esdhc")) 1325 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 1326 1327 esdhc->quirk_ignore_data_inhibit = false; 1328 if (of_device_is_compatible(np, "fsl,p2020-esdhc")) { 1329 /* 1330 * Freescale messed up with P2020 as it has a non-standard 1331 * host control register 1332 */ 1333 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL; 1334 esdhc->quirk_ignore_data_inhibit = true; 1335 } 1336 1337 /* call to generic mmc_of_parse to support additional capabilities */ 1338 ret = mmc_of_parse(host->mmc); 1339 if (ret) 1340 goto err; 1341 1342 mmc_of_parse_voltage(np, &host->ocr_mask); 1343 1344 ret = sdhci_add_host(host); 1345 if (ret) 1346 goto err; 1347 1348 return 0; 1349 err: 1350 sdhci_pltfm_free(pdev); 1351 return ret; 1352 } 1353 1354 static struct platform_driver sdhci_esdhc_driver = { 1355 .driver = { 1356 .name = "sdhci-esdhc", 1357 .of_match_table = sdhci_esdhc_of_match, 1358 .pm = &esdhc_of_dev_pm_ops, 1359 }, 1360 .probe = sdhci_esdhc_probe, 1361 .remove = sdhci_pltfm_unregister, 1362 }; 1363 1364 module_platform_driver(sdhci_esdhc_driver); 1365 1366 MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC"); 1367 MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, " 1368 "Anton Vorontsov <avorontsov@ru.mvista.com>"); 1369 MODULE_LICENSE("GPL v2"); 1370