1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Freescale eSDHC controller driver. 4 * 5 * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc. 6 * Copyright (c) 2009 MontaVista Software, Inc. 7 * 8 * Authors: Xiaobo Xie <X.Xie@freescale.com> 9 * Anton Vorontsov <avorontsov@ru.mvista.com> 10 */ 11 12 #include <linux/err.h> 13 #include <linux/io.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/delay.h> 17 #include <linux/module.h> 18 #include <linux/sys_soc.h> 19 #include <linux/clk.h> 20 #include <linux/ktime.h> 21 #include <linux/dma-mapping.h> 22 #include <linux/mmc/host.h> 23 #include <linux/mmc/mmc.h> 24 #include "sdhci-pltfm.h" 25 #include "sdhci-esdhc.h" 26 27 #define VENDOR_V_22 0x12 28 #define VENDOR_V_23 0x13 29 30 #define MMC_TIMING_NUM (MMC_TIMING_MMC_HS400 + 1) 31 32 struct esdhc_clk_fixup { 33 const unsigned int sd_dflt_max_clk; 34 const unsigned int max_clk[MMC_TIMING_NUM]; 35 }; 36 37 static const struct esdhc_clk_fixup ls1021a_esdhc_clk = { 38 .sd_dflt_max_clk = 25000000, 39 .max_clk[MMC_TIMING_MMC_HS] = 46500000, 40 .max_clk[MMC_TIMING_SD_HS] = 46500000, 41 }; 42 43 static const struct esdhc_clk_fixup ls1046a_esdhc_clk = { 44 .sd_dflt_max_clk = 25000000, 45 .max_clk[MMC_TIMING_UHS_SDR104] = 167000000, 46 .max_clk[MMC_TIMING_MMC_HS200] = 167000000, 47 }; 48 49 static const struct esdhc_clk_fixup ls1012a_esdhc_clk = { 50 .sd_dflt_max_clk = 25000000, 51 .max_clk[MMC_TIMING_UHS_SDR104] = 125000000, 52 .max_clk[MMC_TIMING_MMC_HS200] = 125000000, 53 }; 54 55 static const struct esdhc_clk_fixup p1010_esdhc_clk = { 56 .sd_dflt_max_clk = 20000000, 57 .max_clk[MMC_TIMING_LEGACY] = 20000000, 58 .max_clk[MMC_TIMING_MMC_HS] = 42000000, 59 .max_clk[MMC_TIMING_SD_HS] = 40000000, 60 }; 61 62 static const struct of_device_id sdhci_esdhc_of_match[] = { 63 { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk}, 64 { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk}, 65 { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk}, 66 { .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk}, 67 { .compatible = "fsl,mpc8379-esdhc" }, 68 { .compatible = "fsl,mpc8536-esdhc" }, 69 { .compatible = "fsl,esdhc" }, 70 { } 71 }; 72 MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match); 73 74 struct sdhci_esdhc { 75 u8 vendor_ver; 76 u8 spec_ver; 77 bool quirk_incorrect_hostver; 78 bool quirk_limited_clk_division; 79 bool quirk_unreliable_pulse_detection; 80 bool quirk_tuning_erratum_type1; 81 bool quirk_tuning_erratum_type2; 82 bool quirk_ignore_data_inhibit; 83 bool in_sw_tuning; 84 unsigned int peripheral_clock; 85 const struct esdhc_clk_fixup *clk_fixup; 86 u32 div_ratio; 87 }; 88 89 /** 90 * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register 91 * to make it compatible with SD spec. 92 * 93 * @host: pointer to sdhci_host 94 * @spec_reg: SD spec register address 95 * @value: 32bit eSDHC register value on spec_reg address 96 * 97 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 98 * registers are 32 bits. There are differences in register size, register 99 * address, register function, bit position and function between eSDHC spec 100 * and SD spec. 101 * 102 * Return a fixed up register value 103 */ 104 static u32 esdhc_readl_fixup(struct sdhci_host *host, 105 int spec_reg, u32 value) 106 { 107 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 108 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 109 u32 ret; 110 111 /* 112 * The bit of ADMA flag in eSDHC is not compatible with standard 113 * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is 114 * supported by eSDHC. 115 * And for many FSL eSDHC controller, the reset value of field 116 * SDHCI_CAN_DO_ADMA1 is 1, but some of them can't support ADMA, 117 * only these vendor version is greater than 2.2/0x12 support ADMA. 118 */ 119 if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) { 120 if (esdhc->vendor_ver > VENDOR_V_22) { 121 ret = value | SDHCI_CAN_DO_ADMA2; 122 return ret; 123 } 124 } 125 /* 126 * The DAT[3:0] line signal levels and the CMD line signal level are 127 * not compatible with standard SDHC register. The line signal levels 128 * DAT[7:0] are at bits 31:24 and the command line signal level is at 129 * bit 23. All other bits are the same as in the standard SDHC 130 * register. 131 */ 132 if (spec_reg == SDHCI_PRESENT_STATE) { 133 ret = value & 0x000fffff; 134 ret |= (value >> 4) & SDHCI_DATA_LVL_MASK; 135 ret |= (value << 1) & SDHCI_CMD_LVL; 136 return ret; 137 } 138 139 /* 140 * DTS properties of mmc host are used to enable each speed mode 141 * according to soc and board capability. So clean up 142 * SDR50/SDR104/DDR50 support bits here. 143 */ 144 if (spec_reg == SDHCI_CAPABILITIES_1) { 145 ret = value & ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | 146 SDHCI_SUPPORT_DDR50); 147 return ret; 148 } 149 150 /* 151 * Some controllers have unreliable Data Line Active 152 * bit for commands with busy signal. This affects 153 * Command Inhibit (data) bit. Just ignore it since 154 * MMC core driver has already polled card status 155 * with CMD13 after any command with busy siganl. 156 */ 157 if ((spec_reg == SDHCI_PRESENT_STATE) && 158 (esdhc->quirk_ignore_data_inhibit == true)) { 159 ret = value & ~SDHCI_DATA_INHIBIT; 160 return ret; 161 } 162 163 ret = value; 164 return ret; 165 } 166 167 static u16 esdhc_readw_fixup(struct sdhci_host *host, 168 int spec_reg, u32 value) 169 { 170 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 171 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 172 u16 ret; 173 int shift = (spec_reg & 0x2) * 8; 174 175 if (spec_reg == SDHCI_HOST_VERSION) 176 ret = value & 0xffff; 177 else 178 ret = (value >> shift) & 0xffff; 179 /* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect 180 * vendor version and spec version information. 181 */ 182 if ((spec_reg == SDHCI_HOST_VERSION) && 183 (esdhc->quirk_incorrect_hostver)) 184 ret = (VENDOR_V_23 << SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200; 185 return ret; 186 } 187 188 static u8 esdhc_readb_fixup(struct sdhci_host *host, 189 int spec_reg, u32 value) 190 { 191 u8 ret; 192 u8 dma_bits; 193 int shift = (spec_reg & 0x3) * 8; 194 195 ret = (value >> shift) & 0xff; 196 197 /* 198 * "DMA select" locates at offset 0x28 in SD specification, but on 199 * P5020 or P3041, it locates at 0x29. 200 */ 201 if (spec_reg == SDHCI_HOST_CONTROL) { 202 /* DMA select is 22,23 bits in Protocol Control Register */ 203 dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK; 204 /* fixup the result */ 205 ret &= ~SDHCI_CTRL_DMA_MASK; 206 ret |= dma_bits; 207 } 208 return ret; 209 } 210 211 /** 212 * esdhc_write*_fixup - Fixup the SD spec register value so that it could be 213 * written into eSDHC register. 214 * 215 * @host: pointer to sdhci_host 216 * @spec_reg: SD spec register address 217 * @value: 8/16/32bit SD spec register value that would be written 218 * @old_value: 32bit eSDHC register value on spec_reg address 219 * 220 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 221 * registers are 32 bits. There are differences in register size, register 222 * address, register function, bit position and function between eSDHC spec 223 * and SD spec. 224 * 225 * Return a fixed up register value 226 */ 227 static u32 esdhc_writel_fixup(struct sdhci_host *host, 228 int spec_reg, u32 value, u32 old_value) 229 { 230 u32 ret; 231 232 /* 233 * Enabling IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE] 234 * when SYSCTL[RSTD] is set for some special operations. 235 * No any impact on other operation. 236 */ 237 if (spec_reg == SDHCI_INT_ENABLE) 238 ret = value | SDHCI_INT_BLK_GAP; 239 else 240 ret = value; 241 242 return ret; 243 } 244 245 static u32 esdhc_writew_fixup(struct sdhci_host *host, 246 int spec_reg, u16 value, u32 old_value) 247 { 248 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 249 int shift = (spec_reg & 0x2) * 8; 250 u32 ret; 251 252 switch (spec_reg) { 253 case SDHCI_TRANSFER_MODE: 254 /* 255 * Postpone this write, we must do it together with a 256 * command write that is down below. Return old value. 257 */ 258 pltfm_host->xfer_mode_shadow = value; 259 return old_value; 260 case SDHCI_COMMAND: 261 ret = (value << 16) | pltfm_host->xfer_mode_shadow; 262 return ret; 263 } 264 265 ret = old_value & (~(0xffff << shift)); 266 ret |= (value << shift); 267 268 if (spec_reg == SDHCI_BLOCK_SIZE) { 269 /* 270 * Two last DMA bits are reserved, and first one is used for 271 * non-standard blksz of 4096 bytes that we don't support 272 * yet. So clear the DMA boundary bits. 273 */ 274 ret &= (~SDHCI_MAKE_BLKSZ(0x7, 0)); 275 } 276 return ret; 277 } 278 279 static u32 esdhc_writeb_fixup(struct sdhci_host *host, 280 int spec_reg, u8 value, u32 old_value) 281 { 282 u32 ret; 283 u32 dma_bits; 284 u8 tmp; 285 int shift = (spec_reg & 0x3) * 8; 286 287 /* 288 * eSDHC doesn't have a standard power control register, so we do 289 * nothing here to avoid incorrect operation. 290 */ 291 if (spec_reg == SDHCI_POWER_CONTROL) 292 return old_value; 293 /* 294 * "DMA select" location is offset 0x28 in SD specification, but on 295 * P5020 or P3041, it's located at 0x29. 296 */ 297 if (spec_reg == SDHCI_HOST_CONTROL) { 298 /* 299 * If host control register is not standard, exit 300 * this function 301 */ 302 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL) 303 return old_value; 304 305 /* DMA select is 22,23 bits in Protocol Control Register */ 306 dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5; 307 ret = (old_value & (~(SDHCI_CTRL_DMA_MASK << 5))) | dma_bits; 308 tmp = (value & (~SDHCI_CTRL_DMA_MASK)) | 309 (old_value & SDHCI_CTRL_DMA_MASK); 310 ret = (ret & (~0xff)) | tmp; 311 312 /* Prevent SDHCI core from writing reserved bits (e.g. HISPD) */ 313 ret &= ~ESDHC_HOST_CONTROL_RES; 314 return ret; 315 } 316 317 ret = (old_value & (~(0xff << shift))) | (value << shift); 318 return ret; 319 } 320 321 static u32 esdhc_be_readl(struct sdhci_host *host, int reg) 322 { 323 u32 ret; 324 u32 value; 325 326 if (reg == SDHCI_CAPABILITIES_1) 327 value = ioread32be(host->ioaddr + ESDHC_CAPABILITIES_1); 328 else 329 value = ioread32be(host->ioaddr + reg); 330 331 ret = esdhc_readl_fixup(host, reg, value); 332 333 return ret; 334 } 335 336 static u32 esdhc_le_readl(struct sdhci_host *host, int reg) 337 { 338 u32 ret; 339 u32 value; 340 341 if (reg == SDHCI_CAPABILITIES_1) 342 value = ioread32(host->ioaddr + ESDHC_CAPABILITIES_1); 343 else 344 value = ioread32(host->ioaddr + reg); 345 346 ret = esdhc_readl_fixup(host, reg, value); 347 348 return ret; 349 } 350 351 static u16 esdhc_be_readw(struct sdhci_host *host, int reg) 352 { 353 u16 ret; 354 u32 value; 355 int base = reg & ~0x3; 356 357 value = ioread32be(host->ioaddr + base); 358 ret = esdhc_readw_fixup(host, reg, value); 359 return ret; 360 } 361 362 static u16 esdhc_le_readw(struct sdhci_host *host, int reg) 363 { 364 u16 ret; 365 u32 value; 366 int base = reg & ~0x3; 367 368 value = ioread32(host->ioaddr + base); 369 ret = esdhc_readw_fixup(host, reg, value); 370 return ret; 371 } 372 373 static u8 esdhc_be_readb(struct sdhci_host *host, int reg) 374 { 375 u8 ret; 376 u32 value; 377 int base = reg & ~0x3; 378 379 value = ioread32be(host->ioaddr + base); 380 ret = esdhc_readb_fixup(host, reg, value); 381 return ret; 382 } 383 384 static u8 esdhc_le_readb(struct sdhci_host *host, int reg) 385 { 386 u8 ret; 387 u32 value; 388 int base = reg & ~0x3; 389 390 value = ioread32(host->ioaddr + base); 391 ret = esdhc_readb_fixup(host, reg, value); 392 return ret; 393 } 394 395 static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg) 396 { 397 u32 value; 398 399 value = esdhc_writel_fixup(host, reg, val, 0); 400 iowrite32be(value, host->ioaddr + reg); 401 } 402 403 static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg) 404 { 405 u32 value; 406 407 value = esdhc_writel_fixup(host, reg, val, 0); 408 iowrite32(value, host->ioaddr + reg); 409 } 410 411 static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg) 412 { 413 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 414 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 415 int base = reg & ~0x3; 416 u32 value; 417 u32 ret; 418 419 value = ioread32be(host->ioaddr + base); 420 ret = esdhc_writew_fixup(host, reg, val, value); 421 if (reg != SDHCI_TRANSFER_MODE) 422 iowrite32be(ret, host->ioaddr + base); 423 424 /* Starting SW tuning requires ESDHC_SMPCLKSEL to be set 425 * 1us later after ESDHC_EXTN is set. 426 */ 427 if (base == ESDHC_SYSTEM_CONTROL_2) { 428 if (!(value & ESDHC_EXTN) && (ret & ESDHC_EXTN) && 429 esdhc->in_sw_tuning) { 430 udelay(1); 431 ret |= ESDHC_SMPCLKSEL; 432 iowrite32be(ret, host->ioaddr + base); 433 } 434 } 435 } 436 437 static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg) 438 { 439 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 440 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 441 int base = reg & ~0x3; 442 u32 value; 443 u32 ret; 444 445 value = ioread32(host->ioaddr + base); 446 ret = esdhc_writew_fixup(host, reg, val, value); 447 if (reg != SDHCI_TRANSFER_MODE) 448 iowrite32(ret, host->ioaddr + base); 449 450 /* Starting SW tuning requires ESDHC_SMPCLKSEL to be set 451 * 1us later after ESDHC_EXTN is set. 452 */ 453 if (base == ESDHC_SYSTEM_CONTROL_2) { 454 if (!(value & ESDHC_EXTN) && (ret & ESDHC_EXTN) && 455 esdhc->in_sw_tuning) { 456 udelay(1); 457 ret |= ESDHC_SMPCLKSEL; 458 iowrite32(ret, host->ioaddr + base); 459 } 460 } 461 } 462 463 static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg) 464 { 465 int base = reg & ~0x3; 466 u32 value; 467 u32 ret; 468 469 value = ioread32be(host->ioaddr + base); 470 ret = esdhc_writeb_fixup(host, reg, val, value); 471 iowrite32be(ret, host->ioaddr + base); 472 } 473 474 static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg) 475 { 476 int base = reg & ~0x3; 477 u32 value; 478 u32 ret; 479 480 value = ioread32(host->ioaddr + base); 481 ret = esdhc_writeb_fixup(host, reg, val, value); 482 iowrite32(ret, host->ioaddr + base); 483 } 484 485 /* 486 * For Abort or Suspend after Stop at Block Gap, ignore the ADMA 487 * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC]) 488 * and Block Gap Event(IRQSTAT[BGE]) are also set. 489 * For Continue, apply soft reset for data(SYSCTL[RSTD]); 490 * and re-issue the entire read transaction from beginning. 491 */ 492 static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask) 493 { 494 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 495 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 496 bool applicable; 497 dma_addr_t dmastart; 498 dma_addr_t dmanow; 499 500 applicable = (intmask & SDHCI_INT_DATA_END) && 501 (intmask & SDHCI_INT_BLK_GAP) && 502 (esdhc->vendor_ver == VENDOR_V_23); 503 if (!applicable) 504 return; 505 506 host->data->error = 0; 507 dmastart = sg_dma_address(host->data->sg); 508 dmanow = dmastart + host->data->bytes_xfered; 509 /* 510 * Force update to the next DMA block boundary. 511 */ 512 dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 513 SDHCI_DEFAULT_BOUNDARY_SIZE; 514 host->data->bytes_xfered = dmanow - dmastart; 515 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 516 } 517 518 static int esdhc_of_enable_dma(struct sdhci_host *host) 519 { 520 u32 value; 521 struct device *dev = mmc_dev(host->mmc); 522 523 if (of_device_is_compatible(dev->of_node, "fsl,ls1043a-esdhc") || 524 of_device_is_compatible(dev->of_node, "fsl,ls1046a-esdhc")) 525 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); 526 527 value = sdhci_readl(host, ESDHC_DMA_SYSCTL); 528 529 if (of_dma_is_coherent(dev->of_node)) 530 value |= ESDHC_DMA_SNOOP; 531 else 532 value &= ~ESDHC_DMA_SNOOP; 533 534 sdhci_writel(host, value, ESDHC_DMA_SYSCTL); 535 return 0; 536 } 537 538 static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host) 539 { 540 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 541 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 542 543 if (esdhc->peripheral_clock) 544 return esdhc->peripheral_clock; 545 else 546 return pltfm_host->clock; 547 } 548 549 static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host) 550 { 551 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 552 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 553 unsigned int clock; 554 555 if (esdhc->peripheral_clock) 556 clock = esdhc->peripheral_clock; 557 else 558 clock = pltfm_host->clock; 559 return clock / 256 / 16; 560 } 561 562 static void esdhc_clock_enable(struct sdhci_host *host, bool enable) 563 { 564 u32 val; 565 ktime_t timeout; 566 567 val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 568 569 if (enable) 570 val |= ESDHC_CLOCK_SDCLKEN; 571 else 572 val &= ~ESDHC_CLOCK_SDCLKEN; 573 574 sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL); 575 576 /* Wait max 20 ms */ 577 timeout = ktime_add_ms(ktime_get(), 20); 578 val = ESDHC_CLOCK_STABLE; 579 while (1) { 580 bool timedout = ktime_after(ktime_get(), timeout); 581 582 if (sdhci_readl(host, ESDHC_PRSSTAT) & val) 583 break; 584 if (timedout) { 585 pr_err("%s: Internal clock never stabilised.\n", 586 mmc_hostname(host->mmc)); 587 break; 588 } 589 udelay(10); 590 } 591 } 592 593 static void esdhc_flush_async_fifo(struct sdhci_host *host) 594 { 595 ktime_t timeout; 596 u32 val; 597 598 val = sdhci_readl(host, ESDHC_DMA_SYSCTL); 599 val |= ESDHC_FLUSH_ASYNC_FIFO; 600 sdhci_writel(host, val, ESDHC_DMA_SYSCTL); 601 602 /* Wait max 20 ms */ 603 timeout = ktime_add_ms(ktime_get(), 20); 604 while (1) { 605 bool timedout = ktime_after(ktime_get(), timeout); 606 607 if (!(sdhci_readl(host, ESDHC_DMA_SYSCTL) & 608 ESDHC_FLUSH_ASYNC_FIFO)) 609 break; 610 if (timedout) { 611 pr_err("%s: flushing asynchronous FIFO timeout.\n", 612 mmc_hostname(host->mmc)); 613 break; 614 } 615 usleep_range(10, 20); 616 } 617 } 618 619 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock) 620 { 621 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 622 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 623 int pre_div = 1; 624 int div = 1; 625 int division; 626 ktime_t timeout; 627 long fixup = 0; 628 u32 temp; 629 630 host->mmc->actual_clock = 0; 631 632 if (clock == 0) { 633 esdhc_clock_enable(host, false); 634 return; 635 } 636 637 /* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */ 638 if (esdhc->vendor_ver < VENDOR_V_23) 639 pre_div = 2; 640 641 if (host->mmc->card && mmc_card_sd(host->mmc->card) && 642 esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY) 643 fixup = esdhc->clk_fixup->sd_dflt_max_clk; 644 else if (esdhc->clk_fixup) 645 fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing]; 646 647 if (fixup && clock > fixup) 648 clock = fixup; 649 650 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 651 temp &= ~(ESDHC_CLOCK_SDCLKEN | ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | 652 ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK); 653 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 654 655 while (host->max_clk / pre_div / 16 > clock && pre_div < 256) 656 pre_div *= 2; 657 658 while (host->max_clk / pre_div / div > clock && div < 16) 659 div++; 660 661 if (esdhc->quirk_limited_clk_division && 662 clock == MMC_HS200_MAX_DTR && 663 (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 || 664 host->flags & SDHCI_HS400_TUNING)) { 665 division = pre_div * div; 666 if (division <= 4) { 667 pre_div = 4; 668 div = 1; 669 } else if (division <= 8) { 670 pre_div = 4; 671 div = 2; 672 } else if (division <= 12) { 673 pre_div = 4; 674 div = 3; 675 } else { 676 pr_warn("%s: using unsupported clock division.\n", 677 mmc_hostname(host->mmc)); 678 } 679 } 680 681 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 682 clock, host->max_clk / pre_div / div); 683 host->mmc->actual_clock = host->max_clk / pre_div / div; 684 esdhc->div_ratio = pre_div * div; 685 pre_div >>= 1; 686 div--; 687 688 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 689 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 690 | (div << ESDHC_DIVIDER_SHIFT) 691 | (pre_div << ESDHC_PREDIV_SHIFT)); 692 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 693 694 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && 695 clock == MMC_HS200_MAX_DTR) { 696 temp = sdhci_readl(host, ESDHC_TBCTL); 697 sdhci_writel(host, temp | ESDHC_HS400_MODE, ESDHC_TBCTL); 698 temp = sdhci_readl(host, ESDHC_SDCLKCTL); 699 sdhci_writel(host, temp | ESDHC_CMD_CLK_CTL, ESDHC_SDCLKCTL); 700 esdhc_clock_enable(host, true); 701 702 temp = sdhci_readl(host, ESDHC_DLLCFG0); 703 temp |= ESDHC_DLL_ENABLE; 704 if (host->mmc->actual_clock == MMC_HS200_MAX_DTR) 705 temp |= ESDHC_DLL_FREQ_SEL; 706 sdhci_writel(host, temp, ESDHC_DLLCFG0); 707 temp = sdhci_readl(host, ESDHC_TBCTL); 708 sdhci_writel(host, temp | ESDHC_HS400_WNDW_ADJUST, ESDHC_TBCTL); 709 710 esdhc_clock_enable(host, false); 711 esdhc_flush_async_fifo(host); 712 } 713 714 /* Wait max 20 ms */ 715 timeout = ktime_add_ms(ktime_get(), 20); 716 while (1) { 717 bool timedout = ktime_after(ktime_get(), timeout); 718 719 if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE) 720 break; 721 if (timedout) { 722 pr_err("%s: Internal clock never stabilised.\n", 723 mmc_hostname(host->mmc)); 724 return; 725 } 726 udelay(10); 727 } 728 729 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 730 temp |= ESDHC_CLOCK_SDCLKEN; 731 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 732 } 733 734 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 735 { 736 u32 ctrl; 737 738 ctrl = sdhci_readl(host, ESDHC_PROCTL); 739 ctrl &= (~ESDHC_CTRL_BUSWIDTH_MASK); 740 switch (width) { 741 case MMC_BUS_WIDTH_8: 742 ctrl |= ESDHC_CTRL_8BITBUS; 743 break; 744 745 case MMC_BUS_WIDTH_4: 746 ctrl |= ESDHC_CTRL_4BITBUS; 747 break; 748 749 default: 750 break; 751 } 752 753 sdhci_writel(host, ctrl, ESDHC_PROCTL); 754 } 755 756 static void esdhc_reset(struct sdhci_host *host, u8 mask) 757 { 758 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 759 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 760 u32 val; 761 762 sdhci_reset(host, mask); 763 764 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 765 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 766 767 if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc")) 768 mdelay(5); 769 770 if (mask & SDHCI_RESET_ALL) { 771 val = sdhci_readl(host, ESDHC_TBCTL); 772 val &= ~ESDHC_TB_EN; 773 sdhci_writel(host, val, ESDHC_TBCTL); 774 775 if (esdhc->quirk_unreliable_pulse_detection) { 776 val = sdhci_readl(host, ESDHC_DLLCFG1); 777 val &= ~ESDHC_DLL_PD_PULSE_STRETCH_SEL; 778 sdhci_writel(host, val, ESDHC_DLLCFG1); 779 } 780 } 781 } 782 783 /* The SCFG, Supplemental Configuration Unit, provides SoC specific 784 * configuration and status registers for the device. There is a 785 * SDHC IO VSEL control register on SCFG for some platforms. It's 786 * used to support SDHC IO voltage switching. 787 */ 788 static const struct of_device_id scfg_device_ids[] = { 789 { .compatible = "fsl,t1040-scfg", }, 790 { .compatible = "fsl,ls1012a-scfg", }, 791 { .compatible = "fsl,ls1046a-scfg", }, 792 {} 793 }; 794 795 /* SDHC IO VSEL control register definition */ 796 #define SCFG_SDHCIOVSELCR 0x408 797 #define SDHCIOVSELCR_TGLEN 0x80000000 798 #define SDHCIOVSELCR_VSELVAL 0x60000000 799 #define SDHCIOVSELCR_SDHC_VS 0x00000001 800 801 static int esdhc_signal_voltage_switch(struct mmc_host *mmc, 802 struct mmc_ios *ios) 803 { 804 struct sdhci_host *host = mmc_priv(mmc); 805 struct device_node *scfg_node; 806 void __iomem *scfg_base = NULL; 807 u32 sdhciovselcr; 808 u32 val; 809 810 /* 811 * Signal Voltage Switching is only applicable for Host Controllers 812 * v3.00 and above. 813 */ 814 if (host->version < SDHCI_SPEC_300) 815 return 0; 816 817 val = sdhci_readl(host, ESDHC_PROCTL); 818 819 switch (ios->signal_voltage) { 820 case MMC_SIGNAL_VOLTAGE_330: 821 val &= ~ESDHC_VOLT_SEL; 822 sdhci_writel(host, val, ESDHC_PROCTL); 823 return 0; 824 case MMC_SIGNAL_VOLTAGE_180: 825 scfg_node = of_find_matching_node(NULL, scfg_device_ids); 826 if (scfg_node) 827 scfg_base = of_iomap(scfg_node, 0); 828 if (scfg_base) { 829 sdhciovselcr = SDHCIOVSELCR_TGLEN | 830 SDHCIOVSELCR_VSELVAL; 831 iowrite32be(sdhciovselcr, 832 scfg_base + SCFG_SDHCIOVSELCR); 833 834 val |= ESDHC_VOLT_SEL; 835 sdhci_writel(host, val, ESDHC_PROCTL); 836 mdelay(5); 837 838 sdhciovselcr = SDHCIOVSELCR_TGLEN | 839 SDHCIOVSELCR_SDHC_VS; 840 iowrite32be(sdhciovselcr, 841 scfg_base + SCFG_SDHCIOVSELCR); 842 iounmap(scfg_base); 843 } else { 844 val |= ESDHC_VOLT_SEL; 845 sdhci_writel(host, val, ESDHC_PROCTL); 846 } 847 return 0; 848 default: 849 return 0; 850 } 851 } 852 853 static struct soc_device_attribute soc_tuning_erratum_type1[] = { 854 { .family = "QorIQ T1023", .revision = "1.0", }, 855 { .family = "QorIQ T1040", .revision = "1.0", }, 856 { .family = "QorIQ T2080", .revision = "1.0", }, 857 { .family = "QorIQ LS1021A", .revision = "1.0", }, 858 { }, 859 }; 860 861 static struct soc_device_attribute soc_tuning_erratum_type2[] = { 862 { .family = "QorIQ LS1012A", .revision = "1.0", }, 863 { .family = "QorIQ LS1043A", .revision = "1.*", }, 864 { .family = "QorIQ LS1046A", .revision = "1.0", }, 865 { .family = "QorIQ LS1080A", .revision = "1.0", }, 866 { .family = "QorIQ LS2080A", .revision = "1.0", }, 867 { .family = "QorIQ LA1575A", .revision = "1.0", }, 868 { }, 869 }; 870 871 static void esdhc_tuning_block_enable(struct sdhci_host *host, bool enable) 872 { 873 u32 val; 874 875 esdhc_clock_enable(host, false); 876 esdhc_flush_async_fifo(host); 877 878 val = sdhci_readl(host, ESDHC_TBCTL); 879 if (enable) 880 val |= ESDHC_TB_EN; 881 else 882 val &= ~ESDHC_TB_EN; 883 sdhci_writel(host, val, ESDHC_TBCTL); 884 885 esdhc_clock_enable(host, true); 886 } 887 888 static void esdhc_prepare_sw_tuning(struct sdhci_host *host, u8 *window_start, 889 u8 *window_end) 890 { 891 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 892 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 893 u8 tbstat_15_8, tbstat_7_0; 894 u32 val; 895 896 if (esdhc->quirk_tuning_erratum_type1) { 897 *window_start = 5 * esdhc->div_ratio; 898 *window_end = 3 * esdhc->div_ratio; 899 return; 900 } 901 902 /* Write TBCTL[11:8]=4'h8 */ 903 val = sdhci_readl(host, ESDHC_TBCTL); 904 val &= ~(0xf << 8); 905 val |= 8 << 8; 906 sdhci_writel(host, val, ESDHC_TBCTL); 907 908 mdelay(1); 909 910 /* Read TBCTL[31:0] register and rewrite again */ 911 val = sdhci_readl(host, ESDHC_TBCTL); 912 sdhci_writel(host, val, ESDHC_TBCTL); 913 914 mdelay(1); 915 916 /* Read the TBSTAT[31:0] register twice */ 917 val = sdhci_readl(host, ESDHC_TBSTAT); 918 val = sdhci_readl(host, ESDHC_TBSTAT); 919 920 /* Reset data lines by setting ESDHCCTL[RSTD] */ 921 sdhci_reset(host, SDHCI_RESET_DATA); 922 /* Write 32'hFFFF_FFFF to IRQSTAT register */ 923 sdhci_writel(host, 0xFFFFFFFF, SDHCI_INT_STATUS); 924 925 /* If TBSTAT[15:8]-TBSTAT[7:0] > 4 * div_ratio 926 * or TBSTAT[7:0]-TBSTAT[15:8] > 4 * div_ratio, 927 * then program TBPTR[TB_WNDW_END_PTR] = 4 * div_ratio 928 * and program TBPTR[TB_WNDW_START_PTR] = 8 * div_ratio. 929 */ 930 tbstat_7_0 = val & 0xff; 931 tbstat_15_8 = (val >> 8) & 0xff; 932 933 if (abs(tbstat_15_8 - tbstat_7_0) > (4 * esdhc->div_ratio)) { 934 *window_start = 8 * esdhc->div_ratio; 935 *window_end = 4 * esdhc->div_ratio; 936 } else { 937 *window_start = 5 * esdhc->div_ratio; 938 *window_end = 3 * esdhc->div_ratio; 939 } 940 } 941 942 static int esdhc_execute_sw_tuning(struct mmc_host *mmc, u32 opcode, 943 u8 window_start, u8 window_end) 944 { 945 struct sdhci_host *host = mmc_priv(mmc); 946 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 947 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 948 u32 val; 949 int ret; 950 951 /* Program TBPTR[TB_WNDW_END_PTR] and TBPTR[TB_WNDW_START_PTR] */ 952 val = ((u32)window_start << ESDHC_WNDW_STRT_PTR_SHIFT) & 953 ESDHC_WNDW_STRT_PTR_MASK; 954 val |= window_end & ESDHC_WNDW_END_PTR_MASK; 955 sdhci_writel(host, val, ESDHC_TBPTR); 956 957 /* Program the software tuning mode by setting TBCTL[TB_MODE]=2'h3 */ 958 val = sdhci_readl(host, ESDHC_TBCTL); 959 val &= ~ESDHC_TB_MODE_MASK; 960 val |= ESDHC_TB_MODE_SW; 961 sdhci_writel(host, val, ESDHC_TBCTL); 962 963 esdhc->in_sw_tuning = true; 964 ret = sdhci_execute_tuning(mmc, opcode); 965 esdhc->in_sw_tuning = false; 966 return ret; 967 } 968 969 static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) 970 { 971 struct sdhci_host *host = mmc_priv(mmc); 972 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 973 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 974 u8 window_start, window_end; 975 int ret, retries = 1; 976 bool hs400_tuning; 977 unsigned int clk; 978 u32 val; 979 980 /* For tuning mode, the sd clock divisor value 981 * must be larger than 3 according to reference manual. 982 */ 983 clk = esdhc->peripheral_clock / 3; 984 if (host->clock > clk) 985 esdhc_of_set_clock(host, clk); 986 987 esdhc_tuning_block_enable(host, true); 988 989 hs400_tuning = host->flags & SDHCI_HS400_TUNING; 990 991 do { 992 if (esdhc->quirk_limited_clk_division && 993 hs400_tuning) 994 esdhc_of_set_clock(host, host->clock); 995 996 /* Do HW tuning */ 997 val = sdhci_readl(host, ESDHC_TBCTL); 998 val &= ~ESDHC_TB_MODE_MASK; 999 val |= ESDHC_TB_MODE_3; 1000 sdhci_writel(host, val, ESDHC_TBCTL); 1001 1002 ret = sdhci_execute_tuning(mmc, opcode); 1003 if (ret) 1004 break; 1005 1006 /* If HW tuning fails and triggers erratum, 1007 * try workaround. 1008 */ 1009 ret = host->tuning_err; 1010 if (ret == -EAGAIN && 1011 (esdhc->quirk_tuning_erratum_type1 || 1012 esdhc->quirk_tuning_erratum_type2)) { 1013 /* Recover HS400 tuning flag */ 1014 if (hs400_tuning) 1015 host->flags |= SDHCI_HS400_TUNING; 1016 pr_info("%s: Hold on to use fixed sampling clock. Try SW tuning!\n", 1017 mmc_hostname(mmc)); 1018 /* Do SW tuning */ 1019 esdhc_prepare_sw_tuning(host, &window_start, 1020 &window_end); 1021 ret = esdhc_execute_sw_tuning(mmc, opcode, 1022 window_start, 1023 window_end); 1024 if (ret) 1025 break; 1026 1027 /* Retry both HW/SW tuning with reduced clock. */ 1028 ret = host->tuning_err; 1029 if (ret == -EAGAIN && retries) { 1030 /* Recover HS400 tuning flag */ 1031 if (hs400_tuning) 1032 host->flags |= SDHCI_HS400_TUNING; 1033 1034 clk = host->max_clk / (esdhc->div_ratio + 1); 1035 esdhc_of_set_clock(host, clk); 1036 pr_info("%s: Hold on to use fixed sampling clock. Try tuning with reduced clock!\n", 1037 mmc_hostname(mmc)); 1038 } else { 1039 break; 1040 } 1041 } else { 1042 break; 1043 } 1044 } while (retries--); 1045 1046 if (ret) { 1047 esdhc_tuning_block_enable(host, false); 1048 } else if (hs400_tuning) { 1049 val = sdhci_readl(host, ESDHC_SDTIMNGCTL); 1050 val |= ESDHC_FLW_CTL_BG; 1051 sdhci_writel(host, val, ESDHC_SDTIMNGCTL); 1052 } 1053 1054 return ret; 1055 } 1056 1057 static void esdhc_set_uhs_signaling(struct sdhci_host *host, 1058 unsigned int timing) 1059 { 1060 if (timing == MMC_TIMING_MMC_HS400) 1061 esdhc_tuning_block_enable(host, true); 1062 else 1063 sdhci_set_uhs_signaling(host, timing); 1064 } 1065 1066 static u32 esdhc_irq(struct sdhci_host *host, u32 intmask) 1067 { 1068 u32 command; 1069 1070 if (of_find_compatible_node(NULL, NULL, 1071 "fsl,p2020-esdhc")) { 1072 command = SDHCI_GET_CMD(sdhci_readw(host, 1073 SDHCI_COMMAND)); 1074 if (command == MMC_WRITE_MULTIPLE_BLOCK && 1075 sdhci_readw(host, SDHCI_BLOCK_COUNT) && 1076 intmask & SDHCI_INT_DATA_END) { 1077 intmask &= ~SDHCI_INT_DATA_END; 1078 sdhci_writel(host, SDHCI_INT_DATA_END, 1079 SDHCI_INT_STATUS); 1080 } 1081 } 1082 return intmask; 1083 } 1084 1085 #ifdef CONFIG_PM_SLEEP 1086 static u32 esdhc_proctl; 1087 static int esdhc_of_suspend(struct device *dev) 1088 { 1089 struct sdhci_host *host = dev_get_drvdata(dev); 1090 1091 esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL); 1092 1093 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1094 mmc_retune_needed(host->mmc); 1095 1096 return sdhci_suspend_host(host); 1097 } 1098 1099 static int esdhc_of_resume(struct device *dev) 1100 { 1101 struct sdhci_host *host = dev_get_drvdata(dev); 1102 int ret = sdhci_resume_host(host); 1103 1104 if (ret == 0) { 1105 /* Isn't this already done by sdhci_resume_host() ? --rmk */ 1106 esdhc_of_enable_dma(host); 1107 sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL); 1108 } 1109 return ret; 1110 } 1111 #endif 1112 1113 static SIMPLE_DEV_PM_OPS(esdhc_of_dev_pm_ops, 1114 esdhc_of_suspend, 1115 esdhc_of_resume); 1116 1117 static const struct sdhci_ops sdhci_esdhc_be_ops = { 1118 .read_l = esdhc_be_readl, 1119 .read_w = esdhc_be_readw, 1120 .read_b = esdhc_be_readb, 1121 .write_l = esdhc_be_writel, 1122 .write_w = esdhc_be_writew, 1123 .write_b = esdhc_be_writeb, 1124 .set_clock = esdhc_of_set_clock, 1125 .enable_dma = esdhc_of_enable_dma, 1126 .get_max_clock = esdhc_of_get_max_clock, 1127 .get_min_clock = esdhc_of_get_min_clock, 1128 .adma_workaround = esdhc_of_adma_workaround, 1129 .set_bus_width = esdhc_pltfm_set_bus_width, 1130 .reset = esdhc_reset, 1131 .set_uhs_signaling = esdhc_set_uhs_signaling, 1132 .irq = esdhc_irq, 1133 }; 1134 1135 static const struct sdhci_ops sdhci_esdhc_le_ops = { 1136 .read_l = esdhc_le_readl, 1137 .read_w = esdhc_le_readw, 1138 .read_b = esdhc_le_readb, 1139 .write_l = esdhc_le_writel, 1140 .write_w = esdhc_le_writew, 1141 .write_b = esdhc_le_writeb, 1142 .set_clock = esdhc_of_set_clock, 1143 .enable_dma = esdhc_of_enable_dma, 1144 .get_max_clock = esdhc_of_get_max_clock, 1145 .get_min_clock = esdhc_of_get_min_clock, 1146 .adma_workaround = esdhc_of_adma_workaround, 1147 .set_bus_width = esdhc_pltfm_set_bus_width, 1148 .reset = esdhc_reset, 1149 .set_uhs_signaling = esdhc_set_uhs_signaling, 1150 .irq = esdhc_irq, 1151 }; 1152 1153 static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = { 1154 .quirks = ESDHC_DEFAULT_QUIRKS | 1155 #ifdef CONFIG_PPC 1156 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 1157 #endif 1158 SDHCI_QUIRK_NO_CARD_NO_RESET | 1159 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1160 .ops = &sdhci_esdhc_be_ops, 1161 }; 1162 1163 static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = { 1164 .quirks = ESDHC_DEFAULT_QUIRKS | 1165 SDHCI_QUIRK_NO_CARD_NO_RESET | 1166 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1167 .ops = &sdhci_esdhc_le_ops, 1168 }; 1169 1170 static struct soc_device_attribute soc_incorrect_hostver[] = { 1171 { .family = "QorIQ T4240", .revision = "1.0", }, 1172 { .family = "QorIQ T4240", .revision = "2.0", }, 1173 { }, 1174 }; 1175 1176 static struct soc_device_attribute soc_fixup_sdhc_clkdivs[] = { 1177 { .family = "QorIQ LX2160A", .revision = "1.0", }, 1178 { .family = "QorIQ LX2160A", .revision = "2.0", }, 1179 { .family = "QorIQ LS1028A", .revision = "1.0", }, 1180 { }, 1181 }; 1182 1183 static struct soc_device_attribute soc_unreliable_pulse_detection[] = { 1184 { .family = "QorIQ LX2160A", .revision = "1.0", }, 1185 { }, 1186 }; 1187 1188 static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host) 1189 { 1190 const struct of_device_id *match; 1191 struct sdhci_pltfm_host *pltfm_host; 1192 struct sdhci_esdhc *esdhc; 1193 struct device_node *np; 1194 struct clk *clk; 1195 u32 val; 1196 u16 host_ver; 1197 1198 pltfm_host = sdhci_priv(host); 1199 esdhc = sdhci_pltfm_priv(pltfm_host); 1200 1201 host_ver = sdhci_readw(host, SDHCI_HOST_VERSION); 1202 esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >> 1203 SDHCI_VENDOR_VER_SHIFT; 1204 esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK; 1205 if (soc_device_match(soc_incorrect_hostver)) 1206 esdhc->quirk_incorrect_hostver = true; 1207 else 1208 esdhc->quirk_incorrect_hostver = false; 1209 1210 if (soc_device_match(soc_fixup_sdhc_clkdivs)) 1211 esdhc->quirk_limited_clk_division = true; 1212 else 1213 esdhc->quirk_limited_clk_division = false; 1214 1215 if (soc_device_match(soc_unreliable_pulse_detection)) 1216 esdhc->quirk_unreliable_pulse_detection = true; 1217 else 1218 esdhc->quirk_unreliable_pulse_detection = false; 1219 1220 match = of_match_node(sdhci_esdhc_of_match, pdev->dev.of_node); 1221 if (match) 1222 esdhc->clk_fixup = match->data; 1223 np = pdev->dev.of_node; 1224 clk = of_clk_get(np, 0); 1225 if (!IS_ERR(clk)) { 1226 /* 1227 * esdhc->peripheral_clock would be assigned with a value 1228 * which is eSDHC base clock when use periperal clock. 1229 * For some platforms, the clock value got by common clk 1230 * API is peripheral clock while the eSDHC base clock is 1231 * 1/2 peripheral clock. 1232 */ 1233 if (of_device_is_compatible(np, "fsl,ls1046a-esdhc") || 1234 of_device_is_compatible(np, "fsl,ls1028a-esdhc")) 1235 esdhc->peripheral_clock = clk_get_rate(clk) / 2; 1236 else 1237 esdhc->peripheral_clock = clk_get_rate(clk); 1238 1239 clk_put(clk); 1240 } 1241 1242 if (esdhc->peripheral_clock) { 1243 esdhc_clock_enable(host, false); 1244 val = sdhci_readl(host, ESDHC_DMA_SYSCTL); 1245 val |= ESDHC_PERIPHERAL_CLK_SEL; 1246 sdhci_writel(host, val, ESDHC_DMA_SYSCTL); 1247 esdhc_clock_enable(host, true); 1248 } 1249 } 1250 1251 static int esdhc_hs400_prepare_ddr(struct mmc_host *mmc) 1252 { 1253 esdhc_tuning_block_enable(mmc_priv(mmc), false); 1254 return 0; 1255 } 1256 1257 static int sdhci_esdhc_probe(struct platform_device *pdev) 1258 { 1259 struct sdhci_host *host; 1260 struct device_node *np; 1261 struct sdhci_pltfm_host *pltfm_host; 1262 struct sdhci_esdhc *esdhc; 1263 int ret; 1264 1265 np = pdev->dev.of_node; 1266 1267 if (of_property_read_bool(np, "little-endian")) 1268 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata, 1269 sizeof(struct sdhci_esdhc)); 1270 else 1271 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata, 1272 sizeof(struct sdhci_esdhc)); 1273 1274 if (IS_ERR(host)) 1275 return PTR_ERR(host); 1276 1277 host->mmc_host_ops.start_signal_voltage_switch = 1278 esdhc_signal_voltage_switch; 1279 host->mmc_host_ops.execute_tuning = esdhc_execute_tuning; 1280 host->mmc_host_ops.hs400_prepare_ddr = esdhc_hs400_prepare_ddr; 1281 host->tuning_delay = 1; 1282 1283 esdhc_init(pdev, host); 1284 1285 sdhci_get_of_property(pdev); 1286 1287 pltfm_host = sdhci_priv(host); 1288 esdhc = sdhci_pltfm_priv(pltfm_host); 1289 if (soc_device_match(soc_tuning_erratum_type1)) 1290 esdhc->quirk_tuning_erratum_type1 = true; 1291 else 1292 esdhc->quirk_tuning_erratum_type1 = false; 1293 1294 if (soc_device_match(soc_tuning_erratum_type2)) 1295 esdhc->quirk_tuning_erratum_type2 = true; 1296 else 1297 esdhc->quirk_tuning_erratum_type2 = false; 1298 1299 if (esdhc->vendor_ver == VENDOR_V_22) 1300 host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; 1301 1302 if (esdhc->vendor_ver > VENDOR_V_22) 1303 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; 1304 1305 if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc")) { 1306 host->quirks2 |= SDHCI_QUIRK_RESET_AFTER_REQUEST; 1307 host->quirks2 |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 1308 } 1309 1310 if (of_device_is_compatible(np, "fsl,p5040-esdhc") || 1311 of_device_is_compatible(np, "fsl,p5020-esdhc") || 1312 of_device_is_compatible(np, "fsl,p4080-esdhc") || 1313 of_device_is_compatible(np, "fsl,p1020-esdhc") || 1314 of_device_is_compatible(np, "fsl,t1040-esdhc")) 1315 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 1316 1317 if (of_device_is_compatible(np, "fsl,ls1021a-esdhc")) 1318 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 1319 1320 esdhc->quirk_ignore_data_inhibit = false; 1321 if (of_device_is_compatible(np, "fsl,p2020-esdhc")) { 1322 /* 1323 * Freescale messed up with P2020 as it has a non-standard 1324 * host control register 1325 */ 1326 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL; 1327 esdhc->quirk_ignore_data_inhibit = true; 1328 } 1329 1330 /* call to generic mmc_of_parse to support additional capabilities */ 1331 ret = mmc_of_parse(host->mmc); 1332 if (ret) 1333 goto err; 1334 1335 mmc_of_parse_voltage(np, &host->ocr_mask); 1336 1337 ret = sdhci_add_host(host); 1338 if (ret) 1339 goto err; 1340 1341 return 0; 1342 err: 1343 sdhci_pltfm_free(pdev); 1344 return ret; 1345 } 1346 1347 static struct platform_driver sdhci_esdhc_driver = { 1348 .driver = { 1349 .name = "sdhci-esdhc", 1350 .of_match_table = sdhci_esdhc_of_match, 1351 .pm = &esdhc_of_dev_pm_ops, 1352 }, 1353 .probe = sdhci_esdhc_probe, 1354 .remove = sdhci_pltfm_unregister, 1355 }; 1356 1357 module_platform_driver(sdhci_esdhc_driver); 1358 1359 MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC"); 1360 MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, " 1361 "Anton Vorontsov <avorontsov@ru.mvista.com>"); 1362 MODULE_LICENSE("GPL v2"); 1363