1 /* 2 * Freescale eSDHC controller driver. 3 * 4 * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc. 5 * Copyright (c) 2009 MontaVista Software, Inc. 6 * 7 * Authors: Xiaobo Xie <X.Xie@freescale.com> 8 * Anton Vorontsov <avorontsov@ru.mvista.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or (at 13 * your option) any later version. 14 */ 15 16 #include <linux/err.h> 17 #include <linux/io.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/delay.h> 21 #include <linux/module.h> 22 #include <linux/sys_soc.h> 23 #include <linux/clk.h> 24 #include <linux/ktime.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/mmc/host.h> 27 #include <linux/mmc/mmc.h> 28 #include "sdhci-pltfm.h" 29 #include "sdhci-esdhc.h" 30 31 #define VENDOR_V_22 0x12 32 #define VENDOR_V_23 0x13 33 34 #define MMC_TIMING_NUM (MMC_TIMING_MMC_HS400 + 1) 35 36 struct esdhc_clk_fixup { 37 const unsigned int sd_dflt_max_clk; 38 const unsigned int max_clk[MMC_TIMING_NUM]; 39 }; 40 41 static const struct esdhc_clk_fixup ls1021a_esdhc_clk = { 42 .sd_dflt_max_clk = 25000000, 43 .max_clk[MMC_TIMING_MMC_HS] = 46500000, 44 .max_clk[MMC_TIMING_SD_HS] = 46500000, 45 }; 46 47 static const struct esdhc_clk_fixup ls1046a_esdhc_clk = { 48 .sd_dflt_max_clk = 25000000, 49 .max_clk[MMC_TIMING_UHS_SDR104] = 167000000, 50 .max_clk[MMC_TIMING_MMC_HS200] = 167000000, 51 }; 52 53 static const struct esdhc_clk_fixup ls1012a_esdhc_clk = { 54 .sd_dflt_max_clk = 25000000, 55 .max_clk[MMC_TIMING_UHS_SDR104] = 125000000, 56 .max_clk[MMC_TIMING_MMC_HS200] = 125000000, 57 }; 58 59 static const struct esdhc_clk_fixup p1010_esdhc_clk = { 60 .sd_dflt_max_clk = 20000000, 61 .max_clk[MMC_TIMING_LEGACY] = 20000000, 62 .max_clk[MMC_TIMING_MMC_HS] = 42000000, 63 .max_clk[MMC_TIMING_SD_HS] = 40000000, 64 }; 65 66 static const struct of_device_id sdhci_esdhc_of_match[] = { 67 { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk}, 68 { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk}, 69 { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk}, 70 { .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk}, 71 { .compatible = "fsl,mpc8379-esdhc" }, 72 { .compatible = "fsl,mpc8536-esdhc" }, 73 { .compatible = "fsl,esdhc" }, 74 { } 75 }; 76 MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match); 77 78 struct sdhci_esdhc { 79 u8 vendor_ver; 80 u8 spec_ver; 81 bool quirk_incorrect_hostver; 82 bool quirk_limited_clk_division; 83 bool quirk_unreliable_pulse_detection; 84 bool quirk_fixup_tuning; 85 unsigned int peripheral_clock; 86 const struct esdhc_clk_fixup *clk_fixup; 87 u32 div_ratio; 88 }; 89 90 /** 91 * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register 92 * to make it compatible with SD spec. 93 * 94 * @host: pointer to sdhci_host 95 * @spec_reg: SD spec register address 96 * @value: 32bit eSDHC register value on spec_reg address 97 * 98 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 99 * registers are 32 bits. There are differences in register size, register 100 * address, register function, bit position and function between eSDHC spec 101 * and SD spec. 102 * 103 * Return a fixed up register value 104 */ 105 static u32 esdhc_readl_fixup(struct sdhci_host *host, 106 int spec_reg, u32 value) 107 { 108 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 109 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 110 u32 ret; 111 112 /* 113 * The bit of ADMA flag in eSDHC is not compatible with standard 114 * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is 115 * supported by eSDHC. 116 * And for many FSL eSDHC controller, the reset value of field 117 * SDHCI_CAN_DO_ADMA1 is 1, but some of them can't support ADMA, 118 * only these vendor version is greater than 2.2/0x12 support ADMA. 119 */ 120 if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) { 121 if (esdhc->vendor_ver > VENDOR_V_22) { 122 ret = value | SDHCI_CAN_DO_ADMA2; 123 return ret; 124 } 125 } 126 /* 127 * The DAT[3:0] line signal levels and the CMD line signal level are 128 * not compatible with standard SDHC register. The line signal levels 129 * DAT[7:0] are at bits 31:24 and the command line signal level is at 130 * bit 23. All other bits are the same as in the standard SDHC 131 * register. 132 */ 133 if (spec_reg == SDHCI_PRESENT_STATE) { 134 ret = value & 0x000fffff; 135 ret |= (value >> 4) & SDHCI_DATA_LVL_MASK; 136 ret |= (value << 1) & SDHCI_CMD_LVL; 137 return ret; 138 } 139 140 /* 141 * DTS properties of mmc host are used to enable each speed mode 142 * according to soc and board capability. So clean up 143 * SDR50/SDR104/DDR50 support bits here. 144 */ 145 if (spec_reg == SDHCI_CAPABILITIES_1) { 146 ret = value & ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | 147 SDHCI_SUPPORT_DDR50); 148 return ret; 149 } 150 151 ret = value; 152 return ret; 153 } 154 155 static u16 esdhc_readw_fixup(struct sdhci_host *host, 156 int spec_reg, u32 value) 157 { 158 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 159 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 160 u16 ret; 161 int shift = (spec_reg & 0x2) * 8; 162 163 if (spec_reg == SDHCI_HOST_VERSION) 164 ret = value & 0xffff; 165 else 166 ret = (value >> shift) & 0xffff; 167 /* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect 168 * vendor version and spec version information. 169 */ 170 if ((spec_reg == SDHCI_HOST_VERSION) && 171 (esdhc->quirk_incorrect_hostver)) 172 ret = (VENDOR_V_23 << SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200; 173 return ret; 174 } 175 176 static u8 esdhc_readb_fixup(struct sdhci_host *host, 177 int spec_reg, u32 value) 178 { 179 u8 ret; 180 u8 dma_bits; 181 int shift = (spec_reg & 0x3) * 8; 182 183 ret = (value >> shift) & 0xff; 184 185 /* 186 * "DMA select" locates at offset 0x28 in SD specification, but on 187 * P5020 or P3041, it locates at 0x29. 188 */ 189 if (spec_reg == SDHCI_HOST_CONTROL) { 190 /* DMA select is 22,23 bits in Protocol Control Register */ 191 dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK; 192 /* fixup the result */ 193 ret &= ~SDHCI_CTRL_DMA_MASK; 194 ret |= dma_bits; 195 } 196 return ret; 197 } 198 199 /** 200 * esdhc_write*_fixup - Fixup the SD spec register value so that it could be 201 * written into eSDHC register. 202 * 203 * @host: pointer to sdhci_host 204 * @spec_reg: SD spec register address 205 * @value: 8/16/32bit SD spec register value that would be written 206 * @old_value: 32bit eSDHC register value on spec_reg address 207 * 208 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 209 * registers are 32 bits. There are differences in register size, register 210 * address, register function, bit position and function between eSDHC spec 211 * and SD spec. 212 * 213 * Return a fixed up register value 214 */ 215 static u32 esdhc_writel_fixup(struct sdhci_host *host, 216 int spec_reg, u32 value, u32 old_value) 217 { 218 u32 ret; 219 220 /* 221 * Enabling IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE] 222 * when SYSCTL[RSTD] is set for some special operations. 223 * No any impact on other operation. 224 */ 225 if (spec_reg == SDHCI_INT_ENABLE) 226 ret = value | SDHCI_INT_BLK_GAP; 227 else 228 ret = value; 229 230 return ret; 231 } 232 233 static u32 esdhc_writew_fixup(struct sdhci_host *host, 234 int spec_reg, u16 value, u32 old_value) 235 { 236 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 237 int shift = (spec_reg & 0x2) * 8; 238 u32 ret; 239 240 switch (spec_reg) { 241 case SDHCI_TRANSFER_MODE: 242 /* 243 * Postpone this write, we must do it together with a 244 * command write that is down below. Return old value. 245 */ 246 pltfm_host->xfer_mode_shadow = value; 247 return old_value; 248 case SDHCI_COMMAND: 249 ret = (value << 16) | pltfm_host->xfer_mode_shadow; 250 return ret; 251 } 252 253 ret = old_value & (~(0xffff << shift)); 254 ret |= (value << shift); 255 256 if (spec_reg == SDHCI_BLOCK_SIZE) { 257 /* 258 * Two last DMA bits are reserved, and first one is used for 259 * non-standard blksz of 4096 bytes that we don't support 260 * yet. So clear the DMA boundary bits. 261 */ 262 ret &= (~SDHCI_MAKE_BLKSZ(0x7, 0)); 263 } 264 return ret; 265 } 266 267 static u32 esdhc_writeb_fixup(struct sdhci_host *host, 268 int spec_reg, u8 value, u32 old_value) 269 { 270 u32 ret; 271 u32 dma_bits; 272 u8 tmp; 273 int shift = (spec_reg & 0x3) * 8; 274 275 /* 276 * eSDHC doesn't have a standard power control register, so we do 277 * nothing here to avoid incorrect operation. 278 */ 279 if (spec_reg == SDHCI_POWER_CONTROL) 280 return old_value; 281 /* 282 * "DMA select" location is offset 0x28 in SD specification, but on 283 * P5020 or P3041, it's located at 0x29. 284 */ 285 if (spec_reg == SDHCI_HOST_CONTROL) { 286 /* 287 * If host control register is not standard, exit 288 * this function 289 */ 290 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL) 291 return old_value; 292 293 /* DMA select is 22,23 bits in Protocol Control Register */ 294 dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5; 295 ret = (old_value & (~(SDHCI_CTRL_DMA_MASK << 5))) | dma_bits; 296 tmp = (value & (~SDHCI_CTRL_DMA_MASK)) | 297 (old_value & SDHCI_CTRL_DMA_MASK); 298 ret = (ret & (~0xff)) | tmp; 299 300 /* Prevent SDHCI core from writing reserved bits (e.g. HISPD) */ 301 ret &= ~ESDHC_HOST_CONTROL_RES; 302 return ret; 303 } 304 305 ret = (old_value & (~(0xff << shift))) | (value << shift); 306 return ret; 307 } 308 309 static u32 esdhc_be_readl(struct sdhci_host *host, int reg) 310 { 311 u32 ret; 312 u32 value; 313 314 if (reg == SDHCI_CAPABILITIES_1) 315 value = ioread32be(host->ioaddr + ESDHC_CAPABILITIES_1); 316 else 317 value = ioread32be(host->ioaddr + reg); 318 319 ret = esdhc_readl_fixup(host, reg, value); 320 321 return ret; 322 } 323 324 static u32 esdhc_le_readl(struct sdhci_host *host, int reg) 325 { 326 u32 ret; 327 u32 value; 328 329 if (reg == SDHCI_CAPABILITIES_1) 330 value = ioread32(host->ioaddr + ESDHC_CAPABILITIES_1); 331 else 332 value = ioread32(host->ioaddr + reg); 333 334 ret = esdhc_readl_fixup(host, reg, value); 335 336 return ret; 337 } 338 339 static u16 esdhc_be_readw(struct sdhci_host *host, int reg) 340 { 341 u16 ret; 342 u32 value; 343 int base = reg & ~0x3; 344 345 value = ioread32be(host->ioaddr + base); 346 ret = esdhc_readw_fixup(host, reg, value); 347 return ret; 348 } 349 350 static u16 esdhc_le_readw(struct sdhci_host *host, int reg) 351 { 352 u16 ret; 353 u32 value; 354 int base = reg & ~0x3; 355 356 value = ioread32(host->ioaddr + base); 357 ret = esdhc_readw_fixup(host, reg, value); 358 return ret; 359 } 360 361 static u8 esdhc_be_readb(struct sdhci_host *host, int reg) 362 { 363 u8 ret; 364 u32 value; 365 int base = reg & ~0x3; 366 367 value = ioread32be(host->ioaddr + base); 368 ret = esdhc_readb_fixup(host, reg, value); 369 return ret; 370 } 371 372 static u8 esdhc_le_readb(struct sdhci_host *host, int reg) 373 { 374 u8 ret; 375 u32 value; 376 int base = reg & ~0x3; 377 378 value = ioread32(host->ioaddr + base); 379 ret = esdhc_readb_fixup(host, reg, value); 380 return ret; 381 } 382 383 static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg) 384 { 385 u32 value; 386 387 value = esdhc_writel_fixup(host, reg, val, 0); 388 iowrite32be(value, host->ioaddr + reg); 389 } 390 391 static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg) 392 { 393 u32 value; 394 395 value = esdhc_writel_fixup(host, reg, val, 0); 396 iowrite32(value, host->ioaddr + reg); 397 } 398 399 static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg) 400 { 401 int base = reg & ~0x3; 402 u32 value; 403 u32 ret; 404 405 value = ioread32be(host->ioaddr + base); 406 ret = esdhc_writew_fixup(host, reg, val, value); 407 if (reg != SDHCI_TRANSFER_MODE) 408 iowrite32be(ret, host->ioaddr + base); 409 } 410 411 static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg) 412 { 413 int base = reg & ~0x3; 414 u32 value; 415 u32 ret; 416 417 value = ioread32(host->ioaddr + base); 418 ret = esdhc_writew_fixup(host, reg, val, value); 419 if (reg != SDHCI_TRANSFER_MODE) 420 iowrite32(ret, host->ioaddr + base); 421 } 422 423 static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg) 424 { 425 int base = reg & ~0x3; 426 u32 value; 427 u32 ret; 428 429 value = ioread32be(host->ioaddr + base); 430 ret = esdhc_writeb_fixup(host, reg, val, value); 431 iowrite32be(ret, host->ioaddr + base); 432 } 433 434 static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg) 435 { 436 int base = reg & ~0x3; 437 u32 value; 438 u32 ret; 439 440 value = ioread32(host->ioaddr + base); 441 ret = esdhc_writeb_fixup(host, reg, val, value); 442 iowrite32(ret, host->ioaddr + base); 443 } 444 445 /* 446 * For Abort or Suspend after Stop at Block Gap, ignore the ADMA 447 * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC]) 448 * and Block Gap Event(IRQSTAT[BGE]) are also set. 449 * For Continue, apply soft reset for data(SYSCTL[RSTD]); 450 * and re-issue the entire read transaction from beginning. 451 */ 452 static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask) 453 { 454 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 455 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 456 bool applicable; 457 dma_addr_t dmastart; 458 dma_addr_t dmanow; 459 460 applicable = (intmask & SDHCI_INT_DATA_END) && 461 (intmask & SDHCI_INT_BLK_GAP) && 462 (esdhc->vendor_ver == VENDOR_V_23); 463 if (!applicable) 464 return; 465 466 host->data->error = 0; 467 dmastart = sg_dma_address(host->data->sg); 468 dmanow = dmastart + host->data->bytes_xfered; 469 /* 470 * Force update to the next DMA block boundary. 471 */ 472 dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 473 SDHCI_DEFAULT_BOUNDARY_SIZE; 474 host->data->bytes_xfered = dmanow - dmastart; 475 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 476 } 477 478 static int esdhc_of_enable_dma(struct sdhci_host *host) 479 { 480 u32 value; 481 struct device *dev = mmc_dev(host->mmc); 482 483 if (of_device_is_compatible(dev->of_node, "fsl,ls1043a-esdhc") || 484 of_device_is_compatible(dev->of_node, "fsl,ls1046a-esdhc")) 485 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); 486 487 value = sdhci_readl(host, ESDHC_DMA_SYSCTL); 488 value |= ESDHC_DMA_SNOOP; 489 sdhci_writel(host, value, ESDHC_DMA_SYSCTL); 490 return 0; 491 } 492 493 static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host) 494 { 495 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 496 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 497 498 if (esdhc->peripheral_clock) 499 return esdhc->peripheral_clock; 500 else 501 return pltfm_host->clock; 502 } 503 504 static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host) 505 { 506 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 507 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 508 unsigned int clock; 509 510 if (esdhc->peripheral_clock) 511 clock = esdhc->peripheral_clock; 512 else 513 clock = pltfm_host->clock; 514 return clock / 256 / 16; 515 } 516 517 static void esdhc_clock_enable(struct sdhci_host *host, bool enable) 518 { 519 u32 val; 520 ktime_t timeout; 521 522 val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 523 524 if (enable) 525 val |= ESDHC_CLOCK_SDCLKEN; 526 else 527 val &= ~ESDHC_CLOCK_SDCLKEN; 528 529 sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL); 530 531 /* Wait max 20 ms */ 532 timeout = ktime_add_ms(ktime_get(), 20); 533 val = ESDHC_CLOCK_STABLE; 534 while (1) { 535 bool timedout = ktime_after(ktime_get(), timeout); 536 537 if (sdhci_readl(host, ESDHC_PRSSTAT) & val) 538 break; 539 if (timedout) { 540 pr_err("%s: Internal clock never stabilised.\n", 541 mmc_hostname(host->mmc)); 542 break; 543 } 544 udelay(10); 545 } 546 } 547 548 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock) 549 { 550 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 551 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 552 int pre_div = 1; 553 int div = 1; 554 int division; 555 ktime_t timeout; 556 long fixup = 0; 557 u32 temp; 558 559 host->mmc->actual_clock = 0; 560 561 if (clock == 0) { 562 esdhc_clock_enable(host, false); 563 return; 564 } 565 566 /* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */ 567 if (esdhc->vendor_ver < VENDOR_V_23) 568 pre_div = 2; 569 570 if (host->mmc->card && mmc_card_sd(host->mmc->card) && 571 esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY) 572 fixup = esdhc->clk_fixup->sd_dflt_max_clk; 573 else if (esdhc->clk_fixup) 574 fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing]; 575 576 if (fixup && clock > fixup) 577 clock = fixup; 578 579 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 580 temp &= ~(ESDHC_CLOCK_SDCLKEN | ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | 581 ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK); 582 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 583 584 while (host->max_clk / pre_div / 16 > clock && pre_div < 256) 585 pre_div *= 2; 586 587 while (host->max_clk / pre_div / div > clock && div < 16) 588 div++; 589 590 if (esdhc->quirk_limited_clk_division && 591 clock == MMC_HS200_MAX_DTR && 592 (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 || 593 host->flags & SDHCI_HS400_TUNING)) { 594 division = pre_div * div; 595 if (division <= 4) { 596 pre_div = 4; 597 div = 1; 598 } else if (division <= 8) { 599 pre_div = 4; 600 div = 2; 601 } else if (division <= 12) { 602 pre_div = 4; 603 div = 3; 604 } else { 605 pr_warn("%s: using unsupported clock division.\n", 606 mmc_hostname(host->mmc)); 607 } 608 } 609 610 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 611 clock, host->max_clk / pre_div / div); 612 host->mmc->actual_clock = host->max_clk / pre_div / div; 613 esdhc->div_ratio = pre_div * div; 614 pre_div >>= 1; 615 div--; 616 617 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 618 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 619 | (div << ESDHC_DIVIDER_SHIFT) 620 | (pre_div << ESDHC_PREDIV_SHIFT)); 621 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 622 623 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && 624 clock == MMC_HS200_MAX_DTR) { 625 temp = sdhci_readl(host, ESDHC_TBCTL); 626 sdhci_writel(host, temp | ESDHC_HS400_MODE, ESDHC_TBCTL); 627 temp = sdhci_readl(host, ESDHC_SDCLKCTL); 628 sdhci_writel(host, temp | ESDHC_CMD_CLK_CTL, ESDHC_SDCLKCTL); 629 esdhc_clock_enable(host, true); 630 631 temp = sdhci_readl(host, ESDHC_DLLCFG0); 632 temp |= ESDHC_DLL_ENABLE; 633 if (host->mmc->actual_clock == MMC_HS200_MAX_DTR) 634 temp |= ESDHC_DLL_FREQ_SEL; 635 sdhci_writel(host, temp, ESDHC_DLLCFG0); 636 temp = sdhci_readl(host, ESDHC_TBCTL); 637 sdhci_writel(host, temp | ESDHC_HS400_WNDW_ADJUST, ESDHC_TBCTL); 638 639 esdhc_clock_enable(host, false); 640 temp = sdhci_readl(host, ESDHC_DMA_SYSCTL); 641 temp |= ESDHC_FLUSH_ASYNC_FIFO; 642 sdhci_writel(host, temp, ESDHC_DMA_SYSCTL); 643 } 644 645 /* Wait max 20 ms */ 646 timeout = ktime_add_ms(ktime_get(), 20); 647 while (1) { 648 bool timedout = ktime_after(ktime_get(), timeout); 649 650 if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE) 651 break; 652 if (timedout) { 653 pr_err("%s: Internal clock never stabilised.\n", 654 mmc_hostname(host->mmc)); 655 return; 656 } 657 udelay(10); 658 } 659 660 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 661 temp |= ESDHC_CLOCK_SDCLKEN; 662 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 663 } 664 665 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 666 { 667 u32 ctrl; 668 669 ctrl = sdhci_readl(host, ESDHC_PROCTL); 670 ctrl &= (~ESDHC_CTRL_BUSWIDTH_MASK); 671 switch (width) { 672 case MMC_BUS_WIDTH_8: 673 ctrl |= ESDHC_CTRL_8BITBUS; 674 break; 675 676 case MMC_BUS_WIDTH_4: 677 ctrl |= ESDHC_CTRL_4BITBUS; 678 break; 679 680 default: 681 break; 682 } 683 684 sdhci_writel(host, ctrl, ESDHC_PROCTL); 685 } 686 687 static void esdhc_reset(struct sdhci_host *host, u8 mask) 688 { 689 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 690 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 691 u32 val; 692 693 sdhci_reset(host, mask); 694 695 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 696 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 697 698 if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc")) 699 mdelay(5); 700 701 if (mask & SDHCI_RESET_ALL) { 702 val = sdhci_readl(host, ESDHC_TBCTL); 703 val &= ~ESDHC_TB_EN; 704 sdhci_writel(host, val, ESDHC_TBCTL); 705 706 if (esdhc->quirk_unreliable_pulse_detection) { 707 val = sdhci_readl(host, ESDHC_DLLCFG1); 708 val &= ~ESDHC_DLL_PD_PULSE_STRETCH_SEL; 709 sdhci_writel(host, val, ESDHC_DLLCFG1); 710 } 711 } 712 } 713 714 /* The SCFG, Supplemental Configuration Unit, provides SoC specific 715 * configuration and status registers for the device. There is a 716 * SDHC IO VSEL control register on SCFG for some platforms. It's 717 * used to support SDHC IO voltage switching. 718 */ 719 static const struct of_device_id scfg_device_ids[] = { 720 { .compatible = "fsl,t1040-scfg", }, 721 { .compatible = "fsl,ls1012a-scfg", }, 722 { .compatible = "fsl,ls1046a-scfg", }, 723 {} 724 }; 725 726 /* SDHC IO VSEL control register definition */ 727 #define SCFG_SDHCIOVSELCR 0x408 728 #define SDHCIOVSELCR_TGLEN 0x80000000 729 #define SDHCIOVSELCR_VSELVAL 0x60000000 730 #define SDHCIOVSELCR_SDHC_VS 0x00000001 731 732 static int esdhc_signal_voltage_switch(struct mmc_host *mmc, 733 struct mmc_ios *ios) 734 { 735 struct sdhci_host *host = mmc_priv(mmc); 736 struct device_node *scfg_node; 737 void __iomem *scfg_base = NULL; 738 u32 sdhciovselcr; 739 u32 val; 740 741 /* 742 * Signal Voltage Switching is only applicable for Host Controllers 743 * v3.00 and above. 744 */ 745 if (host->version < SDHCI_SPEC_300) 746 return 0; 747 748 val = sdhci_readl(host, ESDHC_PROCTL); 749 750 switch (ios->signal_voltage) { 751 case MMC_SIGNAL_VOLTAGE_330: 752 val &= ~ESDHC_VOLT_SEL; 753 sdhci_writel(host, val, ESDHC_PROCTL); 754 return 0; 755 case MMC_SIGNAL_VOLTAGE_180: 756 scfg_node = of_find_matching_node(NULL, scfg_device_ids); 757 if (scfg_node) 758 scfg_base = of_iomap(scfg_node, 0); 759 if (scfg_base) { 760 sdhciovselcr = SDHCIOVSELCR_TGLEN | 761 SDHCIOVSELCR_VSELVAL; 762 iowrite32be(sdhciovselcr, 763 scfg_base + SCFG_SDHCIOVSELCR); 764 765 val |= ESDHC_VOLT_SEL; 766 sdhci_writel(host, val, ESDHC_PROCTL); 767 mdelay(5); 768 769 sdhciovselcr = SDHCIOVSELCR_TGLEN | 770 SDHCIOVSELCR_SDHC_VS; 771 iowrite32be(sdhciovselcr, 772 scfg_base + SCFG_SDHCIOVSELCR); 773 iounmap(scfg_base); 774 } else { 775 val |= ESDHC_VOLT_SEL; 776 sdhci_writel(host, val, ESDHC_PROCTL); 777 } 778 return 0; 779 default: 780 return 0; 781 } 782 } 783 784 static struct soc_device_attribute soc_fixup_tuning[] = { 785 { .family = "QorIQ T1040", .revision = "1.0", }, 786 { .family = "QorIQ T2080", .revision = "1.0", }, 787 { .family = "QorIQ T1023", .revision = "1.0", }, 788 { .family = "QorIQ LS1021A", .revision = "1.0", }, 789 { .family = "QorIQ LS1080A", .revision = "1.0", }, 790 { .family = "QorIQ LS2080A", .revision = "1.0", }, 791 { .family = "QorIQ LS1012A", .revision = "1.0", }, 792 { .family = "QorIQ LS1043A", .revision = "1.*", }, 793 { .family = "QorIQ LS1046A", .revision = "1.0", }, 794 { }, 795 }; 796 797 static void esdhc_tuning_block_enable(struct sdhci_host *host, bool enable) 798 { 799 u32 val; 800 801 esdhc_clock_enable(host, false); 802 803 val = sdhci_readl(host, ESDHC_DMA_SYSCTL); 804 val |= ESDHC_FLUSH_ASYNC_FIFO; 805 sdhci_writel(host, val, ESDHC_DMA_SYSCTL); 806 807 val = sdhci_readl(host, ESDHC_TBCTL); 808 if (enable) 809 val |= ESDHC_TB_EN; 810 else 811 val &= ~ESDHC_TB_EN; 812 sdhci_writel(host, val, ESDHC_TBCTL); 813 814 esdhc_clock_enable(host, true); 815 } 816 817 static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) 818 { 819 struct sdhci_host *host = mmc_priv(mmc); 820 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 821 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 822 bool hs400_tuning; 823 u32 val; 824 int ret; 825 826 if (esdhc->quirk_limited_clk_division && 827 host->flags & SDHCI_HS400_TUNING) 828 esdhc_of_set_clock(host, host->clock); 829 830 esdhc_tuning_block_enable(host, true); 831 832 hs400_tuning = host->flags & SDHCI_HS400_TUNING; 833 ret = sdhci_execute_tuning(mmc, opcode); 834 835 if (hs400_tuning) { 836 val = sdhci_readl(host, ESDHC_SDTIMNGCTL); 837 val |= ESDHC_FLW_CTL_BG; 838 sdhci_writel(host, val, ESDHC_SDTIMNGCTL); 839 } 840 841 if (host->tuning_err == -EAGAIN && esdhc->quirk_fixup_tuning) { 842 843 /* program TBPTR[TB_WNDW_END_PTR] = 3*DIV_RATIO and 844 * program TBPTR[TB_WNDW_START_PTR] = 5*DIV_RATIO 845 */ 846 val = sdhci_readl(host, ESDHC_TBPTR); 847 val = (val & ~((0x7f << 8) | 0x7f)) | 848 (3 * esdhc->div_ratio) | ((5 * esdhc->div_ratio) << 8); 849 sdhci_writel(host, val, ESDHC_TBPTR); 850 851 /* program the software tuning mode by setting 852 * TBCTL[TB_MODE]=2'h3 853 */ 854 val = sdhci_readl(host, ESDHC_TBCTL); 855 val |= 0x3; 856 sdhci_writel(host, val, ESDHC_TBCTL); 857 sdhci_execute_tuning(mmc, opcode); 858 } 859 return ret; 860 } 861 862 static void esdhc_set_uhs_signaling(struct sdhci_host *host, 863 unsigned int timing) 864 { 865 if (timing == MMC_TIMING_MMC_HS400) 866 esdhc_tuning_block_enable(host, true); 867 else 868 sdhci_set_uhs_signaling(host, timing); 869 } 870 871 static u32 esdhc_irq(struct sdhci_host *host, u32 intmask) 872 { 873 u32 command; 874 875 if (of_find_compatible_node(NULL, NULL, 876 "fsl,p2020-esdhc")) { 877 command = SDHCI_GET_CMD(sdhci_readw(host, 878 SDHCI_COMMAND)); 879 if (command == MMC_WRITE_MULTIPLE_BLOCK && 880 sdhci_readw(host, SDHCI_BLOCK_COUNT) && 881 intmask & SDHCI_INT_DATA_END) { 882 intmask &= ~SDHCI_INT_DATA_END; 883 sdhci_writel(host, SDHCI_INT_DATA_END, 884 SDHCI_INT_STATUS); 885 } 886 } 887 return intmask; 888 } 889 890 #ifdef CONFIG_PM_SLEEP 891 static u32 esdhc_proctl; 892 static int esdhc_of_suspend(struct device *dev) 893 { 894 struct sdhci_host *host = dev_get_drvdata(dev); 895 896 esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL); 897 898 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 899 mmc_retune_needed(host->mmc); 900 901 return sdhci_suspend_host(host); 902 } 903 904 static int esdhc_of_resume(struct device *dev) 905 { 906 struct sdhci_host *host = dev_get_drvdata(dev); 907 int ret = sdhci_resume_host(host); 908 909 if (ret == 0) { 910 /* Isn't this already done by sdhci_resume_host() ? --rmk */ 911 esdhc_of_enable_dma(host); 912 sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL); 913 } 914 return ret; 915 } 916 #endif 917 918 static SIMPLE_DEV_PM_OPS(esdhc_of_dev_pm_ops, 919 esdhc_of_suspend, 920 esdhc_of_resume); 921 922 static const struct sdhci_ops sdhci_esdhc_be_ops = { 923 .read_l = esdhc_be_readl, 924 .read_w = esdhc_be_readw, 925 .read_b = esdhc_be_readb, 926 .write_l = esdhc_be_writel, 927 .write_w = esdhc_be_writew, 928 .write_b = esdhc_be_writeb, 929 .set_clock = esdhc_of_set_clock, 930 .enable_dma = esdhc_of_enable_dma, 931 .get_max_clock = esdhc_of_get_max_clock, 932 .get_min_clock = esdhc_of_get_min_clock, 933 .adma_workaround = esdhc_of_adma_workaround, 934 .set_bus_width = esdhc_pltfm_set_bus_width, 935 .reset = esdhc_reset, 936 .set_uhs_signaling = esdhc_set_uhs_signaling, 937 .irq = esdhc_irq, 938 }; 939 940 static const struct sdhci_ops sdhci_esdhc_le_ops = { 941 .read_l = esdhc_le_readl, 942 .read_w = esdhc_le_readw, 943 .read_b = esdhc_le_readb, 944 .write_l = esdhc_le_writel, 945 .write_w = esdhc_le_writew, 946 .write_b = esdhc_le_writeb, 947 .set_clock = esdhc_of_set_clock, 948 .enable_dma = esdhc_of_enable_dma, 949 .get_max_clock = esdhc_of_get_max_clock, 950 .get_min_clock = esdhc_of_get_min_clock, 951 .adma_workaround = esdhc_of_adma_workaround, 952 .set_bus_width = esdhc_pltfm_set_bus_width, 953 .reset = esdhc_reset, 954 .set_uhs_signaling = esdhc_set_uhs_signaling, 955 .irq = esdhc_irq, 956 }; 957 958 static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = { 959 .quirks = ESDHC_DEFAULT_QUIRKS | 960 #ifdef CONFIG_PPC 961 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 962 #endif 963 SDHCI_QUIRK_NO_CARD_NO_RESET | 964 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 965 .ops = &sdhci_esdhc_be_ops, 966 }; 967 968 static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = { 969 .quirks = ESDHC_DEFAULT_QUIRKS | 970 SDHCI_QUIRK_NO_CARD_NO_RESET | 971 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 972 .ops = &sdhci_esdhc_le_ops, 973 }; 974 975 static struct soc_device_attribute soc_incorrect_hostver[] = { 976 { .family = "QorIQ T4240", .revision = "1.0", }, 977 { .family = "QorIQ T4240", .revision = "2.0", }, 978 { }, 979 }; 980 981 static struct soc_device_attribute soc_fixup_sdhc_clkdivs[] = { 982 { .family = "QorIQ LX2160A", .revision = "1.0", }, 983 { .family = "QorIQ LX2160A", .revision = "2.0", }, 984 { }, 985 }; 986 987 static struct soc_device_attribute soc_unreliable_pulse_detection[] = { 988 { .family = "QorIQ LX2160A", .revision = "1.0", }, 989 { }, 990 }; 991 992 static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host) 993 { 994 const struct of_device_id *match; 995 struct sdhci_pltfm_host *pltfm_host; 996 struct sdhci_esdhc *esdhc; 997 struct device_node *np; 998 struct clk *clk; 999 u32 val; 1000 u16 host_ver; 1001 1002 pltfm_host = sdhci_priv(host); 1003 esdhc = sdhci_pltfm_priv(pltfm_host); 1004 1005 host_ver = sdhci_readw(host, SDHCI_HOST_VERSION); 1006 esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >> 1007 SDHCI_VENDOR_VER_SHIFT; 1008 esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK; 1009 if (soc_device_match(soc_incorrect_hostver)) 1010 esdhc->quirk_incorrect_hostver = true; 1011 else 1012 esdhc->quirk_incorrect_hostver = false; 1013 1014 if (soc_device_match(soc_fixup_sdhc_clkdivs)) 1015 esdhc->quirk_limited_clk_division = true; 1016 else 1017 esdhc->quirk_limited_clk_division = false; 1018 1019 if (soc_device_match(soc_unreliable_pulse_detection)) 1020 esdhc->quirk_unreliable_pulse_detection = true; 1021 else 1022 esdhc->quirk_unreliable_pulse_detection = false; 1023 1024 match = of_match_node(sdhci_esdhc_of_match, pdev->dev.of_node); 1025 if (match) 1026 esdhc->clk_fixup = match->data; 1027 np = pdev->dev.of_node; 1028 clk = of_clk_get(np, 0); 1029 if (!IS_ERR(clk)) { 1030 /* 1031 * esdhc->peripheral_clock would be assigned with a value 1032 * which is eSDHC base clock when use periperal clock. 1033 * For ls1046a, the clock value got by common clk API is 1034 * peripheral clock while the eSDHC base clock is 1/2 1035 * peripheral clock. 1036 */ 1037 if (of_device_is_compatible(np, "fsl,ls1046a-esdhc")) 1038 esdhc->peripheral_clock = clk_get_rate(clk) / 2; 1039 else 1040 esdhc->peripheral_clock = clk_get_rate(clk); 1041 1042 clk_put(clk); 1043 } 1044 1045 if (esdhc->peripheral_clock) { 1046 esdhc_clock_enable(host, false); 1047 val = sdhci_readl(host, ESDHC_DMA_SYSCTL); 1048 val |= ESDHC_PERIPHERAL_CLK_SEL; 1049 sdhci_writel(host, val, ESDHC_DMA_SYSCTL); 1050 esdhc_clock_enable(host, true); 1051 } 1052 } 1053 1054 static int esdhc_hs400_prepare_ddr(struct mmc_host *mmc) 1055 { 1056 esdhc_tuning_block_enable(mmc_priv(mmc), false); 1057 return 0; 1058 } 1059 1060 static int sdhci_esdhc_probe(struct platform_device *pdev) 1061 { 1062 struct sdhci_host *host; 1063 struct device_node *np; 1064 struct sdhci_pltfm_host *pltfm_host; 1065 struct sdhci_esdhc *esdhc; 1066 int ret; 1067 1068 np = pdev->dev.of_node; 1069 1070 if (of_property_read_bool(np, "little-endian")) 1071 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata, 1072 sizeof(struct sdhci_esdhc)); 1073 else 1074 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata, 1075 sizeof(struct sdhci_esdhc)); 1076 1077 if (IS_ERR(host)) 1078 return PTR_ERR(host); 1079 1080 host->mmc_host_ops.start_signal_voltage_switch = 1081 esdhc_signal_voltage_switch; 1082 host->mmc_host_ops.execute_tuning = esdhc_execute_tuning; 1083 host->mmc_host_ops.hs400_prepare_ddr = esdhc_hs400_prepare_ddr; 1084 host->tuning_delay = 1; 1085 1086 esdhc_init(pdev, host); 1087 1088 sdhci_get_of_property(pdev); 1089 1090 pltfm_host = sdhci_priv(host); 1091 esdhc = sdhci_pltfm_priv(pltfm_host); 1092 if (soc_device_match(soc_fixup_tuning)) 1093 esdhc->quirk_fixup_tuning = true; 1094 else 1095 esdhc->quirk_fixup_tuning = false; 1096 1097 if (esdhc->vendor_ver == VENDOR_V_22) 1098 host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; 1099 1100 if (esdhc->vendor_ver > VENDOR_V_22) 1101 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; 1102 1103 if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc")) { 1104 host->quirks2 |= SDHCI_QUIRK_RESET_AFTER_REQUEST; 1105 host->quirks2 |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 1106 } 1107 1108 if (of_device_is_compatible(np, "fsl,p5040-esdhc") || 1109 of_device_is_compatible(np, "fsl,p5020-esdhc") || 1110 of_device_is_compatible(np, "fsl,p4080-esdhc") || 1111 of_device_is_compatible(np, "fsl,p1020-esdhc") || 1112 of_device_is_compatible(np, "fsl,t1040-esdhc")) 1113 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 1114 1115 if (of_device_is_compatible(np, "fsl,ls1021a-esdhc")) 1116 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 1117 1118 if (of_device_is_compatible(np, "fsl,p2020-esdhc")) { 1119 /* 1120 * Freescale messed up with P2020 as it has a non-standard 1121 * host control register 1122 */ 1123 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL; 1124 } 1125 1126 /* call to generic mmc_of_parse to support additional capabilities */ 1127 ret = mmc_of_parse(host->mmc); 1128 if (ret) 1129 goto err; 1130 1131 mmc_of_parse_voltage(np, &host->ocr_mask); 1132 1133 ret = sdhci_add_host(host); 1134 if (ret) 1135 goto err; 1136 1137 return 0; 1138 err: 1139 sdhci_pltfm_free(pdev); 1140 return ret; 1141 } 1142 1143 static struct platform_driver sdhci_esdhc_driver = { 1144 .driver = { 1145 .name = "sdhci-esdhc", 1146 .of_match_table = sdhci_esdhc_of_match, 1147 .pm = &esdhc_of_dev_pm_ops, 1148 }, 1149 .probe = sdhci_esdhc_probe, 1150 .remove = sdhci_pltfm_unregister, 1151 }; 1152 1153 module_platform_driver(sdhci_esdhc_driver); 1154 1155 MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC"); 1156 MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, " 1157 "Anton Vorontsov <avorontsov@ru.mvista.com>"); 1158 MODULE_LICENSE("GPL v2"); 1159