1 /* 2 * Freescale eSDHC controller driver. 3 * 4 * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc. 5 * Copyright (c) 2009 MontaVista Software, Inc. 6 * 7 * Authors: Xiaobo Xie <X.Xie@freescale.com> 8 * Anton Vorontsov <avorontsov@ru.mvista.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or (at 13 * your option) any later version. 14 */ 15 16 #include <linux/err.h> 17 #include <linux/io.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/delay.h> 21 #include <linux/module.h> 22 #include <linux/sys_soc.h> 23 #include <linux/clk.h> 24 #include <linux/ktime.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/mmc/host.h> 27 #include "sdhci-pltfm.h" 28 #include "sdhci-esdhc.h" 29 30 #define VENDOR_V_22 0x12 31 #define VENDOR_V_23 0x13 32 33 #define MMC_TIMING_NUM (MMC_TIMING_MMC_HS400 + 1) 34 35 struct esdhc_clk_fixup { 36 const unsigned int sd_dflt_max_clk; 37 const unsigned int max_clk[MMC_TIMING_NUM]; 38 }; 39 40 static const struct esdhc_clk_fixup ls1021a_esdhc_clk = { 41 .sd_dflt_max_clk = 25000000, 42 .max_clk[MMC_TIMING_MMC_HS] = 46500000, 43 .max_clk[MMC_TIMING_SD_HS] = 46500000, 44 }; 45 46 static const struct esdhc_clk_fixup ls1046a_esdhc_clk = { 47 .sd_dflt_max_clk = 25000000, 48 .max_clk[MMC_TIMING_UHS_SDR104] = 167000000, 49 .max_clk[MMC_TIMING_MMC_HS200] = 167000000, 50 }; 51 52 static const struct esdhc_clk_fixup ls1012a_esdhc_clk = { 53 .sd_dflt_max_clk = 25000000, 54 .max_clk[MMC_TIMING_UHS_SDR104] = 125000000, 55 .max_clk[MMC_TIMING_MMC_HS200] = 125000000, 56 }; 57 58 static const struct esdhc_clk_fixup p1010_esdhc_clk = { 59 .sd_dflt_max_clk = 20000000, 60 .max_clk[MMC_TIMING_LEGACY] = 20000000, 61 .max_clk[MMC_TIMING_MMC_HS] = 42000000, 62 .max_clk[MMC_TIMING_SD_HS] = 40000000, 63 }; 64 65 static const struct of_device_id sdhci_esdhc_of_match[] = { 66 { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk}, 67 { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk}, 68 { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk}, 69 { .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk}, 70 { .compatible = "fsl,mpc8379-esdhc" }, 71 { .compatible = "fsl,mpc8536-esdhc" }, 72 { .compatible = "fsl,esdhc" }, 73 { } 74 }; 75 MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match); 76 77 struct sdhci_esdhc { 78 u8 vendor_ver; 79 u8 spec_ver; 80 bool quirk_incorrect_hostver; 81 bool quirk_limited_clk_division; 82 bool quirk_unreliable_pulse_detection; 83 bool quirk_fixup_tuning; 84 unsigned int peripheral_clock; 85 const struct esdhc_clk_fixup *clk_fixup; 86 u32 div_ratio; 87 }; 88 89 /** 90 * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register 91 * to make it compatible with SD spec. 92 * 93 * @host: pointer to sdhci_host 94 * @spec_reg: SD spec register address 95 * @value: 32bit eSDHC register value on spec_reg address 96 * 97 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 98 * registers are 32 bits. There are differences in register size, register 99 * address, register function, bit position and function between eSDHC spec 100 * and SD spec. 101 * 102 * Return a fixed up register value 103 */ 104 static u32 esdhc_readl_fixup(struct sdhci_host *host, 105 int spec_reg, u32 value) 106 { 107 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 108 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 109 u32 ret; 110 111 /* 112 * The bit of ADMA flag in eSDHC is not compatible with standard 113 * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is 114 * supported by eSDHC. 115 * And for many FSL eSDHC controller, the reset value of field 116 * SDHCI_CAN_DO_ADMA1 is 1, but some of them can't support ADMA, 117 * only these vendor version is greater than 2.2/0x12 support ADMA. 118 */ 119 if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) { 120 if (esdhc->vendor_ver > VENDOR_V_22) { 121 ret = value | SDHCI_CAN_DO_ADMA2; 122 return ret; 123 } 124 } 125 /* 126 * The DAT[3:0] line signal levels and the CMD line signal level are 127 * not compatible with standard SDHC register. The line signal levels 128 * DAT[7:0] are at bits 31:24 and the command line signal level is at 129 * bit 23. All other bits are the same as in the standard SDHC 130 * register. 131 */ 132 if (spec_reg == SDHCI_PRESENT_STATE) { 133 ret = value & 0x000fffff; 134 ret |= (value >> 4) & SDHCI_DATA_LVL_MASK; 135 ret |= (value << 1) & SDHCI_CMD_LVL; 136 return ret; 137 } 138 139 /* 140 * DTS properties of mmc host are used to enable each speed mode 141 * according to soc and board capability. So clean up 142 * SDR50/SDR104/DDR50 support bits here. 143 */ 144 if (spec_reg == SDHCI_CAPABILITIES_1) { 145 ret = value & ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | 146 SDHCI_SUPPORT_DDR50); 147 return ret; 148 } 149 150 ret = value; 151 return ret; 152 } 153 154 static u16 esdhc_readw_fixup(struct sdhci_host *host, 155 int spec_reg, u32 value) 156 { 157 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 158 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 159 u16 ret; 160 int shift = (spec_reg & 0x2) * 8; 161 162 if (spec_reg == SDHCI_HOST_VERSION) 163 ret = value & 0xffff; 164 else 165 ret = (value >> shift) & 0xffff; 166 /* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect 167 * vendor version and spec version information. 168 */ 169 if ((spec_reg == SDHCI_HOST_VERSION) && 170 (esdhc->quirk_incorrect_hostver)) 171 ret = (VENDOR_V_23 << SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200; 172 return ret; 173 } 174 175 static u8 esdhc_readb_fixup(struct sdhci_host *host, 176 int spec_reg, u32 value) 177 { 178 u8 ret; 179 u8 dma_bits; 180 int shift = (spec_reg & 0x3) * 8; 181 182 ret = (value >> shift) & 0xff; 183 184 /* 185 * "DMA select" locates at offset 0x28 in SD specification, but on 186 * P5020 or P3041, it locates at 0x29. 187 */ 188 if (spec_reg == SDHCI_HOST_CONTROL) { 189 /* DMA select is 22,23 bits in Protocol Control Register */ 190 dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK; 191 /* fixup the result */ 192 ret &= ~SDHCI_CTRL_DMA_MASK; 193 ret |= dma_bits; 194 } 195 return ret; 196 } 197 198 /** 199 * esdhc_write*_fixup - Fixup the SD spec register value so that it could be 200 * written into eSDHC register. 201 * 202 * @host: pointer to sdhci_host 203 * @spec_reg: SD spec register address 204 * @value: 8/16/32bit SD spec register value that would be written 205 * @old_value: 32bit eSDHC register value on spec_reg address 206 * 207 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 208 * registers are 32 bits. There are differences in register size, register 209 * address, register function, bit position and function between eSDHC spec 210 * and SD spec. 211 * 212 * Return a fixed up register value 213 */ 214 static u32 esdhc_writel_fixup(struct sdhci_host *host, 215 int spec_reg, u32 value, u32 old_value) 216 { 217 u32 ret; 218 219 /* 220 * Enabling IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE] 221 * when SYSCTL[RSTD] is set for some special operations. 222 * No any impact on other operation. 223 */ 224 if (spec_reg == SDHCI_INT_ENABLE) 225 ret = value | SDHCI_INT_BLK_GAP; 226 else 227 ret = value; 228 229 return ret; 230 } 231 232 static u32 esdhc_writew_fixup(struct sdhci_host *host, 233 int spec_reg, u16 value, u32 old_value) 234 { 235 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 236 int shift = (spec_reg & 0x2) * 8; 237 u32 ret; 238 239 switch (spec_reg) { 240 case SDHCI_TRANSFER_MODE: 241 /* 242 * Postpone this write, we must do it together with a 243 * command write that is down below. Return old value. 244 */ 245 pltfm_host->xfer_mode_shadow = value; 246 return old_value; 247 case SDHCI_COMMAND: 248 ret = (value << 16) | pltfm_host->xfer_mode_shadow; 249 return ret; 250 } 251 252 ret = old_value & (~(0xffff << shift)); 253 ret |= (value << shift); 254 255 if (spec_reg == SDHCI_BLOCK_SIZE) { 256 /* 257 * Two last DMA bits are reserved, and first one is used for 258 * non-standard blksz of 4096 bytes that we don't support 259 * yet. So clear the DMA boundary bits. 260 */ 261 ret &= (~SDHCI_MAKE_BLKSZ(0x7, 0)); 262 } 263 return ret; 264 } 265 266 static u32 esdhc_writeb_fixup(struct sdhci_host *host, 267 int spec_reg, u8 value, u32 old_value) 268 { 269 u32 ret; 270 u32 dma_bits; 271 u8 tmp; 272 int shift = (spec_reg & 0x3) * 8; 273 274 /* 275 * eSDHC doesn't have a standard power control register, so we do 276 * nothing here to avoid incorrect operation. 277 */ 278 if (spec_reg == SDHCI_POWER_CONTROL) 279 return old_value; 280 /* 281 * "DMA select" location is offset 0x28 in SD specification, but on 282 * P5020 or P3041, it's located at 0x29. 283 */ 284 if (spec_reg == SDHCI_HOST_CONTROL) { 285 /* 286 * If host control register is not standard, exit 287 * this function 288 */ 289 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL) 290 return old_value; 291 292 /* DMA select is 22,23 bits in Protocol Control Register */ 293 dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5; 294 ret = (old_value & (~(SDHCI_CTRL_DMA_MASK << 5))) | dma_bits; 295 tmp = (value & (~SDHCI_CTRL_DMA_MASK)) | 296 (old_value & SDHCI_CTRL_DMA_MASK); 297 ret = (ret & (~0xff)) | tmp; 298 299 /* Prevent SDHCI core from writing reserved bits (e.g. HISPD) */ 300 ret &= ~ESDHC_HOST_CONTROL_RES; 301 return ret; 302 } 303 304 ret = (old_value & (~(0xff << shift))) | (value << shift); 305 return ret; 306 } 307 308 static u32 esdhc_be_readl(struct sdhci_host *host, int reg) 309 { 310 u32 ret; 311 u32 value; 312 313 if (reg == SDHCI_CAPABILITIES_1) 314 value = ioread32be(host->ioaddr + ESDHC_CAPABILITIES_1); 315 else 316 value = ioread32be(host->ioaddr + reg); 317 318 ret = esdhc_readl_fixup(host, reg, value); 319 320 return ret; 321 } 322 323 static u32 esdhc_le_readl(struct sdhci_host *host, int reg) 324 { 325 u32 ret; 326 u32 value; 327 328 if (reg == SDHCI_CAPABILITIES_1) 329 value = ioread32(host->ioaddr + ESDHC_CAPABILITIES_1); 330 else 331 value = ioread32(host->ioaddr + reg); 332 333 ret = esdhc_readl_fixup(host, reg, value); 334 335 return ret; 336 } 337 338 static u16 esdhc_be_readw(struct sdhci_host *host, int reg) 339 { 340 u16 ret; 341 u32 value; 342 int base = reg & ~0x3; 343 344 value = ioread32be(host->ioaddr + base); 345 ret = esdhc_readw_fixup(host, reg, value); 346 return ret; 347 } 348 349 static u16 esdhc_le_readw(struct sdhci_host *host, int reg) 350 { 351 u16 ret; 352 u32 value; 353 int base = reg & ~0x3; 354 355 value = ioread32(host->ioaddr + base); 356 ret = esdhc_readw_fixup(host, reg, value); 357 return ret; 358 } 359 360 static u8 esdhc_be_readb(struct sdhci_host *host, int reg) 361 { 362 u8 ret; 363 u32 value; 364 int base = reg & ~0x3; 365 366 value = ioread32be(host->ioaddr + base); 367 ret = esdhc_readb_fixup(host, reg, value); 368 return ret; 369 } 370 371 static u8 esdhc_le_readb(struct sdhci_host *host, int reg) 372 { 373 u8 ret; 374 u32 value; 375 int base = reg & ~0x3; 376 377 value = ioread32(host->ioaddr + base); 378 ret = esdhc_readb_fixup(host, reg, value); 379 return ret; 380 } 381 382 static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg) 383 { 384 u32 value; 385 386 value = esdhc_writel_fixup(host, reg, val, 0); 387 iowrite32be(value, host->ioaddr + reg); 388 } 389 390 static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg) 391 { 392 u32 value; 393 394 value = esdhc_writel_fixup(host, reg, val, 0); 395 iowrite32(value, host->ioaddr + reg); 396 } 397 398 static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg) 399 { 400 int base = reg & ~0x3; 401 u32 value; 402 u32 ret; 403 404 value = ioread32be(host->ioaddr + base); 405 ret = esdhc_writew_fixup(host, reg, val, value); 406 if (reg != SDHCI_TRANSFER_MODE) 407 iowrite32be(ret, host->ioaddr + base); 408 } 409 410 static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg) 411 { 412 int base = reg & ~0x3; 413 u32 value; 414 u32 ret; 415 416 value = ioread32(host->ioaddr + base); 417 ret = esdhc_writew_fixup(host, reg, val, value); 418 if (reg != SDHCI_TRANSFER_MODE) 419 iowrite32(ret, host->ioaddr + base); 420 } 421 422 static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg) 423 { 424 int base = reg & ~0x3; 425 u32 value; 426 u32 ret; 427 428 value = ioread32be(host->ioaddr + base); 429 ret = esdhc_writeb_fixup(host, reg, val, value); 430 iowrite32be(ret, host->ioaddr + base); 431 } 432 433 static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg) 434 { 435 int base = reg & ~0x3; 436 u32 value; 437 u32 ret; 438 439 value = ioread32(host->ioaddr + base); 440 ret = esdhc_writeb_fixup(host, reg, val, value); 441 iowrite32(ret, host->ioaddr + base); 442 } 443 444 /* 445 * For Abort or Suspend after Stop at Block Gap, ignore the ADMA 446 * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC]) 447 * and Block Gap Event(IRQSTAT[BGE]) are also set. 448 * For Continue, apply soft reset for data(SYSCTL[RSTD]); 449 * and re-issue the entire read transaction from beginning. 450 */ 451 static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask) 452 { 453 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 454 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 455 bool applicable; 456 dma_addr_t dmastart; 457 dma_addr_t dmanow; 458 459 applicable = (intmask & SDHCI_INT_DATA_END) && 460 (intmask & SDHCI_INT_BLK_GAP) && 461 (esdhc->vendor_ver == VENDOR_V_23); 462 if (!applicable) 463 return; 464 465 host->data->error = 0; 466 dmastart = sg_dma_address(host->data->sg); 467 dmanow = dmastart + host->data->bytes_xfered; 468 /* 469 * Force update to the next DMA block boundary. 470 */ 471 dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 472 SDHCI_DEFAULT_BOUNDARY_SIZE; 473 host->data->bytes_xfered = dmanow - dmastart; 474 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 475 } 476 477 static int esdhc_of_enable_dma(struct sdhci_host *host) 478 { 479 u32 value; 480 struct device *dev = mmc_dev(host->mmc); 481 482 if (of_device_is_compatible(dev->of_node, "fsl,ls1043a-esdhc") || 483 of_device_is_compatible(dev->of_node, "fsl,ls1046a-esdhc")) 484 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); 485 486 value = sdhci_readl(host, ESDHC_DMA_SYSCTL); 487 value |= ESDHC_DMA_SNOOP; 488 sdhci_writel(host, value, ESDHC_DMA_SYSCTL); 489 return 0; 490 } 491 492 static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host) 493 { 494 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 495 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 496 497 if (esdhc->peripheral_clock) 498 return esdhc->peripheral_clock; 499 else 500 return pltfm_host->clock; 501 } 502 503 static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host) 504 { 505 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 506 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 507 unsigned int clock; 508 509 if (esdhc->peripheral_clock) 510 clock = esdhc->peripheral_clock; 511 else 512 clock = pltfm_host->clock; 513 return clock / 256 / 16; 514 } 515 516 static void esdhc_clock_enable(struct sdhci_host *host, bool enable) 517 { 518 u32 val; 519 ktime_t timeout; 520 521 val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 522 523 if (enable) 524 val |= ESDHC_CLOCK_SDCLKEN; 525 else 526 val &= ~ESDHC_CLOCK_SDCLKEN; 527 528 sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL); 529 530 /* Wait max 20 ms */ 531 timeout = ktime_add_ms(ktime_get(), 20); 532 val = ESDHC_CLOCK_STABLE; 533 while (!(sdhci_readl(host, ESDHC_PRSSTAT) & val)) { 534 if (ktime_after(ktime_get(), timeout)) { 535 pr_err("%s: Internal clock never stabilised.\n", 536 mmc_hostname(host->mmc)); 537 break; 538 } 539 udelay(10); 540 } 541 } 542 543 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock) 544 { 545 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 546 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 547 int pre_div = 1; 548 int div = 1; 549 int division; 550 ktime_t timeout; 551 long fixup = 0; 552 u32 temp; 553 554 host->mmc->actual_clock = 0; 555 556 if (clock == 0) { 557 esdhc_clock_enable(host, false); 558 return; 559 } 560 561 /* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */ 562 if (esdhc->vendor_ver < VENDOR_V_23) 563 pre_div = 2; 564 565 if (host->mmc->card && mmc_card_sd(host->mmc->card) && 566 esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY) 567 fixup = esdhc->clk_fixup->sd_dflt_max_clk; 568 else if (esdhc->clk_fixup) 569 fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing]; 570 571 if (fixup && clock > fixup) 572 clock = fixup; 573 574 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 575 temp &= ~(ESDHC_CLOCK_SDCLKEN | ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | 576 ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK); 577 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 578 579 while (host->max_clk / pre_div / 16 > clock && pre_div < 256) 580 pre_div *= 2; 581 582 while (host->max_clk / pre_div / div > clock && div < 16) 583 div++; 584 585 if (esdhc->quirk_limited_clk_division && 586 clock == MMC_HS200_MAX_DTR && 587 (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 || 588 host->flags & SDHCI_HS400_TUNING)) { 589 division = pre_div * div; 590 if (division <= 4) { 591 pre_div = 4; 592 div = 1; 593 } else if (division <= 8) { 594 pre_div = 4; 595 div = 2; 596 } else if (division <= 12) { 597 pre_div = 4; 598 div = 3; 599 } else { 600 pr_warn("%s: using unsupported clock division.\n", 601 mmc_hostname(host->mmc)); 602 } 603 } 604 605 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 606 clock, host->max_clk / pre_div / div); 607 host->mmc->actual_clock = host->max_clk / pre_div / div; 608 esdhc->div_ratio = pre_div * div; 609 pre_div >>= 1; 610 div--; 611 612 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 613 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 614 | (div << ESDHC_DIVIDER_SHIFT) 615 | (pre_div << ESDHC_PREDIV_SHIFT)); 616 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 617 618 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && 619 clock == MMC_HS200_MAX_DTR) { 620 temp = sdhci_readl(host, ESDHC_TBCTL); 621 sdhci_writel(host, temp | ESDHC_HS400_MODE, ESDHC_TBCTL); 622 temp = sdhci_readl(host, ESDHC_SDCLKCTL); 623 sdhci_writel(host, temp | ESDHC_CMD_CLK_CTL, ESDHC_SDCLKCTL); 624 esdhc_clock_enable(host, true); 625 626 temp = sdhci_readl(host, ESDHC_DLLCFG0); 627 temp |= ESDHC_DLL_ENABLE; 628 if (host->mmc->actual_clock == MMC_HS200_MAX_DTR) 629 temp |= ESDHC_DLL_FREQ_SEL; 630 sdhci_writel(host, temp, ESDHC_DLLCFG0); 631 temp = sdhci_readl(host, ESDHC_TBCTL); 632 sdhci_writel(host, temp | ESDHC_HS400_WNDW_ADJUST, ESDHC_TBCTL); 633 634 esdhc_clock_enable(host, false); 635 temp = sdhci_readl(host, ESDHC_DMA_SYSCTL); 636 temp |= ESDHC_FLUSH_ASYNC_FIFO; 637 sdhci_writel(host, temp, ESDHC_DMA_SYSCTL); 638 } 639 640 /* Wait max 20 ms */ 641 timeout = ktime_add_ms(ktime_get(), 20); 642 while (!(sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE)) { 643 if (ktime_after(ktime_get(), timeout)) { 644 pr_err("%s: Internal clock never stabilised.\n", 645 mmc_hostname(host->mmc)); 646 return; 647 } 648 udelay(10); 649 } 650 651 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 652 temp |= ESDHC_CLOCK_SDCLKEN; 653 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 654 } 655 656 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 657 { 658 u32 ctrl; 659 660 ctrl = sdhci_readl(host, ESDHC_PROCTL); 661 ctrl &= (~ESDHC_CTRL_BUSWIDTH_MASK); 662 switch (width) { 663 case MMC_BUS_WIDTH_8: 664 ctrl |= ESDHC_CTRL_8BITBUS; 665 break; 666 667 case MMC_BUS_WIDTH_4: 668 ctrl |= ESDHC_CTRL_4BITBUS; 669 break; 670 671 default: 672 break; 673 } 674 675 sdhci_writel(host, ctrl, ESDHC_PROCTL); 676 } 677 678 static void esdhc_reset(struct sdhci_host *host, u8 mask) 679 { 680 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 681 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 682 u32 val; 683 684 sdhci_reset(host, mask); 685 686 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 687 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 688 689 if (mask & SDHCI_RESET_ALL) { 690 val = sdhci_readl(host, ESDHC_TBCTL); 691 val &= ~ESDHC_TB_EN; 692 sdhci_writel(host, val, ESDHC_TBCTL); 693 694 if (esdhc->quirk_unreliable_pulse_detection) { 695 val = sdhci_readl(host, ESDHC_DLLCFG1); 696 val &= ~ESDHC_DLL_PD_PULSE_STRETCH_SEL; 697 sdhci_writel(host, val, ESDHC_DLLCFG1); 698 } 699 } 700 } 701 702 /* The SCFG, Supplemental Configuration Unit, provides SoC specific 703 * configuration and status registers for the device. There is a 704 * SDHC IO VSEL control register on SCFG for some platforms. It's 705 * used to support SDHC IO voltage switching. 706 */ 707 static const struct of_device_id scfg_device_ids[] = { 708 { .compatible = "fsl,t1040-scfg", }, 709 { .compatible = "fsl,ls1012a-scfg", }, 710 { .compatible = "fsl,ls1046a-scfg", }, 711 {} 712 }; 713 714 /* SDHC IO VSEL control register definition */ 715 #define SCFG_SDHCIOVSELCR 0x408 716 #define SDHCIOVSELCR_TGLEN 0x80000000 717 #define SDHCIOVSELCR_VSELVAL 0x60000000 718 #define SDHCIOVSELCR_SDHC_VS 0x00000001 719 720 static int esdhc_signal_voltage_switch(struct mmc_host *mmc, 721 struct mmc_ios *ios) 722 { 723 struct sdhci_host *host = mmc_priv(mmc); 724 struct device_node *scfg_node; 725 void __iomem *scfg_base = NULL; 726 u32 sdhciovselcr; 727 u32 val; 728 729 /* 730 * Signal Voltage Switching is only applicable for Host Controllers 731 * v3.00 and above. 732 */ 733 if (host->version < SDHCI_SPEC_300) 734 return 0; 735 736 val = sdhci_readl(host, ESDHC_PROCTL); 737 738 switch (ios->signal_voltage) { 739 case MMC_SIGNAL_VOLTAGE_330: 740 val &= ~ESDHC_VOLT_SEL; 741 sdhci_writel(host, val, ESDHC_PROCTL); 742 return 0; 743 case MMC_SIGNAL_VOLTAGE_180: 744 scfg_node = of_find_matching_node(NULL, scfg_device_ids); 745 if (scfg_node) 746 scfg_base = of_iomap(scfg_node, 0); 747 if (scfg_base) { 748 sdhciovselcr = SDHCIOVSELCR_TGLEN | 749 SDHCIOVSELCR_VSELVAL; 750 iowrite32be(sdhciovselcr, 751 scfg_base + SCFG_SDHCIOVSELCR); 752 753 val |= ESDHC_VOLT_SEL; 754 sdhci_writel(host, val, ESDHC_PROCTL); 755 mdelay(5); 756 757 sdhciovselcr = SDHCIOVSELCR_TGLEN | 758 SDHCIOVSELCR_SDHC_VS; 759 iowrite32be(sdhciovselcr, 760 scfg_base + SCFG_SDHCIOVSELCR); 761 iounmap(scfg_base); 762 } else { 763 val |= ESDHC_VOLT_SEL; 764 sdhci_writel(host, val, ESDHC_PROCTL); 765 } 766 return 0; 767 default: 768 return 0; 769 } 770 } 771 772 static struct soc_device_attribute soc_fixup_tuning[] = { 773 { .family = "QorIQ T1040", .revision = "1.0", }, 774 { .family = "QorIQ T2080", .revision = "1.0", }, 775 { .family = "QorIQ T1023", .revision = "1.0", }, 776 { .family = "QorIQ LS1021A", .revision = "1.0", }, 777 { .family = "QorIQ LS1080A", .revision = "1.0", }, 778 { .family = "QorIQ LS2080A", .revision = "1.0", }, 779 { .family = "QorIQ LS1012A", .revision = "1.0", }, 780 { .family = "QorIQ LS1043A", .revision = "1.*", }, 781 { .family = "QorIQ LS1046A", .revision = "1.0", }, 782 { }, 783 }; 784 785 static void esdhc_tuning_block_enable(struct sdhci_host *host, bool enable) 786 { 787 u32 val; 788 789 esdhc_clock_enable(host, false); 790 791 val = sdhci_readl(host, ESDHC_DMA_SYSCTL); 792 val |= ESDHC_FLUSH_ASYNC_FIFO; 793 sdhci_writel(host, val, ESDHC_DMA_SYSCTL); 794 795 val = sdhci_readl(host, ESDHC_TBCTL); 796 if (enable) 797 val |= ESDHC_TB_EN; 798 else 799 val &= ~ESDHC_TB_EN; 800 sdhci_writel(host, val, ESDHC_TBCTL); 801 802 esdhc_clock_enable(host, true); 803 } 804 805 static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) 806 { 807 struct sdhci_host *host = mmc_priv(mmc); 808 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 809 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 810 bool hs400_tuning; 811 u32 val; 812 int ret; 813 814 if (esdhc->quirk_limited_clk_division && 815 host->flags & SDHCI_HS400_TUNING) 816 esdhc_of_set_clock(host, host->clock); 817 818 esdhc_tuning_block_enable(host, true); 819 820 hs400_tuning = host->flags & SDHCI_HS400_TUNING; 821 ret = sdhci_execute_tuning(mmc, opcode); 822 823 if (hs400_tuning) { 824 val = sdhci_readl(host, ESDHC_SDTIMNGCTL); 825 val |= ESDHC_FLW_CTL_BG; 826 sdhci_writel(host, val, ESDHC_SDTIMNGCTL); 827 } 828 829 if (host->tuning_err == -EAGAIN && esdhc->quirk_fixup_tuning) { 830 831 /* program TBPTR[TB_WNDW_END_PTR] = 3*DIV_RATIO and 832 * program TBPTR[TB_WNDW_START_PTR] = 5*DIV_RATIO 833 */ 834 val = sdhci_readl(host, ESDHC_TBPTR); 835 val = (val & ~((0x7f << 8) | 0x7f)) | 836 (3 * esdhc->div_ratio) | ((5 * esdhc->div_ratio) << 8); 837 sdhci_writel(host, val, ESDHC_TBPTR); 838 839 /* program the software tuning mode by setting 840 * TBCTL[TB_MODE]=2'h3 841 */ 842 val = sdhci_readl(host, ESDHC_TBCTL); 843 val |= 0x3; 844 sdhci_writel(host, val, ESDHC_TBCTL); 845 sdhci_execute_tuning(mmc, opcode); 846 } 847 return ret; 848 } 849 850 static void esdhc_set_uhs_signaling(struct sdhci_host *host, 851 unsigned int timing) 852 { 853 if (timing == MMC_TIMING_MMC_HS400) 854 esdhc_tuning_block_enable(host, true); 855 else 856 sdhci_set_uhs_signaling(host, timing); 857 } 858 859 #ifdef CONFIG_PM_SLEEP 860 static u32 esdhc_proctl; 861 static int esdhc_of_suspend(struct device *dev) 862 { 863 struct sdhci_host *host = dev_get_drvdata(dev); 864 865 esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL); 866 867 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 868 mmc_retune_needed(host->mmc); 869 870 return sdhci_suspend_host(host); 871 } 872 873 static int esdhc_of_resume(struct device *dev) 874 { 875 struct sdhci_host *host = dev_get_drvdata(dev); 876 int ret = sdhci_resume_host(host); 877 878 if (ret == 0) { 879 /* Isn't this already done by sdhci_resume_host() ? --rmk */ 880 esdhc_of_enable_dma(host); 881 sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL); 882 } 883 return ret; 884 } 885 #endif 886 887 static SIMPLE_DEV_PM_OPS(esdhc_of_dev_pm_ops, 888 esdhc_of_suspend, 889 esdhc_of_resume); 890 891 static const struct sdhci_ops sdhci_esdhc_be_ops = { 892 .read_l = esdhc_be_readl, 893 .read_w = esdhc_be_readw, 894 .read_b = esdhc_be_readb, 895 .write_l = esdhc_be_writel, 896 .write_w = esdhc_be_writew, 897 .write_b = esdhc_be_writeb, 898 .set_clock = esdhc_of_set_clock, 899 .enable_dma = esdhc_of_enable_dma, 900 .get_max_clock = esdhc_of_get_max_clock, 901 .get_min_clock = esdhc_of_get_min_clock, 902 .adma_workaround = esdhc_of_adma_workaround, 903 .set_bus_width = esdhc_pltfm_set_bus_width, 904 .reset = esdhc_reset, 905 .set_uhs_signaling = esdhc_set_uhs_signaling, 906 }; 907 908 static const struct sdhci_ops sdhci_esdhc_le_ops = { 909 .read_l = esdhc_le_readl, 910 .read_w = esdhc_le_readw, 911 .read_b = esdhc_le_readb, 912 .write_l = esdhc_le_writel, 913 .write_w = esdhc_le_writew, 914 .write_b = esdhc_le_writeb, 915 .set_clock = esdhc_of_set_clock, 916 .enable_dma = esdhc_of_enable_dma, 917 .get_max_clock = esdhc_of_get_max_clock, 918 .get_min_clock = esdhc_of_get_min_clock, 919 .adma_workaround = esdhc_of_adma_workaround, 920 .set_bus_width = esdhc_pltfm_set_bus_width, 921 .reset = esdhc_reset, 922 .set_uhs_signaling = esdhc_set_uhs_signaling, 923 }; 924 925 static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = { 926 .quirks = ESDHC_DEFAULT_QUIRKS | 927 #ifdef CONFIG_PPC 928 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 929 #endif 930 SDHCI_QUIRK_NO_CARD_NO_RESET | 931 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 932 .ops = &sdhci_esdhc_be_ops, 933 }; 934 935 static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = { 936 .quirks = ESDHC_DEFAULT_QUIRKS | 937 SDHCI_QUIRK_NO_CARD_NO_RESET | 938 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 939 .ops = &sdhci_esdhc_le_ops, 940 }; 941 942 static struct soc_device_attribute soc_incorrect_hostver[] = { 943 { .family = "QorIQ T4240", .revision = "1.0", }, 944 { .family = "QorIQ T4240", .revision = "2.0", }, 945 { }, 946 }; 947 948 static struct soc_device_attribute soc_fixup_sdhc_clkdivs[] = { 949 { .family = "QorIQ LX2160A", .revision = "1.0", }, 950 { }, 951 }; 952 953 static struct soc_device_attribute soc_unreliable_pulse_detection[] = { 954 { .family = "QorIQ LX2160A", .revision = "1.0", }, 955 { }, 956 }; 957 958 static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host) 959 { 960 const struct of_device_id *match; 961 struct sdhci_pltfm_host *pltfm_host; 962 struct sdhci_esdhc *esdhc; 963 struct device_node *np; 964 struct clk *clk; 965 u32 val; 966 u16 host_ver; 967 968 pltfm_host = sdhci_priv(host); 969 esdhc = sdhci_pltfm_priv(pltfm_host); 970 971 host_ver = sdhci_readw(host, SDHCI_HOST_VERSION); 972 esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >> 973 SDHCI_VENDOR_VER_SHIFT; 974 esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK; 975 if (soc_device_match(soc_incorrect_hostver)) 976 esdhc->quirk_incorrect_hostver = true; 977 else 978 esdhc->quirk_incorrect_hostver = false; 979 980 if (soc_device_match(soc_fixup_sdhc_clkdivs)) 981 esdhc->quirk_limited_clk_division = true; 982 else 983 esdhc->quirk_limited_clk_division = false; 984 985 if (soc_device_match(soc_unreliable_pulse_detection)) 986 esdhc->quirk_unreliable_pulse_detection = true; 987 else 988 esdhc->quirk_unreliable_pulse_detection = false; 989 990 match = of_match_node(sdhci_esdhc_of_match, pdev->dev.of_node); 991 if (match) 992 esdhc->clk_fixup = match->data; 993 np = pdev->dev.of_node; 994 clk = of_clk_get(np, 0); 995 if (!IS_ERR(clk)) { 996 /* 997 * esdhc->peripheral_clock would be assigned with a value 998 * which is eSDHC base clock when use periperal clock. 999 * For ls1046a, the clock value got by common clk API is 1000 * peripheral clock while the eSDHC base clock is 1/2 1001 * peripheral clock. 1002 */ 1003 if (of_device_is_compatible(np, "fsl,ls1046a-esdhc")) 1004 esdhc->peripheral_clock = clk_get_rate(clk) / 2; 1005 else 1006 esdhc->peripheral_clock = clk_get_rate(clk); 1007 1008 clk_put(clk); 1009 } 1010 1011 if (esdhc->peripheral_clock) { 1012 esdhc_clock_enable(host, false); 1013 val = sdhci_readl(host, ESDHC_DMA_SYSCTL); 1014 val |= ESDHC_PERIPHERAL_CLK_SEL; 1015 sdhci_writel(host, val, ESDHC_DMA_SYSCTL); 1016 esdhc_clock_enable(host, true); 1017 } 1018 } 1019 1020 static int esdhc_hs400_prepare_ddr(struct mmc_host *mmc) 1021 { 1022 esdhc_tuning_block_enable(mmc_priv(mmc), false); 1023 return 0; 1024 } 1025 1026 static int sdhci_esdhc_probe(struct platform_device *pdev) 1027 { 1028 struct sdhci_host *host; 1029 struct device_node *np; 1030 struct sdhci_pltfm_host *pltfm_host; 1031 struct sdhci_esdhc *esdhc; 1032 int ret; 1033 1034 np = pdev->dev.of_node; 1035 1036 if (of_property_read_bool(np, "little-endian")) 1037 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata, 1038 sizeof(struct sdhci_esdhc)); 1039 else 1040 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata, 1041 sizeof(struct sdhci_esdhc)); 1042 1043 if (IS_ERR(host)) 1044 return PTR_ERR(host); 1045 1046 host->mmc_host_ops.start_signal_voltage_switch = 1047 esdhc_signal_voltage_switch; 1048 host->mmc_host_ops.execute_tuning = esdhc_execute_tuning; 1049 host->mmc_host_ops.hs400_prepare_ddr = esdhc_hs400_prepare_ddr; 1050 host->tuning_delay = 1; 1051 1052 esdhc_init(pdev, host); 1053 1054 sdhci_get_of_property(pdev); 1055 1056 pltfm_host = sdhci_priv(host); 1057 esdhc = sdhci_pltfm_priv(pltfm_host); 1058 if (soc_device_match(soc_fixup_tuning)) 1059 esdhc->quirk_fixup_tuning = true; 1060 else 1061 esdhc->quirk_fixup_tuning = false; 1062 1063 if (esdhc->vendor_ver == VENDOR_V_22) 1064 host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; 1065 1066 if (esdhc->vendor_ver > VENDOR_V_22) 1067 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; 1068 1069 if (of_device_is_compatible(np, "fsl,p5040-esdhc") || 1070 of_device_is_compatible(np, "fsl,p5020-esdhc") || 1071 of_device_is_compatible(np, "fsl,p4080-esdhc") || 1072 of_device_is_compatible(np, "fsl,p1020-esdhc") || 1073 of_device_is_compatible(np, "fsl,t1040-esdhc")) 1074 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 1075 1076 if (of_device_is_compatible(np, "fsl,ls1021a-esdhc")) 1077 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 1078 1079 if (of_device_is_compatible(np, "fsl,p2020-esdhc")) { 1080 /* 1081 * Freescale messed up with P2020 as it has a non-standard 1082 * host control register 1083 */ 1084 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL; 1085 } 1086 1087 /* call to generic mmc_of_parse to support additional capabilities */ 1088 ret = mmc_of_parse(host->mmc); 1089 if (ret) 1090 goto err; 1091 1092 mmc_of_parse_voltage(np, &host->ocr_mask); 1093 1094 ret = sdhci_add_host(host); 1095 if (ret) 1096 goto err; 1097 1098 return 0; 1099 err: 1100 sdhci_pltfm_free(pdev); 1101 return ret; 1102 } 1103 1104 static struct platform_driver sdhci_esdhc_driver = { 1105 .driver = { 1106 .name = "sdhci-esdhc", 1107 .of_match_table = sdhci_esdhc_of_match, 1108 .pm = &esdhc_of_dev_pm_ops, 1109 }, 1110 .probe = sdhci_esdhc_probe, 1111 .remove = sdhci_pltfm_unregister, 1112 }; 1113 1114 module_platform_driver(sdhci_esdhc_driver); 1115 1116 MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC"); 1117 MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, " 1118 "Anton Vorontsov <avorontsov@ru.mvista.com>"); 1119 MODULE_LICENSE("GPL v2"); 1120